A Design Method for a RISC-VAIA Interrupt-Configured Multi-Privilege Level IMSIC Controller

Abstract

This invention discloses a design method for a RISC-V AIA interrupt-configurable multi-privilege-level IMSIC controller, comprising: setting a programmable configuration register MS_CUT_CFG in the IMSIC to dynamically allocate interrupt file resources for machine mode (M-mode) and supervisor mode (S-mode) at runtime; controlling the allocation ratio of the actual physical storage space of interrupt files in machine mode (M-mode) and supervisor mode (S-mode) through the configuration register MS_CUT_CFG to achieve dynamic reuse of interrupt file resources; physically sharing the same hardware register array for the interrupt enable register group (IE) and interrupt suspend register group (IP) of machine mode (M-mode) and supervisor mode (S-mode); and mapping suspended but executable interrupt requests to the corresponding privilege level and submitting them to the processor core through an interrupt arbitration circuit based on the current value of the configuration register. This invention overcomes the limitations of the static resource configuration strategy for IMSIC interrupt files, significantly enhancing the flexibility and dynamic scenario adaptability of RISC-V AIA interrupt applications.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and in particular to a design method for a RISC-V AIA interrupt-configured multi-privilege level IMSIC controller. Background Technology

[0002] With the widespread application of the open-source instruction set architecture RISC-V in data centers, artificial intelligence, and edge computing, its high-performance interrupt handling capabilities have become a key technical requirement. RISC-V Advanced Interrupt Architecture (AIA), as a next-generation interrupt specification, significantly improves the efficiency and flexibility of parallel interrupt processing in multi-core systems by introducing message-signaled interrupts (MSI) and privileged interrupt management (such as machine mode (M-mode) and supervisor mode (S-mode)).

[0003] When supporting multi-privilege level interrupts, the RISC-V AIA Incoming Message-Signaled Interrupt Controller (IMSIC) employs a static resource configuration strategy. This means that a fixed-size interrupt file space is statically allocated for each privilege level within the IMSIC of each hardware thread (hart). For example, the interrupt files for M-mode and S-mode are independently pre-allocated and cannot be dynamically adjusted. However, the interrupt quantity requirements for different privilege levels vary significantly across different applications. For instance, Supervisor mode (S-mode) needs to handle a large number of external device interrupts (such as PCIe device MSI interrupts), while Machine mode (M-mode) primarily responds to high-priority local events (such as RAS reliability events).

[0004] In this case, the static allocation strategy leads to the following problems: Wasted resources or inability to meet demand: Low-activity privileged IMSIC interrupt file space is idle, while high-activity mode may face insufficient number of interrupts to support; Lack of flexibility and poor adaptability to dynamic scenarios: In virtualization or real-time load fluctuation scenarios, resource allocation cannot be flexibly adjusted; or hardware resource utilization is low, especially in large-scale multi-core systems, resulting in significant area and power consumption overhead. Summary of the Invention

[0005] To address the problems existing in the prior art, the purpose of this invention is to provide a design method for a RISC-V AIA interrupt configuration multi-privilege level IMSIC controller, which breaks through the limitations of the static resource configuration strategy of IMSIC interrupt files, and greatly reduces hardware overhead while meeting the same interrupt scale requirements.

[0006] To achieve the above objectives, the present invention provides a design method for a RISC-V AIA interrupt-configured multi-privilege level IMSIC controller, comprising: In IMSIC, a programmable configuration register MS_CUT_CFG is set to dynamically allocate interrupt file resources between machine mode (M-mode) and supervisor mode (S-mode) at runtime. By configuring the MS_CUT_CFG register, the allocation ratio of the actual physical storage space of interrupt files in machine mode (M-mode) and supervisor mode (S-mode) is controlled, thereby realizing the dynamic reuse of interrupt file resources. The interrupt enable register group (IE) and interrupt suspend register group (IP) of both Machine Mode (M-mode) and Supervisor Mode (S-mode) physically share the same set of hardware register arrays. The interrupt arbitration circuit maps pending but achievable interrupt requests to the corresponding privilege level and submits them to the processor core based on the value of the current configuration register.

[0007] Furthermore, the configuration register MS_CUT_CFG is 5 bits wide, located in the machine-level interrupt file, and is read and written through the indirect access mechanism defined in the AIA specification.

[0008] Furthermore, the mapping relationship between the logical ID of the S-mode interrupt and its physical storage location is as follows: For a 32-bit register architecture, s_eie[i] maps to ; For a 64-bit register architecture, s_eie[i] is mapped to ie[i + ms_cut].

[0009] Furthermore, the claiming operation of the S-mode interrupt in the supervisor mode is implemented by writing to the stopei register, which actually clears the bit at the corresponding offset position in the shared interrupt suspend register group IP.

[0010] Furthermore, the interrupt arbitration circuit selects the interrupt with the smallest ID from all pending and enabled interrupts, and determines whether the interrupt belongs to machine mode (M-mode) or supervisor mode (S-mode) based on the value of the configuration register MS_CUT_CFG.

[0011] Furthermore, the output judgment logic of the interrupt arbitration circuit is as follows: If min_ID[10:6] ≥ MS_CUT, it is determined as an S-mode interrupt, and the output stopei values are {min_ID[10:6]- MS_CUT, min_ID[5:0]}; If min_ID[10:6] < MS_CUT, it is determined as an M-mode interrupt, and the output mtopei value is min_ID.

[0012] Further, the total size of the shared interrupt enable register group IE and interrupt pending register group IP is 2048 bits, which are dynamically allocated to machine mode M-mode and supervisor mode S-mode for use by configuring the configuration register MS_CUT_CFG.

[0013] Further, said method is applicable to each hardware thread hart in a multi-core processor supporting the RISC-V AIA specification.

[0014] Further, said configuration register MS_CUT_CFG is indirectly accessed through a CSR register under machine mode M-mode, and 0x7F reserved in the AIA specification is used for address offset.

[0015] Further, said method also supports the VS-level interrupt file in virtualization extension, and realizes dynamic allocation of M / S / VS three-level interrupt files by extending configuration registers.

[0016] The beneficial effects of the present invention are as follows: the present invention breaks through the limitation of the static resource configuration strategy of the IMSIC interrupt file, supports runtime adjustment of the interrupt file sizes of machine mode M-mode / supervisor mode S-mode, and allocates IMSIC entries on demand to improve the utilization rate of hardware resources, thereby greatly reducing hardware overhead when meeting the requirement of the same interrupt scale, or enabling the same hardware resources to support a larger-scale interrupt source, significantly enhancing the flexibility and dynamic scene adaptability of RISC-V AIA interrupt applications. Description of Drawings

[0017] Figure 1 is an overall structure diagram supporting configurable multi-privilege-level IMSIC; Figure 2 is a configurable IMSIC module structure diagram supporting both machine mode M-mode and supervisor mode S-mode interrupts; Figure 3 is a bit diagram of a multi-privilege-level interrupt number configuration register; Figure 4 is an interrupt arbitration circuit and an interrupt arbitration logic diagram of a multi-privilege-level configurable IMSIC; Figure 5This is a diagram illustrating the access to the multi-privilege level interrupt enable and pending bits in a 32-bit register. Figure 6 This is a diagram illustrating the access to the multi-privilege level interrupt enable and pending bits in a 64-bit register. Detailed Implementation

[0018] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0020] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0021] The following combination Figures 1-6 Specific embodiments of the present invention will be described in detail below. It should be understood that the specific embodiments described herein are for illustrative and explanatory purposes only and are not intended to limit the present invention.

[0022] This invention discloses a design method for a RISC-V AIA interrupt-configured multi-privilege level IMSIC controller. Core innovations include: designing a 5-bit configuration register MS_CUT_CFG to support runtime adjustment of interrupt file size in machine mode (M-mode) and supervisor mode (S-mode); allocating IMSIC entries on demand; designing a scalable interrupt file architecture; employing a dynamic space reuse mechanism based on window switching to allow machine mode (M-mode) and supervisor mode (S-mode) to share the IE / IP interrupt large file group and interrupt arbitration logic circuitry; and ensuring the correctness of interrupt functionality under dynamic configuration by designing hardware logic to remap interrupt logic IDs to hardware IDs, while also complying with AIA specifications.

[0023] like Figure 5 , Figure 6 As shown, enable and suspend register array index remapping: From the user software perspective, the s_eie and s_eip arrays of the S-mode interrupt file are mapped to a shared hardware array via offsets: The actual global index number of the enable / suspend bit of the S-mode interrupt with identifier id is: index = id + ms_cut × 64.

[0024] Right now: For 32-bit wide register design: Write s_eie[i][0:31] → Modify

[0025] Read s_eip[i] [0:31] → Read

[0026] For 64-bit wide register design: Write s_eie[i][0:63]→ modify ie[i+ms_cut][0:63] Read s_eip[i] [0:63] → Read ip[i+ms_cut][0:63] This invention discloses a design method for a RISC-V AIA interrupt-configured multi-privilege IMSIC controller, comprising: In IMSIC, a programmable configuration register MS_CUT_CFG is set to dynamically allocate interrupt file resources between machine mode (M-mode) and supervisor mode (S-mode) at runtime. By configuring the MS_CUT_CFG register, the allocation ratio of the actual physical storage space of interrupt files in machine mode (M-mode) and supervisor mode (S-mode) is controlled, thereby realizing the dynamic reuse of interrupt file resources. The interrupt enable register group (IE) and interrupt suspend register group (IP) of both Machine Mode (M-mode) and Supervisor Mode (S-mode) physically share the same set of hardware register arrays. The interrupt arbitration circuit maps pending but enable interrupt requests to the corresponding privilege level and submits them to the processor core based on the value of the current configuration register.

[0027] Specifically, the following steps are included: Step 1: Place the configuration register MS_CUT_CFG in the IMSIC machine-level interrupt file. It can be accessed indirectly using the miselect (CSR register address 0x350) and mireg (CSR register address 0x351) registers in the RISC-VAIA specification, using a reserved second-level address in the AIA specification for indirect access to the interrupt file, such as 0x7f. To meet the RISC-V AIA specification, the configuration register MS_CUT_CFG only requires 5 bits in hardware implementation.

[0028] The addresses and access methods of the IMSIC multi-privilege configuration registers are as follows: Considering access permission issues, the added configuration register is placed at the Machine level. This design places the configuration register MS_CUT_CFG in the IMSIC machine-level interrupt file, which can be indirectly accessed through the miselect (CSR register address 0x350) and mireg (CSR register address 0x351) registers in the RISC-V AIA specification, using the reserved second-level address 0x7f of the interrupt file for indirect access in the AIA specification. After adding this register, the addressing in the machine-level interrupt file via miselect and mireg is as follows:

[0029] The RISC-V AIA specification states that the number of interrupt IDs supported by the interrupt file (and the number of active bits in each array) is one less than a multiple of 64, with a minimum of 63 and a maximum of 2047. Therefore, from a binary perspective, only the high 5 bits of the configured ID number are needed, while the low 6 bits are irrelevant. The configuration register MS_CUT_CFG only requires 5 bits in its hardware implementation. From a software user's perspective, writing to the other reserved bits of this configuration register is ineffective, and reading them always returns 0.

[0030] like Figure 3 As shown, 0 ≤ ms_cut ≤ 32, the total number of interrupt IDs supported by the Machine level is... The range is from 1 to The total number of interrupt IDs supported by Supervisor level is [number missing]. .

[0031] Step 2: From the user's perspective, the s_eie and s_eip arrays of the S-mode interrupt file in the supervisor mode are mapped to a shared hardware array via offsets. The actual global index number of the enable / suspend bit of the supervisor mode S-mode interrupt with identifier id is index = id + ms_cut × 64.

[0032] Right now: For 32-bit wide register design: Write s_eie[i][0:31] → Modify ; Read s_eip[i] [0:31] → Read ; For 64-bit wide register design: Write s_eie[i][0:63]→ modify ie[i+ms_cut][0:63]; Read s_eip[i] [0:63] → Read ip[i+ms_cut][0:63].

[0033] Step 3: For the configurable IMSIC of this invention, claiming a supervisor mode S-mode interrupt requires mapping the claimed supervisor mode S-mode interrupt ID number to the corresponding bit in the corresponding shared IP register group and then clearing it. Assuming the claimed supervisor mode S-mode interrupt ID number is i, the write operation to stopei will: For 32-bit wide register design: The CSRRW instruction claims the S-mode interruption of the supervisor mode. This logically modifies s_eip[i / 32] [i%32] and physically modifies... ; For 64-bit wide register design: The CSRRW instruction claims the S-mode interruption of the supervisor mode i → logically modifies s_eip[i / 32] [i%64], and physically modifies ip[i / 64+ms_cut] [i%64].

[0034] Step 4: The function of the interrupt arbitration circuit is to select the smallest ID number from all the bits that are set to "1" in all the eip[0]-eip

[63] registers and the corresponding bits in the eie[0]-eie

[63] registers are also set to "1", and output the ID number to the processor core for processing.

[0035] In order to save hardware overhead, from the perspective of hardware resources, the interrupt files of machine and supervisor of IMSIC of the same hart share the ie array, the ip array and the interrupt arbitration circuit.

[0036] The interrupt arbitration circuit selects the interrupt with the smallest sequence number from all bits set to "1" in ip[2047:0], and the sequence number is min_ID≠0, if: When min_ID[10:6]≥MS_CUT and {Min_ID[10:6]–MS_CUT, Min_ID[5:0]}<s_eithreshold, a supervisor mode S-mode interrupt request is sent to the core, and the value of stopei is {Min_ID[10:6]–MS_CUT, Min_ID[5:0]}; When min_ID[10:6]<MS_CUT and Min_ID<s_eithreshold, a machine mode M-mode interrupt request is sent to the core, and the value of mtopei is min_ID.

[0037] Figure 1 It is an overall structure diagram for supporting configurable multi-privilege-level IMSIC. Although the machine mode M-mode interrupt file and the supervisor mode S-mode interrupt file of IMSIC of the same hart logically have independent *select, *ireg, *topei, ethreshold registers and eie, eip register groups, the machine mode M-mode interrupt file and the supervisor mode S-mode interrupt file physically share the same interrupt enable register group IE, interrupt pending register group IP, and interrupt arbitration circuit.

[0038] Figure 2 It is a configurable IMSIC module structure diagram supporting both machine mode M-mode and supervisor mode S-mode interrupts, which is also the module structure and important logic circuit diagram of the configurable IMSIC in the present invention. Each IMSIC must implement the Machine-level interrupt file, and can optionally implement the Supervisor or VS-level interrupt file. These interrupt files are used for interrupt enabling, setting and threshold control of corresponding privilege levels. Software passes through CSR registers of each privilege level It interacts with the corresponding privilege level interrupt file of IMSIC. IMSIC receives all MSI interrupts sent to this HART through the seteipnum register and records them in the interrupt pending register. IMSIC selects all interrupts with both the pending and enable bits set, inputs them to the arbitration circuit, selects the interrupt with the highest priority and above the threshold, and sends it to the set CSR interrupt pending registers (mip, sip, vsip) of the corresponding privilege level of this HART. It also stores the interrupt ID number in the *topei register of each privilege level, thereby achieving dynamic allocation of the M / S / VS three-level interrupt files through extended configuration registers. The software reads and writes the CSR registers of each privilege level. The interrupt is claimed and cleared. `hart` reads this register to claim the corresponding interrupt ID number, and `hart` writes `*topei` to clear the pending bit of the corresponding interrupt in the interruptfile.

[0039] This invention conforms to the RISC-V AIA specification. The RISC-V AIA specification defines the relationship between interrupt priority and interrupt ID number, as well as the use of the eithreshold register. Within a single interrupt file, interrupt priority is directly determined by the interrupt ID number. The smaller the ID number, the higher the corresponding interrupt priority. The eithreshold register is used to set the minimum interrupt priority (i.e., the maximum interrupt ID number) that can be sent from this interrupt file to the connected processing core. When eithreshold is set to a non-zero value P, interrupts with priority P and higher will not trigger interrupt signals, regardless of how the corresponding enable bits in the eie array are set; the effect is equivalent to these interrupts not being enabled. When eithreshold is zero, all enabled interrupt ID numbers can participate in reporting interrupt signals from this interrupt file. The principle of this invention can be extended to interrupt file configurations that support VS-mode.

[0040] Figure 3 To configure the number of interrupts for multiple privilege levels, the configuration register bitmap is provided. In this invention, the configuration register MS_CUT_CFG only requires 5 bits in hardware implementation. From the perspective of software users, writing to the other reserved bits of this configuration register is invalid, and reading is always 0.

[0041] Figure 4It is an interrupt arbitration circuit of multi-privilege-level configurable IMSIC and an interrupt arbitration logic diagram thereof. The interrupt files of machine and supervisor of IMSIC of the same hart share the ie array, the ip array and the interrupt arbitration circuit. The arbitration circuit selects the interrupt with the smallest sequence number from all bits set to "1" in ip[2047:0], and the sequence number is min_ID≠0. If: min_ID[10:6]≥MS_CUT and {Min_ID[10:6]–MS_CUT, Min_ID[5:0]}<s_eithreshold, a supervisor mode S-mode interrupt request is sent to the core, and the value of stopei is {Min_ID[10:6]–MS_CUT, Min_ID[5:0]}; if min_ID[10:6]<MS_CUT and Min_ID<s_eithreshold, a machine mode M-mode interrupt request is sent to the core, and the value of mtopei is min_ID.

[0042] Example: This example takes an IMSIC supporting M-mode and S-mode as an example, where the total size of the interrupt file supports 2047 interrupt IDs (i.e., 32 64-bit registers).

[0043] 1. Design of configuration register MS_CUT_CFG The MS_CUT_CFG register is located in the machine-level interrupt file, and is read and written through two control and status registers (CSR): the machine-level indirect access register miselect (CSR address 0x350) and mireg (CSR address 0x351). When miselect is set to 0x7f, the value read and written from mireg is the value of the MS_CUT_CFG register.

[0044] MS_CUT_CFG is a 5-bit wide field, which represents the size boundary of the M-mode interrupt file. Let the value of MS_CUT_CFG be ms_cut, then: The range of interrupt IDs supported by M-mode is from 1 to .

[0045] The range of interrupt IDs supported by S-mode is from 1 to .

[0046] For example, if ms_cut = 16, M-mode supports 1023 interrupt IDs (1-1023), and S-mode supports 1024 interrupt IDs (1-1024). The software can dynamically adjust the ms_cut value according to the load.

[0047] 2. Sharing and access remapping of interrupt files M-mode and S-mode share the physical interrupt enable (IE) array and interrupt pending (IP) array (total size of 2048 bits), and logical isolation is implemented through a remapping mechanism: Access by M-mode: directly access the low-order part of the shared array. For example, when the M-mode interrupt ID is i, its enable bit and pending bit are located at the i-th bit of the shared array.

[0048] Access by S-mode: mapped to the high-order part of the shared array through an offset. When the S-mode interrupt ID is sid, its actual global index is: For 32-bit systems: (because each 32-bit register manages 32 interrupts).

[0049] For 64-bit systems: index = sid + ms_cut (because each 64-bit register manages 64 interrupts).

[0050] Access process: When software accesses the S-mode interrupt file through the S-mode indirect registers siselect and sireg, the hardware automatically remaps the access to the offset position of the shared array.

[0051] When a device sends an S-mode MSI interrupt with an interrupt ID of sid, the hardware sets the position of the shared IP array to 1.

[0052] 3. Interrupt arbitration mechanism The interrupt arbitration circuit screens enabled and pending interrupts from the shared IP array, and selects the interrupt with the highest priority (smallest ID): The arbitration circuit traverses the shared IP array (2048 bits), finds all interrupts with the IP bit set to 1 and the corresponding IE bit set to 1, and calculates the minimum interrupt ID (recorded as min_ID).

[0053] Determine the ownership of the interrupt according to min_ID and the MS_CUT_CFG value: If min_ID[10:6]<ms_cut, the interrupt belongs to M-mode, set the machine-level topei register (mtopei) to min_ID, and send an M-mode external interrupt request to the hart.

[0054] If min_ID[10:6]>= ms_cut, then the interrupt belongs to S-mode. Set the supervisory level topei register (stopei) to {min_ID[10:6] - ms_cut, min_ID[5:0]} (i.e., remap back to the S-mode logical ID), and send an S-mode external interrupt request to hart.

[0055] The arbitration process adds only a small amount of comparison logic, and the increase in delay is negligible.

[0056] 4. Interruption of Claim and Deletion When an interrupt is claimed, hart reads the corresponding privilege level's topei register (such as stopei) to obtain the interrupt ID.

[0057] When clearing an interrupt, hart writes any value to the topoei register, and the hardware automatically clears the corresponding bit in the shared IP array. For M-mode interrupts, the min_ID bit of the shared IP array is cleared directly.

[0058] For S-mode interruptions, clear the min_ID bit of the shared IP array (i.e., ...). ).

[0059] 5. Hardware Implementation Advantages Area optimization: By sharing the IE / IP array and arbitration circuit, the total area of ​​IMSIC is reduced by approximately 40% compared to the static method.

[0060] Flexibility: The software can quickly adjust interrupt resource allocation through configuration registers to adapt to different application scenarios (such as bare-metal programs or operating systems).

[0061] Compatibility: Fully compliant with the RISC-V AIA specification, requiring no modification to the existing software stack.

[0062] Example effect: This embodiment was verified in FPGA prototyping and ASIC synthesis, showing a significant reduction in IMSIC hardware resource overhead. Interrupt reception or clearing adds only a five-bit adder latency, and updating the topoei register adds only a five-bit subtractor latency. This invention provides an efficient and scalable interrupt solution for RISC-V multi-core systems, particularly suitable for data center and edge computing scenarios.

[0063] The above embodiments are merely typical implementations of the present invention and are not intended to limit the scope of protection of the present invention. Any improvements and modifications based on the core spirit of the present invention should be included within the scope of the claims of the present invention.

[0064] This invention allows the number of interrupts with different privilege levels that the system can support to be configured through software during operation. By sharing the interrupt file (IE / IP array) and the interrupt arbitration circuit, it significantly reduces hardware overhead and improves the utilization of hardware resources. This enables a significant reduction in hardware overhead while meeting the same interrupt scale requirements, or allows the same hardware resources to support a larger scale of interrupt sources.

[0065] By introducing the configuration register MS_CUT_CFG, the interrupt file size for Machine Mode (M-mode) and Supervisor Mode (S-mode) can be allocated on demand. This invention reduces register stack area while maintaining AIA specification compatibility, providing an efficient solution for interrupt optimization in RISC-V multicore systems.

[0066] Any process or method described in the flowcharts of this invention or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more executable instructions for implementing a particular logical function or process, which can be implemented in any computer-readable medium for use by an instruction execution system, apparatus, or device. The computer-readable medium can be any medium containing a program for storage, communication, propagation, or transmission for use by the execution system, apparatus, or device, including read-only memory, magnetic disks, or optical disks.

[0067] In the description of this specification, the references to terms such as "embodiment," "example," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, those skilled in the art can combine or integrate different embodiments or examples and features described in this specification without creating contradiction. Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present invention.

Claims

1. A design method for a RISC-V AIA interrupt-configured multi-privilege level IMSIC controller, characterized in that, include: In IMSIC, a programmable configuration register MS_CUT_CFG is set to dynamically allocate interrupt file resources between machine mode (M-mode) and supervisor mode (S-mode) at runtime. By configuring the MS_CUT_CFG register, the allocation ratio of the actual physical storage space of interrupt files in machine mode (M-mode) and supervisor mode (S-mode) is controlled, thereby realizing the dynamic reuse of interrupt file resources. The interrupt enable register group (IE) and interrupt suspend register group (IP) of both Machine Mode (M-mode) and Supervisor Mode (S-mode) physically share the same set of hardware register arrays. Based on the dynamic space reuse mechanism of window switching, the machine mode (M-mode) and the supervisor mode (S-mode) are allowed to share the IE / IP interrupt large file group and interrupt arbitration logic circuit. This is achieved by designing hardware logic that remaps interrupt logic IDs to hardware IDs. The actual global index number of the enable / suspend bit of the S-mode interrupt with the identifier id is: index = id + ms_cut × 64. The interrupt files of the machine and supervisor modes of the same HART IMSIC share the IE array, IP array, and interrupt arbitration circuit. The interrupt arbitration circuit maps pending but achievable interrupt requests to the corresponding privilege level and submits them to the processor core based on the value of the current configuration register.

2. The design method for a RISC-V AIA interrupt-configured multi-privilege level IMSIC controller according to claim 1, characterized in that, The configuration register MS_CUT_CFG is 5 bits wide, located in the machine-level interrupt file, and is read and written through the indirect access mechanism defined in the AIA specification.

3. The design method for a RISC-V AIA interrupt-configured multi-privilege level IMSIC controller according to claim 1, characterized in that, The mapping relationship between the logical ID of the S-mode interrupt and its physical storage location is as follows: For a 32-bit register architecture, s_eie[i] maps to ; For a 64-bit register architecture, s_eie[i] is mapped to ie[i + ms_cut].

4. The design method for a RISC-V AIA interrupt-configured multi-privilege level IMSIC controller according to claim 1, characterized in that, The claiming operation of the S-mode interrupt in supervisor mode is implemented by writing to the stopei register, which actually clears the bit at the corresponding offset position in the shared interrupt suspend register group IP.

5. The design method for a RISC-V AIA interrupt-configured multi-privilege level IMSIC controller according to claim 1, characterized in that, The interrupt arbitration circuit selects the interrupt with the smallest ID from all pending and enabled interrupts, and determines whether the interrupt belongs to machine mode (M-mode) or supervisor mode (S-mode) based on the value of the configuration register MS_CUT_CFG.

6. The design method for a RISC-V AIA interrupt-configured multi-privilege level IMSIC controller according to claim 5, characterized in that, The output judgment logic of the interrupt arbitration circuit is as follows: If min_ID[10:6] ≥ MS_CUT, it is considered an S-mode interrupt, and the output stopei value is {min_ID[10:6] - MS_CUT, min_ID[5:0]}; If min_ID[10:6] < MS_CUT, it is considered an M-mode interrupt, and the output mtopei value is min_ID.

7. The design method for a RISC-V AIA interrupt-configured multi-privilege level IMSIC controller according to claim 1, characterized in that, The total size of the shared interrupt enable register group (IE) and interrupt suspend register group (IP) is 2048 bits, which are dynamically allocated to machine mode (M-mode) and supervisor mode (S-mode) through the configuration register MS_CUT_CFG.

8. The design method for a RISC-V AIA interrupt-configured multi-privilege level IMSIC controller according to claim 1, characterized in that, The method is applicable to each hardware thread in a multi-core processor that supports the RISC-V AIA specification.

9. The design method for a RISC-V AIA interrupt-configured multi-privilege level IMSIC controller according to claim 1, characterized in that, The configuration register MS_CUT_CFG is accessed indirectly through the CSR register in machine mode M-mode, and the address offset uses 0x7F reserved in the AIA specification.

10. The design method for a RISC-V AIA interrupt-configured multi-privilege level IMSIC controller according to claim 1, characterized in that, The method also supports VS-level interrupt files in virtualization extensions, and achieves dynamic allocation of M / S / VS three-level interrupt files through extended configuration registers.

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