Array substrate, display panel and display device

Abstract

This application discloses an array substrate, a display panel, and a display device. The pixel circuit includes a driving module, a light-emitting control module, a threshold compensation module, and a reset module: the driving module has a first terminal electrically connected to a first signal line, which provides a first power supply voltage and a data voltage in a time-division multiplexing manner; the light-emitting control module has a first terminal electrically connected to a second terminal of the driving module, a second terminal connected to a first electrode of a light-emitting element, a control terminal electrically connected to a light-emitting control signal line, and a second electrode of the light-emitting element electrically connected to a second signal line; the reset module has a first terminal electrically connected to a reset signal line, a second terminal electrically connected to a second terminal of the light-emitting control module, and a first control terminal electrically connected to a first scan line; the threshold compensation module has a first terminal electrically connected to a second terminal of the light-emitting control module, a second terminal electrically connected to the control terminal of the driving module, and a first control terminal electrically connected to a second scan line. Embodiments of this application can improve the performance of display products.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to an array substrate, a display panel, and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and flat panel displays based on light-emitting diodes (LEDs) are widely used in various consumer electronics products such as mobile phones, televisions, laptops, and desktop computers due to their advantages such as high image quality, energy saving, thin body and wide range of applications, becoming the mainstream of display devices.

[0003] However, the performance of current OLED display products needs to be improved. Summary of the Invention

[0004] This application provides an array substrate, a display panel, and a display device, which can improve the performance of display products.

[0005] In a first aspect, embodiments of this application provide an array substrate, including multiple rows of pixel circuits. The pixel circuits include a driving module, a light-emitting control module, a threshold compensation module, and a reset module: the driving module has a first terminal electrically connected to a first signal line, the first signal line providing a first power supply voltage and a data voltage in a time-division multiplexing manner; the light-emitting control module has a first terminal electrically connected to a second terminal of the driving module, its second terminal connected to a first electrode of a light-emitting element, its control terminal electrically connected to a light-emitting control signal line, and the second electrode of the light-emitting element electrically connected to a second signal line; the reset module has a first terminal electrically connected to a reset signal line, its second terminal electrically connected to a second terminal of the light-emitting control module, and its first control terminal electrically connected to a first scan line; the threshold compensation module has a first terminal electrically connected to a second terminal of the light-emitting control module, its second terminal electrically connected to the control terminal of the driving module, and its first control terminal electrically connected to a second scan line.

[0006] In some possible implementations of the first aspect, the driving module includes a first transistor, the threshold compensation module includes a second transistor, the light emission control module includes a third transistor, and the reset module includes a fourth transistor, wherein the first transistor and the third transistor are P-type transistors, and the second transistor and the fourth transistor are N-type transistors. Preferably, the pixel circuit further includes a storage capacitor, the first plate of which is electrically connected to the control terminal of the driving module, and the second plate of which is electrically connected to a fixed voltage terminal.

[0007] In some possible implementations of the first aspect, the second transistor includes a first gate and a second gate, the first gate of the second transistor being electrically connected to a second scan line, and the second gate of the second transistor being electrically connected to a reset signal line. Preferably, the fourth transistor includes a first gate and a second gate, the first gate of the fourth transistor is electrically connected to the first scan line, and the second gate of the fourth transistor is electrically connected to the reset signal line.

[0008] In some possible implementations of the first aspect, the operation of the pixel circuit includes a first reset phase, a data writing phase, and a light emission phase; During the first reset phase, the reset module and threshold compensation module are turned on, the light emission control module is turned off, and the first signal line provides the first power supply voltage. During the data writing phase, the threshold compensation module and the light emission control module are turned on, the reset module is turned off, and the first signal line provides the data voltage. During the light-emitting stage, the light-emitting control module is turned on, the threshold compensation module and the reset stage are turned off, the first signal line provides the first power supply voltage, and the driving module generates a driving current to drive the light-emitting element to emit light.

[0009] In some possible implementations of the first aspect, the operation of the pixel circuit also includes a second reset stage, in which the reset module is turned on and the threshold compensation module and the light emission control module are turned off. Preferably, during the first reset phase and the data writing phase, the second signal line provides a first voltage; during the light emission phase and the second reset phase, the second signal line provides a second voltage, and the first voltage is greater than the second voltage.

[0010] In some possible implementations of the first aspect, the signals on the first scan lines electrically connected to the pixel circuits of different rows are the same, and the pixel circuits of multiple rows perform the first reset phase at the same time. The pixel circuits in different rows write data voltages line by line.

[0011] In some possible implementations of the first aspect, the threshold compensation module includes a second transistor, the array substrate includes a substrate, the first gate of the second transistor is electrically connected to a second scan line, and the area of ​​the second gate of the second transistor is larger than the channel area of ​​the second transistor. Preferably, in the thickness direction of the array substrate, the second gate of the second transistor is located between the channel of the second transistor and the substrate, and the first gate of the second transistor is located on the side of the channel of the second transistor away from the substrate. Preferably, the orthographic projection of the second gate of the second transistor onto the substrate at least partially overlaps with the orthographic projection of the first gate of the second transistor onto the substrate; Preferably, the driving module includes a first transistor, the threshold compensation module includes a second transistor, the first plate of the storage capacitor is electrically connected to the gate of the first transistor, and the second plate of the storage capacitor is electrically connected to a fixed voltage terminal; the first electrode of the second transistor is electrically connected to the second electrode of the first transistor, and the second electrode of the second transistor is electrically connected to the gate of the first transistor through a first connecting portion, wherein in the thickness direction of the array substrate, the first connecting portion and the second plate of the storage capacitor at least partially overlap. Preferably, in the thickness direction of the array substrate, the first connection portion at least partially overlaps with the channel of the second transistor; Preferably, in the thickness direction of the array substrate, the first connection portion is located between the second electrode plate of the storage capacitor and the channel of the second transistor.

[0012] In some possible implementations of the second aspect, the array substrate includes a substrate and a first semiconductor layer, a first metal layer, a second metal layer, a third metal layer, a fourth metal layer, a second semiconductor layer, a fifth metal layer, a sixth metal layer, and a seventh metal layer, sequentially located away from the substrate. The driving module includes a first transistor, the threshold compensation module includes a second transistor, the light emission control module includes a third transistor, the reset module includes a fourth transistor, the first plate of the storage capacitor is electrically connected to the gate of the first transistor, and the second plate of the storage capacitor is electrically connected to the fixed voltage terminal. The active layers of the first transistor and the third transistor are located in the first semiconductor layer, and the gate of the first transistor and the light-emitting control signal line are located in the first metal layer. Preferably, the second electrode plate, the second connecting portion, and the third connecting portion of the storage capacitor are located in the second metal layer, the second connecting portion is connected between the first electrode of the first transistor and the first signal line, and the third connecting portion is connected between the second electrode of the third transistor and the first electrode of the light-emitting element. Preferably, the first connection portion is located in the third metal layer, and the first connection portion is connected between the gate of the first transistor and the second electrode of the second transistor; Preferably, the second gate of the second transistor and the second gate of the fourth transistor are located in the fourth metal layer, the active layer of the second transistor and the active layer of the fourth transistor are located in the second semiconductor layer, and the first gate of the second transistor and the first gate of the fourth transistor are located in the fifth metal layer. Preferably, the first signal line is located in the sixth metal layer; Preferably, the reset signal line is located in the seventh metal layer.

[0013] Secondly, embodiments of this application provide a display panel including an array substrate as described in any of the embodiments of the first aspect.

[0014] Thirdly, embodiments of this application provide a display device, including a display panel as described in the second aspect embodiment.

[0015] According to the array substrate, display panel, and display device provided in the embodiments of this application, the light-emitting control module is connected between the second end of the driving module and the light-emitting element. The first end of the driving module and the first signal line may not be connected to other functional modules. In this way, when the reset module and the threshold compensation module are turned on, and the reset voltage on the reset signal line resets the control end of the driving module, the first signal line can provide a first power supply voltage, so that the voltage difference between the control of the driving module and its first end is relatively large, which can more fully reset the control end of the driving module, thereby improving problems such as ghosting and trailing, and improving the brightness index of the first frame. In addition, the pixel circuit includes four functional modules. The number of functional modules is relatively small, so the pixel circuit occupies less space and can improve the pixel density of the display product.

[0016] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description

[0017] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings, in which the same or similar reference numerals denote the same or similar features, and the drawings are not drawn to scale.

[0018] Figure 1 This illustration shows a schematic diagram of a module structure of a pixel circuit provided in an embodiment of this application; Figure 2 This illustration shows a schematic diagram of a pixel circuit provided in an embodiment of this application; Figure 3 Show Figure 2 A timing diagram; Figure 4 This diagram illustrates a timing schematic of a multi-row pixel circuit provided in an embodiment of this application. Figure 5 Show Figure 4 A timing diagram; Figure 6 This illustration shows a top view of an array substrate provided in an embodiment of this application. Figure 7 This illustration shows a cross-sectional structural diagram of an array substrate provided in an embodiment of this application; Figure 8 This illustration shows a top view of the first semiconductor layer of an array substrate provided in an embodiment of this application. Figure 9 Show Figure 8A top view diagram of a structure with a first metal layer superimposed on top of the existing structure; Figure 10 Show Figure 9 A top view diagram of a structure with a second metal layer superimposed on top of the existing structure; Figure 11 Show Figure 9 A top view diagram of a structure with vias superimposed on top of the existing structure; Figure 12 This is a top view schematic diagram of a first metal layer and a third metal layer stacked in an array substrate provided in an embodiment of this application; Figure 13 Show Figure 11 A top view diagram of a structure with a third metal layer, a fourth metal layer, and vias superimposed on the basis of the above. Figure 14 This illustration shows a top view of a structure in which a second semiconductor layer and a fourth metal layer are stacked in an array substrate according to an embodiment of this application. Figure 15 Show Figure 14 A top view diagram of a structure with a fifth metal layer superimposed on top of the existing structure; Figure 16 Show Figure 13 A top view diagram of a structure in which a second semiconductor layer, a fifth metal layer, and a sixth metal layer are superimposed on the basis of the above. Figure 17 Show Figure 16 An enlarged schematic diagram of a local area in the middle; Figure 18 Show Figure 15 A top view diagram of a structure with a sixth and seventh metal layer superimposed on top of the existing structure; Figure 19 This illustration shows a top view of a structure in which the seventh metal layer and the anode layer are stacked in an array substrate according to an embodiment of this application. Figure 20 This diagram illustrates the layout structure of a pixel circuit according to an embodiment of this application. Figure 21 This is a schematic diagram of a display device provided in an embodiment of this application. Detailed Implementation

[0019] The features and exemplary embodiments of various aspects of this application will now be described in detail. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain this application and are not configured to limit this application. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples of this application.

[0020] Before describing the technical solutions provided in the embodiments of this application, in order to facilitate understanding of the embodiments of this application, this application first specifically explains the problems existing in the related technologies: As a carrier of information and a window for human-computer interaction in the digital age, displays have become an important interface for people to receive visual information, continuously influencing people's lives and the development of the economy and society. It is worth mentioning that with technological advancements and the ever-increasing demands for information interaction, commercial displays are integrating into life at an unprecedented pace. Examples include the integration of various forms of commercial display screens with their environments and the application of functions such as Virtual Reality (VR), Augmented Reality (AR), and holographic projection.

[0021] However, AR / VR display products have a high pixel density (PPI). At a high PPI, the layout space is relatively tight, and the size of the components in the pixel circuit and the parasitic capacitance in the display product are limited, which can easily cause problems such as image retention and ghosting.

[0022] To address the aforementioned technical problems, this application provides an array substrate, a display panel, and a display device. The embodiments of this application will be described below with reference to the accompanying drawings.

[0023] like Figure 1 As shown, the array substrate provided in this embodiment includes multiple rows of pixel circuits. The pixel circuit 10 includes a driving module 11, a threshold compensation module 12, a light emission control module 13, and a reset module 14. The pixel circuit 10 is electrically connected to the light-emitting element 20, which includes, but is not limited to, OLED, LED, and micro LED.

[0024] The first terminal of the driving module 11 is electrically connected to the first signal line L1, which provides the first power supply voltage Vdd and the data voltage Vdata in a time-division multiplexing manner. The driving module 11 is used to generate a driving current to drive the light-emitting element 20 to emit light.

[0025] The first terminal of the light-emitting control module 13 is electrically connected to the second terminal of the drive module 11, and the second terminal of the light-emitting control module 13 is connected to the first electrode of the light-emitting element 20. The control terminal of the light-emitting control module 13 is electrically connected to the light-emitting control signal line EM, and the second electrode of the light-emitting element 20 is electrically connected to the second signal line L2. The light-emitting control module 13 is used to control whether the light-emitting element 20 emits light. When the light-emitting control signal line EM provides a conduction level, the light-emitting control module 13 is turned on, and the drive module 11 and the light-emitting element 20 are connected. The drive current generated by the drive module 11 is transmitted to the first electrode of the light-emitting element 20. When the voltage difference between the first and second electrodes of the light-emitting element 20 is greater than or equal to its turn-on voltage, the light-emitting element 20 can emit light. When the light-emitting control signal line EM provides a cutoff level, the light-emitting control module 13 is turned off, and the light-emitting element 20 does not emit light.

[0026] The first terminal of the reset module 14 is electrically connected to the reset signal line Vref, the second terminal of the reset module 14 is electrically connected to the second terminal of the light-emitting control module 13, and the first control terminal of the reset module 14 is electrically connected to the first scan line S1. The reset module 14 is used to reset the control terminal of the drive module 11, and the reset module 14 can also be used to reset the first electrode of the light-emitting element 20.

[0027] The first terminal of the threshold compensation module 12 is electrically connected to the second terminal of the light emission control module 13, the second terminal of the threshold compensation module 12 is electrically connected to the control terminal of the drive module 11, and the first control terminal of the threshold compensation module 12 is electrically connected to the second scan line S2. The threshold compensation module 12 is used to compensate for the threshold voltage of the drive module 11.

[0028] When the first scan line S1 provides a conduction level and the second scan line S2 provides a conduction level, the reset module 14 and the threshold compensation module 12 are turned on. The reset voltage on the reset signal line Vref can be written to the control terminal of the drive module 11. Since there are no other modules connected between the first terminal of the drive module 11 and the first signal line L1, the first signal line L1 can provide the first power supply voltage Vdd at this time, so that the voltage difference between the control of the drive module 11 and its first terminal is relatively large, which can more fully reset the control terminal of the drive module 11, thereby improving problems such as ghosting and trailing, and improving the brightness index of the first frame.

[0029] According to the array substrate provided in the embodiments of this application, the light-emitting control module 13 is connected between the second end of the driving module 11 and the light-emitting element 20. The first end of the driving module 11 and the first signal line L1 may not be connected to other functional modules. In this way, when the reset module 14 and the threshold compensation module 12 are turned on, and the reset voltage on the reset signal line Vref resets the control end of the driving module 11, the first signal line L1 can provide the first power supply voltage Vdd, so that the voltage difference between the control of the driving module 11 and its first end is relatively large, which can more fully reset the control end of the driving module 11, thereby improving problems such as ghosting and trailing, and improving the brightness index of the first frame. In addition, the pixel circuit 10 includes four functional modules. The number of functional modules is relatively small, so the pixel circuit occupies less space and can improve the pixel density of the display product.

[0030] In some embodiments, such as Figure 2 As shown, the driving module 11 includes a first transistor T1, the threshold compensation module 12 includes a second transistor T2, the light emission control module 13 includes a third transistor T3, and the reset module 14 includes a fourth transistor T4. The first terminal of the first transistor T1 is electrically connected to the first signal line L1; the first terminal of the third transistor T3 is electrically connected to the second terminal of the first transistor T1; the second terminal of the third transistor T3 is electrically connected to the first terminal of the light emission element 20; and the gate of the third transistor T3 is electrically connected to the light emission control signal line EM. The first terminal of the second transistor T2 is electrically connected to the second terminal of the third transistor T3; the second terminal of the second transistor T2 is electrically connected to the gate of the first transistor T1; and the first gate of the second transistor T2 is electrically connected to the second scan line S2. The first terminal of the fourth transistor T4 is electrically connected to the reset signal line Vref; the second terminal of the fourth transistor T4 is electrically connected to the second terminal of the third transistor T3; and the first gate of the fourth transistor T4 is electrically connected to the first scan line S1.

[0031] The first transistor T1 and the third transistor T3 can be P-type transistors, while the second transistor T2 and the fourth transistor T4 can be N-type transistors. P-type transistors have relatively high carrier mobility, therefore, the first transistor T1 and the third transistor T3 are chosen as P-type transistors to improve the driving capability of the pixel circuit for the light-emitting element. N-type transistors have relatively low leakage current, therefore, the second transistor T2 is chosen as an N-type transistor. The first transistor T1 has a low gate leakage current, which improves the gate potential stability of the first transistor T1, thereby improving the brightness stability of the light-emitting element. The fourth transistor T4 is chosen as an N-type transistor, resulting in a lower leakage current at the first electrode of the light-emitting element 20 during the light-emitting stage, which also improves the brightness stability of the light-emitting element.

[0032] For example, the active layer material of a P-type transistor may include low-temperature polysilicon (LTPS), and the active layer material of an N-type transistor may include indium gallium zinc oxide (IGZO).

[0033] In some embodiments, such as Figure 2 As shown, the pixel circuit 10 also includes a storage capacitor Cst. The first plate of the storage capacitor Cst is electrically connected to the control terminal of the driving module 11, and the second plate of the storage capacitor Cst is electrically connected to a fixed voltage terminal. The storage capacitor Cst is used to store the data voltage written to the control terminal of the driving module 11 to stabilize the control terminal potential of the driving module 11. The gate of the first transistor T1 is the control terminal of the driving module 11.

[0034] For example, the fixed voltage terminal connected to the second plate of the storage capacitor Cst can provide a first power supply voltage Vdd, which can be a positive voltage.

[0035] Understandably, the larger the capacitance value of the storage capacitor Cst, the more stable the control terminal potential of the drive module 11 will be.

[0036] In some embodiments, such as Figure 2 As shown, the second transistor T2 includes a first gate and a second gate. The first gate of the second transistor T2 is electrically connected to the second scan line S2, and the second gate of the second transistor T2 is electrically connected to the reset signal line Vref. The reset voltage of the reset signal line Vref is a negative voltage.

[0037] For example, if the second transistor T2 is an N-type transistor, and the second gate of the second transistor T2 is connected to the first power supply voltage Vdd, the threshold voltage of the second transistor T2 will drift negatively (i.e., the threshold voltage of the second transistor T2 will be biased towards the negative) because the first power supply voltage Vdd is a relatively high voltage. Its first gate will then need to be connected to a more negative low voltage (e.g., a low voltage VGL of about -20V) to better turn off the second transistor T2. Otherwise, the second transistor T2 is prone to leakage when it is turned off. However, if a more negative low voltage is provided to the first gate of the second transistor T2 to turn off the second transistor T2, the power consumption required will be higher.

[0038] In this embodiment, the second gate of the second transistor T2 is electrically connected to the reset signal line Vref, that is, the second gate of the second transistor T2 is connected to a negative voltage, which can solve the problem that the threshold voltage of the second transistor T2 is biased to a negative value due to the second gate being connected to a positive voltage, thereby improving the leakage current problem of the second transistor T2 in the off state; and when the second transistor T2 is turned off, it is not necessary to provide a more negative low voltage to its first gate, which can reduce power consumption.

[0039] In some embodiments, such as Figure 2 As shown, the fourth transistor T4 includes a first gate and a second gate. The first gate of the fourth transistor T4 is electrically connected to the first scan line S1, and the second gate of the fourth transistor T4 is electrically connected to the reset signal line Vref.

[0040] When light shines on the channel semiconductor layer of a transistor, it excites electron-hole pairs, forming an additional photocurrent. This leads to a significant increase in the off-state leakage current of the transistor. The increased leakage current can cause threshold voltage drift and also cause problems such as screen flicker, crosstalk, and low screen retention.

[0041] For example, the second gate of the second transistor T2 can be used to shield the channel of the second transistor T2, and the second gate of the fourth transistor T4 can be used to shield the channel of the fourth transistor T4, thereby blocking ambient light from entering, reducing photogenerated leakage current, and improving the stability of the second transistor T2 and the fourth transistor T4.

[0042] In some embodiments, please refer to the reference Figure 2 and Figure 3 The operation of the pixel circuit 10 includes a first reset stage R1, a data writing stage W, and a light emission stage E; wherein, During the first reset phase R1, the reset module 14 and the threshold compensation module 12 are turned on, the light emission control module 13 is turned off, and the first signal line L1 provides the first power supply voltage Vdd.

[0043] During the data writing phase W, the threshold compensation module 12 and the light emission control module 13 are turned on, the reset module 14 is turned off, and the first signal line L1 provides the data voltage Vdata. During the light-emitting stage E, the light-emitting control module 13 is turned on, the threshold compensation module 12 and the reset module 14 are turned off, the first signal line L1 provides the first power supply voltage Vdd, and the driving module 11 generates a driving current to drive the light-emitting element 20 to emit light.

[0044] For example, the first transistor T1 and the third transistor T3 are P-type transistors, and the second transistor T2 and the fourth transistor T4 are N-type transistors. For a P-type transistor, its on-level is low and its off-level is high; for an N-type transistor, its on-level is high and its off-level is low.

[0045] Specifically, in the first reset phase R1, the first scan line S1 and the second scan line S2 are provided with a high level, the light emission control signal line EM is provided with a high level, the first signal line L1 provides the first power supply voltage Vdd, the second transistor T2 and the fourth transistor T4 are turned on, the third transistor T3 is turned off, and the reset signal on the reset signal line Vref is written to the gate of the first transistor T1 to reset the gate of the first transistor T1. At this time, the first terminal of the first transistor T1 is connected to the first power supply voltage Vdd, making the gate-source voltage difference of the first transistor T1 relatively large, which can more fully reset the gate potential of the first transistor T1, thereby improving problems such as ghosting and trailing, and improving the brightness index of the first frame.

[0046] During the data writing phase W, the first scan line S1 provides a low level, the second scan line S2 provides a high level, the light emission control signal line EM provides a low level, the first signal line L1 provides the data voltage Vdata, the first transistor T1, the second transistor T2, and the third transistor T3 are turned on, the fourth transistor T4 is turned off, the gate potential of the first transistor T1 gradually increases until the gate potential of the first transistor T1 equals Vdata + Vth, the first transistor T1 is turned off, the data voltage writing ends, and the information of the threshold voltage Vth of the first transistor T1 is stored in the storage capacitor Cst, thus completing the threshold voltage compensation.

[0047] During the light-emitting phase E, the first scan line S1 and the second scan line S2 provide a low level, the light-emitting control signal line EM provides a low level, the first signal line L1 provides the first power supply voltage Vdd, the third transistor T3 is turned on, the second transistor T2 and the fourth transistor T4 are turned off, the first transistor T1 generates a drive current, and the light-emitting element 20 emits light. At this time, the gate-source voltage of the first transistor Vgs = Vg - Vs = Vdata + Vth - Vdd, and the drive current is approximately I = K*(Vdd - Vdata). 2 K is a constant, and K is related to the channel width-to-length ratio of the first transistor T1.

[0048] In some embodiments, please refer to Figure 2 and Figure 3 The operation of the pixel circuit also includes a second reset stage R2, which can be between the data writing stage W and the light emission stage E. During the second reset stage R2, the reset module 14 is turned on, and the threshold compensation module 12 and the light emission control module 13 are turned off.

[0049] Specifically, in the second reset phase R2, the first scan line S1 provides a high level, the second scan line S2 provides a low level, the light emission control signal line EM provides a high level, the fourth transistor T4 is turned on, the second transistor T2 and the third transistor T3 are turned off, and the reset voltage on the reset signal line Vref is written to the first electrode of the light emission element 20 to reset the first electrode of the light emission element 20, which can further improve the image retention problem.

[0050] In some embodiments, such as Figure 3 As shown, during the first reset phase R1 and the data writing phase W, the second signal line L2 provides a first voltage V1; during the light emission phase E and the second reset phase R2, the second signal line L2 provides a second voltage V2, and the first voltage V1 is greater than the second voltage V2. For example, the first voltage V1 is a positive voltage, and the second voltage V2 is a negative voltage.

[0051] For example, in the first reset phase R1 and the second reset phase R2, the reset signal of the reset signal line Vref is written to the first pole of the light-emitting element 20. The difference between the voltage of the reset signal and the first voltage V1 is less than the turn-on voltage of the light-emitting element, so as to prevent the light-emitting element 20 from emitting light in the first reset phase R1.

[0052] During the data writing phase W, the data voltage Vdata is transmitted to the first electrode of the light-emitting element 20 through the first transistor T1 and the third transistor T3. The difference between the data voltage Vdata and the first voltage V1 is less than the turn-on voltage of the light-emitting element, thus preventing the light-emitting element 20 from emitting light during the data writing phase W.

[0053] During the light-emitting stage E, the driving current generated by the first transistor T1 flows into the first electrode of the light-emitting element 20 through the third transistor T3. At this time, the second signal line L2 provides a low voltage (second voltage V2), which enables the light-emitting element 20 to emit light.

[0054] For example, the first signal line L1 provides a data voltage Vdata during the data writing phase W, and the first signal line L1 provides a first power supply voltage Vdd during the first reset phase R1, the second reset phase R2, and the light emission phase E.

[0055] For example, such as Figure 4 As shown, the first signal line L1 can be electrically connected to the first pin 1 of the driver chip via the fifth transistor T5, and the first pin 1 provides the data voltage Vdata; the first signal line L1 can also be electrically connected to the second pin 2 of the driver chip via the sixth transistor T6, and the second pin 2 provides the first power supply voltage Vdd. The gate of the fifth transistor T5 is connected to the first control signal SW1, and the gate of the sixth transistor T6 is connected to the second control signal SW2. Please refer to the reference. Figure 4 and Figure 5During the first reset phase R1, the second reset phase R2, and the light emission phase E, the first control signal SW1 is at a cutoff level (e.g., high level), the second control signal SW2 is at a conduction level (e.g., low level), and the first power supply voltage Vdd is written to the first signal line L1. During the data writing phase W, the first control signal SW1 is at a conduction level (e.g., low level), the second control signal SW2 is at a cutoff level (e.g., high level), and the data voltage Vdata is written to the first signal line L1.

[0056] Of course, in other embodiments, the data voltage Vdata and the first power supply voltage Vdd can be provided to the first signal line L1 in a time-division manner by the same pin of the driver chip.

[0057] In some embodiments, such as Figure 6 As shown, multiple pixel circuits in the array substrate 100 are arranged in an array along the intersecting first direction X and second direction Y. For example, the first direction X is the row direction and the second direction Y is the column direction. Please refer to the reference. Figure 5 and Figure 6 The signals on the first scan lines S1 electrically connected to the pixel circuits 10 in different rows are the same. For example, the first scan lines S1 electrically connected to the pixel circuits 10 in different rows are all electrically connected to the third pin 3 of the driver chip IC. The first scan line S1 provides the first scan signal, which is a global signal, meaning that the pixel circuits 10 in different rows simultaneously execute the first reset stage R1 and the second reset stage R2. When the first scan signal is a global signal, there is no need to set up a gate driving circuit to provide the first scan signal, which can reduce the number of gate driving circuits required and is beneficial for narrow bezels of the display panel.

[0058] In some embodiments, data voltages are written to the pixel circuits in different rows one by one. For example, the display panel includes n rows of pixel circuits 10. Figure 5 In the diagram, S2-row1 represents the second scan line electrically connected to the first row of pixel circuits, EM-row1 represents the light emission control signal line electrically connected to the first row of pixel circuits, S2-rown represents the second scan line electrically connected to the nth row of pixel circuits, and EM-rown represents the light emission control signal line electrically connected to the nth row of pixel circuits. During the scanning phase WC, the second scan lines S2-row1 to S2-rown, electrically connected to the first row of pixel circuits, are successively turned on (e.g., high level), and the light emission control signal lines EM-row1 to EM-rown, electrically connected to the first row of pixel circuits, are successively turned on (e.g., low level). Thus, during the scanning phase WC, the first row of pixel circuits to the nth row of pixel circuits execute the writing phase W line by line, and the first row of pixel circuits to the nth row of pixel circuits write the data voltage Vdata line by line.

[0059] For example, the display panel includes a first gate driving circuit GIP1 and a second gate driving circuit GIP2. The first gate driving circuit GIP1 is electrically connected to the second scan line S2, and the second gate driving circuit GIP2 is electrically connected to the light emission control signal line EM.

[0060] For example, multiple pixel circuits 10 in the same column can be electrically connected to the same first signal line L1, and multiple pixel circuits 10 in different columns can be electrically connected to different first signal lines L1.

[0061] In some embodiments, please refer to the reference Figure 2 and Figure 7 ,as well as Figures 8 to 20 The layout shown includes a threshold compensation module 12 with a second transistor T2 and a reset module 14 with a fourth transistor T4. The second transistor T2 and the fourth transistor T4 are N-type transistors. The array substrate includes a substrate 01, the first gate g21 of the second transistor T2 is electrically connected to the second scan line S2, and the area of ​​the second gate g22 of the second transistor T2 is larger than the area of ​​the channel b2 of the second transistor T2.

[0062] In the thickness direction Z of the array substrate, the second gate g22 of the second transistor T2 is located between the substrate 01 and the channel b2 of the second transistor T2, and the first gate g21 of the second transistor T2 is located on the side of the channel b2 of the second transistor T2 away from the substrate 01.

[0063] The orthographic projection of the second gate g22 of the second transistor T2 onto the substrate O1 at least partially overlaps with the orthographic projection of the first gate g21 of the second transistor T2 onto the substrate O1. In the thickness direction Z of the array substrate, the area where the active layer of the second transistor T2 overlaps with the first gate g21 is the channel b2 of the second transistor T2. In the thickness direction Z, the second gate g22 at least partially overlaps with the first gate g21, meaning the second gate g22 at least partially overlaps with the channel b2 of the second transistor T2. In this way, the second gate g22 can shield the channel b2 of the second transistor T2 from light, thereby improving the stability of the second transistor T2.

[0064] For example, the orthogonal projection of the second gate g22 of the second transistor T2 on the substrate 01 covers the orthogonal projection of the first gate g21 of the second transistor T2 on the substrate 01; that is, the orthogonal projection of the second gate g22 of the second transistor T2 on the substrate 01 covers the orthogonal projection of the channel b2 of the second transistor T2 on the substrate 01, so that the channel b2 of the second transistor T2 can be better shielded from light.

[0065] In some embodiments, the first gate g41 of the fourth transistor T4 is electrically connected to the first scan line S1, and the orthographic projection of the second gate g42 of the fourth transistor T4 on the substrate O1 at least partially overlaps with the orthographic projection of the first gate g41 of the fourth transistor T4 on the substrate O1. In the thickness direction Z of the array substrate, the area where the active layer of the fourth transistor T4 overlaps with the first gate g41 is the channel b4 of the fourth transistor T4. In the thickness direction Z, the second gate g42 at least partially overlaps with the first gate g41, that is, the second gate g42 at least partially overlaps with the channel b4 of the fourth transistor T4. In this way, the second gate g42 can block light from the channel b4 of the fourth transistor T4 to improve the stability of the fourth transistor T4.

[0066] For example, the orthogonal projection of the second gate g42 of the fourth transistor T4 onto the substrate 01 covers the orthogonal projection of the first gate g41 of the fourth transistor T4 onto the substrate 01; that is, the orthogonal projection of the second gate g42 of the fourth transistor T4 onto the substrate 01 covers the orthogonal projection of the channel b4 of the fourth transistor T4 onto the substrate 01, thus enabling better light shielding of the channel b4 of the fourth transistor T4.

[0067] For example, in the thickness direction Z of the array substrate, the second gate g22 of the second transistor T2 is located between the substrate O1 and the first gate g21 of the second transistor T2, and the second gate g42 of the fourth transistor T4 is located between the substrate O1 and the first gate g41 of the fourth transistor T4. For instance, the second gate g22 of the second transistor T2 and the second gate g42 of the fourth transistor T4 are located in one of the metal layers, and the first gate g21 of the second transistor T2 and the first gate g41 of the fourth transistor T4 are located in another metal layer.

[0068] For example, the second gate g42 of the fourth transistor T4 is electrically connected to the reset signal line Vref through the eighth via h8.

[0069] Please refer to the reference. Figure 2 and Figure 7 ,as well as Figure 8 value Figure 20The layout shown includes a driving module 11 comprising a first transistor T1, a threshold compensation module 12 comprising a second transistor T2, a first plate of a storage capacitor Cst electrically connected to the gate of the first transistor T1, and a second plate of the storage capacitor Cst electrically connected to a fixed voltage terminal; a first terminal of the second transistor T2 electrically connected to the second terminal of the first transistor T1, and a second terminal of the second transistor T2 electrically connected to the gate g1 of the first transistor T1 via a first connection portion 31; in the thickness direction Z of the array substrate, the first connection portion 31 at least partially overlaps with the second plate c12 of the storage capacitor. The potential of the first connection portion 31 is the same as the potential of the gate g1 of the first transistor T1, and the at least partial overlap of the first connection portion 31 with the second plate c12 is equivalent to increasing the capacitance value of the storage capacitor Cst, thereby improving the gate potential stability of the first transistor T1.

[0070] Specifically, the second terminal of the second transistor T2 can be electrically connected to the first connection portion 31 through the ninth via h9, and the first connection portion 31 can be electrically connected to the gate g1 of the first transistor T1 through the third via h3.

[0071] For example, in the thickness direction Z of the array substrate, the first connection portion 31 at least partially overlaps with the channel b2 of the second transistor T2; in this way, the first connection portion 31 can shield the channel b2 of the second transistor T2 from light, thereby improving the stability of the second transistor T2.

[0072] For example, in the thickness direction Z of the array substrate, the first connection portion 31 is located between the second electrode plate c12 of the storage capacitor and the channel b2 of the second transistor T2.

[0073] In some embodiments, please refer to the reference Figure 2 and Figure 7 The array substrate includes a substrate 01 and a first semiconductor layer P-SI, a first metal layer M1, a second metal layer M2, a third metal layer M3, a fourth metal layer M4, a second semiconductor layer IGZO, a fifth metal layer M5, a sixth metal layer M6 and a seventh metal layer M7, which are sequentially located away from the substrate 01. The driving module 11 includes a first transistor T1, the threshold compensation module 12 includes a second transistor T2, the light emission control module 13 includes a third transistor T3, the reset module 14 includes a fourth transistor T4, the first plate of the storage capacitor Cst is electrically connected to the gate of the first transistor T1, and the second plate of the storage capacitor Cst is electrically connected to the fixed voltage terminal.

[0074] The active layers of the first transistor T1 and the third transistor T3 are located on the first semiconductor layer P-SI, and the gate g1 of the first transistor T1 and the light-emitting control signal line EM are located on the first metal layer M1. The gate g1 of the first transistor T1 is multiplexed as the first plate c11 of the storage capacitor Cst.

[0075] The second electrode plate c12, the second connection part 51, and the third connection part 52 of the storage capacitor Cst are located in the second metal layer M2. The second connection part 51 is connected between the first electrode of the first transistor T1 and the first signal line L1, and the third connection part 52 is connected between the second electrode of the third transistor T3 and the first electrode RE of the light-emitting element.

[0076] For example, the second connection portion 51 is electrically connected to the first electrode of the first transistor T1 through the first via h1, and the second connection portion 51 is electrically connected to the first signal line L1 through the fifth via h5. This example is equivalent to splitting the deep via between the first signal line L1 and the first electrode of the first transistor T1 into two shallow vias to reduce the problems of signal crosstalk and PPI limitation caused by excessively deep vias.

[0077] The second terminal of the third transistor T3 is electrically connected to the third connection portion 52 through the second via h2. The third connection portion 52 is electrically connected to the first terminal of the second transistor T2 and the second terminal of the fourth transistor T4 through the fourth via h4. The first terminals of the second transistor T2 and the second terminals of the fourth transistor T4 are electrically connected to the fourth connection portion 71 through the seventh via h7. The fourth connection portion 71 is electrically connected to the first terminal RE of the light-emitting element through the anode via. This example is equivalent to splitting the deep via between the first terminal RE of the light-emitting element and the second terminal of the third transistor T3 into multiple shallow vias to reduce the problems of signal crosstalk and PPI limitation caused by excessively deep vias.

[0078] For example, the first connection portion 31 is located in the third metal layer M3, and the first connection portion 31 is connected between the gate of the first transistor T1 and the second electrode of the second transistor T2. For example, the first connection portion 31 is electrically connected to the gate g1 of the first transistor T1 through the third via h3, and the first connection portion 31 is electrically connected to the second electrode of the second transistor T2 through the ninth via h9.

[0079] The second gate g22 of the second transistor T2 and the second gate g42 of the fourth transistor T4 are located in the fourth metal layer M4. The active layer of the second transistor T2 and the active layer of the fourth transistor T4 are located in the second semiconductor layer IGZO. The first gate g21 of the second transistor T2 and the first gate g41 of the fourth transistor T4 are located in the fifth metal layer M5.

[0080] The first signal line L1 is located in the sixth metal layer M6; The reset signal line Vref is located in the seventh metal layer M7. The fourth connection part 71 is located in the seventh metal layer M7.

[0081] In the example above, a seven-layer metal structure is used, and both the N-type second transistor T2 and the fourth transistor T4 are light-shielded, which improves the stability of the transistors. Furthermore, the second transistor T2 and the third transistor T3 at least partially overlap in the thickness direction Z, which reduces the area occupied by the pixel circuit and improves the PPI.

[0082] The following is for reference. Figures 8 to 20 The layout structure of each film layer of the array substrate is illustrated by way of example. Figures 8 to 20 The diagram shows the layout of the area where a pixel circuit is located.

[0083] like Figure 8 As shown, the first semiconductor layer P-SI includes an active layer of a first transistor and an active layer of a third transistor. The active layer of the first transistor includes a channel b1, with the first and second terminals of the first transistor being the first and second electrodes, respectively. The active layer of the third transistor includes a channel b3, with the first and second terminals of the third transistor being the first and second electrodes, respectively. Exemplarily, the active layers of the first and third transistors can be integrally formed. The active layers of the first and third transistors can generally be arranged in a "Z" shape. The channel b1 of the first transistor extends along a second direction Y, and the channel b3 of the third transistor extends along the second direction Y. In the second direction Y, the length of the channel b1 of the first transistor is greater than the length of the channel b3 of the third transistor.

[0084] like Figure 9 As shown, the first metal layer M1 includes the gate g1 of the first transistor T1 and the gate g3 of the third transistor T3. The gate g1 of the first transistor T1 is reset to the first plate c11 of the storage capacitor, and the gate g3 of the third transistor T3 is multiplexed with the light-emitting control signal line EM. For example, the length of the channel b1 of the first transistor T1 in the second direction Y is greater than the width of the channel b1 in the first direction X. The gate g1 of the first transistor T1 includes a first half g11 and a second half g12 adjacent in the first direction X. The first half g11 at least partially overlaps with the channel b1, and the second half g12 does not overlap with the channel b1. Please refer to the reference. Figure 9 and Figure 16 The center of the gate g1 of the first transistor T1 is offset relative to the channel b1, which can reduce the overlap between the gate g1 and the first signal line L1.

[0085] like Figure 10As shown, the second metal layer M2 includes a second electrode plate c12 for a storage capacitor, a second connection portion 51, and a third connection portion 52. The second connection portion 51 is connected between the first electrode of the first transistor T1 and the first signal line L1, and the third connection portion 52 is connected between the second electrode of the third transistor T3 and the first electrode RE of the light-emitting element. For example, the width of the second electrode plate c12 in the first direction X is greater than its length in the second direction Y.

[0086] like Figure 11 As shown, the second connection part 51 is electrically connected to the first electrode of the first transistor T1 through the first via h1, and the second electrode of the third transistor T3 is electrically connected to the third connection part 52 through the second via h2.

[0087] like Figure 12 As shown, the third metal layer M3 includes a first connection portion 31, which is electrically connected to the gate g1 of the first transistor T1 through a third via h3. The projected area of ​​the first connection portion 31 on the substrate is smaller than the projected area of ​​the gate g1 on the substrate. Please refer to the reference. Figure 12 and Figure 13 The first connecting portion 31 and the second gate g22 at least partially overlap. In the second direction Y, the end of the first connecting portion 31 away from the third transistor T3 may be recessed, and the first connecting portion 31 and the second connecting portion 51 may not overlap.

[0088] like Figure 13 As shown, the fourth metal layer M4 includes a second gate g22 of the second transistor and a second gate g42 of the fourth transistor. Exemplarily, the orthogonal projection shape of the second gate g22 onto the substrate is approximately "U" shaped.

[0089] like Figure 14 As shown, the second semiconductor layer IGZO includes the active layer of a second transistor and also includes the active layer of a fourth transistor. The active layer of the second transistor includes a channel b2, with the two ends of channel b2 being the first and second terminals of the second transistor, respectively. The active layer of the fourth transistor includes a channel b4, with the two ends of b4 being the first and second terminals of the fourth transistor, respectively. The width of the active layer in different regions within the second semiconductor layer IGZO may vary in the idyllic direction X. Please refer to the reference. Figure 14 and Figure 16 The extension direction of the active layer in the second semiconductor layer IGZO is consistent with the extension direction of the active layer in the first semiconductor layer P-SI, and the active layer of the second semiconductor layer IGZO and the active layer of the first semiconductor layer P-SI overlap at least partially.

[0090] like Figure 15As shown, the fifth metal layer M5 includes the first gate g21 of the second transistor T2 and the first gate g41 of the fourth transistor T4. The first gate g21 of the second transistor T2 is multiplexed with the second scan line S2, and the first gate g41 of the fourth transistor T4 is multiplexed with the first scan line S1. The extension direction of the scan lines in the fifth metal layer M5 intersects with the extension direction of the active layer in the second semiconductor layer IGZO.

[0091] like Figure 16 and Figure 17 As shown, the sixth metal layer M6 includes a first signal line L1, which is electrically connected to the second connection portion 51 through a fifth via h5. The first signal line L1 extends along the second direction Y.

[0092] like Figure 18 As shown, the seventh metal layer M7 includes a reset signal line Vref, which is electrically connected to the first electrode of the fourth transistor T4 through a sixth via h6. The seventh metal layer M7 also includes a fourth connection portion 71, which is electrically connected to the second electrode of the fourth transistor T4 and the first electrode of the second transistor T2 through a seventh via h7. The reset signal line Vref extends along a first direction X. At least a portion of the first signal line L1 may be located within the seventh metal layer M7. First signal lines L1 from different film layers can be connected through vias to form a grid-like structure of first signal lines L1.

[0093] like Figure 19 As shown, the first electrode RE of the light-emitting element is electrically connected to the fourth connection part 71 through the tenth via h10 (anode via).

[0094] like Figure 20 The diagram shows the layout of the pixel circuit, which is composed of the stacked structure of each film layer.

[0095] like Figure 20 As shown, the four transistors (TFT1~TFT4) of the pixel circuit are arranged sequentially along the second direction Y on the substrate by their orthogonal projections, which can save the layout area and help improve the pixel density.

[0096] Based on the same technical concept, embodiments of this application also provide a display panel, which includes an array substrate as described in any of the above embodiments.

[0097] The display panel provided in this application embodiment has the beneficial effects of the array substrate provided in this application embodiment. For details, please refer to the specific description of the array substrate in the above embodiments. This embodiment will not repeat the description here.

[0098] This application also provides a display device, such as... Figure 21 As shown, the display device 1000 includes the display panel described in any of the above embodiments.

[0099] Figure 21 This embodiment uses a wearable product as an example to illustrate the display device 1000. It is understood that the display device provided in this application embodiment can be other display devices with display functions, such as mobile phones, computers, televisions, and in-vehicle display devices; this application does not impose specific limitations on these. The display device provided in this application embodiment has the beneficial effects of the display panel provided in this application embodiment. For details, please refer to the specific descriptions of the display panel in the above embodiments; these will not be repeated here.

[0100] The embodiments described above are not exhaustive, nor do they limit the application to the specific embodiments described herein. Clearly, many modifications and variations can be made based on the above description. These embodiments are selected and specifically described in this specification to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to effectively utilize this application and its modifications. This application is limited only by the claims and their full scope and equivalents.

Claims

1. An array substrate, characterized in that, The pixel circuit includes multiple rows of the aforementioned pixel circuitry, which comprises a driving module, an emissivity control module, a threshold compensation module, and a reset module. The driving module has a first terminal electrically connected to a first signal line, and the first signal line provides a first power supply voltage and a data voltage in a time-division manner. The light-emitting control module has a first end electrically connected to the second end of the driving module, a second end connected to the first electrode of the light-emitting element, a control end electrically connected to the light-emitting control signal line, and the second electrode of the light-emitting element electrically connected to the second signal line. The reset module has a first terminal electrically connected to the reset signal line, a second terminal electrically connected to the second terminal of the light emission control module, and a first control terminal electrically connected to the first scan line. The threshold compensation module has its first end electrically connected to the second end of the light emission control module, its second end electrically connected to the control end of the driving module, and its first control end electrically connected to the second scan line.

2. The array substrate according to claim 1, characterized in that, The driving module includes a first transistor, the threshold compensation module includes a second transistor, the light emission control module includes a third transistor, and the reset module includes a fourth transistor. The first transistor and the third transistor are P-type transistors, and the second transistor and the fourth transistor are N-type transistors. The pixel circuit also includes a storage capacitor, the first plate of which is electrically connected to the control terminal of the driving module, and the second plate of which is electrically connected to a fixed voltage terminal.

3. The array substrate according to claim 2, characterized in that, The second transistor includes a first gate and a second gate, the first gate of the second transistor is electrically connected to the second scan line, and the second gate of the second transistor is electrically connected to the reset signal line; Preferably, the fourth transistor includes a first gate and a second gate, the first gate of the fourth transistor is electrically connected to the first scan line, and the second gate of the fourth transistor is electrically connected to the reset signal line.

4. The array substrate according to any one of claims 1-3, characterized in that, The operation of the pixel circuit includes a first reset stage, a data writing stage, and a light emission stage. During the first reset phase, the reset module and the threshold compensation module are turned on, the light emission control module is turned off, and the first signal line provides a first power supply voltage. During the data writing phase, the threshold compensation module and the light emission control module are turned on, the reset module is turned off, and the first signal line provides the data voltage. During the light-emitting phase, the light-emitting control module is turned on, the threshold compensation module and the reset phase are turned off, the first signal line provides a first power supply voltage, and the driving module generates a driving current to drive the light-emitting element to emit light.

5. The array substrate according to claim 4, characterized in that, The operation of the pixel circuit also includes a second reset stage, in which the reset module is turned on and the threshold compensation module and the light emission control module are turned off. During the first reset phase and the data write phase, the second signal line provides a first voltage; During the light-emitting phase and the second reset phase, the second signal line provides a second voltage, and the first voltage is greater than the second voltage.

6. The array substrate according to claim 1, characterized in that, The signals on the first scan line electrically connected to the pixel circuits in different rows are the same, the pixel circuits in multiple rows perform the first reset phase at the same time, and the pixel circuits in different rows write data voltages line by line.

7. The array substrate according to claim 6, characterized in that, The array substrate includes a substrate, the threshold compensation module includes a second transistor, the first gate of the second transistor is electrically connected to the second scan line, the area of ​​the second gate of the second transistor is larger than the channel area of ​​the second transistor, in the thickness direction of the array substrate, the second gate of the second transistor is located between the channel of the second transistor and the substrate, the first gate of the second transistor is located on the side of the channel of the second transistor away from the substrate, and the orthographic projection of the second gate of the second transistor on the substrate at least partially overlaps with the orthographic projection of the first gate of the second transistor on the substrate; Preferably, the driving module includes a first transistor, the threshold compensation module includes a second transistor, the first plate of the storage capacitor is electrically connected to the gate of the first transistor, and the second plate of the storage capacitor is electrically connected to a fixed voltage terminal; the first electrode of the second transistor is electrically connected to the second electrode of the first transistor, and the second electrode of the second transistor is electrically connected to the gate of the first transistor through a first connecting portion; in the thickness direction of the array substrate, the first connecting portion at least partially overlaps with the second plate of the storage capacitor. Preferably, in the thickness direction of the array substrate, the first connection portion at least partially overlaps with the channel of the second transistor; Preferably, in the thickness direction of the array substrate, the first connection portion is located between the second electrode plate of the storage capacitor and the channel of the second transistor.

8. The array substrate according to any one of claims 5-7, characterized in that, The array substrate includes a substrate and a first semiconductor layer, a first metal layer, a second metal layer, a third metal layer, a fourth metal layer, a second semiconductor layer, a fifth metal layer, a sixth metal layer, and a seventh metal layer, which are sequentially located away from the substrate. The driving module includes a first transistor, the threshold compensation module includes a second transistor, the light emission control module includes a third transistor, the reset module includes a fourth transistor, the first plate of the storage capacitor is electrically connected to the gate of the first transistor, and the second plate of the storage capacitor is electrically connected to a fixed voltage terminal. The active layers of the first transistor and the third transistor are located in the first semiconductor layer, and the gate of the first transistor and the light-emitting control signal line are located in the first metal layer. Preferably, the second electrode plate, the second connection portion, and the third connection portion of the storage capacitor are located in the second metal layer, the second connection portion is connected between the first electrode of the first transistor and the first signal line, and the third connection portion is connected between the second electrode of the third transistor and the first electrode of the light-emitting element. Preferably, the first connection portion is located in the third metal layer, and the first connection portion is connected between the gate of the first transistor and the second electrode of the second transistor; Preferably, the second gate of the second transistor and the second gate of the fourth transistor are located in the fourth metal layer, the active layer of the second transistor and the active layer of the fourth transistor are located in the second semiconductor layer, and the first gate of the second transistor and the first gate of the fourth transistor are located in the fifth metal layer. Preferably, the first signal line is located in the sixth metal layer; Preferably, the reset signal line is located in the seventh metal layer.

9. A display panel, characterized in that, Includes the array substrate as described in any one of claims 1-8.

10. A display device, characterized in that, Includes the display panel as described in claim 9.

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