Overcurrent protection circuit and electronic device

Abstract

The application discloses an overcurrent protection circuit and electronic equipment, and belongs to the technical field of protection. The overcurrent protection circuit is connected with a battery assembly. A current detection circuit is used for outputting a first trigger signal in response to the fact that the charging current of the battery assembly is greater than a first preset current or the discharging current of the battery assembly is greater than a second preset current. A driving circuit is used for stopping the output of a driving signal according to the first trigger signal. A switch circuit is used for stopping the transmission of the charging current or the discharging current based on the stop of the driving signal. Thus, the circuit design is simplified, and the cost is reduced.

Description

Technical Field

[0001] This application belongs to the field of protection circuit technology, and in particular relates to an overcurrent protection circuit and electronic device. Background Technology

[0002] A battery management system (BMS) typically includes an overcurrent protection circuit for overcurrent protection of the battery. When the overcurrent protection circuit detects an overcurrent signal in the battery's charging and discharging circuit, it shuts off the switching transistors in the battery's charging and discharging circuit, thereby cutting off the battery's charging and discharging circuit and preventing the huge energy generated by the overcurrent from damaging the battery, switching circuit, and external wiring harness.

[0003] Existing overcurrent protection circuits include a first detection unit, a second detection unit, a current sensing element connected in series with the battery cell, a first switching unit, and a second switching unit to form a charging circuit or a discharging circuit. The first detection unit corresponds to the first switching unit, and the second detection unit corresponds to the second switching unit. Each detection unit controls the corresponding switching unit to turn on or off based on the voltage across the same current sensing element detected, thereby controlling the circuit's on / off state. The detection of current flowing through the battery cell is achieved by having the first and second detection units detect the voltage across the same current sensing element.

[0004] However, the above-mentioned overcurrent protection circuit requires two detection units to realize charging current detection and discharging current detection respectively, which makes the hardware design complex and costly.

[0005] Therefore, the related overcurrent protection circuit hardware design is complex and costly. Summary of the Invention

[0006] In view of the above problems, this application provides an overcurrent protection circuit and electronic device, which aims to solve the problems of complex and costly hardware design of related overcurrent protection circuits.

[0007] In a first aspect, this application provides an overcurrent protection circuit, connected to a battery assembly, comprising:

[0008] A current detection circuit is used to output a first trigger signal in response to the charging current of the battery assembly being greater than a first preset current or the discharging current of the battery assembly being greater than a second preset current.

[0009] A driving circuit, connected to the current detection circuit, is used to stop transmitting the charging current or the discharging current based on the disconnection of the first trigger signal.

[0010] In the technical solution of this application embodiment, the current detection circuit outputs a first trigger signal in response to the charging current of the battery assembly being greater than a first preset current or the discharging current of the battery assembly being greater than a second preset current; therefore, charging current detection and discharging current detection are realized simultaneously through one current detection circuit, eliminating the need to configure two detection circuits, simplifying hardware design and reducing costs.

[0011] In some embodiments, the current detection circuit includes:

[0012] A sampling circuit is used to sample the charging current of the battery assembly to output a charging sampling signal, or to sample the discharging current of the battery assembly to output a discharging sampling signal.

[0013] An amplifier circuit, connected to the sampling circuit, is used to output a charging detection signal based on a reference voltage and the charging sampling signal, or to output a discharging detection signal based on a reference voltage and the discharging sampling signal.

[0014] A comparator circuit, connected to the amplifier circuit and the driver circuit, is used to output the first trigger signal in response to the charging detection signal being greater than a first preset voltage or the discharging detection signal being less than a second preset voltage.

[0015] Wherein, the voltage of the charging detection signal is the difference between the reference voltage and the first amplified voltage, and the first amplified voltage is the product of the voltage and the gain of the charging sampling signal;

[0016] The voltage of the discharge detection signal is the sum of the reference voltage and the second amplified voltage, where the second amplified voltage is the product of the voltage and the gain of the discharge sampling signal.

[0017] By adopting the above scheme, the charging current detection and discharging current detection share the sampling circuit, amplification circuit and comparison circuit, thus realizing the simultaneous detection of charging current and discharging current through a single current detection circuit. This eliminates the need for two detection circuits, simplifies the hardware design and reduces costs.

[0018] In some embodiments, the current detection circuit further includes:

[0019] A first adjustment circuit, connected to the comparison circuit, is used to output the first preset voltage according to the first adjustment signal;

[0020] The second adjustment circuit, connected to the comparison circuit, is used to output the second preset voltage according to the second adjustment signal.

[0021] By adopting the above scheme, the first preset voltage and the second preset voltage can be adjusted, which improves the flexibility of the overcurrent protection circuit. Compared with the overcurrent judgment by microprocessor, the hardware scheme has a faster response speed, higher timeliness, and is safer and more reliable.

[0022] In some embodiments, it also includes:

[0023] A control circuit, connected to the first adjustment circuit and the second adjustment circuit, is used to respond to a small current charging command and output the first adjustment signal in a first state so that the first adjustment circuit outputs the first preset voltage located in a first numerical range.

[0024] By adopting the above solution, charging and discharging under low-current charging conditions were achieved, and the product's functionality was enriched.

[0025] In some embodiments, the control circuit is further configured to, in response to a sleep command, output the first adjustment signal in a second state to cause the first adjustment circuit to output the first preset voltage located in a second numerical range, and output the second adjustment signal in a first state to cause the second adjustment circuit to output the second preset voltage located in a first preset range.

[0026] By adopting the above solution, charging and discharging under dormant conditions were achieved, and the product's functionality was enriched.

[0027] The control circuit is also configured to respond to an operating command by outputting the second adjustment signal of the second state so that the second adjustment circuit outputs the second preset voltage located in the second preset range;

[0028] By adopting the above solution, charging and discharging under normal operating conditions were achieved, and the product's functions were enriched.

[0029] The control circuit is also configured to respond to a wake-up command by outputting the first adjustment signal in the third state to make the first adjustment circuit output the first preset voltage in the third numerical range, and outputting the second adjustment signal in the third state to make the second adjustment circuit output the second preset voltage in the third preset range.

[0030] The values ​​in the first numerical interval decrease sequentially to the values ​​in the third numerical interval; the values ​​in the first preset interval increase sequentially to the values ​​in the third preset interval.

[0031] By adopting the above scheme, charging and discharging under wake-up conditions are realized, and the vehicle outputs different levels of first preset voltage and different levels of second preset voltage under different operating conditions, which improves the flexibility of the overcurrent protection circuit and enriches the product's functions.

[0032] In some embodiments, it also includes:

[0033] A delay circuit, connected to the current detection circuit, is used to output a first trigger signal after a first preset duration in response to the duration of the first trigger signal being greater than a first preset duration.

[0034] The driving circuit is used to disconnect the output of the driving signal according to the first trigger signal after a first preset time.

[0035] By adopting the above scheme, the possibility of grounding errors caused by interference signals in the first trigger signal is reduced, and the stability of the overcurrent protection circuit is improved.

[0036] In some embodiments, it also includes:

[0037] A third adjustment circuit, connected to the delay circuit, is used to adjust the first preset duration in the delay circuit according to a third adjustment signal.

[0038] By adopting the above scheme, the first preset duration in the delay circuit can be adjusted, which improves the flexibility of the overcurrent protection circuit.

[0039] In some embodiments, the control circuit is also connected to the third adjustment circuit and is further configured to output the third adjustment signal of the first state in response to a low-current charging command so that the first preset duration of the delay circuit is located in the first interval.

[0040] By adopting the above solution, overcurrent protection under low-current charging conditions is achieved, and the product's functionality is enriched.

[0041] In some embodiments, the control circuit is further configured to, in response to a sleep command, output the third adjustment signal of the second state so that the first preset duration of the delay circuit is located in the second interval.

[0042] By adopting the above solution, overcurrent protection under sleep conditions is achieved, and the product's functionality is enriched.

[0043] In some embodiments, the control circuit is further configured to, in response to an operating command, output the third adjustment signal of the third state so that the first preset duration of the delay circuit is located in the third interval.

[0044] By adopting the above solution, overcurrent protection under normal operating conditions is achieved, and the product's functionality is enriched.

[0045] The control circuit is also configured to respond to a wake-up command by outputting the third adjustment signal of the fourth state so that the first preset duration of the delay circuit is located in the fourth interval.

[0046] The above technical solution achieves overcurrent protection under wake-up conditions, enriches the product's functionality, and allows for different preset durations for different vehicle operating conditions, improving the flexibility of the overcurrent protection circuit and further enhancing the product's functionality.

[0047] In some embodiments, the driving circuit includes:

[0048] A latching module, connected to the current detection circuit, is used to latch the first trigger signal to output a turn-off signal;

[0049] A drive module, connected to the latch module, is used to disconnect the output of the drive signal according to the turn-off signal.

[0050] Through the above technical solution, the first trigger signal is converted into a turn-off signal after being latched, and the turn-off signal controls the disconnection of the drive signal, which reduces the possibility of spike signal interference in the first trigger signal and improves the stability of the overcurrent protection circuit.

[0051] In some embodiments, the latching module is specifically used to latch the first trigger signal in order to output the shutdown signal and the wake-up signal;

[0052] The overcurrent protection circuit also includes a control circuit connected to the latch module; the control circuit is used to enter the working state according to the wake-up signal and output a reset signal;

[0053] The latching circuit is also used to stop the output of the shutdown signal according to the reset signal;

[0054] The driving circuit is also used to output the driving signal according to the shutdown signal, so that the switching circuit transmits the charging circuit or the discharging current according to the driving signal.

[0055] Through the above technical solution, the control circuit enters the working state after receiving the wake-up signal and outputs a reset signal to stop the output of the shutdown signal. This allows the switching circuit to transmit the charging or discharging current according to the drive signal, thereby realizing circuit reset after an overcurrent fault and improving the ease of use of the overcurrent protection circuit.

[0056] In some embodiments, the control circuit is further configured to stop outputting the reset signal in response to the number of times the wake-up signal is received within a second preset time period being greater than a preset number, so as to turn off the switching circuit.

[0057] The above technical solution completely shuts down the switching circuit when an overcurrent fault is detected more than a preset number of times within a second preset time period, thereby improving the reliability and safety of the overcurrent protection circuit.

[0058] In some embodiments, the control circuit is further configured to output a second trigger signal and output a first enable signal and / or a second enable signal;

[0059] The driving signal includes a first sub-driving signal and a second sub-driving signal;

[0060] The driving circuit includes:

[0061] The first driving module, connected to the control circuit and the switching circuit, is used to output the first sub-driving signal in response to the disconnection of the shutdown signal, according to the first enable signal and the second trigger signal.

[0062] The second drive module, connected to the control circuit and the switching circuit, is used to output the second sub-drive signal in response to the disconnection of the shutdown signal, according to the second enable signal and the second trigger signal.

[0063] The switching circuit is specifically used to transmit the charging current or the discharging current based on the first sub-driving signal and / or the second sub-driving signal.

[0064] The above technical solution improves the flexibility of switching circuit control by using two sub-drive signals to control the switching circuit.

[0065] In some embodiments, the switching circuit includes:

[0066] A first switch is connected to the battery assembly and the first drive module, and is used to transmit the charging current or the discharging current according to the first sub-drive signal;

[0067] The second switch, connected to the first switch and the second drive module, is used to transmit the charging current or the discharging current according to the second sub-drive signal.

[0068] The above technical solution allows for the separate control of the first and second switches, improving the flexibility of the overcurrent protection circuit.

[0069] Secondly, embodiments of the present invention also provide an electronic device, the electronic device including a battery assembly and the overcurrent protection circuit described above.

[0070] By adopting the above solutions, since the electronic device includes the overcurrent protection circuit of any of the above solutions, the safety and reliability of the overcurrent protection circuit can be improved, and it can be applied to high-power scenarios.

[0071] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description

[0072] Various other advantages and benefits will become apparent to those skilled in the art upon reading the detailed description of the preferred embodiments below. The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of this application. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0073] Figure 1 A schematic diagram of an overcurrent protection circuit provided in an embodiment of this application;

[0074] Figure 2 A schematic diagram of a current detection circuit in an overcurrent protection circuit provided in an embodiment of this application;

[0075] Figure 3 This is a schematic diagram of another structure of the current detection circuit in the overcurrent protection circuit provided in one embodiment of this application;

[0076] Figure 4 This is a schematic diagram of another structure of the overcurrent protection circuit provided in one embodiment of this application;

[0077] Figure 5 This is a schematic diagram of another structure of the overcurrent protection circuit provided in one embodiment of this application;

[0078] Figure 6 This is a schematic diagram of another structure of the overcurrent protection circuit provided in one embodiment of this application;

[0079] Figure 7 This is a schematic diagram of another structure of the overcurrent protection circuit provided in one embodiment of this application;

[0080] Figure 8 This is a schematic diagram of another structure of the overcurrent protection circuit provided in one embodiment of this application;

[0081] Figure 9 This is a schematic diagram of another structure of the overcurrent protection circuit provided in one embodiment of this application;

[0082] Figure 10 A schematic diagram of a partial circuit example of an overcurrent protection circuit provided in an embodiment of this application;

[0083] Figure 11 This is a schematic diagram of a partial circuit example of the driving unit in an overcurrent protection circuit provided in an embodiment of this application. Detailed Implementation

[0084] The embodiments of the technical solution of this application will now be described in detail with reference to the accompanying drawings. These embodiments are only used to more clearly illustrate the technical solution of this application and are therefore merely examples, and should not be used to limit the scope of protection of this application.

[0085] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the application; the terms “comprising” and “having”, and any variations thereof, in the specification, claims, and foregoing description of the drawings are intended to cover non-exclusive inclusion.

[0086] In the description of the embodiments of this application, technical terms such as "first" and "second" are used only to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, "multiple" means two or more, unless otherwise explicitly defined.

[0087] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0088] In the description of the embodiments in this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0089] In the description of the embodiments of this application, the term "multiple" refers to two or more (including two), similarly, "multiple sets" refers to two or more (including two sets), and "multiple pieces" refers to two or more (including two pieces).

[0090] Currently, judging from market trends, overcurrent protection is being used more and more widely. It is extensively applied in various fields, including electric bicycles, motorcycles, automobiles, military equipment, and aerospace. As the application areas of overcurrent protection continue to expand, the market demand is also constantly increasing.

[0091] To address the issues of complex hardware design and high cost, the applicant discovered that a single current detection circuit can be configured in the design. This current detection circuit simultaneously detects both the charging and discharging currents of the battery to output a first trigger signal, causing the switching circuit to stop transmitting either the charging or discharging current. This simplifies the hardware design of the overcurrent protection circuit and reduces costs.

[0092] The overcurrent protection circuit disclosed in this application can be used in electrical devices. These electrical devices can be, but are not limited to, electric toys, power tools, electric vehicles, electric cars, ships, spacecraft, etc. Electric toys can include stationary or mobile electric toys, such as game consoles, electric car toys, electric ship toys, and electric airplane toys, etc. Spacecraft can include airplanes, rockets, space shuttles, and spacecraft, etc.

[0093] According to some embodiments of this application, refer to Figure 1 , Figure 1 A schematic diagram of an overcurrent protection circuit according to an embodiment of this application is shown. For ease of explanation, only the parts relevant to this embodiment are shown, and are described in detail below:

[0094] The aforementioned overcurrent protection circuit is connected to the battery assembly 90 and includes a current detection circuit 01, a latching circuit 02, a drive circuit 03, and a switching circuit 04.

[0095] The current detection circuit 01 is used to output a first trigger signal in response to the charging current of the battery assembly 90 being greater than a first preset current or the discharging current of the battery assembly 90 being greater than a second preset current.

[0096] The drive circuit 10 is connected to the current detection circuit 01 and is used to disconnect the output of the drive signal according to the first trigger signal.

[0097] Switching circuit 04, connected to driving circuit 03, is used to stop transmitting charging current or discharging current based on driving signal disconnection.

[0098] The current detection circuit 01 can be connected to the negative terminal of the battery pack 90 and connected in series in the main charging and discharging circuit of the battery pack 90.

[0099] The switching circuit 04 may include two field-effect transistors, wherein the sources of the two field-effect transistors are connected in common.

[0100] In the technical solution of this application embodiment, the current detection circuit 01 outputs a first trigger signal in response to the charging current of the battery component 90 being greater than a first preset current or the discharging current of the battery component 90 being greater than a second preset current; therefore, charging current detection and discharging current detection are realized simultaneously through one current detection circuit 01, eliminating the need to configure two detection circuits, simplifying hardware design and reducing costs.

[0101] According to some embodiments of this application, optionally, please continue to refer to Figure 2 The current detection circuit 01 includes a sampling circuit 011, an amplification circuit 012, and a comparison circuit 013.

[0102] The sampling circuit 011 is used to sample the charging current of the battery pack 90 to output a charging sampling signal, or to sample the discharging current of the battery pack 90 to output a discharging sampling signal.

[0103] Amplifier circuit 012, connected to sampling circuit 011, is used to output a charging detection signal based on reference voltage and charging sampling signal, or to output a discharging detection signal based on reference voltage and discharging sampling signal.

[0104] The comparator circuit 013, connected to the amplifier circuit 012 and the driver circuit 10, is used to output a first trigger signal in response to a charging detection signal being less than a first preset voltage or a discharging detection signal being greater than a second preset voltage.

[0105] The voltage of the charging detection signal is the difference between the reference voltage and the first amplified voltage, where the first amplified voltage is the product of the voltage of the charging sampling signal and the gain. The voltage of the discharging detection signal is the sum of the reference voltage and the second amplified voltage, where the second amplified voltage is the product of the voltage of the discharging sampling signal and the gain.

[0106] It is understood that the sampling circuit 011 may include a resistor component. The voltage of both the charging sampling signal and the discharging sampling signal is the voltage across the resistor component.

[0107] The voltage V1 of the charging detection signal can be obtained using the following formula: V1 = VREF - V * GAIN

[0108] Where VREF is the reference voltage, V is the voltage of the charging sampling signal, and GAIN is the gain.

[0109] The voltage V2 of the discharge detection signal can be obtained by the following formula: V2 = VREF + V*GAIN

[0110] Where VREF is the reference voltage, V is the voltage of the discharge sampling signal, and GAIN is the gain.

[0111] By adopting the above scheme, the charging current detection and discharging current detection share the sampling circuit 011, the amplification circuit 012, and the comparison circuit 013, thereby realizing the simultaneous detection of charging current and discharging current through a single current detection circuit 01. This eliminates the need for two detection circuits, simplifies the hardware design, and reduces costs.

[0112] According to some embodiments of this application, optionally, please continue to refer to Figure 3 , Figure 3 A schematic diagram of the current detection circuit in an overcurrent protection circuit according to another embodiment of this application is shown. For ease of explanation, only the parts relevant to this embodiment are shown, and are described in detail below:

[0113] The above-mentioned overcurrent protection circuit, in addition to Figure 2 In addition to all the components and parts of the current detection circuit shown, the overcurrent protection circuit also includes a first adjustment circuit 05 and a second adjustment circuit 06.

[0114] The first adjustment circuit 05 is connected to the comparison circuit 013 and is used to output a first preset voltage according to the first adjustment signal.

[0115] The second adjustment circuit 06 is connected to the comparison circuit 013 and is used to output a second preset voltage according to the second adjustment signal.

[0116] In specific implementation, the first adjustment signal may include multiple first sub-adjustment signals, and the first control word corresponding to the multiple first sub-adjustment signals is configured with a first preset voltage at different levels. The second adjustment signal may include multiple second sub-adjustment signals, and the second control word corresponding to the multiple second sub-adjustment signals is configured with a second preset voltage at different levels.

[0117] By adopting the above scheme, the first preset voltage and the second preset voltage can be adjusted, which improves the flexibility of the overcurrent protection circuit. Compared with the overcurrent judgment by microprocessor, the hardware scheme has a faster response speed, higher timeliness, and is safer and more reliable.

[0118] According to some embodiments of this application, optionally, please continue to refer to Figure 4 , Figure 4 A schematic diagram of an overcurrent protection circuit according to another embodiment of this application is shown. For ease of explanation, only the parts relevant to this embodiment are shown, and are described in detail below:

[0119] The above-mentioned overcurrent protection circuit, in addition to Figure 1 In addition to all the components and parts of the overcurrent protection circuit shown, the overcurrent protection circuit also includes control circuit 07.

[0120] The control circuit 07 is connected to the first adjustment circuit 05 and the second adjustment circuit 06, and is used to respond to the small current charging command to output a first adjustment signal of the first state so that the first adjustment circuit 05 outputs a first preset voltage in the first value range.

[0121] When charging with a small current and limiting the discharge output, the charging current is limited by the overcurrent capability of the body diode of the field effect transistor in the switching circuit 04. The body diode usually has a small overcurrent capability, can withstand a small maximum current, and has a very short overcurrent time. Therefore, a large first preset voltage needs to be set.

[0122] By adopting the above solution, overcurrent protection under low-current charging conditions is achieved, and the product's functionality is enriched.

[0123] According to some embodiments of this application, optionally, the control circuit 07 is further configured to respond to a sleep command by outputting a first adjustment signal of the second state to cause the first adjustment circuit 05 to output a first preset voltage within a second numerical range, and outputting a second adjustment signal of the first state to cause the second adjustment circuit 06 to output a second preset voltage within a first preset range.

[0124] Understandably, most loads stop working in sleep mode, hence the setting of a larger first preset voltage and a smaller second preset voltage.

[0125] By adopting the above solution, a faster overcurrent protection response is achieved under dormant conditions, and the product's functionality is enriched.

[0126] According to some embodiments of this application, optionally, the control circuit 07 is further configured to output a second adjustment signal of the second state in response to an operating command, so that the second adjustment circuit 06 outputs a second preset voltage located in a second preset range.

[0127] Understandably, after the vehicle is woken up and powered on at high voltage (i.e., after normal operation), the load is mainly supplied by the power battery through the DC-DC converter module. Therefore, the battery module does not draw a large supply current; in most cases, the DC-DC converter module charges the low-voltage battery module. The preset voltage for charging current protection is set according to the overcurrent capability of the switching circuit or charging module. The preset voltage for discharging current protection is set according to the discharging overcurrent capability of the switching circuit.

[0128] By adopting the above solution, overcurrent protection under normal operating conditions is achieved, and the product's functionality is enriched.

[0129] According to some embodiments of this application, optionally, the control circuit 07 is further configured to respond to a wake-up command by outputting a first adjustment signal of a third state to cause the first adjustment circuit 05 to output a first preset voltage located in a third numerical range, and outputting a second adjustment signal of a third state to cause the second adjustment circuit 06 to output a second preset voltage located in a third preset range.

[0130] Among them, the values ​​in the first numerical interval decrease sequentially to the values ​​in the third numerical interval; the values ​​in the first preset interval increase sequentially to the values ​​in the third preset interval.

[0131] Understandably, the required charging and discharging currents differ depending on the vehicle's operating conditions. In practice, the vehicle requires a larger starting current to transition from sleep mode to low-voltage power-on (i.e., wake-up), and the discharging current increases rapidly.

[0132] By adopting the above solution, overcurrent protection under wake-up conditions is achieved, the product's functions are enriched, and the vehicle can output different levels of the first preset voltage and the second preset voltage under different operating conditions, which improves the flexibility of the overcurrent protection circuit and enriches the product's functions.

[0133] According to some embodiments of this application, optionally, please continue to refer to Figure 5 , Figure 5 A schematic diagram of an overcurrent protection circuit according to another embodiment of this application is shown. For ease of explanation, only the parts relevant to this embodiment are shown, and are described in detail below:

[0134] The above-mentioned overcurrent protection circuit, in addition to Figure 4 In addition to all the components and parts of the overcurrent protection circuit shown, the overcurrent protection circuit also includes a delay circuit 08.

[0135] The delay circuit 08 is connected to the current detection circuit 01 and is used to output the first trigger signal after the first preset duration in response to the first trigger signal having a duration greater than the first preset duration.

[0136] The drive circuit 10 is specifically used to disconnect the output of the drive signal according to the first trigger signal after a first preset time.

[0137] Understandably, the delay circuit 08 is specifically used to determine whether the level of the first trigger signal after the preset transition (such as transitioning to a high level) remains for a first preset duration when the first trigger signal undergoes a preset transition. If the level of the first trigger signal after the transition does not remain for the first preset duration, the first trigger signal after the first preset duration is output. This prevents the possibility of false triggering when the first trigger signal is subject to spike signal interference.

[0138] By adopting the above scheme, the possibility of grounding errors caused by interference signals in the first trigger signal is reduced, and the stability of the overcurrent protection circuit is improved.

[0139] According to some embodiments of this application, optionally, please continue to refer to Figure 6 , Figure 6 A schematic diagram of an overcurrent protection circuit according to another embodiment of this application is shown. For ease of explanation, only the parts relevant to this embodiment are shown, and are described in detail below:

[0140] The above-mentioned overcurrent protection circuit, in addition to Figure 5 In addition to all the components and parts of the overcurrent protection circuit shown, it also includes a third regulating circuit 09.

[0141] The third adjustment circuit 09 is connected to the delay circuit 08 and is used to adjust the first preset duration in the delay circuit 08 according to the third adjustment signal.

[0142] By adjusting the first preset duration in the delay circuit 08, the actual needs under different operating conditions can be met, and the sensitivity of the overcurrent protection circuit can be adjusted according to the actual needs.

[0143] By adopting the above scheme, the first preset duration in the delay circuit 08 is adjustable, which improves the flexibility of the overcurrent protection circuit.

[0144] According to some embodiments of this application, optionally, the control circuit 07 is also connected to the third adjustment circuit 09 and is also used to output a third adjustment signal of the first state in response to a small current charging command so that the first preset duration of the delay circuit 08 is located in the first interval.

[0145] Understandably, under low-current charging conditions, the charging current is limited by the overcurrent capability of the body diode of the field-effect transistor in the switching circuit 04. The body diode usually has a small overcurrent capability and can withstand a very short overcurrent time, so a small first preset duration needs to be set.

[0146] By adopting the above solution, overcurrent protection under low-current charging conditions is achieved, and the product's functionality is enriched.

[0147] According to some embodiments of this application, optionally, the control circuit 07 is further configured to output a third adjustment signal of the second state in response to a sleep command so that the first preset duration of the delay circuit 08 is located in the second interval.

[0148] Understandably, the overcurrent threshold is relatively small in the sleep mode, and can be set according to the overcurrent duration capability of the components in the switching circuit 04 under this overcurrent threshold.

[0149] By adopting the above solution, overcurrent protection under sleep conditions is achieved, and the product's functionality is enriched.

[0150] According to some embodiments of this application, optionally, the control circuit 07 is also configured to output a third adjustment signal of the third state in response to an operation command so that the first preset duration of the delay circuit 08 is located in the third interval.

[0151] Under normal operating conditions, the overcurrent threshold is relatively large and can be set according to the overcurrent duration capability of the components in the switching circuit 04 at this overcurrent threshold.

[0152] By adopting the above solution, overcurrent protection under normal operating conditions is achieved, and the product's functionality is enriched.

[0153] According to some embodiments of this application, optionally, the control circuit 07 is further configured to output a third adjustment signal of the fourth state in response to a wake-up command so that the first preset duration of the delay circuit 08 is located in the fourth interval.

[0154] Understandably, the overcurrent threshold is relatively large under wake-up conditions, and can be set according to the overcurrent duration capability of the components in the switching circuit 04 under this overcurrent threshold.

[0155] The above technical solution achieves overcurrent protection upon power-on, and allows for the configuration of different overcurrent protection current thresholds and delay filtering durations based on the magnitude and duration of the pulse peak current, combined with the overcurrent capabilities of the switching circuit, battery, and wiring harness under different operating conditions. This improves the effectiveness of overcurrent protection under various conditions and avoids false triggering of overcurrent protection caused by fixed thresholds for different operating conditions. It also enriches the product's functionality and increases the flexibility of the overcurrent protection circuit.

[0156] According to some embodiments of this application, optionally, please continue to refer to Figure 7 , Figure 7 A schematic diagram of an overcurrent protection circuit according to another embodiment of this application is shown. For ease of explanation, only the parts relevant to this embodiment are shown, and are described in detail below:

[0157] The above-mentioned overcurrent protection circuit, in addition to Figure 1 In addition to all the components and parts of the overcurrent protection circuit shown, the drive circuit 10 includes a latch module 02 and a drive module 03.

[0158] The latch module 02 is connected to the current detection circuit 01 and is used to latch the first trigger signal to output a turn-off signal;

[0159] The drive module 03, connected to the latch module 02, is used to disconnect the output of the drive signal according to the turn-off signal.

[0160] It is understandable that the shutdown signal can be a level signal, and the latch module 02 is specifically used to latch the first trigger signal to maintain the output of the shutdown signal.

[0161] Through the above technical solution, the first trigger signal is latched and then converted into a turn-off signal. The turn-off signal controls the disconnection of the drive signal, which reduces the possibility of spike signal interference in the first trigger signal and improves the stability of the overcurrent protection circuit.

[0162] According to some embodiments of this application, optionally, please continue to refer to Figure 7 , Figure 7 A schematic diagram of an overcurrent protection circuit according to another embodiment of this application is shown. For ease of explanation, only the parts relevant to this embodiment are shown, and are described in detail below:

[0163] The latch module 02 is specifically used to latch the first trigger signal in order to output a shutdown signal and a wake-up signal.

[0164] The above-mentioned overcurrent protection circuit, in addition to Figure 1 In addition to all the components and parts of the overcurrent protection circuit shown, the overcurrent protection circuit also includes a control circuit 07 connected to the latch module 02.

[0165] The control circuit 07 is used to enter the working state according to the wake-up signal and output a reset signal.

[0166] The latching module 02 is also used to stop the output of the shutdown signal based on the reset signal.

[0167] The drive circuit 03 is also used to output a drive signal according to the stop signal of the turn-off signal, so that the switch circuit 04 can transmit the charging circuit or the discharging current according to the drive signal.

[0168] In practice, overcurrent conditions may be caused by load changes or other occasional factors. Therefore, in the event of an overcurrent, the switch circuit 04 should be turned off first to avoid occasional overcurrent faults, and then the switch circuit 04 should be turned on to carry out normal charging and discharging.

[0169] Through the above technical solution, the control circuit 07 enters the working state after receiving the wake-up signal and outputs a reset signal to stop the output of the shutdown signal. This allows the switching circuit 04 to transmit the charging or discharging current according to the drive signal, thereby realizing the circuit reset after an overcurrent fault and improving the ease of use of the overcurrent protection circuit.

[0170] In some embodiments, optionally, the control circuit 07 is further configured to stop outputting a reset signal in response to the number of times a wake-up signal is received within a second preset time period being greater than a preset number, so as to turn off the switch circuit 04.

[0171] Understandably, if a preset number of overcurrent faults occur within a short period of time, it indicates a more serious fault, such as a load short circuit or a line short circuit. In this case, the switching circuit 04 must be completely shut down to reduce the possibility of device breakdown damage and safety accidents.

[0172] Through the above technical solution, if an overcurrent fault is detected more than a preset number of times within the second preset time period, the switching circuit 04 is completely shut down, thereby improving the reliability and safety of the overcurrent protection circuit.

[0173] According to some embodiments of this application, optionally, please continue to refer to Figure 8 , Figure 8 A schematic diagram of an overcurrent protection circuit according to another embodiment of this application is shown. For ease of explanation, only the parts relevant to this embodiment are shown, and are described in detail below:

[0174] The above-mentioned overcurrent protection circuit, in addition to Figure 1In addition to all the components and parts of the overcurrent protection circuit shown, the drive circuit 03 includes a first drive module 031 and a second drive module 032.

[0175] The control circuit 07 is also used to output a second trigger signal, and to output a first enable signal and / or a second enable signal.

[0176] The driving signals include a first sub-driving signal and a second sub-driving signal.

[0177] The first drive module 031 is connected to the control circuit 07 and the switch circuit 04, and is used to output a first sub-drive signal in response to the disconnection of the turn-off signal according to the first enable signal and the second trigger signal.

[0178] The second drive module 032, connected to the control circuit 07 and the switch circuit 04, is used to output a second sub-drive signal in response to the disconnection of the turn-off signal, based on the second enable signal and the second trigger signal.

[0179] The switching circuit 04 is specifically used to transmit charging current or discharging current based on the first sub-drive signal and / or the second sub-drive signal.

[0180] The above technical solution improves the flexibility of switching circuit control by using two sub-drive signals to control the switching circuit.

[0181] According to some embodiments of this application, optionally, please continue to refer to Figure 9 , Figure 9 A schematic diagram of an overcurrent protection circuit according to another embodiment of this application is shown. For ease of explanation, only the parts relevant to this embodiment are shown, and are described in detail below:

[0182] The above-mentioned overcurrent protection circuit, in addition to Figure 8 In addition to all the components and assemblies of the overcurrent protection circuit shown, the switching circuit 04 includes a first switch 041 and a second switch 042.

[0183] The first switch 041 is connected to the battery assembly 90 and the first drive module 031, and is used to transmit charging current or discharging current according to the first sub-drive signal.

[0184] The second switch 042 is connected to the first switch 041 and the second drive module 032, and is used to transmit charging current or discharging current according to the second sub-drive signal.

[0185] It is understood that the first switch 041 and the second switch 042 each include a field-effect transistor, and the sources of the two field-effect transistors are connected in common, so that when one field-effect transistor is turned on, a small current can be charged through the body diode of the other field-effect transistor.

[0186] The above technical solution allows for the separate control of the first switch 041 and the second switch 042, improving the flexibility of the overcurrent protection circuit.

[0187] In some embodiments, optionally, please refer to Figure 10 The first switch 041 includes a first field-effect transistor M1; the drain of the first field-effect transistor M1 forms the charging current output terminal and the discharging current input terminal of the first switch 041, and is connected to the battery assembly 90 to output charging current or receive discharging current; the source of the first field-effect transistor M1 forms the charging current input terminal and the discharging current output terminal of the first switch 041, and is connected to the second switch 042 to receive charging current or output discharging current; the gate and the source of the first field-effect transistor M1 together form the first sub-drive signal input terminal of the first switch 041, and is connected to the first drive module 031 to receive the first sub-drive signal.

[0188] The circuit of the first switch is simple and reliable.

[0189] The second switch 042 includes a second field-effect transistor M2; the source of the second field-effect transistor M2 constitutes the charging current output terminal and the discharging current input terminal of the second switch 042, and is connected to the first switch 041 to output charging current or receive discharging current; the drain of the second field-effect transistor M2 constitutes the charging current input terminal and the discharging current output terminal of the second switch 042, and is connected to the charging current or output discharging current; the gate of the second field-effect transistor M2 and the source of the second field-effect transistor M2 together constitute the second sub-drive signal input terminal of the second switch 042, and is connected to the second drive module 032 to receive the second sub-drive signal.

[0190] The circuit of the second switch is simple and reliable.

[0191] The sampling circuit 011 includes a first resistor R1; the first end of the first resistor R1 constitutes the charging current input terminal and the discharging current output terminal of the sampling circuit 011, and is connected to the battery assembly 90 to receive the charging current or output the discharging current; the second end of the first resistor R1 constitutes the charging current output terminal and the discharging current input terminal of the sampling circuit 011, and is connected to the discharging current; the first end and the second end of the first resistor R1 together constitute the charging sampling signal output terminal and the discharging sampling signal output terminal of the sampling circuit 011, and are connected to the amplifier circuit 012 to output the charging sampling signal or the discharging sampling signal.

[0192] The sampling circuit is simple and reliable.

[0193] Amplifier circuit 012 includes amplifier U1; the positive inverting input terminal IN+ and the negative inverting input terminal IN- of amplifier U1 together constitute the charging sampling signal input terminal and the discharging sampling signal input terminal of amplifier circuit 012, which are connected to sampling circuit 011 to receive charging sampling signal or discharging sampling signal; the output terminal OUT of amplifier U1 constitutes the output terminal of amplifier circuit 012, which is connected to comparator circuit 013 to output charging detection signal or discharging detection signal; the reference voltage input terminal REF of amplifier U1 constitutes the reference voltage input terminal of amplifier circuit 012 to receive reference voltage.

[0194] This amplifier circuit achieves potential shifting, thereby adapting to the input voltage of the comparator circuit.

[0195] The comparator circuit 013 includes a first comparator U2 and a second comparator U3. The inverting input terminal of the first comparator U2 and the non-inverting input terminal of the second comparator U3 are connected and together form the detection signal input terminal of the comparator circuit 013, which is connected to the amplifier circuit 012 to receive a charging detection signal or a discharging detection signal. The non-inverting input terminal of the first comparator U2 forms the second preset voltage input terminal of the comparator circuit 013 and is connected to the second adjustment circuit 06 to receive a second preset voltage. The inverting input terminal of the second comparator U3 forms the first preset voltage input terminal of the comparator circuit 013 and is connected to the first adjustment circuit 05 to receive a first preset voltage. The output terminals of the first comparator U2 and the second comparator U3 are connected and together form the output terminal of the comparator circuit 013, which is connected to the delay circuit 08 to output a first trigger signal.

[0196] The comparator circuit has a simple hardware design and high reliability.

[0197] The delay circuit 08 includes a delay module U4, a second resistor R2, a third resistor R3, a fourth resistor R4, and a fifth resistor R5. The setting terminal SET of the delay module U4 is connected to the third adjustment circuit 09. The input terminal IN of the delay module U4 constitutes the input terminal of the delay circuit 08 and is connected to the current detection circuit 01 to receive the first trigger signal. The output terminal OUT of the delay module U4 is connected to the first end of the fourth resistor R4. The second end of the fourth resistor R4 and the first end of the fifth resistor R5 are connected and together constitute the output terminal of the delay circuit 08, which is connected to the latch circuit 02 to output the first trigger signal after a first preset time. The power supply terminal V+ of the delay module U4 and the first end of the second resistor R2 are connected to the first power supply VAA. The programmable divider terminal DIV of the delay module U4 is connected to the second end of the second resistor R2 and the first end of the third resistor R3. The ground terminal GND of the delay module U4 and the second end of the third resistor R3 are connected to the power ground.

[0198] This delay circuit enables adjustable delay duration, offering high flexibility.

[0199] The latch circuit 02 includes a first latch U5, a second latch U6, a third field-effect transistor M3, a first diode D1, a second diode D2, a third diode D3, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15, a sixteenth resistor R16, a seventeenth resistor R17, an eighteenth resistor R18, and a nineteenth resistor R19. The clock terminal CP of the first latch U5 constitutes the first trigger signal input terminal of the latch circuit 02, which is connected to the delay circuit 08 to receive the first trigger signal after a first preset time. The data terminal D is connected to the first terminal of the sixth resistor R6. The main reset terminal / MR of the first latch U5 is connected to the drain of the third field-effect transistor M3 and the first terminal of the thirteenth resistor R13. The output terminal Q of the first latch U5 is connected to the anodes of the first diode D1, the second diode D2, and the third diode D3. The cathode of the first diode D1 is connected to the first terminal of the fourteenth resistor R14, and the cathode of the second diode D2 is connected to the first terminal of the sixteenth resistor R16. The second terminals of the fourteenth resistor R14, the first terminals of the fifteenth resistor R15, the second terminals of the sixteenth resistor R16, and the first terminals of the seventeenth resistor R17 together constitute the wake-up signal output terminal of the latch circuit 02, which is connected to the control circuit 07. The third diode D3 is connected to the first terminal of the eighteenth resistor R18; the second terminal of the eighteenth resistor R18 and the first terminal of the nineteenth resistor R19 together form the shutdown signal output terminal of the latch circuit 02, which is connected to the drive circuit 03 to output the shutdown signal; the first terminal of the seventh resistor R7 and the first terminal of the ninth resistor R9 together form the reset signal input terminal of the latch circuit 02 to receive the reset signal; the second terminal of the seventh resistor R7 is connected to the first terminal of the eighth resistor R8 and the clock terminal CP of the second latch U6; the second terminal of the ninth resistor R9 is connected to the first terminal of the tenth resistor R10 and the data terminal D of the second latch U6; the output terminal Q of the second latch U6 is connected to the eleventh resistor R18. The first end of R11 is connected, the second end of the eleventh resistor R11 is connected to the first end of the twelfth resistor R12 and the gate of the third field-effect transistor M3, the power supply terminal Vcc of the first latch U5, the power supply terminal Vcc of the second latch U6 and the main reset terminal / MR of the second latch U6 are connected to the first power supply VAA, the ground terminal GND of the first latch U5, the ground terminal GND of the second latch U6, the source of the third field-effect transistor M3, the second end of the sixth resistor R6, the second end of the eighth resistor R8, the second end of the tenth resistor R10, the second end of the twelfth resistor R12, the second end of the fifteenth resistor R15, the second end of the seventeenth resistor R17 and the second end of the nineteenth resistor R19 are connected to the power supply ground.

[0200] This latching circuit enables latching and resetting, enriching the product's functionality.

[0201] The second adjustment circuit 06 includes a third latch U7, a fourth field-effect transistor M4, a fifth field-effect transistor M5, a sixth field-effect transistor M6, a twentieth resistor R20, a twenty-first resistor R21, a twenty-second resistor R22, a twenty-third resistor R23, and a twenty-fourth resistor R24. The first input terminal a1, the second input terminal a2, the third input terminal a3, and the clock terminal CP of the third latch U7 together constitute the input terminal of the second adjustment circuit 06, which is connected to the control circuit 07 to receive the second adjustment signal. The third output terminal b3 of the third latch U7 is connected to the gate of the fourth field-effect transistor M4, the second output terminal b2 of the third latch U7 is connected to the gate of the fifth field-effect transistor M5, and the first output terminal b1 of the third latch U7 is connected to the gate of the sixth field-effect transistor M6. The drain of the fourth field-effect transistor M4 is connected to the first terminal of the twenty-second resistor R22, the drain of the fifth field-effect transistor M5 is connected to the first terminal of the twenty-third resistor R23, and the drain of the sixth field-effect transistor M6 is connected to the first terminal of the twenty-fourth resistor R24. The source of the fourth field-effect transistor M4 is connected to the source of the fifth field-effect transistor M5, the source of the sixth field-effect transistor M6, and the first terminal of the twenty-first resistor R21. The first terminal of the twentieth resistor R20, the second terminal of the twenty-second resistor R22, the second terminal of the twenty-third resistor R23, and the second terminal of the twenty-fourth resistor R24 ​​are connected and form the output terminal of the second adjustment circuit 06, which is connected to the comparator circuit 013 to output the second preset voltage. The second terminal of the twentieth resistor R20 is connected to the reference power supply VREF2, and the second terminal of the twenty-first resistor R21 is connected to the power supply ground.

[0202] The second adjustment circuit can output different voltage levels, and the circuit is simple and reliable.

[0203] The first adjustment circuit 05 includes a fourth latch U8, a seventh field-effect transistor M7, an eighth field-effect transistor M8, a ninth field-effect transistor M9, a twenty-fifth resistor R25, a twenty-sixth resistor R26, a twenty-seventh resistor R27, a twenty-eighth resistor R28, and a twenty-ninth resistor R29. The first input terminal a1, the second input terminal a2, the third input terminal a3, and the clock terminal CP of the fourth latch U8 together constitute the input terminal of the first adjustment circuit 05, which is connected to the control circuit 07 to receive the first adjustment signal. The third output terminal b3 of the fourth latch U8 is connected to the gate of the seventh field-effect transistor M7, the second output terminal b2 of the fourth latch U8 is connected to the gate of the eighth field-effect transistor M8, and the first output terminal b1 of the fourth latch U8 is connected to the gate of the ninth field-effect transistor M9. The drain of the seventh field-effect transistor M7 is connected to the first end of the twenty-seventh resistor R27; the drain of the eighth field-effect transistor M8 is connected to the first end of the twenty-eighth resistor R28; the drain of the ninth field-effect transistor M9 is connected to the first end of the twenty-ninth resistor R29; and the first end of the twenty-sixth resistor R26 is connected to the source of the seventh field-effect transistor M7, the source of the eighth field-effect transistor M8, and the source of the ninth field-effect transistor M9. The first end of the twenty-fifth resistor R25, the second end of the twenty-seventh resistor R27, the second end of the twenty-eighth resistor R28, and the second end of the twenty-ninth resistor R2 are connected and together form the output terminal of the first adjustment circuit 05, which is connected to the comparator circuit 013 to output the first preset voltage. The second end of the twenty-fifth resistor R25 is connected to the reference power supply VREF2, and the second end of the twenty-sixth resistor R26 is connected to the power supply ground.

[0204] The first adjustment circuit can output different levels of output voltage, and the circuit is simple and reliable.

[0205] The third adjustment circuit 09 includes a fifth latch U9, a tenth field-effect transistor M10, an eleventh field-effect transistor M11, a twelfth field-effect transistor M12, a thirtieth resistor R30, a thirty-first resistor R31, a thirty-second resistor R32, and a thirty-third resistor R33. The first input terminal a1, the second input terminal a2, the third input terminal a3, and the clock terminal CP of the fifth latch U9 together constitute the input terminal of the third adjustment circuit 09, which is connected to the control circuit 07 to receive the third adjustment signal. The third output terminal b3 of the fifth latch U9 is connected to the gate of the tenth field-effect transistor M10, and the second output terminal b2 of the fifth latch U9 is connected to the gate of the eleventh field-effect transistor M10. The gate of M11 is connected; the first output terminal b1 of the fifth latch U9 is connected to the gate of the twelfth field-effect transistor M12; the drain of the tenth field-effect transistor M10 is connected to the first end of the thirtieth resistor R30; the drain of the eleventh field-effect transistor M11 is connected to the first end of the thirty-first resistor R31; the drain of the twelfth field-effect transistor M12 is connected to the first end of the thirty-second resistor R32; the first end of the thirty-third resistor R33 is connected to the source of the tenth field-effect transistor M10, the source of the eleventh field-effect transistor M11, and the source of the twelfth field-effect transistor M12; the second ends of the thirtieth resistor R30, the third-first resistor R31, and the third-second resistor R32 are connected and together connected to the delay circuit 08.

[0206] This second adjustment circuit can provide resistor networks with different resistance levels, and the circuit is simple and reliable.

[0207] The control circuit 07 includes a microprocessor U10; the first general-purpose input / output terminal P1.1 of the microprocessor U10 constitutes the second trigger signal output terminal of the control circuit 07, connected to the first drive module 031 and the second drive module 032 to output a second trigger signal; the second general-purpose input / output terminal P1.2 of the microprocessor U10 constitutes the first enable signal output terminal of the control circuit 07, connected to the first drive module 031 to output a first enable signal; the third general-purpose input / output terminal P1.3 of the microprocessor U10 constitutes the second enable signal output terminal of the control circuit 07, connected to the first drive module 031 to output a first enable signal; and the second general-purpose input / output terminal P1.3 of the microprocessor U10 constitutes the second enable signal output terminal of the control circuit 07, connected to the first drive module 031 to output a second trigger signal. The second drive module 032 is connected to output a second enable signal; the fourth general-purpose input / output terminal P1.4, the fifth general-purpose input / output terminal P1.5, the sixth general-purpose input / output terminal P1.6, and the seventh general-purpose input / output terminal P1.7 of the microprocessor U10 together constitute the second adjustment signal output terminal of the control circuit 07, which is connected to the second adjustment circuit 06 to output a second adjustment signal; the eighth general-purpose input / output terminal P1.8 and the ninth general-purpose input / output terminal P1 of the microprocessor U10 are also connected. 9. The tenth general-purpose input / output terminal P2.0 and the eleventh general-purpose input / output terminal P2.1 of the microprocessor U10 together constitute the first adjustment signal output terminal of the control circuit 07, which is connected to the first adjustment circuit 05 to output the first adjustment signal; the twelfth general-purpose input / output terminal P2.2, the thirteenth general-purpose input / output terminal P2.3, the fourteenth general-purpose input / output terminal P2.4, and the fifteenth general-purpose input / output terminal P2.5 of the microprocessor U10 together constitute the third... The adjustment signal output terminal is connected to the third adjustment circuit 09 to output the third adjustment signal; the sixteenth general-purpose input / output terminal P2.6 and the seventeenth general-purpose input / output terminal P2.7 of the microprocessor U10 together constitute the reset signal output terminal of the control circuit 07, which is connected to the latch circuit 02 to output the reset signal; the eighteenth general-purpose input / output terminal P2.8 and the nineteenth general-purpose input / output terminal P2.9 of the microprocessor U10 together constitute the wake-up signal input terminal of the control circuit 07, which is connected to the latch circuit 02 to receive the wake-up signal.

[0208] In some embodiments, optionally, please refer to Figure 11Both the first drive module 031 and the second drive module 032 include a drive unit. The drive unit includes a sixth latch U11, a MOSFET driver U12, a fourth diode D4, a fifth diode D5, a sixth diode D6, a first inductor L1, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a thirty-fourth resistor R34, a thirty-fifth resistor R35, a thirty-sixth resistor R36, a thirty-seventh resistor R37, and a thirty-eighth resistor R38. The clock terminal CP of the sixth latch U11 and the first terminal of the thirty-fourth resistor R34 are connected and together form the second trigger signal input terminal of the drive unit, which is connected to the control circuit 07 to receive the second trigger signal. The data terminal D of the sixth latch U11 and the first terminal of the thirty-fifth resistor R35 are connected and together form the enable signal input terminal of the drive unit, which is connected to the control circuit 07 to receive the first enable signal or the second enable signal; the main reset terminal / MR of the sixth latch U11, the power supply terminal Vcc of the sixth latch U11, the first terminal of the first capacitor C1 and the first terminal of the second capacitor C2 are connected to the first power supply VAA; the output terminal Q of the sixth latch U11 is connected to the first terminal of the thirty-sixth resistor R36; the second terminal of the thirty-sixth resistor R36 is connected to the first terminal of the thirty-seventh resistor R37 and the positive terminal of the fourth diode D4; the positive terminal of the fifth diode D5 constitutes the turn-off signal input terminal of the drive unit, which is connected to the latch. The circuit 02 is connected to receive the turn-off signal; the cathode of the fourth diode D4 is connected to the cathode of the fifth diode D5 and the input terminal IN of the MOSFET driver U12; the ground terminal GND of the MOSFET driver U12 is connected to the anode of the sixth diode D6 and the first terminal of the thirty-eighth resistor R38; the second terminal of the thirty-eighth resistor R38 is connected to the current detection terminal RS of the MOSFET driver U12; the switching terminal SW of the MOSFET driver U12 is connected to the first terminal of the first inductor L1; the second terminal of the first inductor L1, the power supply terminal Vcc of the MOSFET driver U12, the first terminal of the third capacitor C3, and the first terminal of the fourth capacitor C4 are all connected to the second power supply V. BB, the boost converter output terminal OUT of MOSFET driver U12 is connected to the second terminal of the third capacitor C3; the gate terminal Gate and the source terminal Source of MOSFET driver U12 together constitute the sub-drive signal output terminal of the drive unit, which is connected to the first drive module 031 or the second drive module 032 to output the first sub-drive signal or the second sub-drive signal; the second terminal of the thirty-fourth resistor R34, the second terminal of the thirty-fifth resistor R35, the second terminal of the first capacitor C1, the second terminal of the second capacitor C2, the second terminal of the thirty-seventh resistor R37, the cathode of the sixth diode D6, and the second terminal of the fourth capacitor C4 are all connected to the power supply ground.

[0209] This drive component can output or disconnect sub-drive signals under the excitation of multiple input signals, providing flexible drive control.

[0210] Understandably, in the first drive module 031, the data terminal D of the sixth latch U11 and the first terminal of the thirty-fifth resistor R35 are connected and together constitute the enable signal input terminal of the drive unit, which is connected to the control circuit 07 to receive the first enable signal; the gate terminal Gate and the source terminal Source of the MOSFET driver U12 together constitute the sub-drive signal output terminal of the drive unit, which is connected to the first drive module 031 to output the first sub-drive signal.

[0211] In the second drive module 032, the data terminal D of the sixth latch U11 and the first terminal of the thirty-fifth resistor R35 are connected and together form the enable signal input terminal of the drive unit, which is connected to the control circuit 07 to receive the second enable signal; the gate terminal Gate and the source terminal Source of the MOSFET driver U12 together form the sub-drive signal output terminal of the drive unit, which is connected to the second drive module 032 to output the second sub-drive signal.

[0212] The following is combined with Figure 10 and Figure 11 The circuit principle is explained as shown below:

[0213] Microprocessor U1 outputs a second adjustment signal from the fourth general-purpose input / output terminal P1.4, the fifth general-purpose input / output terminal P1.5, the sixth general-purpose input / output terminal P1.6, and the seventh general-purpose input / output terminal P1.7 of microprocessor U10 to the first input terminal a1, the second input terminal a2, the third input terminal a3, and the clock terminal CP of third latch U7. Third latch U7 latches the second adjustment signal, and the latched second adjustment signal controls the fourth field-effect transistor M4 to the sixth field-effect transistor M6 to turn on or off, thereby adjusting the resistance value of the first resistor network including the twenty-first resistor R21 to the twenty-fourth resistor R24. The first resistor network and the twentieth resistor R20 divide the voltage of the reference power supply VREF2 and output a second preset voltage to the non-inverting input terminal of the first comparator U2.

[0214] Microprocessor U1 outputs a first adjustment signal from the eighth general-purpose input / output terminal P1.8, the ninth general-purpose input / output terminal P1.9, the tenth general-purpose input / output terminal P2.0, and the eleventh general-purpose input / output terminal P2.1 of microprocessor U10 to the first input terminal a1, the second input terminal a2, the third input terminal a3, and the clock terminal CP of the fourth latch U8. The fourth latch U8 latches the first adjustment signal, and the latched first adjustment signal controls the seventh field-effect transistor M7 to the ninth field-effect transistor M9 to turn on or off, thereby adjusting the resistance value of the second resistor network including the twenty-sixth resistor R26 to the twenty-ninth resistor R29. The second resistor network and the twenty-fifth resistor R25 divide the voltage of the reference power supply VREF2 and output a first preset voltage to the inverting input terminal of the second comparator U3.

[0215] Microprocessor U1 outputs a third adjustment signal from the twelfth general-purpose input / output terminal P2.2, the thirteenth general-purpose input / output terminal P2.3, the fourteenth general-purpose input / output terminal P2.4, and the fifteenth general-purpose input / output terminal P2.5 of microprocessor U10 to the first input terminal a1, the second input terminal a2, the third input terminal a3, and the clock terminal CP of the fifth latch U9. The fifth latch U9 latches the third adjustment signal, and the latched third adjustment signal controls the tenth field-effect transistor M10 to the twelfth field-effect transistor M12 to turn on or off, thereby adjusting the resistance value of the third resistor network including the thirtieth resistor R30 to the thirty-third resistor R33, and then sets the first preset duration of the delay module U4 through the resistance value of the third resistor network.

[0216] When the battery assembly 90 is charging, the first resistor R1 samples the charging current of the battery assembly 90 to output a charging sampling signal to the positive input terminal IN+ and the negative input terminal IN- of the amplifier U1. The amplifier U1 outputs a charging detection signal to the inverting input terminal of the first comparator U2 and the positive input terminal of the second comparator U3 according to the reference voltage and the charging sampling signal. The second comparator U3 responds to the charging detection signal being less than the first preset voltage by outputting a first trigger signal (high level) to the input terminal IN of the delay module U4.

[0217] When the battery assembly 90 is discharging, the first resistor R1 samples the discharge current of the battery assembly 90 and outputs a discharge sampling signal to the positive input terminal IN+ and the negative input terminal IN- of the amplifier U1. The amplifier U1 outputs a discharge detection signal to the inverting input terminal of the first comparator U2 and the positive input terminal of the second comparator U3 according to the reference voltage and the discharge sampling signal. The first comparator U2 responds to the discharge detection signal being greater than the second preset voltage and outputs a first trigger signal (high level) to the input terminal IN of the delay module U4.

[0218] The delay module U4 responds to the first trigger signal having a duration longer than a first preset duration by outputting a first trigger signal (high level) after the first preset duration from its output terminal OUT. Since the second latch U6 does not receive a reset signal at this time, the gate of the third field-effect transistor M3 is pulled low from its output terminal Q. The main reset terminal / MR of the first latch U5 is high, so the output terminal of the first latch U5 is high. After passing through the third diode D3, a high-level turn-off signal is output to the first drive module 031 and the second drive module 032.

[0219] In the first driving module 031 and the second driving module 032, the positive terminal of the fifth diode D5 is connected to a high-level turn-off signal so that the gate terminal of the MOSFET driver U12 is at a low level, thereby turning off the first field-effect transistor M1 and the second field-effect transistor M2.

[0220] It should be noted that, simultaneously, after the third diode D3 outputs a high-level shutdown signal to the first drive module 031 and the second drive module 032, the first diode D1 and the second diode D2 output high-level wake-up signals to the eighteenth general-purpose input / output terminal P2.8 and the nineteenth general-purpose input / output terminal P2.9 of the microprocessor U10. According to the wake-up signal, the microprocessor U1 outputs a reset signal from the sixteenth general-purpose input / output terminal P2.6 and the seventeenth general-purpose input / output terminal P2.7 of the microprocessor U10 to the clock terminal CP and the data terminal D of the second latch U6. The output terminal Q of the second latch U6 jumps to a high level, so the main reset terminal / MR of the first latch U5 is low, and the output terminal of the first latch U5 is low. After the third diode D3, the output of the high-level shutdown signal to the first drive module 031 and the second drive module 032 stops.

[0221] In the first drive module 031 and the second drive module 032, the positive terminal of the fifth diode D5 is no longer connected to a high-level turn-off signal (i.e., a low level). At this time, when the first enable signal and the second trigger signal output by the microprocessor U1 are connected, the gate terminal of the MOSFET driver U12 in the first drive module 031 is at a high level, thereby turning on the first field-effect transistor M1. Furthermore, when the second enable signal and the second trigger signal output by the microprocessor U1 are connected, the gate terminal of the MOSFET driver U12 in the second drive module 032 is at a high level, thereby turning on the second field-effect transistor M2. Thus, charging current and charging voltage are transmitted.

[0222] Understandably, when charging with a small current and limiting the discharge output, the first field-effect transistor M1 is turned off and the second field-effect transistor M2 is turned on.

[0223] According to some embodiments of this application, this application also provides an electronic device, including a battery assembly and an overcurrent protection circuit of any of the above solutions.

[0224] Since electronic devices include overcurrent protection circuits based on any of the above solutions, the safety and reliability of the overcurrent protection circuits can be improved, and they can be applied to high-power scenarios.

[0225] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and not to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application, and they should all be covered within the scope of the claims and specification of this application. In particular, as long as there is no structural conflict, the various technical features mentioned in the embodiments can be combined in any way. This application is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

Claims

1. An overcurrent protection circuit, characterized in that, Connected to the battery assembly, including: A current detection circuit is used to output a first trigger signal in response to the charging current of the battery assembly being greater than a first preset current or the discharging current of the battery assembly being greater than a second preset current. The driving circuit, connected to the current detection circuit, is used to disconnect the output of the driving signal according to the first trigger signal; A switching circuit, connected to the driving circuit, is used to stop transmitting the charging current or the discharging current based on the disconnection of the driving signal.

2. The overcurrent protection circuit as described in claim 1, characterized in that, The current detection circuit includes: A sampling circuit is used to sample the charging current of the battery assembly to output a charging sampling signal, or to sample the discharging current of the battery assembly to output a discharging sampling signal. An amplifier circuit, connected to the sampling circuit, is used to output a charging detection signal based on a reference voltage and the charging sampling signal, or to output a discharging detection signal based on a reference voltage and the discharging sampling signal. A comparator circuit, connected to the amplifier circuit and the driver circuit, is used to output the first trigger signal in response to the charging detection signal being greater than a first preset voltage or the discharging detection signal being less than a second preset voltage. Wherein, the voltage of the charging detection signal is the difference between the reference voltage and the first amplified voltage, and the first amplified voltage is the product of the voltage and the gain of the charging sampling signal; The voltage of the discharge detection signal is the sum of the reference voltage and the second amplified voltage, where the second amplified voltage is the product of the voltage and the gain of the discharge sampling signal.

3. The overcurrent protection circuit as described in claim 2, characterized in that, The current detection circuit also includes: A first adjustment circuit, connected to the comparison circuit, is used to output the first preset voltage according to the first adjustment signal; The second adjustment circuit, connected to the comparison circuit, is used to output the second preset voltage according to the second adjustment signal.

4. The overcurrent protection circuit as described in claim 3, characterized in that, Also includes: A control circuit, connected to the first adjustment circuit and the second adjustment circuit, is used to respond to a small current charging command and output a first adjustment signal of a first state so that the first adjustment circuit outputs the first preset voltage located in a first numerical range.

5. The overcurrent protection circuit as described in claim 4, characterized in that, The control circuit is further configured to respond to a sleep command by outputting the first adjustment signal in the second state to cause the first adjustment circuit to output the first preset voltage located in the second numerical range, and outputting the second adjustment signal in the first state to cause the second adjustment circuit to output the second preset voltage located in the first preset range.

6. The overcurrent protection circuit as described in any one of claims 4 to 5, characterized in that, The control circuit is also configured to respond to an operating command by outputting the second adjustment signal of the second state so that the second adjustment circuit outputs the second preset voltage located in the second preset range.

7. The overcurrent protection circuit as described in any one of claims 4 to 6, characterized in that, The control circuit is also configured to respond to a wake-up command by outputting the first adjustment signal in the third state to make the first adjustment circuit output the first preset voltage in the third numerical range, and outputting the second adjustment signal in the third state to make the second adjustment circuit output the second preset voltage in the third preset range. The values ​​in the first numerical interval decrease sequentially to the values ​​in the third numerical interval; the values ​​in the first preset interval increase sequentially to the values ​​in the third preset interval.

8. The overcurrent protection circuit as described in any one of claims 1 to 7, characterized in that, Also includes: A delay circuit, connected to the current detection circuit, is used to output a first trigger signal after a first preset duration in response to the duration of the first trigger signal being greater than a first preset duration. The driving circuit is specifically used to disconnect the output of the driving signal according to the first trigger signal after a first preset time.

9. The overcurrent protection circuit as described in claim 8, characterized in that, Also includes: A third adjustment circuit, connected to the delay circuit, is used to adjust the first preset duration in the delay circuit according to a third adjustment signal.

10. The overcurrent protection circuit as described in claim 9, characterized in that, The control circuit is also connected to the third adjustment circuit and is further configured to respond to a low-current charging command by outputting the third adjustment signal in the first state so that the first preset duration of the delay circuit is located in the first interval.

11. The overcurrent protection circuit as described in any one of claims 9 to 10, characterized in that, The control circuit is also used to respond to a vehicle sleep command by outputting the third adjustment signal of the second state so that the first preset duration of the delay circuit is located in the second interval.

12. The overcurrent protection circuit as described in any one of claims 9 to 11, characterized in that, The control circuit is also used to respond to the vehicle operation command and output the third adjustment signal of the third state so that the first preset duration of the delay circuit is located in the third interval.

13. The overcurrent protection circuit as described in any one of claims 9 to 12, characterized in that, The control circuit is also used to respond to a vehicle wake-up command by outputting the third adjustment signal of the fourth state so that the first preset duration of the delay circuit is located in the fourth interval.

14. The overcurrent protection circuit as described in claim 1, characterized in that, The driving circuit includes: A latching module, connected to the current detection circuit, is used to latch the first trigger signal to output a turn-off signal; A drive module, connected to the latch module, is used to disconnect the output of the drive signal according to the turn-off signal.

15. The overcurrent protection circuit as described in claim 14, characterized in that, The latching module is specifically used to latch the first trigger signal in order to output the shutdown signal and the wake-up signal; The overcurrent protection circuit also includes a control circuit connected to the latch module; the control circuit is used to enter the working state according to the wake-up signal and output a reset signal; The latch module is also used to stop the output of the shutdown signal according to the reset signal; The driving circuit is also used to output the driving signal according to the shutdown signal, so that the switching circuit transmits the charging circuit or the discharging current according to the driving signal.

16. The overcurrent protection circuit as described in claim 15, characterized in that, The control circuit is also configured to stop outputting the reset signal in response to the fact that the number of times the wake-up signal is received within a second preset time period is greater than a preset number, so as to turn off the switching circuit.

17. The overcurrent protection circuit as described in claim 15, characterized in that, The control circuit is also used to output a second trigger signal, and to output a first enable signal and / or a second enable signal; The driving signal includes a first sub-driving signal and a second sub-driving signal; The driving circuit includes: The first driving module, connected to the control circuit and the switching circuit, is used to output the first sub-driving signal in response to the disconnection of the shutdown signal, according to the first enable signal and the second trigger signal. The second drive module, connected to the control circuit and the switching circuit, is used to output the second sub-drive signal in response to the disconnection of the shutdown signal, according to the second enable signal and the second trigger signal. The switching circuit is specifically used to transmit the charging current or the discharging current based on the first sub-driving signal and / or the second sub-driving signal.

18. The overcurrent protection circuit as described in claim 17, characterized in that, The switching circuit includes: A first switch is connected to the battery assembly and the first drive module, and is used to transmit the charging current or the discharging current according to the first sub-drive signal; The second switch, connected to the first switch and the second drive module, is used to transmit the charging current or the discharging current according to the second sub-drive signal.

19. An electronic device, characterized in that, The electronic device includes a battery assembly and an overcurrent protection circuit as described in any one of claims 1 to 18.

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