Inspection and manufacturing methods for chips and light-emitting elements

Abstract

According to aspects of this disclosure, a wafer, a method for inspecting light-emitting elements, and a method for manufacturing light-emitting elements are provided. The wafer includes a substrate, a plurality of light-emitting elements disposed on the substrate, a connection unit disposed between and connected to the plurality of light-emitting elements, and a support unit disposed between the connection unit and the substrate. The plurality of light-emitting elements are spaced apart from the substrate. Therefore, the plurality of light-emitting elements are spaced apart from the substrate to facilitate the separation of the light-emitting elements from the substrate in subsequent processes.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0174963, filed on November 29, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure relates to methods for inspecting and manufacturing wafers and light-emitting elements, and more specifically, to methods for inspecting and manufacturing wafers and light-emitting elements, on which effective inspection processes can be performed. Background Technology

[0004] As display devices used as monitors for computers, televisions, or cellular phones, there are organic light-emitting display (OLED) devices that are self-emissive and liquid crystal display (LCD) devices that require a separate light source.

[0005] The applications of display devices have diversified to include personal digital assistants and computer and television displays, and research is underway on display devices with large display areas and reduced size and weight.

[0006] Furthermore, in recent years, LED display devices have garnered attention as the next generation of display devices. Because LEDs are formed from inorganic rather than organic materials, they offer superior reliability, resulting in a longer lifespan compared to liquid crystal displays or organic light-emitting diode displays. In addition, LEDs possess fast light emission speed, excellent luminous efficiency, and strong shock resistance, leading to excellent stability and the ability to display high-brightness images. Summary of the Invention

[0007] The purpose of this disclosure is to provide a method for inspecting and manufacturing wafers and light-emitting elements that allows for rapid inspection processes.

[0008] Another objective of this disclosure is to provide a method for manufacturing a wafer on which defect inspection can be performed using a probe card with a simplified structure, as well as a method for manufacturing light-emitting elements.

[0009] Another objective of this disclosure is to provide a wafer, a method for inspecting light-emitting elements, and a method for manufacturing light-emitting elements that simply removes defective light-emitting elements from multiple light-emitting elements.

[0010] The purpose of this disclosure is not limited to the above-mentioned purposes, and other purposes not mentioned above will be clearly understood by those skilled in the art from the following description.

[0011] According to an aspect of this disclosure, a chip includes: a substrate; a plurality of light-emitting elements disposed on the substrate; a connecting unit disposed between and connected to the plurality of light-emitting elements; and a support unit disposed between the connecting unit and the substrate. The plurality of light-emitting elements are spaced apart from the substrate. Therefore, the plurality of light-emitting elements are spaced apart from the substrate to facilitate easy separation of the light-emitting elements from the substrate in subsequent processes.

[0012] According to an aspect of this disclosure, a method for inspecting light-emitting elements includes: fabricating a wafer on which a plurality of light-emitting elements are formed; and inspecting the plurality of light-emitting elements by contacting the wafer with a probe card. Inspecting the plurality of light-emitting elements includes contacting a common inspection electrode between the plurality of light-emitting elements and an individual electrode of each of the plurality of light-emitting elements with a plurality of pin electrodes of the probe card. Therefore, by means of the common inspection electrode, voltage is simultaneously applied to the plurality of light-emitting elements, thereby reducing the inspection time.

[0013] According to an aspect of this disclosure, a method for manufacturing a light-emitting element includes: forming an epitaxial layer including a buffer layer on a substrate; forming a plurality of light-emitting elements and connection units by etching the epitaxial layer; and forming a porous region and support units by etching the buffer layer. Thus, the buffer layer of the epitaxial layer is partially etched to form support units supporting the light-emitting elements and a porous region beneath the light-emitting elements.

[0014] Further details of the exemplary implementation are included in the detailed implementation and the accompanying drawings.

[0015] According to this disclosure, a porous region is formed between the light-emitting element and the substrate to facilitate the separation of the light-emitting element from the substrate in subsequent processes.

[0016] According to this disclosure, multiple light-emitting elements share a common inspection electrode, enabling simultaneous inspection of multiple light-emitting elements.

[0017] According to this disclosure, inspecting multiple light-emitting elements simultaneously saves inspection time for multiple light-emitting elements.

[0018] According to this disclosure, a buffer layer beneath the light-emitting element is partially etched using a photoresist pattern to form interconnect units and a porous structure, which allows the light-emitting element to be easily separated from the substrate.

[0019] The effects of this disclosure are not limited to those illustrated above, and this specification includes many more effects. Attached Figure Description

[0020] The foregoing and other aspects, features and other advantages of this disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0021] Figure 1 This is a plan view of a wafer according to an exemplary embodiment of the present disclosure;

[0022] Figure 2 It is along Figure 1 A cross-sectional view taken from A-A';

[0023] Figure 3 It is along Figure 1 A cross-sectional view of BB′;

[0024] Figure 4A and Figure 4B This is an inspection method for light-emitting elements according to an exemplary embodiment of the present disclosure; and

[0025] Figures 5A to 5H This is a process diagram illustrating a method for manufacturing a light-emitting element according to an exemplary embodiment of the present disclosure. Detailed Implementation

[0026] The advantages and features of this disclosure, as well as methods for achieving these advantages and features, will become clear from the exemplary embodiments described in detail below, together with the accompanying drawings. However, this disclosure is not limited to the exemplary embodiments disclosed herein, but will be implemented in various forms. The exemplary embodiments are provided by way of example only so that those skilled in the art can fully understand the disclosure and scope of this disclosure.

[0027] The shapes, dimensions, ratios, angles, numbers, etc., shown in the accompanying drawings to describe exemplary embodiments of this disclosure are merely examples, and this disclosure is not limited thereto. Throughout the specification, similar reference numerals generally denote similar elements. Furthermore, in the following description of this disclosure, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of this disclosure. Terms such as “comprising,” “having,” and “consisting of” as used herein are generally intended to allow for the addition of additional components, unless these terms are used in conjunction with the term “only.” Unless otherwise expressly stated, any reference to the singular may include the plural.

[0028] Even without explicit explanation, components are interpreted as including the normal tolerance range.

[0029] When using terms such as “on top of,” “above,” “below,” and “next to” to describe the positional relationship between two parts, one or more parts may be located between the two parts unless these terms are used with “immediately next to” or “directly.”

[0030] When an element or layer is placed "on" another element or layer, the other layer or element can be directly inserted onto or between the other element.

[0031] Although the terms "first," "second," etc., are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from other components. Therefore, the first component referred to below may be the second component in the technical concept of this disclosure.

[0032] Throughout the specification, similar reference numerals generally denote similar elements.

[0033] For ease of description, the dimensions and thickness of each component shown in the accompanying drawings are illustrated, and this disclosure is not limited to the dimensions and thickness of the components shown.

[0034] Features of various embodiments of this disclosure may partially or completely support or combine with each other, and may be chained and operated in technically different ways, and the embodiments may be performed independently or in association with each other.

[0035] In the following, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0036] Figure 1 This is a plan view of a wafer according to an exemplary embodiment of the present disclosure. Figure 2 It is along Figure 1 The cross-sectional view taken from A-A'. Figure 3 It is along Figure 1 The cross-sectional view of BB′.

[0037] Reference Figures 1 to 3 The wafer 100 is a component on which a plurality of light-emitting elements 120 are formed. The wafer 100 includes a substrate 110, a support unit 140, a common inspection electrode CE, and a plurality of light-emitting elements 120.

[0038] First, the substrate 110 is a substrate on which a plurality of light-emitting elements 120 are grown. Depending on the type of semiconductor material constituting the plurality of light-emitting elements 120, the substrate 110 can be formed of various materials. For example, the substrate 110 can be formed of sapphire, gallium nitride (GaN), silicon (Si) or silicon carbide (SiC), but is not limited thereto.

[0039] Multiple light-emitting elements 120 are disposed on a substrate 110. The multiple light-emitting elements 120 are semiconductor devices that emit light through current. The light-emitting elements 120 can be either light-emitting diodes (LEDs) or micro LEDs, but the exemplary embodiments of this disclosure are not limited thereto. After forming an epitaxial layer EPI by growing a semiconductor material, such as gallium nitride (GaN), on the substrate 110, the epitaxial layer is etched into multiple blocks to form the multiple light-emitting elements 120. Reference will be made below. Figures 5A to 5H This describes a detailed description of the manufacturing method of the plurality of light-emitting elements 120.

[0040] Each of the plurality of light-emitting elements 120 includes a first semiconductor layer 121, a light-emitting layer 122, a second semiconductor layer 123, and an independent electrode 124.

[0041] A first semiconductor layer 121 of a plurality of light-emitting elements 120 is disposed on a substrate 110, and a second semiconductor layer 123 is disposed on the first semiconductor layer 121. Either the first semiconductor layer 121 or the second semiconductor layer 123 is a semiconductor layer doped with an n-type impurity, and the other is a semiconductor layer doped with a p-type impurity. For example, the first semiconductor layer 121 and the second semiconductor layer 123 may be semiconductor layers doped with n-type or p-type impurities in materials such as gallium nitride (GaN), indium aluminum phosphide (InAlP), or gallium arsenide (GaAs). The p-type impurity may be magnesium (Mg), zinc (Zn), or beryllium (Be), and the n-type impurity may be silicon (Si), germanium, or tin (Sn), but is not limited thereto.

[0042] A light-emitting layer 122 is disposed between a first semiconductor layer 121 and a second semiconductor layer 123. The light-emitting layer 122 emits light based on the current supplied to the light-emitting element 120. For example, the light-emitting layer 122 may be formed of a single layer or a multiple quantum well (MQW) structure, and may be formed of, for example, indium gallium nitride (InGaN) or gallium nitride (GaN), but is not limited thereto.

[0043] An independent electrode 124 is disposed on the second semiconductor layer 123. The independent electrode 124 is configured with a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO), but is not limited thereto.

[0044] A connection unit 140 is disposed between the plurality of light-emitting elements 120. The connection unit 140 is a portion that connects to and is integrally formed with the plurality of first semiconductor layers 121. For example, the connection unit 140 extends from each of the plurality of first semiconductor layers 121 to the first semiconductor layer 121 of an adjacent light-emitting element 120. The connection unit 140 is configured such that it surrounds each of the plurality of first semiconductor layers 121. The plurality of first semiconductor layers 121 are connected to each other via the connection unit 140.

[0045] A support unit 130 is disposed between the connecting unit 140 and the substrate 110. The support unit 130 supports the connecting unit 140 to allow the connecting unit 140 to remain spaced from the substrate 110, so that the plurality of light-emitting elements 120 are also spaced from the substrate 110. The support unit 130 may be formed from a buffer layer 130a of a plurality of layers forming the epitaxial layer EPI.

[0046] A porous region AG is formed below a plurality of light-emitting elements 120 that are spaced apart from the substrate 110 by a support unit 130 and a connecting unit 140. That is, the plurality of light-emitting elements 120 and the connecting unit 140 are floated on the substrate 110 by the support unit 130, so that a porous region AG, which serves as an empty space, is formed between the plurality of light-emitting elements 120 and the substrate 110.

[0047] At the same time, refer to Figure 2 The width of the connecting unit 140 is greater than the width of the support unit 130. The connecting unit 140 is configured by overlapping portions with the support unit 130 and with the porous region AG. The thickness of the connecting unit 140 is less than the thickness of the first semiconductor layer 121. In this case, the light-emitting element 120 is separated from the substrate 110 by cutting the portion of the connecting unit 140 overlapping with the porous region AG. Furthermore, the thickness of the connecting unit 140 is formed to be less than the thickness of the first semiconductor layer 121, making it easier to cut the portion of the connecting unit 140 overlapping with the porous region AG. Therefore, when separating the light-emitting element 120 from the substrate 110, the connecting unit 140 is cut to separate the light-emitting element 120 from the connecting unit 140, the support unit 130, and the substrate 110.

[0048] Next, a common inspection electrode CE is disposed on the connection unit 140. The common inspection electrode CE is electrically connected to the first semiconductor layer 121 of the plurality of light-emitting elements 120 through the connection unit 140. The plurality of light-emitting elements 120 share a common inspection electrode CE. The common inspection electrode CE is a temporary electrode used for inspecting the light-emitting elements 120. After the inspection process of the light-emitting elements 120 is completed, the common inspection electrode CE is separated from the light-emitting elements 120. For example, the common inspection electrode CE may be formed of an opaque conductive material, such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or alloys thereof, but is not limited thereto.

[0049] Reference Figure 1 and Figure 3 Multiple openings OA are disposed in the region between multiple light-emitting elements 120. Multiple openings OA are formed in the connecting unit 140 and the buffer layer 130a. One of the multiple light-emitting elements 120 is disposed between a pair of openings OA. A portion of the edge of the light-emitting element 120 is opposite to the opening OA, and the other edges are connected to the connecting unit 140. The multiple openings OA are connected to the porous region AG.

[0050] When manufacturing multiple light-emitting elements 120, multiple openings OA are provided to form a porous region AG below the light-emitting elements 120. Etchant for the etching buffer layer 130a is injected through the multiple openings OA to form the porous region AG, as will be described below. Figures 5A to 5H To describe in more detail.

[0051] Figure 4A and Figure 4B This is an inspection method for light-emitting elements according to an exemplary embodiment of the present disclosure.

[0052] Reference Figure 4A The probe card PC is a component used to detect non-luminous defects in multiple light-emitting elements 120. For example, the probe card PC supplies current to multiple light-emitting elements 120 to detect defective light-emitting elements 120 that are not lit.

[0053] The probe card PC includes multiple pin electrodes PIN. The multiple pin electrodes PIN are electrodes that supply current to multiple light-emitting elements 120, and include multiple first pin electrodes PIN1 and second pin electrodes PIN2.

[0054] The plurality of first pin electrodes PIN1 are electrodes that contact the individual electrode 124 of each of the plurality of light-emitting elements 120. The plurality of first pin electrodes PIN1 apply voltage to the plurality of individual electrodes 124.

[0055] The second pin electrode PIN2 is an electrode that contacts the common inspection electrode CE. The second pin electrode PIN2 applies a voltage to the common inspection electrode CE, and the voltage applied from the second pin electrode PIN2 is applied to each of the plurality of first semiconductor layers 121 via the common inspection electrode CE and the connection unit 140. Although one second pin electrode PIN2 is shown in the figures, multiple second pin electrodes PIN2 may be provided, but the second pin electrode is not limited to this.

[0056] When inspecting multiple light-emitting elements 120, multiple pin electrodes PIN of the probe card PC can contact the common inspection electrode CE on the wafer 100 and the individual electrodes 124 of the light-emitting elements 120. By applying electrical signals from the multiple pin electrodes PIN to the common inspection electrode CE and the individual electrodes 124, current flows into the multiple light-emitting elements 120, illuminating them. Therefore, the probe card PC is used to supply current to multiple light-emitting elements to detect defective light-emitting elements 120 that are not lit.

[0057] Reference Figure 4B When a defective light-emitting element 120 that is not lit is detected, it is easy to remove only the defective light-emitting element 120. For example, when the light-emitting element 120 on the right side is defective, the connecting unit 140 supporting the light-emitting element 120 on the right side is irradiated with a laser to cut the connecting unit 140, and the light-emitting element 120 is separated from the substrate 110. Therefore, by irradiating the portion of the connecting unit 140 that overlaps with the porous region AG with a laser to cut the connecting unit 140, the defective light-emitting element 120 can be easily separated from the substrate 110 and removed.

[0058] Based on the inspection method for the light-emitting element 120 according to an exemplary embodiment of the present disclosure, multiple light-emitting elements 120 share a common inspection electrode CE, making it easier to light up multiple light-emitting elements 120 and shortening the inspection time. For example, by means of the common inspection electrode CE, voltage is simultaneously applied to the first semiconductor layer 121 of multiple light-emitting elements 120, making it easier to light up multiple light-emitting elements 120 simultaneously. Therefore, multiple light-emitting elements 120 are lit up simultaneously to perform the inspection process in one go, and the inspection time is shortened.

[0059] In the inspection method for the light-emitting element 120 according to an exemplary embodiment of the present disclosure, multiple light-emitting elements 120 share a common inspection electrode CE to reduce the number of pin electrodes PIN of the probe card PC used to illuminate the multiple light-emitting elements 120. For example, if the multiple light-emitting elements 120 do not share a common inspection electrode CE, but instead include separate inspection electrodes, the number of pin electrodes PIN for illuminating the multiple light-emitting elements 120 may increase. In contrast, the inspection method for the light-emitting element 120 according to an exemplary embodiment of the present disclosure uses only a plurality of first pin electrodes PIN1 in contact with the multiple light-emitting elements 120 and a second pin electrode PIN2 in contact with the common inspection electrode CE to perform the inspection process. Therefore, the structure of the probe card PC is simplified.

[0060] Based on the inspection method for light-emitting elements 120 according to an exemplary embodiment of the present disclosure, defective light-emitting elements 120 among the plurality of light-emitting elements 120 on the wafer 100 are selectively removed, and defective light-emitting elements 120 are prevented from entering the display device. For example, the plurality of light-emitting elements 120 disposed on the wafer 100 are inspected simultaneously to detect defective light-emitting elements 120. A portion of the connection unit 140 supporting the defective light-emitting element 120 is irradiated with a laser to cut the connection unit 140, making it easy to remove the defective light-emitting element 120 from the wafer 100. Therefore, with the plurality of light-emitting elements 120 disposed on the wafer 100, after removing the defective light-emitting elements 120 by performing the inspection process, the remaining normal light-emitting elements 120 are transferred to the display device to be used. Therefore, the occurrence of defective light-emitting elements 120 entering the display device is minimized, and the yield of the device using the light-emitting elements 120 of the wafer 100 according to the exemplary embodiment of the present disclosure can be improved.

[0061] In the following text, reference will be made to Figures 5A to 5H The manufacturing method of the light-emitting element 120 is described below.

[0062] Figures 5A to 5H This is a process diagram illustrating a method for manufacturing a light-emitting element according to an exemplary embodiment of the present disclosure. Figures 5A to 5E as well as Figure 5G and Figure 5H Based on Figure 3 The process diagram is shown in the cross-sectional view.

[0063] Reference Figure 5A An epitaxial layer EPI is formed on the substrate 110. The epitaxial layer EPI is a layer including a semiconductor layer forming a plurality of light-emitting elements 120, and is formed by growing a semiconductor crystal on the substrate 110.

[0064] The epitaxial layer EPI includes a buffer layer 130a, a first semiconductor material layer 121a, a light-emitting material layer 122a, and a second semiconductor material layer 123a. The epitaxial layer EPI is formed by sequentially growing the buffer layer 130a, the first semiconductor material layer 121a, the light-emitting material layer 122a, and the second semiconductor material layer 123a on a substrate 110.

[0065] The buffer layer 130a is formed of undoped gallium nitride (un-GaN) and is subsequently formed as the support unit 130. The first semiconductor material layer 121a is the layer that constitutes the first semiconductor layer 121 of the connection unit 140 and the light-emitting element 120. The light-emitting material layer 122a and the second semiconductor material layer 123a are the layers that constitute the light-emitting layer 122 and the second semiconductor layer 123 of the light-emitting element 120, respectively.

[0066] Next, an individual electrode 124 for each of the plurality of light-emitting elements 120 is formed on the epitaxial layer EPI. The individual electrode 124 is first formed on the epitaxial layer EPI before etching.

[0067] Reference Figure 5B Mesa-etching is performed on the epitaxial layer EPI. The epitaxial layer EPI is etched in the form of light-emitting elements 120. For example, the second semiconductor material layer 123a and the light-emitting material layer 122a are etched to form a plurality of second semiconductor layers 123 and a plurality of light-emitting layers 122, respectively. The first semiconductor material layer 121a is etched to form a plurality of first semiconductor layers 121 and interconnect units 140. When etching the first semiconductor material layer 121a, the first semiconductor material layer 121a located in the region between the light-emitting elements 120 is etched to retain the lower portion to form the interconnect units 140.

[0068] Next, a common inspection electrode CE is formed on the connection unit 140. The common inspection electrode CE is formed on the connection unit 140 such that it corresponds to the area where the support unit 130 is to be disposed.

[0069] Reference Figure 5C Multiple openings OA are formed in the region between multiple light-emitting elements 120. A portion of the connecting unit 140 and a portion of the buffer layer 130a overlapping with the multiple openings OA are etched to form multiple openings OA in the region between the multiple light-emitting elements 120. Furthermore, when forming the multiple openings OA, the remaining portion of the epitaxial layer EPI formed in the region other than the region where the light-emitting elements 120, support unit 130, and connecting unit 140 are disposed is also etched and removed.

[0070] Reference Figure 5DA photoresist PR is formed on wafer 100 and subjected to exposure. When forming the porous region AG and support unit 130, the photoresist PR is configured to guide partial removal of the buffer layer 130a beneath the light-emitting element 120. The porous region AG and support unit 130 are formed by partially removing the buffer layer 130a beneath the light-emitting element 120 based on the photoresist PR. Through an exposure and development process, the photoresist PR is formed into a photoresist pattern PRP.

[0071] At this time, in order to partially remove the buffer layer 130a disposed below the light-emitting element 120, the photoresist PR is configured as a bilayer structure with different development rates. Specifically, the photoresist PR includes a first photoresist PR1 and a second photoresist PR2. The first photoresist PR1 is formed of a material with a faster development rate, and for example, is formed of a release resist (LOR). The second photoresist PR2 is formed of a material with a slower development rate, and for example, is formed of a positive photoresist.

[0072] A first photoresist PR1 is formed in a plurality of openings OA. The first photoresist PR1 is configured to contact the buffer layer 130a to be removed. Furthermore, when there is an area on the outermost surface of the epitaxial layer EPI where the buffer layer 130a to be removed is exposed, the first photoresist PR1 is formed to contact the exposed buffer layer 130a. For example, in subsequent processing, the side surface to be removed is exposed to… Figure 5D The buffer layer 130a in the leftmost region allows the first photoresist PR1 to be formed in contact with the side surface of the buffer layer 130a.

[0073] A second photoresist PR2 is formed on the first photoresist PR1, thereby covering all the plurality of light-emitting elements 120 and the first photoresist PR1. The second photoresist PR2 is provided to cover the entire substrate 110.

[0074] Next, a mask is applied to the photoresist PR, and an exposure process is performed. The mask includes multiple opening regions MOA, and the multiple opening regions MOA of the mask overlap with multiple openings OA. A portion of the second photoresist PR2 exposed from the opening regions MOA of the mask is exposed to light to alter its chemical properties, making it easier to dissolve in the developer. At this time, the size of the opening regions MOA is formed to be smaller than the size of the openings OA, such that a portion of the second photoresist PR2 surrounding the side surface of the light-emitting element 120 is not exposed, while only the remaining portions of the second photoresist PR2 overlapping with the opening regions MOA are partially exposed.

[0075] Next, refer to Figure 5E A development process is performed to form a photoresist pattern PRP. A developer is applied to remove the exposed portion of the second photoresist PR2. The portion of the second photoresist PR2 that overlaps with the opening region MOA of the mask is removed by the developer, and the remaining portion of the second photoresist PR2 is formed into a photoresist pattern PRP configured such that it surrounds the side surface of the light-emitting element 120. The first photoresist PR1 exposed from the second photoresist PR2 is also removed together with the developer.

[0076] At this time, the development rate of the first photoresist PR1 can be faster than that of the second photoresist PR2. Therefore, during the development process, the first photoresist PR1 is completely removed, and an undercut structure UC is formed between the second photoresist PR2 and the side surface of the buffer layer 130a. Furthermore, the first photoresist PR1 is removed to expose the side surface of the buffer layer 130a.

[0077] Therefore, the second photoresist PR2 overlapping with the opening region MOA is removed by the development process, and the first photoresist PR1 is completely removed to form a photoresist pattern PRP. The photoresist pattern PRP covers the top and side surfaces of the light-emitting element 120 to protect the light-emitting element 120 from the etchant. The photoresist pattern PRP includes a photoresist opening POA overlapping with the opening OA, and in the photoresist opening POA, the side surface of the photoresist pattern PRP can form an undercut structure with the side surface of the buffer layer 130a. In addition, a portion of the outermost surface of the photoresist pattern PRP can form an undercut structure with the side surface of the buffer layer 130a.

[0078] Reference Figure 5E and Figure 5F The undercut structure is formed adjacent to the light-emitting element 120. For example, the undercut structure is disposed along the periphery of the opening OA and is disposed adjacent to the light-emitting element 120. Furthermore, the undercut structure is also disposed in the region of the outermost area of ​​the substrate 110 adjacent to the light-emitting element 120. For example, in... Figure 5F In this case, an undercut structure is formed on the lower side of the substrate 110 adjacent to the light-emitting element 120. Therefore, the undercut structure is formed in the peripheral region of the plurality of openings OA and in a portion of the outermost region of the substrate 110.

[0079] Next, refer to Figure 5F and Figure 5GAn etchant is applied to the undercut structure to etch the buffer layer 130a. The buffer layer 130a is patterned using a wet etching method. For example, the wafer 100 is immersed in the etchant so that the etchant can contact portions of the buffer layer 130a exposed from the photoresist pattern PRP. As the etchant, a solution for etching the buffer layer 130a can be used, and for example, a KOH solution can be used, but the etchant is not limited to these. At this time, the light-emitting element 120 surrounded by the photoresist pattern PRP can be protected from the etchant.

[0080] KOH solution is an etchant for gallium nitride (GaN) and has the characteristic of etching GaN in the horizontal direction but not in the vertical direction. Therefore, the buffer layer 130a, exposed from the photoresist pattern PRP and formed of gallium nitride, is etched in the horizontal direction by KOH solution. For example, as... Figure 5G As shown, etching is performed in the horizontal direction, and the width of the buffer layer 130a in the porous region AG below the light-emitting element 120 gradually decreases. Furthermore, in Figure 5F The buffer layer 130a is etched in the direction of the arrow.

[0081] The buffer layer 130a overlapping the light-emitting element 120 has a larger area exposed from the photoresist pattern PRP, allowing for faster etching by the etchant. For example, the portion of the buffer layer 130a located in the porous region AG and overlapping with the light-emitting element 120 has an undercut structure on both sides and is etched simultaneously in both directions. Finally, the buffer layer 130a below the light-emitting element 120 is completely removed to form the porous region AG. Furthermore, the buffer layer 130a located below the common inspection electrode CE has a narrower area exposed from the photoresist pattern PRP, resulting in less exposure to the etchant. Therefore, at least a portion of the buffer layer 130a located below the common inspection electrode CE is still configured as the support unit 130.

[0082] Finally, refer to Figure 5H After the etching process of the buffer layer 130a is completed, the photoresist pattern PRP is removed to complete the fabrication process of multiple light-emitting elements 120.

[0083] Based on the manufacturing method of the light-emitting element 120 according to an exemplary embodiment of the present disclosure, a buffer layer 130a is exposed from a photoresist pattern PRP to selectively etch only the buffer layer 130a to form a porous region AG and a support unit 130. A first photoresist PR1 with a faster development rate is formed between the buffer layers 130a, and a second photoresist PR2 with a slower development rate is formed between the light-emitting elements 120. Therefore, through exposure and development processes, the first photoresist PR1 is completely removed, and only the portion of the second photoresist PR2 covering the light-emitting elements 120 is retained. The buffer layer 130a exposed from the photoresist pattern PRP is etched to readily form the porous region AG beneath the light-emitting element 120 and the support unit 130 beneath the common inspection electrode CE. Therefore, based on the manufacturing method of the light-emitting element 120 according to an exemplary embodiment of the present disclosure, by partially etching the buffer layer 130a below the light-emitting element 120 to form a wafer 100, defective light-emitting elements can be easily removed from the wafer 100.

[0084] Exemplary implementations of this disclosure can also be described as follows:

[0085] According to aspects of this disclosure, the chip includes: a substrate; a plurality of light-emitting elements disposed on the substrate; a connecting unit disposed between and connected to the plurality of light-emitting elements; and a support unit disposed between the connecting unit and the substrate. The plurality of light-emitting elements are arranged to be spaced apart from the substrate.

[0086] Multiple light-emitting elements can be configured to be spaced apart from the substrate by a support unit of a support connection unit, so as to form a porous region between the multiple light-emitting elements and the substrate.

[0087] Each of the multiple light-emitting elements may include a first semiconductor layer, a light-emitting layer on the first semiconductor layer, a second semiconductor layer on the light-emitting layer, and an independent electrode on the second semiconductor layer, and the connection unit may be connected to the first semiconductor layer.

[0088] The connection unit can be integrally formed with the first semiconductor layer, and the thickness of the connection unit can be less than the thickness of the first semiconductor layer.

[0089] The connecting unit can be formed by the portion overlapping the porous region and the portion overlapping the support unit.

[0090] The chip may also include a common inspection electrode disposed on the connection unit.

[0091] The chip may also include an opening disposed between multiple light-emitting elements, and the opening may be connected to a porous region.

[0092] According to an aspect of this disclosure, a method for inspecting light-emitting elements includes: preparing a wafer on which a plurality of light-emitting elements are formed; and inspecting the plurality of light-emitting elements by contacting the wafer with a probe card, wherein inspecting the plurality of light-emitting elements includes: contacting a common inspection electrode between the plurality of light-emitting elements and an individual electrode of each of the plurality of light-emitting elements with a plurality of pin electrodes of the probe card.

[0093] The chip may include: a substrate below a plurality of light-emitting elements; a connecting unit disposed between the plurality of light-emitting elements and connecting the plurality of light-emitting elements to each other; and a support unit disposed between the connecting unit and the substrate, wherein the plurality of light-emitting elements and the connecting unit may be configured to be spaced apart from the substrate.

[0094] Each of the plurality of light-emitting elements may include: a first semiconductor layer connected to the connection unit; a light-emitting layer on the first semiconductor layer; and a second semiconductor layer between the light-emitting layer and an independent electrode, and when the plurality of light-emitting elements are inspected, the plurality of light-emitting elements may be configured to emit light by voltages from a common inspection electrode and the connection unit and voltages from the independent electrodes.

[0095] The inspection method for light-emitting elements may also include: after inspecting multiple light-emitting elements, removing defective light-emitting elements that do not emit light from among the multiple light-emitting elements.

[0096] Removing defective light-emitting elements may include cutting the connecting unit by irradiating it with a laser.

[0097] According to aspects of this disclosure, a method for manufacturing a light-emitting element includes: forming an epitaxial layer including a buffer layer on a substrate; forming a plurality of light-emitting elements and connection units by etching the epitaxial layer; and forming a porous region and a support unit by etching the buffer layer.

[0098] The epitaxial layer may include: a first semiconductor material layer on the buffer layer; a light-emitting material layer on the first semiconductor material layer; and a second semiconductor material layer on the light-emitting material layer. Forming a plurality of light-emitting elements and interconnecting units may include: forming a plurality of second semiconductor layers by etching the second semiconductor material layer; forming a plurality of light-emitting layers by etching the light-emitting material layer; and forming a plurality of first semiconductor layers and interconnecting units by etching the first semiconductor material layer.

[0099] The interconnect unit can connect multiple first semiconductor layers to each other.

[0100] Forming porous regions and support units by etching a buffer layer may include: forming multiple openings in the connection units and buffer layer in the region between multiple light-emitting elements; forming a photoresist pattern on the substrate; and etching the buffer layer.

[0101] Forming a photoresist pattern may include: forming a first photoresist in a plurality of openings; forming a second photoresist on the first photoresist, a plurality of light-emitting elements and connecting units; removing portions of the second photoresist that overlap with the plurality of openings, and removing all of the first photoresist, wherein the photoresist pattern may cover the top and side surfaces of the plurality of light-emitting elements, and a buffer layer may be exposed from the photoresist pattern.

[0102] The first photoresist can be formed from a material having a faster development rate than the second photoresist.

[0103] Etching the buffer layer can be a wet etching step by applying an etchant to the buffer layer, and the etchant can be a solution that etches the buffer layer in the horizontal direction.

[0104] When etching the buffer layer, the portion of the buffer layer that overlaps with multiple light-emitting elements can be removed to form a porous region, while the other portions of the buffer layer that overlap with the connecting units can be retained to form a support unit.

[0105] Although exemplary embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto and may be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, exemplary embodiments of the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are illustrative in all respects and do not limit the present disclosure. All technical concepts within the equivalent scope of the present disclosure should be construed as falling within the scope of the present disclosure.

Claims

1. A chip, comprising: substrate; Multiple light-emitting elements disposed on the substrate; A connecting unit is disposed between and connected to the plurality of light-emitting elements; as well as A support unit is disposed between the connecting unit and the substrate. The plurality of light-emitting elements are arranged to be spaced apart from the substrate.

2. The wafer according to claim 1, wherein, The plurality of light-emitting elements are configured such that they are spaced apart from the substrate by a support unit that supports the connecting unit, thereby forming a porous region between the plurality of light-emitting elements and the substrate.

3. The wafer according to claim 2, wherein, Each of the plurality of light-emitting elements includes: First semiconductor layer; A light-emitting layer on the first semiconductor layer; The second semiconductor layer on the light-emitting layer; and Independent electrodes on the second semiconductor layer, and The connection unit is connected to the first semiconductor layer.

4. The wafer according to claim 3, wherein, The connection unit is integrally formed with the first semiconductor layer, and the thickness of the connection unit is less than the thickness of the first semiconductor layer.

5. The wafer according to claim 3, wherein, The connecting unit is formed by a portion overlapping the porous region and a portion overlapping the support unit.

6. The wafer according to claim 3, further comprising: A common inspection electrode is provided on the connection unit.

7. The wafer according to claim 2, further comprising: An opening is provided between the plurality of light-emitting elements. The opening is connected to the porous region.

8. The wafer according to claim 6, wherein, The common inspection electrode is electrically connected to the first semiconductor layer of the plurality of light-emitting elements through the connection unit.

9. A method for inspecting a light-emitting element, comprising: Prepare a wafer according to any one of claims 1 to 8; as well as The plurality of light-emitting elements are inspected by contacting the wafer with a probe card. The inspection of the plurality of light-emitting elements includes: contacting the common inspection electrode among the plurality of light-emitting elements and the individual electrode of each of the plurality of light-emitting elements with the plurality of pin electrodes of the probe card.

10. The method for inspecting a light-emitting element according to claim 9, wherein, When inspecting the plurality of light-emitting elements, the plurality of light-emitting elements are configured to emit light by voltages from the common inspection electrode and the connection unit, as well as voltages from the individual electrodes.

11. The method for inspecting a light-emitting element according to claim 10, further comprising: After inspecting the plurality of light-emitting elements, remove any defective light-emitting elements that are not emitting light.

12. The method for inspecting a light-emitting element according to claim 11, wherein, Removing defective light-emitting elements includes: The connecting unit is cut by irradiating it with a laser.

13. The method for inspecting a light-emitting element according to claim 9, wherein, The plurality of pin electrodes includes a plurality of first pin electrodes in contact with the plurality of light-emitting elements and a second pin electrode in contact with the common inspection electrode.

14. A method for manufacturing a light-emitting element, comprising: An epitaxial layer including a buffer layer is formed on the substrate; Multiple light-emitting elements and interconnect units are formed by etching the epitaxial layer; as well as The buffer layer is etched to form porous regions and support units.

15. The method for manufacturing a light-emitting element according to claim 14, wherein, The epitaxial layer includes: A first semiconductor material layer on the buffer layer; A light-emitting material layer on the first semiconductor material layer; and A second semiconductor material layer on the light-emitting material layer, and The formation of multiple light-emitting elements and connection units includes: Multiple second semiconductor layers are formed by etching the second semiconductor material layer, multiple light-emitting layers are formed by etching the light-emitting material layer, and multiple first semiconductor layers and the connection unit are formed by etching the first semiconductor material layer.

16. The method for manufacturing a light-emitting element according to claim 15, wherein, The connection unit connects the plurality of first semiconductor layers to each other.

17. The method for manufacturing a light-emitting element according to claim 14, wherein, Forming porous regions and support units by etching the buffer layer includes: Multiple openings are formed in the connecting unit and the buffer layer in the region between the plurality of light-emitting elements; A photoresist pattern is formed on the substrate; and The buffer layer is etched.

18. The method for manufacturing a light-emitting element according to claim 17, wherein, Forming photoresist patterns includes: A first photoresist is formed in the plurality of openings; A second photoresist is formed on the first photoresist, the plurality of light-emitting elements, and the connecting unit; A mask comprising multiple opening regions is formed on the second photoresist, and Remove the portion of the second photoresist that overlaps with the plurality of opening regions, and remove all of the first photoresist. The photoresist pattern covers the top and side surfaces of the plurality of light-emitting elements, and the buffer layer is exposed from the photoresist pattern.

19. The method for manufacturing a light-emitting element according to claim 18, wherein, The first photoresist is formed of a material having a development rate that is faster than that of the second photoresist.

20. The method for manufacturing a light-emitting element according to claim 17, wherein, Etching the buffer layer is a wet etching step performed by applying an etchant to the buffer layer, wherein the etchant is a solution that etches the buffer layer in the horizontal direction.

21. The method for manufacturing a light-emitting element according to claim 20, wherein, When etching the buffer layer, the portion of the buffer layer that overlaps with the plurality of light-emitting elements is removed to form the porous region, and at least a portion of the buffer layer that overlaps with the connecting unit is retained to form the support unit.

22. The method for manufacturing a light-emitting element according to claim 18, wherein, The mask has multiple opening regions that overlap with multiple openings, and the size of the opening regions is formed to be smaller than the size of the openings.

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