A method and system for anisotropic patterning correction of wafer warpage
By designing and fabricating a patterned stress balancing layer, the problem that traditional uniform stress balancing layers cannot correct complex warpages was solved, achieving precise and designable correction of wafer warpage.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHENZHEN UNIV
- Filing Date
- 2026-01-27
- Publication Date
- 2026-06-02
AI Technical Summary
Traditional uniform stress balancing layers are difficult to accurately correct complex warped morphologies such as saddle-shaped surfaces and parabolic cylinders, and cannot provide direction-specific curvature compensation.
By obtaining the anisotropic curvature compensation value of the wafer to be corrected, a patterned stress balance layer is designed using inversion calculation and quantitative relationship model, and a stress balance layer with a specific pattern is prepared to achieve anisotropic curvature compensation.
It achieves precise correction of complex warped morphologies, provides a predictable and designable correction process, ensures correction accuracy and repeatability, and can independently control the degree of anisotropy.
Smart Images
Figure CN122138706A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of advanced electronic packaging technology, specifically to a method and system for anisotropic patterning correction of wafer warpage. Background Technology
[0002] In semiconductor manufacturing, advanced packaging, and microelectromechanical systems (MEMS) processing, wafer (or substrate) warpage is a common and critical issue that significantly impacts process yield and device performance. Wafer warpage is primarily caused by stress mismatch introduced during multilayer thin film deposition and patterning processes on its front side, as well as differences in the coefficients of thermal expansion during subsequent thermal processing. To correct or suppress wafer warpage, various methods have been developed: First, external force is applied to forcefully flatten the wafer using clamping equipment such as electrostatic chucks or vacuum chucks, but this can easily damage wafers with significant warpage or thin wafers and cannot eliminate the root cause of internal stress. Second, warpage is suppressed by temporarily bonding the wafer to glass or silicon substrates and thinning and grinding, but this increases bonding and adhesive removal processes and may introduce new warpage due to material incompatibility. Third, stress distribution is adjusted using thermal treatments such as laser annealing or localized thermal gradients, but this may conflict with the device's thermal budget and introduce new thermal stress.
[0003] In recent years, back-side stress balancing layer engineering has been regarded as a long-term systematic solution for fundamentally correcting wafer warpage. This involves introducing a continuous, uniform stress film on the back side of the wafer as a stress balancing layer. This film generates a torque opposite to the stress effect on the front side through its inherent tensile or compressive stress, thereby restoring the wafer to a flat state or achieving a controllable bending state.
[0004] However, existing stress balancing methods based on continuous uniform thin films have significant limitations: they typically only produce approximately isotropic, spherically symmetric curvature compensation. This is because the stress state of a uniformly deposited film is usually isotropic within the wafer surface, resulting in essentially the same bending effect in any direction. In reality, wafer warpage morphologies produced in actual processes are often complex and diverse, not simply spherical curvature, but commonly include saddle-shaped (saddle-shaped surface), parabolic cylindrical, and other warpages with significant anisotropic characteristics. Faced with such complex warpages, traditional uniform stress balancing layers struggle to provide direction-specific corrective forces, failing to achieve precise and consistent global correction. Summary of the Invention
[0005] The purpose of this invention is to provide an anisotropic patterning correction method and system for wafer warpage, in order to solve the problem mentioned in the background art that the traditional back uniform stress balancing layer cannot generate anisotropic curvature compensation that matches the warpage morphology when correcting complex warpages (such as saddle-shaped surfaces, parabolic cylinders, etc.), resulting in poor correction effect or failure.
[0006] To achieve the above objectives, the present invention adopts the following technical solution: According to one aspect of the present invention, an anisotropic patterning correction method for wafer warpage is provided, the method comprising: Obtain the target anisotropic curvature compensation value of the wafer to be corrected, including the curvature compensation value in the first direction and the curvature compensation value in the second direction, which are perpendicular to each other; Based on the curvature compensation values in the first and second directions, the mechanical parameters of the wafer substrate, and the preset patterned stress balance layer thickness, the target equivalent thin film stress values that the stress balance layer needs to achieve in the first and second directions are calculated by inversion. Taking the patterned stress balance layer as the design object, the geometric parameters of the patterned stress balance layer are determined by a quantitative relationship model based on the target equivalent film stress value, the intrinsic stress of the selected film material, and Poisson's ratio. The quantitative relationship model is used to characterize the mapping relationship between the geometric parameters and the anisotropic equivalent film stress generated by the patterned stress balance layer. Based on the geometric parameters, a corresponding patterned stress balancing layer is prepared on the back side of the wafer to complete warpage correction.
[0007] Based on the aforementioned scheme, obtaining the target anisotropic curvature compensation value of the wafer to be corrected includes measuring the current warp morphology of the wafer to be corrected, obtaining the current curvature value C1 along the first direction and the current curvature value C2 along the second direction; and according to the preset target curvature value C... 1,target With C 2,target The curvature compensation value κ1=C in the first direction is calculated. 1,target -C1, and the second direction curvature compensation value κ2=C 2,target -C2.
[0008] Based on the aforementioned scheme, the inversion calculation is performed using a modified Stoney formula: ; Wherein, κ1 is the curvature compensation value in the first direction, and κ2 is the curvature compensation value in the second direction. The target equivalent thin film stress value in the first direction. This represents the target equivalent thin film stress value in the second direction. E s The Young's modulus of the wafer substrate, ν s t is the Poisson's ratio of the wafer substrate, t is the preset patterned stress balance layer thickness, and h is the thickness of the wafer substrate.
[0009] Based on the aforementioned scheme, the quantitative relationship model includes a dimensionless function for characterizing the stress relaxation effect at the edge of the thin wire. .
[0010] Based on the aforementioned scheme, the dimensionless function It's about the aspect ratio of the thin line. The function, with the expression: ; Where t is the thickness of the wire, b is the width of the wire, and m is the thickness of the wire. j It is a constant sequence.
[0011] Based on the aforementioned scheme, the pattern of the patterned stress balance layer is an array of fine lines extending in a single direction.
[0012] Based on the aforementioned scheme, the pattern of the patterned stress balance layer is a composite pattern composed of two or more sub-patterns with different extension directions.
[0013] Based on the aforementioned scheme, the patterned stress balancing layer is composed of two or more thin film materials with different intrinsic stresses.
[0014] Based on the aforementioned scheme, the patterned stress balancing layer is composed of two or more layers of patterned thin films stacked together, each layer having an independent pattern and / or material properties.
[0015] According to another aspect of the present invention, an anisotropic patterning correction system for wafer warpage is provided, the system comprising a measurement and setting module, a calculation module, a parameter design module, and a patterning preparation module; The measurement and setting module is used to provide target curvature compensation values for the wafer to be corrected in two mutually perpendicular directions; The calculation module is used to calculate the required target equivalent thin film stress value based on the target curvature compensation value, wafer substrate parameters, and preset patterned stress balance layer thickness. The parameter design module is used to determine the geometric parameters of the patterned stress balance layer based on a quantitative relationship model according to the target equivalent thin film stress value and the thin film material parameters. The quantitative relationship model characterizes the mapping relationship between the geometric parameters and the anisotropic equivalent thin film stress. The patterning preparation module is used to prepare the patterned stress balance layer on the back side of the wafer according to the geometric parameters.
[0016] As can be seen from the above technical solution, the present invention has at least the following advantages and positive effects compared with the prior art: By designing and fabricating a stress balance layer with a specific pattern on the back side of the wafer, the anisotropic control of the overall thin film stress state of the back stress layer is realized in principle; this enables the independent design of curvature compensation in both size and direction for warp differences in different directions of the wafer, thereby accurately adapting to and correcting various complex asymmetric warp morphologies such as bowl-shaped surfaces, saddle-shaped surfaces, and parabolic cylinders. Starting from the measured anisotropic curvature compensation target, the required equivalent stress is calculated through a mechanical inversion model, and then the specific pattern geometric dimensions are accurately solved by a quantitative relationship model that reveals the mapping relationship between pattern geometric parameters and equivalent stress; this achieves predictability and designability of the correction process, ensuring correction accuracy and repeatability. By adjusting the geometric parameters of a single pattern (especially the aspect ratio), the degree of anisotropy can be adjusted within a continuous range, and even the curvature compensation direction can be reversed. Furthermore, by combining sub-patterns of different directions, materials, and sizes, design flexibility and control freedom are provided.
[0017] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit the invention. Attached Figure Description
[0018] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention. It is obvious that the drawings described below are merely some embodiments of the invention, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort. In the drawings: Figure 1 This is a schematic diagram of an anisotropic patterning correction method for wafer warpage according to the present invention. Figure 2 This is a schematic diagram of a combined pattern design for the patterned stress balance layer of the present invention; Figure 3 This is a schematic diagram of an anisotropic patterning correction system for wafer warping according to the present invention. Detailed Implementation
[0019] To more clearly illustrate the purpose, technical solutions, and advantages of the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein. On the contrary, these embodiments are provided so that the present invention will be more comprehensive and complete, and fully convey the concept of the exemplary embodiments to those skilled in the art.
[0020] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a full understanding of embodiments of the invention. However, those skilled in the art will recognize that the technical solutions of the invention can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of the invention.
[0021] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities can be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.
[0022] The flowcharts shown in the accompanying drawings are merely illustrative and do not necessarily include all content and operations / steps, nor do they necessarily have to be performed in the described order. For example, some operations / steps can be broken down, while others can be combined or partially combined; therefore, the actual execution order may change depending on the specific circumstances.
[0023] The present invention will now be described in detail with reference to specific embodiments.
[0024] Example 1
[0025] like Figure 1 As shown, this embodiment provides a method for anisotropic patterning correction of wafer warpage. The specific steps of this method are as follows: S1: Obtain the target anisotropic curvature compensation value of the wafer to be corrected, including the curvature compensation value in the first direction and the curvature compensation value in the second direction, which are perpendicular to each other.
[0026] Non-contact surface topography measurement instruments, such as laser interferometers, white-light interferometers, or phase measurement deflection systems, are used to scan and measure the entire wafer or key areas to be corrected, acquiring its three-dimensional topography data, i.e., the current warp topography of the wafer. During measurement, the wafer is supported in a way that minimizes elastic deformation introduced by gravity, such as using three-point back-support, multi-point edge support, or electrostatic chucks, to make it as close as possible to a free state without external mechanical constraints, thereby ensuring that the measured topography data can accurately reflect its intrinsic warp. Surface fitting is performed on the obtained discrete height coordinate data, and by calculating the second derivative of the fitted surface in each principal direction, the distribution characteristics of the wafer surface curvature or radius of curvature can be obtained. Among them, the distribution characteristics of wafer surface curvature or radius of curvature, parameters characterizing the degree of bending at various points or the whole wafer surface and their spatial variations; discrete height coordinate data, obtained by scanning with a non-contact surface topography measuring instrument, is a dataset representing the height of each measurement point on the wafer surface relative to a selected reference plane. This data can be represented as each grid node (X) on a planar grid defined by the X and Y axes. i , Y i The Z-coordinate value corresponding to ) i .
[0027] Based on the obtained three-dimensional topography data, the curvature characteristics of the wafer to be corrected in its current state are determined. Specifically, surface fitting is performed on the topography data (e.g., fitting to a quadratic surface using the least squares method) to obtain a continuous surface function; the curvature values of the fitted surface along two predefined and mutually perpendicular global reference directions are calculated. In this embodiment, these two reference directions are defined as a first direction (e.g., the x-direction) and a second direction (e.g., the y-direction), and the current curvature value C1 of the wafer along the first direction and the current curvature value C2 along the second direction are calculated. In this embodiment, when the wafer surface is convexly curved along a certain reference direction (i.e., the center of curvature is located on one side of the back side of the wafer), the curvature value in that direction is defined as positive; conversely, when it is concavely curved, the value is negative.
[0028] Furthermore, the target curvature state of the wafer after correction is set according to process requirements. This target state can be a perfectly flat ideal state (i.e., target curvature value C). 1,target =0, C 2,target =0), or a slightly curved state preset to meet specific needs. Calculate the required target curvature compensation values κ1 and κ2, which are to transform the wafer from the current curvature state (C1, C2) to the aforementioned target curvature state (C... 1,target C 2,target The required change in curvature. Its quantitative relationship is: κ1 = C 1,target -C1;κ2=C 2,target-C2. The resulting set of curvature compensation values κ1 and κ2 quantifies the magnitude and direction of the bending correction amounts introduced in the first and second directions, respectively, to counteract the existing warping. This set of anisotropic curvature compensation values constitutes the basic input parameters for subsequent stress design and patterning implementation. Its non-zero and anisotropic (κ1≠κ2) characteristics are the basis for this method to effectively correct complex asymmetric warping such as saddle-shaped surfaces.
[0029] Optionally, when correcting known typical warpage patterns caused by fixed process root causes (such as specific morphologies caused by stress mismatch in multilayer thin films in the front-end process), target curvature compensation values κ1 and κ2 can be directly defined based on historical data, process simulation, or empirical formulas, without the need for real-time morphology measurement and calculation for each wafer; this mode is suitable for efficient correction of common warpage problems in mass production.
[0030] S2: Based on the curvature compensation values in the first and second directions, the mechanical parameters of the wafer substrate, and the preset patterned stress balance layer thickness, the target equivalent thin film stress values that the stress balance layer needs to achieve in the first and second directions are calculated by inversion.
[0031] Obtain or set the necessary parameters for the calculation, including the mechanical parameters of the wafer substrate and the thickness of the wafer under the current process conditions. h (Known quantities), and the pre-defined physical thickness of the thin film for the patterned stress balance layer. t Among these, the mechanical parameters of the wafer substrate include the Young's modulus of the wafer substrate. E s Compared to Poisson ν s This is an inherent property of wafer materials (such as single-crystal silicon), which can be obtained by consulting material databases or through standard mechanical tests. The thickness of the stress balance layer... t The deposition capability of the selected thin film material, the subsequent patterning accuracy requirements, and its relationship with the overall wafer thickness need to be considered. h Proportional relationship (usually (To be preset)
[0032] The target curvature compensation values κ1 and κ2 obtained in step S1 (corresponding to curvature compensation in the first and second directions, respectively), along with the aforementioned parameters: Young's modulus E s Poisson's ratio ν s Thickness of the stress balancing layer t and wafer thickness h Substitute the following set of mechanical equations based on the modified Stoney formula: ; This set of equations describes the in-plane anisotropic biaxial stress on a thin substrate. , The curvature change caused by the thin film layer.
[0033] Based on the modified Stoney formula, the target equivalent thin film stress value is further derived. and The required intrinsic relationships must be satisfied to match the typical warping morphology of different types. Specifically, two combination quantities directly related to the corrective effect are defined: and According to the formula It can be seen that, K 1 and K 2 The sign and magnitude of these values directly determine the direction and relative magnitude of the resulting curvature compensations κ1 and κ2. Based on this: For the correction of bowl-shaped (spherical) surface warping, the target equivalent film stress must meet the following requirements: ; Right now K 1 and K 2 Same number.
[0034] For the correction of saddle-shaped surface warping, the target equivalent film stress must satisfy: ; Right now K 1 and K 2 Different sign.
[0035] For the correction of parabolic cylindrical warping, the target equivalent membrane stress must satisfy:
[0036] Right now K 1 and K 2 One of them is zero.
[0037] Determine the target stress based on the above relationship. and The constraint conditions are used as optimization objectives or verification criteria in subsequent inversion calculations and model solving in step S3, thereby ensuring that the final designed patterned stress balance layer can produce anisotropic curvature compensation that accurately matches the warped shape to be corrected.
[0038] Inversion calculations solve the above equations to obtain the target equivalent film stress value that the stress balance layer needs to achieve: and : ; Calculated and The curvature compensation was quantified, and the patterned stress balance layer was required to present an average stress level overall. This manifests as the stress anisotropy state necessary to generate anisotropic curvature compensation. and The sign (positive for tensile stress, negative for compressive stress) and relative magnitude together determine the direction and distribution of the corrective torque, so as to specifically counteract different types of warping shapes such as bowl-shaped (same sign curvature) and saddle-shaped (opposite sign curvature).
[0039] It is necessary to check whether the calculation result is within the stress range achievable by the selected thin film material through the process; if it is outside this range, it indicates that the currently preset thin film thickness t is unsuitable, and it is necessary to go back and adjust the preset stress layer thickness. t And recalculate until a physically realizable result is obtained. and .
[0040] S3: Taking the patterned stress balance layer as the design object, the geometric parameters of the patterned stress balance layer are determined by a quantitative relationship model based on the target equivalent thin film stress value, the intrinsic stress of the selected thin film material, and Poisson's ratio.
[0041] In this embodiment, the input parameters include: the target equivalent thin film stress determined in step S2. and The intrinsic stress σ0 of the selected thin film material under uniform, patternless deposition (obtainable through process calibration); and the Poisson's ratio ν of the thin film material. f In this embodiment, the basic premise is to design a thin line array that extends along a single direction (e.g., the y-direction), where the length direction of the thin line is defined as the second direction (y-direction) and the width direction is defined as the first direction (x-direction).
[0042] Furthermore, a quantitative relationship model is applied to characterize the mapping relationship between geometric parameters and the anisotropic equivalent film stress generated by the patterned stress equilibrium layer, considering the edge stress relaxation effect caused by the three-dimensional structure of the fine wires. For a unidirectional fine wire array, the quantitative relationship between its macroscopic equivalent film stress and microscopic geometric parameters and material properties is defined by the following set of equations: ; in, , The target equivalent stress is input (corresponding to the x, y directions); σ0, ν ft, b, d are the input thin film material properties; t, b, d are the geometric parameters of the thin wire to be solved, representing the thickness, width and center distance between adjacent thin wires, respectively. The dimensionless function characterizing the stress relaxation effect at the edge of a thin wire is defined as: ; In the formula, m j The sequence is a constant and can be determined through theoretical derivation and numerical fitting methods. In practical applications, it can be adjusted and optimized accordingly. Example parameter values are shown in Table 1. Table 1
[0043] Furthermore, a model based on process constraints is used for solving. Because this system of equations contains... t , b , d With three unknowns but only two equations, a unique solution must be determined by considering process constraints. The following strategy is typically used to obtain a definite solution: 1) Based on the actual situation of the manufacturing process, set stable or restricted parameters in advance; usually, based on the uniformity and controllability of the thin film deposition process, preset the film thickness t; or, based on the resolution limit of the photolithography process, preset the minimum linewidth b or minimum spacing d.
[0044] 2) Using the preset parameters as known quantities, solve for the remaining two parameters (e.g., the Newton-Raphson iteration method) using numerical methods. b and d ), so that it precisely satisfies the system of equations; the solution process ensures that the obtained geometric parameters ( b , d All values are positive and satisfy the following conditions: b < d This is to ensure the lines are separated.
[0045] A set of parameters obtained by solving ( t , b , d The unique definition of the target stress () , A fine line array pattern. By adjusting the aspect ratio ( t / b ) and duty cycle ( b / d The degree of anisotropy is controlled by the aspect ratio (). t / b ) is control and The key factor in relative size. It is predicted that there is a critical aspect ratio; when actually designed... t / bWhen the value exceeds this critical value, κ1 and κ2 will have opposite signs, thus generating the alternating positive and negative bending moments required to correct the saddle-shaped warping. The obtained linewidth needs to be verified. b and spacing d Is it within the capabilities of the current photolithography and etching processes? If not, you need to go back, adjust the preset parameters, and solve it again.
[0046] S4: Based on the combination of key geometric parameters, a corresponding patterned stress balancing layer is prepared on the back side of the wafer to complete warpage correction.
[0047] Based on a defined combination of key geometric parameters (t, b, d), a fine line array pattern with predetermined geometric features is fabricated on the back side of the wafer using conventional semiconductor microfabrication processes (such as standard procedures including thin film deposition, photolithography, and etching). This constructs an anisotropic stress balance layer, thereby correcting wafer warpage. Preferably, the wafer warpage state is retested after fabrication to verify the correction effect.
[0048] It should be noted that the aforementioned design method for unidirectional fine-line arrays, based on its quantitative relationship model, can derive the curvature compensation ratio generated in two orthogonal directions of the wafer for an array of the same material and in a single direction. / There are theoretical limits to controllability. When using a single material and a unidirectional pattern, what can be achieved... / The ratio is limited to a certain numerical range; although this range can cover most common anisotropic warping correction needs (such as certain bowl-shaped or saddle-shaped surface adjustments), for some special and complex warping morphologies that require extreme stress ratios or specific non-limit ratios, the design freedom of a single pattern may be insufficient.
[0049] Therefore, the patterned design of the wafer backside stress balancing layer proposed in this embodiment, based on the same core principle of controlling macroscopic equivalent stress through geometric patterns, can be further extended to create a variety of patterned styles to achieve more flexible or complex stress control goals. For example... Figure 2As shown, a composite pattern design is provided, in which the patterned stress balance layer is composed of two different sub-pattern units, pattern A and pattern B, which are periodically alternating in a plane and covering the entire area. In one embodiment, pattern A and pattern B can be arrays of fine lines with different extension directions, such as pattern A being an array extending along a first direction (e.g., the x-direction) and pattern B being an array extending along a second direction orthogonal to it (e.g., the y-direction); preferably, the fine line arrays can be arranged and combined in multiple extension directions. In one embodiment, pattern A and pattern B can be designed as a grid pattern composed of two sets of orthogonal fine line arrays interlaced; by combining sub-pattern units with different extension directions and different geometric feature dimensions (e.g., width, spacing) in a specific area ratio, a composite patterned stress layer with a predetermined macroscopic anisotropic stress state can be synthesized. In one embodiment, the stress balance layer can be composed of two or more types of units with different intrinsic stresses (σ0) and different Poisson's ratios (ν). f The thin film material can be used; for example, fine lines formed from materials with high tensile stress can be combined and arranged with fine lines formed from materials with high compressive stress. In another embodiment, the patterned stress balancing layer can be composed of two or more stacked patterned thin films; each layer has an independent pattern and / or material properties.
[0050] By independently designing the material, orientation, geometry, and area proportion of each sub-pattern, the final stress tensor can be continuously and independently controlled over a wider range. and The numerical value and ratio, thereby achieving the... / A wider range of adjustment for the ratio.
[0051] Example 2
[0052] like Figure 3 As shown in the figure, this embodiment exemplarily presents an anisotropic patterning correction system for wafer warpage, including a measurement and setting module, a calculation module, a parameter design module, and a patterning preparation module.
[0053] The measurement and setting module provides target curvature compensation values κ1 and κ2 for the wafer to be corrected in two mutually perpendicular directions. It can be further divided into a measurement unit and a setting unit. The measurement unit acquires the current warp topography data of the wafer, which can be achieved by integrating a non-contact optical measurement device (such as a laser interferometer or white light interferometer). This device scans the wafer placed on the support stage to obtain the three-dimensional topography coordinate data of the surface. The setting unit processes the data and calculates the target compensation values, and may include a data processing unit and an input interface. The data processing unit receives the topography data from the measurement unit and extracts the current curvature values (C1, C2) along the preset first and second directions using built-in algorithms (such as surface fitting and differential calculation). The input interface allows the operator to input or select a preset target curvature state (C1, C2). target C 2,target Finally, the unit is determined according to the formula κ1=C. 1,target -C1;κ2=C 2,target -C2 calculates and outputs the target curvature compensation values κ1 and κ2.
[0054] The calculation module is used to calculate the required target equivalent thin film stress value based on the target curvature compensation values κ1 and κ2, the wafer substrate parameters, and the preset patterned stress balance layer thickness. Pre-store or receive the mechanical parameters of the wafer substrate (Young's modulus E). s Poisson's ratio s The input parameters κ1, κ2, and κ2 are used together with a pre-programmed inversion calculation formula (e.g., a solution algorithm based on the modified Stoney formula) to calculate and output a pair of target equivalent film stress values. and The inversion algorithm can use mechanical models of different accuracies (such as the classic Stoney formula) as needed, and the calculation module can be configured to allow users to select different models for calculation.
[0055] The parameter design module is used to design parameters based on the target equivalent thin film stress value. , Based on a quantitative relationship model, the geometric parameters of the patterned stress equilibrium layer are determined using the thin film material parameters. This quantitative relationship model characterizes the mapping relationship between the geometric parameters and the anisotropic equivalent thin film stress. This module includes a model database and a parameter solver; the model database stores one or more quantitative relationship models, each defining the mapping relationship between the geometric parameters of a specific pattern type (such as a fine line array) and the macroscopic equivalent thin film stress; the parameter solver receives data from the calculation module. , And the thin film material parameters selected by the user (intrinsic stress σ0, Poisson's ratio ν)f The module invokes the corresponding quantitative relationship model based on the selected pattern type and solves for the combination of geometric parameters that satisfy the target stress value using a numerical iterative algorithm (such as Newton's method). (For example, for a fine line array, it solves for the fine line thickness t, width b, and spacing d.) This module supports interactive design, allowing users to set certain geometric parameters (such as a fixed thickness t) as constraints and then solve for the remaining parameters. It also supports the design of composite patterns, solving for complex parameter combinations by weighted summation of the contributions of different sub-patterns.
[0056] A patterning preparation module is used to prepare the patterned stress balance layer on the back side of the wafer according to the geometric parameters. It typically integrates or controls the following process equipment in sequence: thin film deposition equipment, such as a sputtering stage or chemical vapor deposition equipment, for depositing a stress film with a design thickness t on the back side of the wafer; patterning equipment, such as a lithography machine (including coating, exposure, and development units) and a dry etching machine, which receives design parameters (such as linewidth b and spacing d) and forms the design pattern on the deposited film by loading a corresponding mask or directly based on the graphic data; and a process control unit, which coordinates the actions of each device to ensure that the geometric parameters are accurately transferred.
[0057] Other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of the invention are indicated by the claims. It should be understood that the invention is not limited to the precise structures described above and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the invention is limited only by the appended claims.
Claims
1. A method for anisotropic patterning correction of wafer warpage, characterized in that, The method includes: Obtain the target anisotropic curvature compensation value of the wafer to be corrected, including the curvature compensation value in the first direction and the curvature compensation value in the second direction, which are perpendicular to each other; Based on the curvature compensation values in the first and second directions, the mechanical parameters of the wafer substrate, and the preset patterned stress balance layer thickness, the target equivalent thin film stress values that the stress balance layer needs to achieve in the first and second directions are calculated by inversion. Taking the patterned stress balance layer as the design object, the geometric parameters of the patterned stress balance layer are determined by a quantitative relationship model based on the target equivalent film stress value, the intrinsic stress of the selected film material, and Poisson's ratio. The quantitative relationship model is used to characterize the mapping relationship between the geometric parameters and the anisotropic equivalent film stress generated by the patterned stress balance layer. Based on the geometric parameters, a corresponding patterned stress balancing layer is prepared on the back side of the wafer to complete warpage correction.
2. The method for anisotropic patterning correction of wafer warpage according to claim 1, characterized in that, The step of obtaining the target anisotropic curvature compensation value of the wafer to be corrected includes measuring the current warp shape of the wafer to be corrected, obtaining the current curvature value C1 along the first direction and the current curvature value C2 along the second direction; and according to the preset target curvature value C 1,target With C 2,target The curvature compensation value κ1=C in the first direction is calculated. 1,target -C1, and the second direction curvature compensation value κ2=C 2,target -C2.
3. The method for anisotropic patterning correction of wafer warpage according to claim 2, characterized in that, The inversion calculation is based on the modified Stoney formula: ， Wherein, κ1 is the curvature compensation value in the first direction, and κ2 is the curvature compensation value in the second direction. The target equivalent thin film stress value in the first direction. This represents the target equivalent thin film stress value in the second direction. E s The Young's modulus of the wafer substrate, ν s t is the Poisson's ratio of the wafer substrate, t is the preset patterned stress balance layer thickness, and h is the thickness of the wafer substrate.
4. The method for anisotropic patterning correction of wafer warpage according to claim 1, characterized in that, The quantitative relationship model includes a dimensionless function to characterize the stress relaxation effect at the edge of the thin wire. .
5. The method for anisotropic patterning correction of wafer warpage according to claim 4, characterized in that, The dimensionless function It's about the aspect ratio of the thin line. The function, with the expression: ， Where t is the thickness of the wire, b is the width of the wire, and m is the thickness of the wire. j It is a constant sequence.
6. The method for anisotropic patterning correction of wafer warpage according to claim 1, characterized in that, The patterned stress balance layer is an array of fine lines extending in a single direction.
7. The method for anisotropic patterning correction of wafer warpage according to claim 1, characterized in that, The pattern of the patterned stress balance layer is a composite pattern composed of two or more sub-patterns with different extension directions.
8. The method for anisotropic patterning correction of wafer warpage according to claim 1, characterized in that, The patterned stress balancing layer is composed of two or more thin film materials with different intrinsic stresses.
9. The method for anisotropic patterning correction of wafer warpage according to claim 1, characterized in that, The patterned stress balancing layer is composed of two or more stacked patterned thin films, each layer having an independent pattern and / or material properties.
10. An anisotropic patterning correction system for wafer warpage, used to implement the method as described in any one of claims 1-9, characterized in that, It includes a measurement and setting module, a calculation module, a parameter design module, and a patterning preparation module; The measurement and setting module is used to provide target curvature compensation values for the wafer to be corrected in two mutually perpendicular directions; The calculation module is used to calculate the required target equivalent thin film stress value based on the target curvature compensation value, wafer substrate parameters, and preset patterned stress balance layer thickness. The parameter design module is used to determine the geometric parameters of the patterned stress balance layer based on a quantitative relationship model according to the target equivalent thin film stress value and the thin film material parameters. The quantitative relationship model characterizes the mapping relationship between the geometric parameters and the anisotropic equivalent thin film stress. The patterning preparation module is used to prepare the patterned stress balance layer on the back side of the wafer according to the geometric parameters.