Modulation method, system, product, medium and device for parallel three-level inverter

Abstract

The present application belongs to the technical field of power supply and distribution. A parallel three-level inverter modulation method, system, product, medium and equipment are proposed, which equivalent double parallel three-level inverters as a whole five-level inverter, inject zero sequence components to the initial three-phase reference signal to obtain the reference signal, identify the resultant vector through rounding and remainder operation, and then adjust the reference signal according to the sum of the three-phase state of the initial resultant vector to output a five-segment switching sequence, and then decompose the equivalent five-level reference signal into two sets of three-level reference signals, allocate the reference signals by dividing the half-carrier period and compare them with the triangular carrier to obtain a three-level vector sequence combination. The present application realizes the comprehensive optimization of common-mode voltage, zero-sequence circulating current and output current ripple, avoids complex sector judgment and duty cycle calculation, and reduces the implementation complexity and computational burden.

Description

Technical Field

[0001] This invention relates to the field of power supply and distribution technology, specifically to a modulation method, system, product, medium, and equipment for a parallel three-level inverter. Background Technology

[0002] The statements in this section are merely background information related to the present invention and do not necessarily constitute prior art.

[0003] With the rapid development of high-power AC power drive technology, T-type three-level inverters have been widely used in related fields due to their significant advantages such as simple topology, fewer power devices, low conduction losses, and balanced loss distribution. In applications with high power and rated current requirements, a single three-level inverter is often limited by the capacity of semiconductor devices, making it difficult to meet actual power requirements. Parallel inverter topologies have become an effective alternative to achieve higher rated power output, and related technology development has become an important research direction in the industry. In the field of inverter modulation technology, there are two main core methods: carrier modulation and space vector modulation. Among them, carrier modulation occupies an important position in practical engineering applications due to its advantages such as simple implementation process and low computational load. At the same time, integrated modulation strategies, with their excellent overall performance in reducing output current ripple and suppressing circulating current, have gradually become a research hotspot, providing new ideas for the performance optimization of parallel inverters.

[0004] In the actual operation of parallel three-level inverters, the presence of common-mode voltage can cause a series of adverse effects, threatening the stable operation of the system. Therefore, targeted suppression measures must be taken. Compared with solutions that add hardware equipment, software solutions that reduce common-mode voltage by improving inverter modulation strategies are more practical, as they do not require additional system size or cost. Furthermore, the common-mode voltage difference between inverters operating in parallel can induce high-frequency zero-sequence circulating current. This circulating current leads to increased system power loss and decreased operating efficiency, seriously affecting the normal operation of the parallel system. This is a key technical problem that needs to be addressed first in parallel inverter applications. Currently, how to achieve comprehensive optimization of common-mode voltage, zero-sequence circulating current, and output current ripple has become a significant challenge for the development of parallel three-level inverter technology. At the same time, existing integrated modulation strategies are mostly based on space vector modulation, which suffers from complex structures and difficulties in engineering implementation, making it difficult to meet the demands for simplicity and economy in practical applications. Therefore, a better modulation scheme is urgently needed to overcome the current technical bottlenecks. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention provides a modulation method, system, product, medium, and device for parallel three-level inverters. Through a carrier-based integrated modulation strategy, it achieves comprehensive optimization of common-mode voltage, output current quality, and zero-sequence circulating current. The reference signal is decomposed according to the optimized allocation principle and corresponds to two sub-inverters, avoiding complex sector judgment and duty cycle calculation, thus reducing implementation complexity and computational burden.

[0006] To achieve the above objectives, the present invention adopts the following technical solution: In a first aspect, the present invention provides a modulation method for a parallel three-level inverter.

[0007] A modulation method for a parallel three-level inverter includes the following steps: The dual parallel three-level inverter is regarded as an overall five-level inverter. Zero-sequence components are injected into the initial three-phase reference signal to obtain the reference signal. The reference signal is then rounded and the remainder is calculated to obtain the interval identification signal and the phase state change sequence identification signal. Based on the sum of the three-phase states of the initial synthetic vector corresponding to the interval identification signal, and combined with the phase state change sequence identification signal, the reference signal is modified and adjusted to obtain the adjusted equivalent five-level reference signal; The equivalent five-level reference signal is decomposed into two sets of first three-level reference signals and second three-level reference signals applicable to the sub-inverter; Two consecutive carrier cycles are divided into four half-carrier cycles. In the first and fourth half-carrier cycles, the first three-level reference signal is assigned to the first inverter and the second three-level reference signal is assigned to the second inverter. In the second and third half-carrier cycles, the second three-level reference signal is assigned to the first inverter and the first three-level reference signal is assigned to the second inverter. The reference signal allocated to the corresponding inverter in each half-carrier cycle is compared with two triangular carriers applicable to the three-level inverter to obtain a combination of three-level vector sequences.

[0008] Secondly, the present invention provides a parallel three-level inverter modulation system.

[0009] A parallel three-level inverter modulation system, comprising: The identification signal generation unit is configured to: treat the dual parallel three-level inverter as an overall five-level inverter, inject a zero-sequence component into the initial three-phase reference signal to obtain a reference signal, and perform rounding and remainder operations on the reference signal to obtain the interval identification signal and the phase state change sequence identification signal; The reference signal adjustment unit is configured to modify and adjust the reference signal based on the sum of the three-phase states of the starting composite vector corresponding to the interval identifier signal and the phase state change sequence identifier signal, so as to obtain the adjusted equivalent five-level reference signal. The reference signal decomposition unit is configured to decompose the equivalent five-level reference signal into two sets of first three-level reference signals and second three-level reference signals applicable to the sub-inverter. The signal distribution unit is configured to: divide two consecutive carrier cycles into four half-carrier cycles; in the first half-carrier cycle and the fourth half-carrier cycle, distribute a first three-level reference signal to the first inverter and distribute a second three-level reference signal to the second inverter; in the second half-carrier cycle and the third half-carrier cycle, distribute a second three-level reference signal to the first inverter and distribute a first three-level reference signal to the second inverter. The carrier comparison unit is configured to compare the reference signal allocated to the corresponding inverter in each half-carrier cycle with two triangular carriers applicable to the three-level inverter to obtain a combination of three-level vector sequences.

[0010] Thirdly, the present invention provides a computer device, comprising: a processor and a computer-readable storage medium; A processor, adapted to execute computer programs; A computer-readable storage medium storing a computer program, which, when executed by a processor, implements the parallel three-level inverter modulation method of the first aspect of the present invention.

[0011] Fourthly, the present invention provides a computer-readable storage medium storing a computer program adapted to be loaded by a processor and to execute the parallel three-level inverter modulation method of the first aspect of the present invention.

[0012] Fifthly, the present invention provides a computer program product, which includes a computer program. When the computer program is executed by a processor, it implements the parallel three-level inverter modulation method of the first aspect of the present invention.

[0013] Compared with the prior art, the beneficial effects of the present invention are: This invention equates a dual-parallel three-level inverter to an overall five-level inverter. Combining the simplicity of carrier modulation with the advantages of integrated modulation, an integrated modulation strategy is employed. A reference signal is constructed by injecting zero-sequence components, and the synthesized vector is identified through rounding and remainder operations. The reference signal is then adjusted, decomposed, and rationally allocated to form a complete modulation process. This solves the problem in existing technologies of simultaneously optimizing the three core indicators of common-mode voltage, output current quality, and zero-sequence circulating current. It breaks the contradiction between optimizing a single indicator and worsening other indicators, overcoming the limitations of traditional modulation methods such as insufficient control freedom and inability to achieve synergistic improvement of multiple indicators. This improves the overall operating performance of the parallel three-level inverter, not only making the output current more stable but also simultaneously reducing the adverse effects of common-mode voltage and zero-sequence circulating current, thus improving the overall quality of system power conversion and reducing the debugging difficulty and operational risks caused by conflicts between multiple indicators.

[0014] This invention equates a dual-parallel three-level inverter to an overall five-level inverter, fully utilizing the greater control freedom of a five-level system. In the switching sequence design, a vector with a smaller common-mode voltage amplitude is selected, and the reference voltage synthesis is ensured by the three closest vectors. This solves the technical challenge of mutual constraints between common-mode voltage suppression and current ripple optimization in traditional three-level modulation systems, breaking the dilemma of being unable to balance both. It overcomes the bottleneck of limited control flexibility in single three-level systems, the difficulty in finding a balance between common-mode voltage control and current ripple optimization, and the defect of some solutions that severely degrade current quality in pursuit of extremely low common-mode voltage. This improves the accuracy of system voltage modulation, significantly reduces output current ripple, and makes load operation more stable. Simultaneously, it effectively controls the common-mode voltage within a reasonable range, reducing its potential interference to the system and ensuring the high quality and stability of the inverter's output power.

[0015] This invention prioritizes the use of vector design for a three-level switching sequence with a small rate of change of zero-sequence circulating current. It alternates between vector combinations with opposite common-mode voltage differences in each half-cycle, and rationally allocates five-level vectors to control the sum of the three-phase state differences. This solves the core problem of high-frequency zero-sequence circulating current caused by common-mode voltage differences between parallel inverters, leading to increased system power loss and decreased operating efficiency. It overcomes the technical difficulties of traditional modulation methods, such as poor zero-sequence circulating current suppression, excessively high circulating current peaks, and inability to stably return to zero, as well as the defects of continuous circulating current accumulation due to unreasonable vector allocation. It improves the operational coordination and stability of the parallel system, reduces the loss of inverter power devices due to zero-sequence circulating current, extends equipment lifespan, and ensures high power output efficiency during long-term system operation, guaranteeing efficient operation of parallel inverters under stable conditions.

[0016] This invention presents a carrier-based integrated modulation method that decomposes the equivalent five-level reference signal into two sets of three-level reference signals suitable for sub-inverters according to a predetermined allocation principle. Modulation is completed through simple logical judgment and basic addition and subtraction operations, eliminating the need for complex sector judgment and duty cycle calculation. This solves the problems of existing integrated modulation strategies, which are mostly based on space vector modulation, resulting in complex implementation, heavy computational burden, and difficulty in engineering implementation. It also overcomes the shortcomings of parallel inverter modulation schemes, such as insufficient practicality and difficulty in large-scale promotion. This invention overcomes the technical bottlenecks of traditional space vector modulation, such as cumbersome sector division and complex duty cycle calculation leading to poor real-time performance and high hardware implementation costs, as well as the defect of modulation strategies being out of touch with actual engineering application requirements. It improves the engineering practicality and operability of the modulation strategy, reduces the system's computational load, increases the modulation response speed, reduces hardware resource consumption, lowers system construction and debugging costs, and ensures the stability, reliability, and efficiency of the modulation process, facilitating engineering application and promotion.

[0017] Advantages of additional aspects of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0018] The accompanying drawings, which form part of this invention, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an improper limitation of the invention.

[0019] Figure 1 A schematic diagram of the topology of a parallel three-level inverter system provided as an exemplary embodiment of the present invention; Figure 2 A five-level space vector diagram for reducing common-mode voltage is provided as an exemplary embodiment of the present invention; Figure 3 A schematic diagram of the switching sequence and circulating current in sub-region 12 of sector I provided as an exemplary embodiment of the present invention; Figure 4 A carrier modulation diagram of a switching sequence in sub-region 12 of sector I is provided as an exemplary embodiment of the present invention; Figure 5 A block diagram illustrating a carrier-based modulation method for a parallel three-level inverter, provided as an exemplary embodiment of the present invention; Figure 6 A simulation result diagram is provided for an exemplary embodiment of the present invention; Figure 6 Figure (a) shows the simulation results of conventional interleaved modulation in a parallel three-level inverter. Figure 6 Figure (b) shows the simulation results of the method of the present invention in a parallel three-level inverter; Figure 7A schematic diagram of a parallel three-level inverter modulation system provided as an exemplary embodiment of the present invention; Figure 8 A schematic diagram of a computer device provided for an exemplary embodiment of the present invention. Detailed Implementation

[0020] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0021] It should be noted that the following detailed descriptions are exemplary and intended to provide further illustration of the invention. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains.

[0022] Integrated modulation, which considers the parallel inverter as a whole, provides greater control freedom when selecting vector combinations, thus exhibiting better overall performance in reducing current ripple and suppressing zero-sequence circulating current. However, existing integrated modulation strategies are all based on space vector modulation, which is extremely complex to implement. To achieve lower common-mode voltage, zero-sequence circulating current, and output current harmonics in parallel three-level inverters compared to interleaved modulation, and also for practical application, this invention proposes a carrier-based integrated modulation method.

[0023] Parallel T-type three-level inverter system, such as Figure 1 As shown, each inverter includes phase A, phase B, and phase C bridge arms, and each phase bridge arm includes four power switching transistors. The DC side includes two series-connected filter capacitors, with a neutral point formed between the two filter capacitors. The power switching transistors here are insulated-gate bipolar transistors (IGBTs). It is understood that in some other implementations, other types of transistors may also be used for the power switching transistors, which will not be elaborated here.

[0024] Specifically, each three-level inverter generates three different voltage levels through different switching combinations. V dc / 2、0、- V dc / 2 are denoted as 2, 1, and 0 respectively; the phase voltages of inverter 1 and inverter 2 can be expressed as: (1); in, V x1 and V x2 Inverter 1 and Inverter 2 respectively x Phase voltage, S x1 and S x2 Inverter 1 and Inverter 2 respectively xPhase branch switch status, V dc This represents the amplitude of the DC power supply. For a dual-parallel inverter, the AC output voltage can be expressed as: (2); because V x1 and V x2 Only one of the three values ​​can be obtained, therefore equation (2) has five possible results, which means the equivalent voltage V x There are five voltage levels, represented by 0 to 4. Table 1 shows the parallel output states formed by the combination of three-level states. Therefore, the dual parallel three-level inverter can be equivalent to a five-level system for research and analysis.

[0025] Table 1: Five-level output states of parallel three-level inverters

[0026] The common-mode voltage in a parallel three-level inverter is the voltage difference between the load neutral point O and the DC bus neutral point, which can be expressed as: (3); Combining formulas (1)-(3), the common-mode voltage can be expressed as: (4); in, S x For a five-level inverter system x Phase switching states. Based on the relationship between common-mode voltage and switching states in equation (4), the common-mode voltage corresponding to any five-level vector can be obtained. For any given vector, if the sum of its three-phase switching states is equal to 6, the corresponding common-mode voltage is zero; if the sum of the switching states is equal to 5 or 7, the amplitude of the common-mode voltage is V dc / 12, and so on.

[0027] The comprehensive optimization of multiple indicators depends not only on selecting an appropriate common-mode voltage to reduce electromagnetic interference and leakage current, but also on ensuring the necessary conditions for output current ripple and zero-sequence circulating current suppression. However, simply selecting a vector state with zero common-mode voltage will inevitably degrade current quality, which contradicts the comprehensive optimization. V dc / 12 is a relatively suitable common-mode voltage state, close to zero common-mode voltage. For example... Figure 2 As shown, the common-mode voltage amplitude is selected from the five-level space vector within ± V dcVectors within / 12, the sum of these vector three-phase switch states ranges from 5 to 7, ensuring not only that the system common-mode voltage is within / 12, but also that the vectors are within / 12. V dc It is within 12, and maintains the integrity of the five-level vector plane.

[0028] Because sector II to VI can be inferred by analogy from sector I during modulation, sector I can be used as an example for analysis. Table 2 lists the optimized five-level switching sequence within one switching cycle of sub-regions 1-16 of sector I. Since... Figure 2 In this configuration, only one state corresponding to the minimum common-mode voltage remains available at each vector position. Therefore, it is a five-segment switching sequence composed of the three most recent vectors, ensuring optimal switching performance and output current quality. It's important to note that there are two special regions, sub-regions 10 and 16, which, unlike the other regions, inherently contain vectors 400 and 440. Therefore, under high-modulation conditions, the common-mode voltage may briefly increase to [a certain value]. V dc / 6.

[0029] Table 2: Switching sequence of each sub-region of sector I in parallel three-level inverters using the method of this invention sub-region <![CDATA[Switch sequence( S a S b S c )]]> 1 221-222-322-222-221 2 311-321-322-321-311 3 221-321-322-321-221 4 221-321-331-321-221 5 311-411-421-411-311 6 311-321-421-321-311 7 320-321-421-321-320 8 320-321-331-321-320 9 320-330-331-330-320 10 400-410-411-410-400 11 410-411-421-411-410 12 410-420-421-420-410 13 320-420-430-420-320 14 320-420-430-420-320 15 320-330-430-330-320 16 330-430-440-430-330 The common-mode voltage difference (DCMV) between parallel inverters will cause zero-sequence circulating current ( i ZSCC Zero-sequence circulating current is defined as the sum of the three-phase currents of the sub-inverter. The rate of change of zero-sequence circulating current can be expressed as: (5); in, L 1 represents the inductance on the first inverter side. L 2 represents the inductance on the second inverter side.

[0030] Because of inductance L 1. L 2 and V dc The rate of change of the zero-sequence circulating current remains constant, and is primarily determined by the sum of the three-phase switch state differences between inverter 1 and inverter 2. To minimize the circulating current, the five-level vector should be distributed as evenly as possible across the two sets of three-level states. An example illustrating this state allocation principle is provided: when the reference signal is located in sub-sector 12 of sector I, the corresponding five-level switch sequence is: 410-420-421-420-410. A schematic diagram of the switch sequence for two consecutive cycles is shown below. Figure 3As shown. All even-numbered five-level states 0, 2, and 4 are equally divided into two identical states 00, 11, and 22. Odd-numbered states 1 and 3 cannot be equally divided. The rate of change is minimized when the three-level states are divided into 01 and 12. Simultaneously, the three-phase states are coordinated to ensure the use of vectors with a small sum of three-phase state differences (0, ±1). Furthermore, vector combinations with opposite common-mode voltage differences are alternated every half-cycle to reduce circulating current peaks. For example, in the 410 three-level states (210 and 200), the sum of the three-phase state differences is 1; in the 421 three-level states (210 and 211), the sum of the three-phase state differences is -1. Additionally, it can be seen that... Figure 3 The circulating current must return to its initial value at the end of a switching cycle, and its average value over two consecutive cycles must be zero to ensure normal system operation.

[0031] Therefore, the comprehensive optimization of the three indicators of common-mode voltage, zero-sequence circulating current, and line current ripple must simultaneously meet the following four conditions: 1) Use a common-mode voltage with a small amplitude (0, ± V dc 1) Use a vector with a small zero-sequence circulating current rate of change (0, ±1). 2) Use a vector with a small zero-sequence circulating current rate of change (0, ±1). 3) Use the nearest three vectors to synthesize the reference voltage to minimize current ripple. 4) Reduce implementation complexity and computational burden.

[0032] The following is a carrier implementation scheme for vector allocation and sequence combination: Inject appropriate zero-sequence components into the initial three-phase reference signal v com Composition of reference signal v x_ref This can be equivalent to achieving multilevel space vector modulation. v x_ref Comparing with a co-directional four-carrier signal yields a seven-segment, five-level sequence composed of the three most recent vectors. However, to reduce common-mode voltage, this paper employs a five-segment switching sequence, requiring modification and adjustment of the reference signal. Furthermore, to avoid complex sector determination, the reference signal is rounded and moduloed to identify the composite vector. Definition v x_sec and v x_mod for: (6); Among them, floor() and mod() are the floor function and the remainder function, respectively. v x_sec It belongs to (0,1,2,3,4) and is used to identify the five-level interval where the current reference signal is located. v x_modIt is the equivalent reference signal normalized to the interval [0, 0.5). v x_ref The difference between the value and the lower edge of the corresponding five-level interval is used to determine the sequence of phase state transitions in the vector sequence. For example, when... v x_ref When =0.8, v x_sec and v x_mod They are equal to 3 and 0.3 respectively. v a_sec， v b_sec， v c_sec [] represents the starting synthesis vector corresponding to the five-level sequence. For example, in sub-region 12, [ v a_sec， v b_sec， v c_sec ] equals

[310] .

[0033] Reference signal before adjustment v x_ref This will generate eight possible initial composite vectors: 300, 320, 221, 210, 310, 330, 211, and 321. The sum of the three-phase states of the initial composite vector can be 3, 4, 5, or 6. Therefore, the adjustment of the reference signal based on the different sums of the three-phase states is summarized in Table 3.

[0034] Table 3: Summary of Reference Signal Adjustment The sum of the three phase states Reference signal adjustment 3 <![CDATA[All increase by (0.5 - v DD_mod )]]> 4 <![CDATA[All increase (0.5 - v MM_mod )]]> 5 <![CDATA[Both decrease v NN_mod > 6 <![CDATA[Both decrease v DD_mod > Subscripts MM, DD, and NN are defined as follows: v x_mod The phase of the maximum, median and minimum values.

[0035] Reference signals in sub-region 12 v x_ref The initial switching sequence is 310-410-420-421-420-410-310. This is to limit the common-mode voltage amplitude within... V dc Within the range of / 12, vector 310 is no longer used within sub-sector 12. The initial three-phase state sum of the synthesized vector 310 is 4. v x_mod The maximum value is v a_mod , a The phase jumps first, so v x_ref All increased by 0.5- va_mod This is so that the reference signal is shifted upwards as a whole. a The phase clamp remains in state 4 without a state transition. After adjustment, the initial synthesis vector of the sequence in sub-region 12 becomes 410, and the dwell time of vector 310 is taken over by vector 420, thus obtaining the optimal sequence 410-420-421-420-410.

[0036] Reference signal in sub-region 9 v x_ref The initial switching sequence is 330-331-431-441-431-331-330. The reference signal needs to be adjusted to avoid using vectors 431 and 441. The sum of the three-phase states of the initial synthesized vector 330 is 6. v x_mod Minimum value is v b_mod The median is v a_mod , a Xiangzai b A state transition occurs before the phase. If v x_ref All decrease to minimum value v b_mod The sequence 330-331-431-331-330 still cannot meet the common-mode voltage amplitude requirement, therefore v x_ref To reduce the median value v a_mod This results in a relatively large overall downward shift of the reference signal. Thus, the initial synthesis vector 320 in sub-region 9 replaces vector 431, and the dwell time of vector 441 is taken over by 330. The five-level sequence then becomes 320-330-331-330-320, where... a The phase is always clamped in state 3.

[0037] After the five-level sequence is determined, the three-level sequence combinations of each sub-region are derived through circulation suppression analysis, and carrier modulation is used to generate vector sequences.

[0038] When implementing a carrier wave with a three-level sequence combination, the equivalent five-level reference signal will be used. v x_ref Decomposed into two sets of three-level reference signals suitable for the sub-inverter v x_ref1 and v x_ref2 ,satisfy v x_ref = 0.5( v x_ref1 + v x_ref2To satisfy the state allocation rule for zero-sequence circulating current suppression, two consecutive carrier cycles are divided into four half-carrier cycles. In the first and fourth half-carrier cycles, v x_ref1 Assigned to inverter 1, v x_ref2 It is allocated to inverter 2, and during the second and third half-carrier cycles, v x_ref2 Assigned to inverter 1, v x_ref1 The signal is allocated to inverter 2, where the reference signal is compared with the dual carrier waves to obtain a vector sequence combination. To better understand the implementation process, Figure 7 Taking sub-region 12 as an example, the carrier modulation diagram of the corresponding three-level vector sequence combination is given. It can be seen that the reference signal satisfying the required sequence in sub-region 12... v x_ref1 and v x_ref2 for: (7); in, v x_ref1 For the three-level reference signal applicable to the first inverter, v x_ref2 For the three-level reference signal applicable to the second inverter, For the A-phase reference signal applicable to the first inverter, For the B-phase reference signal applicable to the first inverter, For the C-phase reference signal applicable to the first inverter, This is the A-phase reference signal applicable to the second inverter; This is the B-phase reference signal applicable to the second inverter; This is the C-phase reference signal applicable to the second inverter; The five-level reference signal representing phase A; The five-level reference signal representing phase B; The five-level reference signal represents phase C.

[0039] When located in other sub-regions, similar analysis can be used to deduce the same conclusion. v x_ref1 and v x_ref2 Although different sub-regions have different reference signal decompositions, they exhibit regularity. To facilitate decomposition, an intermediate reference signal is first defined. v x_inte1 and v x_inte2 : (8); in,v x_inte1 It is to realize the state decomposition mapping from a five-level system to two three-level systems. v x_inte1 +1 corresponds to the highest output level of the inverter; for example, 410 is mapped to 210 and 200. Combining equations (7) and (8), we get: (9); in, This represents the first intermediate reference signal corresponding to phase A; This represents the second intermediate reference signal corresponding to phase A; This represents the first intermediate reference signal corresponding to phase B; This represents the second intermediate reference signal corresponding to phase B; This represents the first intermediate reference signal corresponding to phase C; This represents the second intermediate reference signal corresponding to phase C.

[0040] like Figure 7 As shown, sub-region 12 satisfies v b_mod > v c_mod > v a_mod =0, b Xiang Xianyu c Phase transition state. The initial composite vector is 410, based on each phase. v x_mod The sizes (i.e., the order of phase state transitions) are rearranged to 104, and the parity of 104 is [odd, even, even]. In fact, sub-regions 12 of sectors I to VI... v MM_sec， v DD_sec， v NN_sec Since both are 104, their parity must also be the same. Therefore, according to [ v MM_sec， v DD_sec， v NN_sec The parity of the reference signal (odd and even numbers are represented by 1 and 0 respectively) is summarized and applied to different sub-regions of each sector. There are three different cases of correspondence between the intermediate reference signal and the three-level reference signal, as shown below.

[0041] [ v MM_sec， v DD_sec， v NN_sec When the parity is [1,0,0], [1,1,1] or [0,1,0]: (10); [ v MM_sec， v DD_sec， v NN_sec When the parity is [0,1,1] or [0,0,1]: (11); [ v MM_sec， v DD_sec， v NN_sec When the parity is [0,0,0], [1,1,0], [1,0,1] (for sub-regions 10 and 16): (12); in, v MM_sec Represents the interval identification signal v x_sec correspond v x_mod The components of the MM phase; v DD_sec代表 Interval identification signal v x_sec correspond v x_mod The components of the DD phase; v NN_sec代表 Interval identification signal v x_sec correspond v x_mod The components of the NN phase; This represents a three-level reference signal corresponding to the MM phase applicable to the first sub-inverter; The first intermediate reference signal, representing the corresponding MM phase, is used to realize the state decomposition mapping from a five-level system to a three-level system; This represents a three-level reference signal corresponding to the DD phase applicable to the first sub-inverter; The first intermediate reference signal, representing the corresponding DD phase, is used to realize the state decomposition mapping from a five-level system to a three-level system; This represents a three-level reference signal corresponding to the NN phase, applicable to the first sub-inverter; The second intermediate reference signal, representing the corresponding NN phase, is used to assist in the decomposition of the three-level reference signal; This represents a three-level reference signal corresponding to the MM phase applicable to the second sub-inverter; The second intermediate reference signal, representing the corresponding MM phase, is used to assist in the decomposition of the three-level reference signal; This represents a three-level reference signal corresponding to the DD phase, applicable to the second sub-inverter; The second intermediate reference signal, representing the corresponding DD phase, is used to assist in the decomposition of the three-level reference signal; This represents a three-level reference signal corresponding to the NN phase, applicable to the second sub-inverter; This represents the first intermediate reference signal corresponding to the NN phase, used to realize the state decomposition mapping from a five-level system to a three-level system.

[0042] Although this invention aims to improve the performance of existing methods, the entire process does not require complex calculations, only simple logical judgments and basic addition and subtraction operations. The overall block diagram of the proposed method is as follows: Figure 5 As shown, the dual three-phase reference signals of the two sub-inverters are obtained, avoiding sector judgment and duty cycle calculation, and completing the carrier realization of the proposed vector sequence.

[0043] Typical parameters of a parallel three-level inverter system are shown in Table 4.

[0044] Table 4: System Parameter Table parameter numerical values <![CDATA[ V dc ]]> 100V <![CDATA[ L 1]]> 6mH <![CDATA[ L 2]]> 6mH 8Ω carrier frequency 2500Hz Figure 6 (a) and Figure 6 Figure (b) shows the simulation results of conventional interleaved modulation and the method of this invention in a parallel three-level inverter (modulation ratio of 0.8), respectively. From top to bottom, the three-phase output current, common-mode voltage (CMV), and zero-sequence circulating current are recorded. i ZSCC The simulation waveforms are shown. First, regarding the common-mode voltage, the simulation results show that the amplitude of the interleaved common-mode voltage is... V dc / 6, and the proposed method can reduce the common-mode voltage amplitude to V dc / 12. Secondly, in terms of output current harmonics, the current quality of the method of the present invention is significantly better than that of interleaved modulation. Figure 6 In (a) of the diagram, circulation i ZSCC The root mean square value is 0.588A. Figure 6 In (b) of the present invention, the method of circulation i ZSCC The root mean square value was reduced to 0.286 A. Clearly, compared to the large circulating current generated by interleaved modulation, this method reduces the circulating current by rationally allocating the vector state. The simulation results above show that the method of this invention significantly improves output current harmonics, common-mode voltage, and circulating current.

[0045] Figure 7 A parallel three-level inverter modulation system is shown, comprising: The identification signal generation unit 701 is configured to: treat the dual parallel three-level inverter as an overall five-level inverter, inject a zero-sequence component into the initial three-phase reference signal to obtain a reference signal, and perform rounding and remainder operations on the reference signal to obtain the interval identification signal and the phase state change sequence identification signal; The reference signal adjustment unit 702 is configured to modify and adjust the reference signal based on the sum of the three-phase states of the starting composite vector corresponding to the interval identification signal and in combination with the phase state change sequence identification signal, so as to obtain the adjusted equivalent five-level reference signal. The reference signal decomposition unit 703 is configured to decompose the equivalent five-level reference signal into two sets of first three-level reference signals and second three-level reference signals applicable to the sub-inverter. The signal distribution unit 704 is configured to: divide two consecutive carrier cycles into four half-carrier cycles; in the first half-carrier cycle and the fourth half-carrier cycle, distribute a first three-level reference signal to the first inverter and distribute a second three-level reference signal to the second inverter; in the second half-carrier cycle and the third half-carrier cycle, distribute a second three-level reference signal to the first inverter and distribute a first three-level reference signal to the second inverter. The carrier comparison unit 705 is configured to compare the reference signal allocated to the corresponding inverter in each half-carrier cycle with two triangular carriers applicable to the three-level inverter to obtain a combination of three-level vector sequences.

[0046] It is understood that the aforementioned units can be individually or entirely merged into one or more other units, or some of the units can be further divided into multiple functionally smaller units. This achieves the same operation without affecting the technical effects of the embodiments of the present invention. The aforementioned units are based on logical functional division. In practical applications, the function of one unit can be implemented by multiple units, or the function of multiple units can be implemented by one unit. In other embodiments of the present invention, the system may also include other units. In practical applications, these functions can also be implemented with the assistance of other units, and can be implemented collaboratively by multiple units.

[0047] According to another embodiment of the present invention, the system of this embodiment can be constructed by running a computer program (including program code) capable of performing the steps involved in the corresponding method of the present invention on a general-purpose computing device, such as a computer, which includes processing elements and storage elements such as a central processing unit (CPU), random access memory (RAM), and read-only memory (ROM). The computer program can be recorded on, for example, a computer-readable recording medium, loaded into the aforementioned computing device through the computer-readable recording medium, and run therein.

[0048] Figure 8 A computer device is shown, which includes a processor 801, a communication interface 802, and a computer-readable storage medium 803. The processor 801, communication interface 802, and computer-readable storage medium 803 can be connected via a bus or other means.

[0049] The communication interface 802 is used to receive and send data. The computer-readable storage medium 803 can be stored in the memory of the electronic device. The computer-readable storage medium 803 is used to store computer programs, which include program instructions. The processor 801 is used to execute the program instructions stored in the computer-readable storage medium 803.

[0050] The processor 801 is the computing and control core of electronic devices. It is suitable for implementing one or more instructions, specifically for loading and executing one or more instructions to achieve corresponding methods or functions.

[0051] Processor 801 is configured to perform the following procedure: The dual parallel three-level inverter is regarded as an overall five-level inverter. Zero-sequence components are injected into the initial three-phase reference signal to obtain the reference signal. The reference signal is then rounded and the remainder is calculated to obtain the interval identification signal and the phase state change sequence identification signal. Based on the sum of the three-phase states of the initial synthetic vector corresponding to the interval identification signal, and combined with the phase state change sequence identification signal, the reference signal is modified and adjusted to obtain the adjusted equivalent five-level reference signal; The equivalent five-level reference signal is decomposed into two sets of first three-level reference signals and second three-level reference signals applicable to the sub-inverter; Two consecutive carrier cycles are divided into four half-carrier cycles. In the first and fourth half-carrier cycles, the first three-level reference signal is assigned to the first inverter and the second three-level reference signal is assigned to the second inverter. In the second and third half-carrier cycles, the second three-level reference signal is assigned to the first inverter and the first three-level reference signal is assigned to the second inverter. The reference signal allocated to the corresponding inverter in each half-carrier cycle is compared with two triangular carriers applicable to the three-level inverter to obtain a combination of three-level vector sequences.

[0052] This invention also provides a computer-readable storage medium, which is a memory device in an electronic device for storing programs and data. It is understood that the computer-readable storage medium here may include both built-in storage media in the electronic device and extended storage media supported by the electronic device. The computer-readable storage medium provides storage space for storing the processing system of the electronic device.

[0053] Furthermore, this storage space also contains one or more instructions suitable for loading and execution by the processor. These instructions can be one or more computer programs (including program code). It should be noted that the computer-readable storage medium here can be a high-speed RAM memory; alternatively, it can also be at least one computer-readable storage medium located remotely from the aforementioned processor.

[0054] In one embodiment, the computer-readable storage medium stores one or more instructions; the processor loads and executes the one or more instructions stored in the computer-readable storage medium to perform the following process: The dual parallel three-level inverter is regarded as an overall five-level inverter. Zero-sequence components are injected into the initial three-phase reference signal to obtain the reference signal. The reference signal is then rounded and the remainder is calculated to obtain the interval identification signal and the phase state change sequence identification signal. Based on the sum of the three-phase states of the initial synthetic vector corresponding to the interval identification signal, and combined with the phase state change sequence identification signal, the reference signal is modified and adjusted to obtain the adjusted equivalent five-level reference signal; The equivalent five-level reference signal is decomposed into two sets of first three-level reference signals and second three-level reference signals applicable to the sub-inverter; Two consecutive carrier cycles are divided into four half-carrier cycles. In the first and fourth half-carrier cycles, the first three-level reference signal is assigned to the first inverter and the second three-level reference signal is assigned to the second inverter. In the second and third half-carrier cycles, the second three-level reference signal is assigned to the first inverter and the first three-level reference signal is assigned to the second inverter. The reference signal allocated to the corresponding inverter in each half-carrier cycle is compared with two triangular carriers applicable to the three-level inverter to obtain a combination of three-level vector sequences.

[0055] The present invention also provides a computer program product or computer program comprising computer instructions stored in a computer-readable storage medium. A processor of an electronic device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the electronic device to perform the following process: The dual parallel three-level inverter is regarded as an overall five-level inverter. Zero-sequence components are injected into the initial three-phase reference signal to obtain the reference signal. The reference signal is then rounded and the remainder is calculated to obtain the interval identification signal and the phase state change sequence identification signal. Based on the sum of the three-phase states of the initial synthetic vector corresponding to the interval identification signal, and combined with the phase state change sequence identification signal, the reference signal is modified and adjusted to obtain the adjusted equivalent five-level reference signal; The equivalent five-level reference signal is decomposed into two sets of first three-level reference signals and second three-level reference signals applicable to the sub-inverter; Two consecutive carrier cycles are divided into four half-carrier cycles. In the first and fourth half-carrier cycles, the first three-level reference signal is assigned to the first inverter and the second three-level reference signal is assigned to the second inverter. In the second and third half-carrier cycles, the second three-level reference signal is assigned to the first inverter and the first three-level reference signal is assigned to the second inverter. The reference signal allocated to the corresponding inverter in each half-carrier cycle is compared with two triangular carriers applicable to the three-level inverter to obtain a combination of three-level vector sequences.

[0056] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed in this invention can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can implement the described functions using different methods for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0057] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, as a computer program product. A computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the flow or function according to the embodiments of the present invention is generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in or transmitted through a computer-readable storage medium. The computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic cable, digital cable) or wireless (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that a computer can access or a data processing device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state drive), etc.

[0058] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A modulation method for a parallel three-level inverter, characterized by, Includes the following processes: The dual parallel three-level inverter is regarded as an overall five-level inverter. A zero-sequence component is injected into the initial three-phase reference signal to obtain a reference signal. The reference signal is then rounded and the remainder is calculated to obtain the interval identification signal and the phase state change sequence identification signal. Based on the sum of the three-phase states of the starting synthetic vector corresponding to the interval identification signal, and combined with the phase state change sequence identification signal, the reference signal is modified and adjusted to obtain the adjusted equivalent five-level reference signal; The equivalent five-level reference signal is decomposed into two sets of first three-level reference signals and second three-level reference signals applicable to the sub-inverter; Two consecutive carrier cycles are divided into four half-carrier cycles. In the first and fourth half-carrier cycles, the first three-level reference signal is assigned to the first inverter and the second three-level reference signal is assigned to the second inverter. In the second and third half-carrier cycles, the second three-level reference signal is assigned to the first inverter and the first three-level reference signal is assigned to the second inverter. The reference signal allocated to the corresponding inverter in each half-carrier cycle is compared with two triangular carriers applicable to the three-level inverter to obtain a combination of three-level vector sequences.

2. The parallel three-level inverter modulation method as described in claim 1, characterized in that, The reference signal is rounded and its remainder is calculated to obtain an interval identifier signal and a phase state change sequence identifier signal, including: ； in, The interval identifier signal is used to identify the five-level interval in which the current reference signal is located; The signal representing the sequence of phase state changes is an equivalent reference signal normalized to the interval [0, 0.5). It is the difference between the reference signal and the lower edge of the five-level interval it belongs to, and is used to determine the sequence of phase state changes in the vector sequence. Represents a reference signal. Represents the floor function. This represents the remainder function.

3. The parallel three-level inverter modulation method as described in claim 2, characterized in that, Based on the sum of the three-phase states of the initial composite vector corresponding to the interval identification signal, and in conjunction with the phase state change sequence identification signal, the reference signal is modified and adjusted, including: The sum of the three-phase states of the initial composite vector includes 3, 4, 5, and 6. The adjustment method of the reference signal is as follows: When the sum of the three-phase states is 3, the reference signal increases by (0.5-) v DD_mod ); When the sum of the three-phase states is 4, the reference signal increases by (0.5-) v MM_mod ); When the sum of the three-phase states is 5, the reference signal decreases. v NN_mod ; When the sum of the three-phase states is 6, the reference signals all decrease. v DD_mod ; in, v DD_mod for The value corresponding to the DD phase. v MM_mod for The value corresponding to the MM phase. v NN_mod for In the phase corresponding to NN, MM, DD, and NN are respectively defined as... v x_mod The phase of the maximum, median and minimum values.

4. The parallel three-level inverter modulation method as described in claim 1, characterized in that, The equivalent five-level reference signal is decomposed into two sets of first three-level reference signals and second three-level reference signals suitable for the sub-inverter, including: [ v MM_sec， v DD_sec， v NN_sec When the parity is [1,0,0], [1,1,1] or [0,1,0]: ； [ v MM_sec， v DD_sec， v NN_sec When the parity is [0,1,1] or [0,0,1]: ； [ v MM_sec， v DD_sec， v NN_sec When the parity is [0,0,0], [1,1,0], or [1,0,1]: ； in, , v x_inte1 It is to realize the state decomposition mapping from a five-level system to two three-level systems. v x_inte1 +1 corresponds to the highest output level of the inverter. v MM_sec Represents the interval identification signal v x_sec correspond v x_mod The components of the MM phase; v DD_sec代表 Interval identification signal v x_sec correspond v x_mod The components of the DD phase; v NN_sec代表 Interval identification signal v x_sec correspond v x_mod The components of the NN phase; This represents a three-level reference signal applicable to the corresponding MM phase of the first inverter; This represents the first intermediate reference signal corresponding to the MM phase; This represents a three-level reference signal applicable to the corresponding DD phase of the first sub-inverter; This represents the first intermediate reference signal corresponding to the DD phase; This represents a three-level reference signal applicable to the corresponding NN phase of the first sub-inverter; This represents the second intermediate reference signal corresponding to the NN phase; This represents a three-level reference signal corresponding to the MM phase applicable to the second sub-inverter; This represents the second intermediate reference signal corresponding to the MM phase; This represents a three-level reference signal applicable to the corresponding DD phase of the second sub-inverter; This represents the second intermediate reference signal corresponding to the DD phase; This represents a three-level reference signal applicable to the corresponding NN phase of the second sub-inverter; This represents the first intermediate reference signal corresponding to the NN phase.

5. The parallel three-level inverter modulation method as described in claim 1, characterized in that, AC output voltage of dual parallel three-level inverter , It has five voltage levels, represented by 0, 1, 2, 3, and 4 respectively. The five voltage levels correspond to... V dc The multiples of / 2 are -1, -0.5, 0, 0.5, and 1, respectively. x1 and V x2 The first inverter and the second inverter are respectively Phase voltage, where x is any one of phases A, B, and C. V dc This represents the amplitude of the DC power supply.

6. The parallel three-level inverter modulation method as described in claim 5, characterized in that, ； in, S x1 and S x2 The first inverter and the second inverter are respectively x Phase branch switch status.

7. A parallel three-level inverter modulation system, characterized in that, include: The identification signal generation unit is configured to: treat the dual parallel three-level inverter as an overall five-level inverter, inject a zero-sequence component into the initial three-phase reference signal to obtain a reference signal, and perform rounding and remainder operation on the reference signal to obtain an interval identification signal and a phase state change sequence identification signal; The reference signal adjustment unit is configured to modify and adjust the reference signal according to the sum of the three-phase states of the starting composite vector corresponding to the interval identification signal and in combination with the phase state change sequence identification signal to obtain the adjusted equivalent five-level reference signal. The reference signal decomposition unit is configured to decompose the equivalent five-level reference signal into two sets of first three-level reference signals and second three-level reference signals suitable for the sub-inverter. The signal distribution unit is configured to: divide two consecutive carrier cycles into four half-carrier cycles; in the first half-carrier cycle and the fourth half-carrier cycle, distribute a first three-level reference signal to the first inverter and distribute a second three-level reference signal to the second inverter; in the second half-carrier cycle and the third half-carrier cycle, distribute a second three-level reference signal to the first inverter and distribute a first three-level reference signal to the second inverter. The carrier comparison unit is configured to compare the reference signal allocated to the corresponding inverter in each half-carrier cycle with two triangular carriers applicable to the three-level inverter to obtain a combination of three-level vector sequences.

8. A computer device, characterized in that, include: Processor and computer-readable storage media; A processor, adapted to execute computer programs; A computer-readable storage medium storing a computer program, which, when executed by the processor, implements the parallel three-level inverter modulation method as described in any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program adapted to be loaded by a processor and executed as described in any one of claims 1 to 6.

10. A computer program product, characterized in that, The computer program product includes a computer program that, when executed by a processor, implements the parallel three-level inverter modulation method as described in any one of claims 1 to 6.

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