A test circuit and a test method for a power semiconductor device

Abstract

The application relates to the technical field of power semiconductor device testing, and discloses a test circuit and a test method of a power semiconductor device. The test circuit comprises an energy storage module, a controller, a first switch control module and a second switch control module, the energy storage module is used for providing a power supply signal for the test circuit, the energy storage module, the first switch control module and the second switch control module are sequentially electrically connected, and two ends of the second switch control module are used for connecting a to-be-tested power semiconductor device in parallel; the controller is connected with control ends of the respective switch control modules, and the on and off of the first switch control module and the second switch control module are controlled to control the charging and discharging of an output capacitor of the to-be-tested power semiconductor device. Therefore, relevant personnel can measure the application characteristics of the power semiconductor device by evaluating the output capacitor loss, and the reliability of the power semiconductor device is improved.

Description

Technical Field

[0001] This application relates to the field of power semiconductor device testing technology, and in particular to a test circuit and test method for power semiconductor devices. Background Technology

[0002] With the continuous advancement of technology, power semiconductor devices have become an indispensable core component in modern power electronic devices, meeting the high-performance requirements of many fields, from home appliances to industrial automation, from electric vehicles to renewable energy systems, and playing a vital role in numerous fields.

[0003] In existing technologies, the application characteristics of power semiconductor devices are typically measured by evaluating switching losses and conduction losses. While this method provides important performance metrics, it is insufficient to fully reflect the overall performance and applicability of the device. This evaluation approach may lead to deviations in the device's performance in real-world applications, causing unpredictable consequences. Summary of the Invention

[0004] In view of this, the present application provides a test circuit and test method for power semiconductor devices, which can effectively solve the problem that the prior art of evaluating the application characteristics of power semiconductor devices by assessing switching losses and conduction losses may lead to deviations in the actual application of the devices and cause unpredictable effects.

[0005] In a first aspect, embodiments of this application provide a test circuit for a power semiconductor device, comprising: an energy storage module, a controller, a first switch control module, and a second switch control module, wherein the energy storage module is used to supply power to the test circuit;

[0006] The positive output of the energy storage module is electrically connected to the input of the first switch control module, the output of the first switch control module is connected to the input of the second switch control module, the output of the second switch control module is connected to the negative output of the energy storage module, and the two ends of the second switch control module are used to receive a power semiconductor device in parallel.

[0007] The controller is electrically connected to the control terminals of the first switch control module and the second switch control module, respectively. The controller is used to control the charging and discharging of the output capacitor of the power semiconductor device under test by controlling the on and off states of the first switch control module and the second switch control module.

[0008] In some embodiments, the test circuit for the power semiconductor device further includes an anti-interference module, one end of which is connected to the control terminal of the power semiconductor device under test, and the other end of which is connected to the negative output terminal of the energy storage module.

[0009] In some embodiments, the anti-interference module includes an anti-interference resistor, one end of which is connected to the control terminal of the power semiconductor device under test, and the other end of which is connected to the negative output terminal of the energy storage module.

[0010] In some embodiments, the resistance value of the anti-interference resistor is a first preset ohm.

[0011] In some embodiments, the test circuit of the power semiconductor device further includes a filter module, wherein the input terminal of the filter module is connected to the positive output terminal of the energy storage module, and the output terminal of the filter module is connected to the input terminal of the first switch control module.

[0012] In some embodiments, the filtering module includes at least one set of filtering units, each set of filtering units including a first filtering capacitor and a second filtering capacitor, one end of the first filtering capacitor being connected to the positive output terminal of the energy storage module, the other end of the first filtering capacitor being connected to one end of the second filtering capacitor, and the other end of the second filtering capacitor being connected to the negative output terminal of the energy storage module.

[0013] In some embodiments, the energy storage module includes at least two energy storage capacitors connected in series.

[0014] In some embodiments, the first switch control module includes: a first switch transistor, the input terminal of the first switch transistor being electrically connected to the energy storage module, the output terminal of the first switch transistor being connected to the input terminal of the second switch control module, and the control terminal of the first switch transistor being electrically connected to the controller.

[0015] In some embodiments, the second switch control module includes: a second switch transistor, the input terminal of which is connected to the input terminal of the power semiconductor device under test, the output terminal of which is connected to the negative output terminal of the energy storage module, and the control terminal of which is electrically connected to the controller.

[0016] Secondly, embodiments of this application provide a testing method for a power semiconductor device, wherein the testing method is applied to a testing circuit for at least one power semiconductor device as described in the first aspect above, and the testing method includes:

[0017] Obtain the first temperature of the power semiconductor device under test;

[0018] By controlling the first switch control module and the second switch control module, the output capacitor of the power semiconductor device under test is charged and discharged according to the set operating frequency;

[0019] Obtain the second temperature of the power semiconductor device under test;

[0020] The temperature rise of the power semiconductor under test is obtained based on the first temperature and the second temperature.

[0021] The embodiments of this application have the following beneficial effects:

[0022] The test circuit for the power semiconductor device of this application includes: an energy storage module, a controller, a first switch control module, and a second switch control module. The energy storage module provides a power signal to the test circuit. The energy storage module is electrically connected to the input terminal of the first switch control module. The output terminal of the first switch control module is connected to the input terminal of the second switch control module, and the output terminal of the second switch control module is connected to the negative output terminal of the energy storage module. The input terminal of the second switch control module is connected to the input terminal of the power semiconductor device under test (PSD), and the output terminal of the PSD is connected to the negative output terminal of the energy storage module. The controller is electrically connected to the control terminals of both the first and second switch control modules. The controller controls the charging and discharging of the output capacitor of the PSD by controlling the on / off state of the first and second switch control modules. This allows relevant personnel to evaluate the output capacitor loss of the PSD and measure the application characteristics of the power semiconductor device by evaluating the switching loss, conduction loss, and output capacitor loss. This evaluation method can more comprehensively reflect the overall performance and applicability of the device, improving the reliability of the power semiconductor device. Attached Figure Description

[0023] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 A schematic diagram of the MOS transistor structure according to an embodiment of this application is shown;

[0025] Figure 2 A first structural schematic diagram of the test circuit of a power semiconductor device according to an embodiment of this application is shown;

[0026] Figure 3 This paper shows a second structural schematic diagram of the test circuit for a power semiconductor device according to an embodiment of the present application;

[0027] Figure 4 A circuit diagram of a test circuit for a power semiconductor device according to an embodiment of this application is shown;

[0028] Figure 5A waveform diagram of a test circuit for a power semiconductor device according to an embodiment of this application is shown;

[0029] Figure 6 A schematic flowchart of a testing method for a power semiconductor device according to an embodiment of this application is shown.

[0030] Explanation of key component symbols:

[0031] 10: Energy storage module; 20: Controller; 30: First switch control module; 40: Second switch control module; 50: Power semiconductor device under test; 60: Anti-interference module; 70: Filtering module. Detailed Implementation

[0032] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0033] The components of the embodiments of this application described and illustrated in the accompanying drawings can be arranged and designed in a variety of different configurations. Therefore, the following detailed description of the embodiments of this application provided in the drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0034] In the following text, the terms "comprising," "having," and their cognates, which may be used in various embodiments of this application, are intended only to indicate a particular feature, number, step, operation, element, component, or combination thereof, and should not be construed as primarily excluding the presence of one or more other features, numbers, steps, operations, elements, components, or combinations thereof, or adding the possibility of one or more combinations thereof. Furthermore, the terms "first," "second," "third," etc., are used only for distinguishing descriptions and should not be construed as indicating or implying relative importance.

[0035] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the various embodiments of this application pertain. Terms (such as those defined in commonly used dictionaries) shall be interpreted as having the same meaning as in their contextual meaning in the relevant technical field and shall not be construed as having an idealized or overly formal meaning, unless clearly defined in the various embodiments of this application.

[0036] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0037] Considering that existing technologies measure the application characteristics of power semiconductor devices by evaluating switching losses and conduction losses, which may lead to deviations in the actual performance of the devices and cause unpredictable consequences, this application provides a test circuit and test method for power semiconductor devices. The controller in this application controls the charging and discharging of the output capacitor of the power semiconductor device under test by controlling the on / off states of a first switch control module and a second switch control module. This allows relevant personnel to evaluate the output capacitor loss of the power semiconductor device under test, and to measure the application characteristics of the power semiconductor device by evaluating switching losses, conduction losses, and output capacitor losses. This evaluation method can more comprehensively reflect the overall performance and applicability of the device, improving the reliability of the power semiconductor device.

[0038] It is understood that the power semiconductor device under test in this application can be any kind of power semiconductor device. The power semiconductor device under test can be a MOSFET, an IGBT, a transistor, a GaN device, etc., and by way of example, the power semiconductor device under test is a MOSFET.

[0039] Due to the internal structure and material properties of power semiconductor devices, parasitic capacitance exists between any two pins of a power semiconductor device. Figure 1 A schematic diagram of a MOSFET structure is shown. Specifically, there is a gate-source parasitic capacitance Cgs between the gate and source of MOSFET M1, a gate-drain parasitic capacitance Cgd between the gate and logic gate of MOSFET M1, and a drain-source parasitic capacitance Cds between the drain and source of MOSFET M1. The gate-drain parasitic capacitance Cgd and the drain-source parasitic capacitance Cds together constitute the output capacitor Coss. The output capacitor Coss charges and discharges when the power semiconductor device switches. During the discharge process, some energy is converted into heat, resulting in an energy difference during the charging and discharging process of the output capacitor Coss, causing losses in the output capacitor Coss. The charging and discharging of the output capacitor Coss can be controlled using the test circuit of the power semiconductor device described in this application.

[0040] The test circuit for this power semiconductor device will be described below with reference to some specific embodiments.

[0041] Figure 2A schematic diagram of a test circuit for a power semiconductor device according to an embodiment of this application is shown. Exemplarily, the test circuit for the power semiconductor device includes: an energy storage module 10, a controller 20, a first switch control module 30, and a second switch control module 40. The energy storage module 10 provides a power signal to the test circuit. Exemplarily, the energy storage module 10 includes an energy storage capacitor, which powers the test circuit.

[0042] The positive output of the energy storage module 10 is electrically connected to the input of the first switch control module 30. The output of the first switch control module 30 is connected to the input of the second switch control module 40, and the output of the second switch control module 40 is connected to the negative output of the energy storage module 10. The input of the second switch control module 40 is used to connect to the input of the power semiconductor device under test 50, and the output of the power semiconductor device under test 50 is connected to the negative output of the energy storage module 10. Furthermore, the control terminal of the power semiconductor device under test 50 is used to input the turn-off control signal of the power semiconductor device under test 50 to avoid the generation of switching losses or conduction losses in the power semiconductor device under test 50.

[0043] Understandably, controller 20 can be any type of controller, including MCU, FPGA, DSP, CPU, etc. Exemplarily, controller 20 is an MCU, electrically connected to the control terminals of the first switch control module 30 and the second switch control module 40, respectively, to control the on / off states of the first switch control module 30 and the second switch control module 40.

[0044] Understandably, the first switch control module 30 can be any type of switch circuit. A switching transistor can be included in the first switch control module 30, and the controller 20 controls the on / off state of the first switch control module 30 through the switching transistor. Alternatively, an optocoupler can be included in the first switch control module 30, and the controller 20 controls the on / off state of the first switch control module 30 through the optocoupler. A relay can also be included in the first switch control module 30, and the controller 20 controls the on / off state of the first switch control module 30 through the relay, etc. The second switch control module 40 can have the same structure as the first switch control module 30, or it can have a different structure.

[0045] The controller 20 controls the charging and discharging of the output capacitor Coss of the power semiconductor device under test 50 by controlling the on and off states of the first switch control module 30 and the second switch control module 40. Specifically, the controller can control the first switch control module 30 and the second switch control module 40 to be turned on sequentially according to a preset timing sequence. For example, when the first switch control module 30 is turned on and the second switch control module 40 is turned off, the output capacitor Coss of the power semiconductor device under test 50 is charged; when the second switch control module 40 is turned on and the first switch control module 30 is turned off, the output capacitor Coss of the power semiconductor device under test 50 is discharged. The charging and discharging frequency of the output capacitor Coss can be controlled according to the actual application. It can be understood that the on and off process of the power semiconductor device under test 50 is the charging and discharging process of the output capacitor Coss of the power semiconductor device under test 50. Therefore, the charging and discharging frequency of the output capacitor Coss is the operating frequency of the power semiconductor device under test 50.

[0046] The charging and discharging process of the output capacitor Coss converts some energy into heat, causing the temperature of the power semiconductor device under test (PSD) 50 to rise. The energy consumption of the output capacitor Coss of the PSD 50 can be evaluated based on the temperature rise of the PSD 50 before and after multiple charge-discharge cycles at the operating frequency. The higher the temperature rise of the PSD 50 after discharge, the greater the energy consumption of the output capacitor Coss. It is understood that the temperature rise of the PSD 50 is detected by a sensor and calculated by the controller 20, or it can be measured and calculated by relevant personnel.

[0047] Furthermore, the controller 20 can adjust the operating frequency of the power semiconductor device under test 50 by adjusting the signals input to the first switch control module 30 and the second switch control module 40. Then, based on the temperature rise of the power semiconductor device under test 50, the controller can evaluate the change in output loss (Coss) of the output capacitor of the power semiconductor device under test at different operating frequencies. This ensures that researchers not only consider the chip area of ​​the power semiconductor device as a factor affecting its temperature rise, but also the impact of the output capacitor Coss loss on the temperature rise, further optimizing the thermal management of the power semiconductor device, improving its efficiency, and enhancing its reliability.

[0048] In this embodiment, the test circuit for the power semiconductor device uses a controller 20 to control the charging and discharging of the output capacitor Coss of the power semiconductor device 50 under test by controlling the on / off states of the first switch control module 30 and the second switch control module 40. This allows personnel to evaluate the output capacitor Coss loss of the power semiconductor device 50 under test and consider the output capacitor Coss loss as one of the factors affecting temperature rise, thus helping them design more efficient, reliable, and cost-effective power semiconductor devices.

[0049] As an alternative solution, Figure 3 The diagram shown is another schematic representation of a test circuit for a power semiconductor device. Accordingly, Figure 4 As shown Figure 3 A circuit diagram of a test circuit for power semiconductor devices.

[0050] In one embodiment, such as Figure 3 and Figure 4 As shown, based on the above embodiment, the energy storage module 10 includes a first energy storage capacitor EC1 and a second energy storage capacitor EC2. The first energy storage capacitor EC1 serves as the top energy storage capacitor to provide a power signal to the test circuit. The second energy storage capacitor EC2 serves as the end energy storage capacitor, with its positive terminal connected to the negative terminal of the first energy storage capacitor EC1. Its negative terminal serves as the output negative terminal of the energy storage module 10. By setting two energy storage capacitors, the total energy storage capacity of the energy storage module 10 can be increased. At the same time, the voltage can be shared by the series-connected energy storage capacitors, so that the voltage borne by each energy storage capacitor is lower than its rated value, thereby improving the safety and reliability of the system.

[0051] It is understood that, as another implementation, the energy storage module 10 may also include three energy storage capacitors. The energy storage module 10 may include any number of capacitors, more than one, and the parameters of each energy storage capacitor can be set according to the actual application.

[0052] Exemplary, such as Figure 4 As shown, the first switch control module 30 includes a first switch transistor Q1, and the second switch control module 40 has the same structure as the first switch control module 30, including a second switch transistor Q2. The input terminal of the first switch transistor Q1 is connected to the positive terminal of the first energy storage capacitor EC1, and the output terminal of the first switch transistor Q1 is connected to the input terminal of the second switch transistor Q2. The input terminal of the second switch transistor Q2 is also used to connect to the input terminal of the power semiconductor device under test 50, and the output terminal of the second switch transistor Q2 is connected to the output negative terminal of the energy storage module 10. The controller 20 is electrically connected to the control terminals of the first switch transistor Q1 and the second switch transistor Q2 respectively. By controlling the conduction and cutoff of the first switch transistor Q1 and the second switch transistor Q2, the controller controls the charging and discharging of the output capacitor Coss of the power semiconductor device under test 50.

[0053] Specifically, Figure 5 A waveform diagram of a test circuit for a power semiconductor device is shown. In the T0-T1 stage, the first switch Q1 is turned on and the second switch Q2 is turned off, and the output capacitor Coss of the power semiconductor device under test 50 is charged. In the T1-T2 stage, the first switch Q1 is turned off and the second switch Q2 is turned off. In the T2-T3 stage, the first switch Q1 is turned off and the second switch Q2 is turned on, and the output capacitor Coss of the power semiconductor device under test 50 is discharged.

[0054] T1, T2, T3, and T4 can be set according to the actual application. For example, the period of the control signal of the first switch Q1 can be set to 13us, where the first 3us is a high-level signal and the first switch Q1 is turned on, and the last 10us is a low-level signal and the first switch Q1 is turned off. The period and pulse width of the second switch Q2 are the same as those of the first switch Q1. When the first switch Q1 is turned off for 0.5us, the second switch Q2 is turned on.

[0055] When the first switch Q1 is turned on and the second switch Q2 is turned off, the voltage Vgs between the gate and source of the first switch Q1 gradually decreases. The signal from the energy storage module 10 charges the gate-drain parasitic capacitance Cgd and drain-source parasitic capacitance Cds of the power semiconductor device under test 50, i.e., the output capacitance Coss of the power semiconductor device under test 50, through the first switch Q1. After the output capacitance Coss is charged, the voltage rises.

[0056] When the output capacitor Coss is fully charged, the first switch Q1 is turned off and the second switch Q2 is turned on. The Vgs of the first switch increases, and the second switch Q2 forms a circuit with the output capacitor Coss of the power semiconductor device under test 50. The energy of the output capacitor Coss is released through this circuit. After the output capacitor Coss is fully discharged, the output capacitor Coss of the power semiconductor device under test 50 completes a charging and discharging process.

[0057] The test circuit for the power semiconductor device in this embodiment incorporates multiple energy storage capacitors in the energy storage module 10. These multiple capacitors significantly increase the total energy storage capacity of the energy storage module 10 while simultaneously reducing the operating voltage of each capacitor, thus improving circuit reliability. Furthermore, switching transistors are incorporated into the first switch control module 30 and the second switch control module 40. These transistors control the on / off states of the first and second switch control modules 30 and 40, respectively. The switching transistors are easy to drive and have low cost.

[0058] In one embodiment, such as Figure 3 and Figure 4As shown, based on the above embodiment, the test circuit for the power semiconductor device further includes an anti-interference module 60. One end of the anti-interference module 60 is connected to the control terminal of the power semiconductor device under test 50, and the other end is connected to the negative output terminal of the energy storage module 10. Exemplarily, the anti-interference module 60 is an anti-interference resistor R1. Using the anti-interference resistor R1, the signal at the control terminal of the power semiconductor device under test 50 is pulled low, preventing the second switching transistor Q2 from conducting and causing electromagnetic interference to the power semiconductor device under test 50. This prevents the power semiconductor device under test 50 from being mis-connected, ensuring that the temperature rise of the power semiconductor device under test 50 is only related to the energy consumption of the output capacitor Coss.

[0059] The resistance value of the anti-interference resistor R1 can be set according to the actual application. It is understood that the anti-interference resistor R1 should be low resistance. For example, the resistance value of the anti-interference resistor R1 is 0.2Ω.

[0060] To improve the signal quality of the energy storage module 10, the test circuit of the power semiconductor device also includes a filter module 70. The input terminal of the filter module 70 is connected to the output terminal of the energy storage module 10, and the output terminal of the filter module 70 is connected to the input terminal of the first switch control module 30. The filter module 70 is used to filter the signal of the energy storage module 10.

[0061] Exemplarily, the filter module 70 includes two sets of filter units. The first set of filter units includes a first filter capacitor C1 and a second filter capacitor C2. One end of the first filter capacitor C1 is connected to the positive terminal of the first energy storage capacitor EC1, and the other end of the first filter capacitor C1 is connected to one end of the second filter capacitor C2. The other end of the second filter capacitor C2 is connected to the negative output terminal of the energy storage module 10. The second set of filter units includes a third filter capacitor C3 and a fourth filter capacitor C4. The third filter capacitor C3 and the fourth filter capacitor C4 are connected in series and then in parallel with the first filter capacitor C1 and the second filter capacitor C2. The series-connected filter capacitors can share the voltage stress on each series-connected filter capacitor, reducing the risk of overvoltage damage to a single filter capacitor. The parallel-connected filter capacitors can significantly reduce the equivalent series resistance of the entire filter module 70, thereby reducing losses caused by internal resistance and improving system efficiency.

[0062] In this embodiment, the test circuit for the power semiconductor device includes anti-interference resistors R1 at the control and output terminals of the power semiconductor device under test (DUT) 50. These resistors prevent the DUT from experiencing mis-conduction, which could lead to switching or conduction losses, ensuring that the temperature rise of the DUT 50 is only related to the energy consumption of the output capacitor Coss. Furthermore, a filter module 70 is provided at the output terminal of the energy storage module 10. This filter module 70 improves the quality of the signal input to the first switching transistor Q1, further enhancing the stability and reliability of the circuit.

[0063] This application also provides a testing method for power semiconductor devices. Figure 6 The diagram shown is a schematic flowchart of a testing method for a power semiconductor device according to an embodiment of this application. This testing method is applied to the testing circuit of the power semiconductor device mentioned in the above embodiment. The testing method is executed by the controller 20 in the testing circuit of the power semiconductor device and includes:

[0064] Step S101: Obtain the first temperature of the power semiconductor device 50 under test.

[0065] The temperature of the power semiconductor device 50 under test is detected by a temperature sensor or other temperature detection device before the output capacitor Coss is charged and discharged, and the temperature is transmitted to the controller 20 as the first temperature.

[0066] Step S102: By controlling the first switch control module 30 and the second switch control module 40, the output capacitor Coss of the power semiconductor device under test 50 is charged and discharged according to the set operating frequency.

[0067] Understandably, the operating frequency of the power semiconductor device under test 50 can be set according to the actual application. The turn-on and turn-off process of the power semiconductor device under test 50 is the charging and discharging process of the output capacitor Coss of the power semiconductor device under test 50. Therefore, the operating frequency of the power semiconductor device under test 50 is the charging and discharging frequency of the output capacitor Coss.

[0068] When the first switch control module 30 is turned on and the second switch control module 40 is turned off, the output capacitor Coss of the power semiconductor device under test 50 is charged; when the second switch control module 40 is turned on and the first switch control module 30 is turned off, the output capacitor Coss of the power semiconductor device under test 50 is discharged. By controlling the on and off states of the first switch control module 30 and the second switch control module 40, the charging and discharging frequency of the output capacitor Coss is controlled, so that the output capacitor Coss is charged and discharged multiple times.

[0069] Step S103: Obtain the second temperature of the power semiconductor device 50 under test.

[0070] The temperature of the power semiconductor device 50 under test after multiple charge-discharge cycles of the output capacitor Coss is detected by a temperature sensor or other temperature detection device and transmitted to the controller 20. Furthermore, the temperature of the power semiconductor device 50 under test after multiple charge-discharge cycles of the output capacitor Coss can be collected multiple times to obtain a stable temperature after multiple charge-discharge cycles, and this stable temperature is used as the second temperature.

[0071] Step S104: Obtain the temperature rise of the power semiconductor under test based on the first and second temperatures.

[0072] Subtracting the first temperature from the second temperature gives the temperature rise of the power semiconductor under test. Based on the temperature rise of the power semiconductor device 50 under test, relevant personnel can evaluate the Coss energy consumption of the output capacitor of the power semiconductor device 50 under test. The higher the temperature rise of the power semiconductor device 50 under test after discharge, the greater the Coss energy consumption of the output capacitor.

[0073] In this embodiment, by obtaining the temperature difference between the power semiconductor device 50 under test before multiple charge-discharge cycles at the operating frequency and the temperature after multiple charge-discharge cycles at the operating frequency, the temperature rise caused by output loss is obtained. This allows relevant personnel to evaluate the Coss loss of the output capacitor of the power semiconductor device 50 under test based on the temperature rise, further improving the reliability of the power semiconductor device.

[0074] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can also be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings show the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that, in alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, and combinations of blocks in the block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0075] In addition, the functional modules or units in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0076] If the aforementioned functions are implemented as software functional modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a smartphone, personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application.

[0077] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. A test circuit for a power semiconductor device, characterized in that, include: The test circuit includes an energy storage module, a controller, a first switch control module, and a second switch control module, wherein the energy storage module is used to supply power to the test circuit. The positive output of the energy storage module is electrically connected to the input of the first switch control module, the output of the first switch control module is connected to the input of the second switch control module, the output of the second switch control module is connected to the negative output of the energy storage module, and the two ends of the second switch control module are used to receive a power semiconductor device in parallel. The controller is electrically connected to the control terminals of the first switch control module and the second switch control module, respectively. The controller is used to control the charging and discharging of the output capacitor of the power semiconductor device under test by controlling the on and off states of the first switch control module and the second switch control module.

2. The test circuit for the power semiconductor device according to claim 1, characterized in that, The test circuit for the power semiconductor device further includes an anti-interference module, one end of which is connected to the control terminal of the power semiconductor device under test, and the other end of which is connected to the negative output terminal of the energy storage module.

3. The test circuit for the power semiconductor device according to claim 2, characterized in that, The anti-interference module includes an anti-interference resistor, one end of which is connected to the control terminal of the power semiconductor device under test, and the other end of which is connected to the negative output terminal of the energy storage module.

4. The test circuit for the power semiconductor device according to claim 3, characterized in that, The resistance value of the anti-interference resistor is a first preset ohm.

5. The test circuit for the power semiconductor device according to claim 1, characterized in that, The test circuit for the power semiconductor device further includes a filter module, the input terminal of which is connected to the positive output of the energy storage module, and the output terminal of which is connected to the input of the first switch control module.

6. The test circuit for the power semiconductor device according to claim 5, characterized in that, The filtering module includes at least one set of filtering units, each set of filtering units including a first filtering capacitor and a second filtering capacitor. One end of the first filtering capacitor is connected to the positive output terminal of the energy storage module, the other end of the first filtering capacitor is connected to one end of the second filtering capacitor, and the other end of the second filtering capacitor is connected to the negative output terminal of the energy storage module.

7. The test circuit for the power semiconductor device according to claim 1, characterized in that, The energy storage module includes at least two energy storage capacitors connected in series.

8. The test circuit for the power semiconductor device according to claim 1, characterized in that, The first switch control module includes: a first switch transistor, the input terminal of which is electrically connected to the energy storage module, the output terminal of which is connected to the input terminal of the second switch control module, and the control terminal of which is electrically connected to the controller.

9. The test circuit for the power semiconductor device according to claim 1, characterized in that, The second switch control module includes: a second switch transistor, the input terminal of which is connected to the input terminal of the power semiconductor device under test, the output terminal of which is connected to the negative output terminal of the energy storage module, and the control terminal of which is electrically connected to the controller.

10. A testing method for power semiconductor devices, characterized in that, A test circuit applied to the power semiconductor device according to any one of claims 1-9, the test method comprising: Obtain the first temperature of the power semiconductor device under test; By controlling the first switch control module and the second switch control module, the output capacitor of the power semiconductor device under test is charged and discharged according to the set operating frequency; Obtain the second temperature of the power semiconductor device under test; The temperature rise of the power semiconductor under test is obtained based on the first temperature and the second temperature.

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