Power device dynamic and static test and modeling integrated system and method

Abstract

The application provides a power device dynamic and static test and modeling integrated system and method. The system comprises a device under test bearing and safety interface module, a dynamic double pulse test module for dynamic test of the power device, a static parameter test module for static test of the power device, a heating and temperature control module for heating, temperature measurement and temperature control of the power device, a parasitic consistency simulation and modeling module for generating an initial model according to the dynamic and static test results, performing model transient characteristic simulation and outputting a target high-precision device electrothermal model, a test task scheduling and instrument control module for overall coordination of test processes of the test modules and model generation and simulation output of the parasitic consistency simulation and modeling module, and a hardware data interaction module for performing configuration, triggering and reading operations on each hardware device of the dynamic double pulse test module and the static parameter test module. The application ensures consistency of the model and the actual test conditions and system-level engineering practicability.

Description

Technical Field

[0001] This invention relates to the field of power semiconductor device testing and model building technology, specifically to an integrated system and method for dynamic and static testing and modeling of power devices, and also to a corresponding integrated device and computer-readable storage medium. Background Technology

[0002] Third-generation wide-bandgap power devices are characterized by high voltage withstand, high temperature, and high switching speed. In practical applications, they are often subjected to extreme switching stresses and complex parasitic coupling environments with high dv / dt and high di / dt. Comprehensive and accurate dynamic and static electrical characterization, whether for single dies or packaged devices, is fundamentally crucial for evaluating device consistency and ensuring the reliability of multi-core parallel modules and the final system. However, while existing discrete testing schemes have accumulated massive amounts of test data, the physical separation of dynamic and static test links and the lack of strict alignment of parasitic parameter boundaries make it difficult to deeply integrate and utilize this fragmented data. The vast amount of test data often remains at a superficial stage of "looking at the results" without core value, failing to be directly and automatically transformed into high-precision device electrical models. Therefore, it is difficult to truly serve downstream applications in device selection, system-level high-fidelity simulation, and reliability design.

[0003] Meanwhile, the "engineering usability characteristics" of power devices depend not only on static indicators (such as breakdown, leakage current, on-resistance, threshold, etc.), but also strongly on their dynamic switching processes (such as turn-on / turn-off losses, ringing, overshoot, reverse recovery, short-circuit robustness, etc.). Furthermore, dynamic behavior is extremely sensitive to the parasitic parameters of the test / application platform (package / fixture / busbar / PCB trace / probe access method, etc.). Even if the device model is relatively accurate, as long as the parasitic environment of the test board and the simulation circuit is inconsistent, the simulation waveform based on the model is difficult to align with the actual measurement, and the constructed model cannot directly guide the actual circuit simulation design and parameter selection.

[0004] In the prior art: In static testing, the common industry approach is to use voltage and current measuring sources and LCR meters as measurement instruments, and to achieve different port connections and multiplexing of different ranges and functions through matrix switching to complete tests such as output characteristics, transfer characteristics, and leakage current, as well as to characterize CV / small signal parameters with high-voltage bias. The industry already has relatively mature dedicated power device analyzers and curve tracing systems, such as Keysight's B1505A and B1506A.

[0005] In dynamic testing, the mainstream method for characterizing switching losses, reverse recovery, and dynamic charge / capacitance effects remains the dual-pulse test (DPT) topology. Existing solutions typically consist of a DC bus capacitor, a power loop, an inductive load, a driver board, and a high-bandwidth measurement link, reducing overshoot and ringing by decreasing the power loop inductance. However, for wide-bandgap devices, especially in die or packaged interconnect scenarios, the impact of loop parasitics and the measurement link on the waveform is more significant: different fixtures and connection methods introduce different equivalent loop inductances and parasitic capacitances, thus altering overshoot, ringing frequency, and attenuation, consequently affecting switching losses and the stability of model parameter inversion.

[0006] In power semiconductor device modeling, existing technologies mostly involve exporting static IV / CV characteristic data and then performing parameter fitting and correction in environments such as SPICE or behavioral simulation. The fitting objectives are often to minimize static curve errors or to approximate dynamic waveform matching under a specific operating condition, typically lacking direct utilization and constraints of measured double-pulse data. Therefore, during subsequent experimental verification, the dynamic consistency of the model often decreases significantly due to factors such as parasitic parameters of the test board, driving conditions, bus voltage and current levels, and temperature drift, leading to substantial errors between simulation and actual measurements. Meanwhile, although upstream chip design and process development chains widely use modeling and parameter extraction platforms such as EDA / TCAD / SPICE to serve process and circuit design, the objective functions of these workflows usually revolve around the consistency of device structure, process parameters, and electrical characteristics, rather than application-oriented device modeling. They do not generate devices usable for circuit simulation from measurement data, thus still falling short of providing downstream system-level application models that can characterize high-precision, multi-operating-condition, and real-world applications.

[0007] As mentioned above, although the existing power semiconductor device testing and modeling system has formed three relatively mature technical routes—static testing, dynamic testing, and model extraction—there are still gaps and defects among them. This makes it difficult to guarantee dynamic consistency and engineering usability of the model under real-world application conditions, resulting in the following technical problems: (1) The test conditions and calibration conditions are inconsistent. Existing static and dynamic testing equipment is mostly segmented: static testing machines (such as the Keysight B1506A) measure static parameters such as IV / CV under DC bias, while dynamic testing requires a separate dual-pulse platform. Due to significant differences in circuit topology, parasitic parameters, and other circuit characteristics between testing platforms, the test results often fail to represent the behavior of devices in a unified system. Even if some platforms attempt to improve consistency through low parasitic busbars or standard fixtures, they cannot fundamentally eliminate the systematic errors caused by differences in static / dynamic testing environments.

[0008] (2) The test link and the modeling link are disconnected. Traditional modeling workflows typically follow an open-loop model of "testing—exporting data—offline fitting—simulation verification." Testing platforms usually only provide curve data for static parameters, and modeling software (such as Saber and PSpice) requires manual import of test data and manual parameter tuning to obtain approximate results. This model lacks synchronous modeling of the parasitic environment and temperature conditions of the testing process, leading to difficulties in strictly aligning simulation results with actual double-pulse experimental verification. This results in poor model transferability and frequent secondary corrections required in engineering applications.

[0009] (3) Lack of dynamic closed-loop verification and automatic modeling capabilities Existing model parameter extraction processes heavily rely on engineers' experience, and the fitting targets are often limited to static characteristic curves or approximate waveform matching for a few operating conditions. Once the model is applied to operating conditions with different parasitic parameter boundaries, its accuracy and stability decrease significantly. In addition, the modeling process usually lacks automated iterative optimization capabilities based on comparison with measured dynamic results, making it difficult to form a data-driven closed-loop correction for real operating conditions. Summary of the Invention

[0010] To address the aforementioned shortcomings in the prior art, this invention provides an integrated system and method for dynamic and static testing and modeling of power devices, along with a corresponding integrated device and computer-readable storage medium.

[0011] According to a first aspect of the present invention, an integrated system for dynamic and static testing and modeling of power devices is provided, comprising: The device under test (DUT) carries a security interface module, which receives power devices used for testing and modeling. These power devices are either bare power chips or packaged devices. The dynamic double-pulse test module is used to perform dynamic testing of power devices and output dynamic test results. The static parameter testing module is used to perform static tests on power devices and output the static test results. The heating and temperature control module is used to heat, measure and control the temperature of the power device so that the static parameter test module and the dynamic double pulse test module can perform tests under the set temperature conditions. Parasitic consistency simulation and modeling module, which is used to generate an initial model based on the dynamic test results and the static test results, perform transient characteristic simulation of the model, and output the electrothermal model of the target high-precision device; The test task scheduling and instrument control module is used to coordinate the test process of the static parameter test module and the dynamic double pulse test module, as well as the model generation and simulation output of the parasitic consistency simulation and modeling module. The hardware data interaction module serves as the underlying hardware data interaction channel, performing configuration, triggering, and reading operations on the hardware devices of the dynamic double-pulse test module and the static parameter test module through standard interfaces.

[0012] Preferably, the above system further includes: The user interaction module provides a test configuration interface and visualizes test results and generated models. The data management and storage module adopts a unified data structure to manage and store the entire data chain, including device information, test conditions, raw waveforms, feature extraction, model version, and error evaluation. The test task scheduling and instrument control module coordinates the parameter configuration of the user interaction module and the data acquisition and archiving of the data management and storage module.

[0013] According to a second aspect of the present invention, a method for integrating dynamic and static testing and modeling of power devices using the system described above is provided, comprising: Perform unified static and dynamic tests on power devices on the same platform to obtain static and dynamic test data at a set temperature point; Based on the static and dynamic test results, an initial model is generated, and transient characteristic simulation of the model is performed. Finally, a high-precision electrothermal model of the target device with consistent operating conditions is output, completing the dynamic and static testing and modeling of the power device.

[0014] According to a third aspect of the present invention, a computer terminal is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the computer program, can be used to run the system described above in the present invention.

[0015] According to a fourth aspect of the present invention, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, can be used to run the system described above in the present invention.

[0016] By adopting the above technical solution, the present invention has at least one of the following beneficial effects compared with the prior art: To address the issue of inconsistencies between test and calibration conditions, this invention enables integrated static and dynamic testing of power devices at a set temperature on the same platform, ensuring consistency between the test and calibration system conditions and guaranteeing data continuity and comparability.

[0017] To address the issue of disconnect between the test and modeling links, this invention establishes a modeling mechanism that ensures consistency between the test and simulation environments. This mechanism extracts parasitic parameters of the test loop during the testing phase and embeds them into the model building process. Simultaneously, the test temperature conditions and thermal boundary conditions are mapped to the thermal network model in the simulation domain, achieving physical and electrothermal consistency between the test board and the simulation circuit, thereby eliminating system deviations caused by the disconnection of links.

[0018] To address the lack of dynamic closed-loop verification and automatic modeling capabilities, this invention constructs a model closed-loop optimization and one-click generation technology based on dynamic result differences. After acquiring static and dynamic data, the system can automatically identify the differences between simulation and measured data, and correct the model parameters and related features according to the difference results until the preset accuracy requirements are met, thus achieving full automation and self-consistency from testing to model generation.

[0019] In summary, this invention solves the problems of fragmented static / dynamic testing, inconsistencies between testing and simulation environments at the electrothermal boundary, and lack of closed-loop verification in the modeling process in the prior art. It proposes an integrated dynamic and static testing and modeling technology for power devices, realizing a unified platform for testing, simulation, and model generation, and improving the engineering usability and reproducibility of the model under real-world application conditions. Attached Figure Description

[0020] Other features, objects, and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings: Figure 1 This is a diagram showing the overall working architecture of a power device dynamic and static testing and modeling integrated system in a preferred embodiment of the present invention.

[0021] Figure 2 This is a diagram illustrating the overall coordination architecture of the test task scheduling and instrument control module in a preferred embodiment of the present invention.

[0022] Figure 3 This is a flowchart of the modeling and automatic optimization process of the parasitic consistency simulation and modeling module in a preferred embodiment of the present invention.

[0023] Figure 4 This is a comparison chart of static parameter (CV) verification results in a specific verification example of the present invention.

[0024] Figure 5 The above is a comparison diagram of the superposition of the model qualitative waveform and the actual switching waveform in a specific verification example of the present invention; wherein, (a) is a superposition comparison diagram of the simulated waveform and the actual waveform during the turn-on process, and (b) is a superposition comparison diagram of the simulated waveform and the actual waveform during the turn-off process.

[0025] Figure 6This is a comparison chart showing the trend of switching energy of the actual / model device changing with current under different operating conditions in a specific verification example of the present invention.

[0026] Figure 7 This is a schematic diagram of the simulation verification of a three-phase inverter system based on a test-generated model in a specific verification example of the present invention.

[0027] Figure 8 This is a flowchart illustrating the integrated dynamic and static testing and modeling process for power devices in a preferred embodiment of the present invention. Detailed Implementation

[0028] The embodiments of the present invention are described in detail below: These embodiments are implemented based on the technical solution of the present invention, and provide detailed implementation methods and specific operation processes. It should be noted that those skilled in the art can make several modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention.

[0029] Addressing the need for consistency between real-world operating conditions and model accuracy for wide-bandgap devices like silicon carbide (SiC) across the testing, verification, and application stages, this paper specifically focuses on the integrated static and dynamic testing, characterization, and modeling of bare dies and packaged SiC power devices. In existing technologies, static and dynamic testing are typically performed on different equipment and fixtures, resulting in fragmented test data and processes. Furthermore, the test conditions differ from actual application conditions, and inconsistencies exist between the test platform and the parasitic parameters and loop structures in the system environment. This makes it difficult for models built based on static measurements to accurately reproduce actual test behavior under real dynamic conditions. In addition, existing model building processes generally lack closed-loop optimization mechanisms for measured dynamic waveforms, relying on manual parameter adjustments, which is inefficient and fails to guarantee consistency with actual dynamic characteristics. In summary, existing technologies suffer from fragmented static / dynamic testing, inconsistencies between test and simulation environments, and a lack of closed-loop feedback in the modeling process.

[0030] To address the aforementioned issues, one embodiment of the present invention provides an integrated system for dynamic and static testing and modeling of power devices. This system enables unified static and dynamic testing of power devices on a single platform, ensuring a consistent testing and modeling environment. It also achieves automatic closed-loop optimization of the model based on dynamic result feedback and one-click model generation, thereby improving the consistency between the built model and the measured dynamic behavior and its system-level engineering applicability.

[0031] Specifically, the integrated system for dynamic and static testing and modeling of power devices provided in this embodiment may include: The device under test (DUT) carries a safety interface module, which receives power devices used for testing and modeling. These power devices can be bare power chips or packaged devices. The dynamic double-pulse test module is used to perform dynamic testing of power devices and output dynamic test results. The static parameter testing module is used to perform static tests on power devices and output the static test results. Heating and temperature control module: This module is used to heat, measure and control the temperature of power devices so that the static parameter test module and the dynamic dual-pulse test module can perform tests under the set temperature conditions. Parasitic consistency simulation and modeling module: This module is used to generate an initial model based on dynamic and static test results, perform transient characteristic simulation of the model, and output the electrothermal model of the target high-precision device; The test task scheduling and instrument control module is used to coordinate the test process of the static parameter test module and the dynamic double pulse test module, as well as the model generation and simulation output of the parasitic consistency simulation and modeling module. The hardware data interaction module serves as the underlying hardware data interaction channel, performing configuration, triggering, and reading operations on various hardware devices of the dynamic double pulse test module and the static parameter test module through standard interfaces.

[0032] In some preferred embodiments, the device under test (DUT) carrier and security interface module may further include: The safety interface unit provides electrical isolation, overvoltage and overcurrent protection, port multiplexing and switching, and safety interlock between static parameter testing and dynamic double-pulse testing, ensuring that the reference port definition remains consistent when the same device under test switches between different test modes.

[0033] The bearing fixture unit is used to mechanically support, position and press the device under test, lead out the Kelvin terminal, and fix the power terminal and signal terminal, while maintaining the physical contact interface and lead parasitic boundary shared by static parameter testing and dynamic dual-pulse testing.

[0034] The loading interface unit is used to realize the manual or automatic clamping, positioning and import of the device under test. It works with the carrier fixture unit and the safety interface unit to enable the static parameter test module and the dynamic dual-pulse test module to share the same device under test access path without changing the test socket, thereby forming a unified dynamic and static hardware test link.

[0035] In some preferred embodiments, the static parameter test module and the dynamic dual-pulse test module share the device under test (DUT) carrier and safety interface module. With the test task scheduling of the test task scheduling and instrument control module, the same DUT can continuously and automatically complete the entire process of static-dynamic testing at a set temperature point under the action of the heating and temperature control module, without changing the test socket, maintaining the same connection boundary and the same lead parasitic environment.

[0036] In some preferred embodiments, the above-mentioned static parameter testing module may further include: a measurement source meter unit, a measurement impedance unit, a switch matrix board, and a lower-level control board; wherein, the switch matrix board receives the overall coordination signal of the test task scheduling and instrument control module through the lower-level control board, controls the measurement source meter unit, the measurement impedance unit, and the power path, and automatically switches the connection mode, range, and test function of different ports to realize DC parameter testing at a set temperature and AC small-signal characterization measurement of device capacitance or impedance parameters under DC bias conditions.

[0037] In some preferred embodiments, the aforementioned dynamic dual-pulse test module may further include: a DC source, a driver, a pulse signal generator board, and an oscilloscope, used to form a dynamic transient test circuit to acquire the transient waveforms of the gate-source voltage, drain-source voltage, and drain or collector current of the device under test at a set temperature; and automatically calculate key dynamic characteristic features by performing synchronous trigger alignment, effective switching interval division, threshold determination, extreme value search, slope calculation, and energy integration on the original transient waveform; wherein, the key dynamic characteristic features include at least: turn-on delay time, turn-off delay time, turn-on energy, turn-off energy, voltage change rate, current change rate, peak voltage, peak current, reverse recovery time, reverse recovery charge, and reverse recovery energy; and then the original transient waveform and the extracted features are uploaded to the host computer for archiving.

[0038] In some preferred embodiments, the dynamic double-pulse test module may further include: for performing reverse recovery tests and / or short-circuit tests on power devices.

[0039] In some preferred embodiments, the parasitic consistency simulation and modeling module described above may further include: The modeling unit is used to acquire the required curves and waveforms after completing static and dynamic tests. Using static parameter data measured under different temperature conditions, such as IV and CV, it directly calculates, empirically maps, or fits the electrical parameters and temperature-dependent parameters of the initial model. It also uses key dynamic characteristics extracted from the dynamic waveforms as dynamic constraints to jointly generate the initial model and output a model file for circuit simulation. The initial model includes at least: a static current model, a nonlinear capacitance and charge model, and a body diode-related model. Static parameters are observable electrical quantities obtained from tests, used to characterize the observable electrical characteristics of the device under test, including at least: threshold voltage, on-resistance, leakage current, and capacitance curves. The model parameters of the initial model are model coefficients corresponding to the simulation model structure, used to characterize the internal coefficients of the simulation model, including at least: static current model parameters, nonlinear capacitance or charge model parameters, and body diode-related model parameters. The former are the input basis for calculating or fitting the latter.

[0040] The model transient simulation unit, based on an initial model and incorporating a parasitic parameter network of the test hardware, performs transient characteristic simulation of the model and electrothermal coupling transient characteristics, obtaining simulation waveforms. Error quantification and evaluation are then performed using the measured operating waveforms as a benchmark to obtain the comprehensive error of the dynamic waveforms. The parasitic parameter network of the test hardware is an equivalent network constructed based on the parasitic resistance, parasitic inductance, and parasitic capacitance of the dynamic test power board, busbars, fixtures, interconnect traces, probe access, and package leads. This network is obtained through at least one of the following methods: layout or structural parameter extraction, impedance measurement, calibration experiments, and three-dimensional electromagnetic field simulation. It is provided to the model transient simulation unit as simulation boundary conditions consistent with the actual board. Simultaneously, the model transient simulation unit also combines a thermal impedance model or a thermal network model to perform joint simulation of device temperature-related electrical parameter changes. The thermal impedance model can be obtained through at least one of the following methods: finite element thermal simulation, thermal transient testing, thermal parameter identification, or table lookup fitting.

[0041] The model closed-loop automatic optimization unit uses the difference in dynamic results as the basis for correction. It performs feature correction based on the difference results, gradually improving the consistency between simulation and measured results until the preset accuracy requirements are met, and outputs the target high-precision power device electrical model.

[0042] In some preferred embodiments, the above system may further include: The user interaction module provides a test configuration interface and visualizes test results and generated models. The data management and storage module adopts a unified data structure to manage and store the entire data chain, including device information, test conditions, raw waveforms, feature extraction, model version, and error evaluation. The test task scheduling and instrument control module coordinates the parameter configuration of the user interaction module and the data acquisition and archiving of the data management and storage module.

[0043] The technical solutions provided by the above embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0044] like Figure 1 The diagram shows the overall architecture of an integrated system for dynamic and static testing and modeling of power devices. The system comprises a device-under-test (DUT) support and safety interface module, a dynamic dual-pulse testing module, a static parameter testing module, a heating and temperature control module, a parasitic consistency simulation and modeling module, and a test task scheduling and instrument control module. The system can be configured with replaceable support structures and electrical connection schemes for both bare power chips and packaged devices, ensuring consistency between the electrical reference plane and the measurement reference under different packaging forms. Specifically: The test device consists of a device under test (DUT) bearing and safety interface module, a dynamic dual-pulse test module, a static parameter test module, and a heating and temperature control module. The parasitic consistency simulation and modeling module, test task scheduling and instrument control module, user interaction module, and data management and storage module are located in the host computer.

[0045] like Figure 2 As shown, the host computer, with the test task scheduling and instrument control module at its core, coordinates the test processes of the static test module and the dynamic double-pulse test module, temperature setting and control, parameter configuration of the user interaction module, data acquisition and archiving of the data management and storage module, and electrothermal model generation and simulation output of the parasitic consistency simulation and modeling module. The data management and storage module employs a unified data structure to manage the entire data chain from "device information - test conditions - original waveform - feature extraction - model version - error evaluation," ensuring traceability and reproducible experimental conditions for the same device under different operating conditions and model versions. The underlying hardware data interaction channel uses a standard interface to... Figure 1 The hardware of the dynamic and static testing devices, such as the source meter, oscilloscope, and switch matrix, is configured, triggered, and read.

[0046] The system's testing equipment internally constructs a unified dynamic and static hardware testing link (such as a dynamic dual-pulse testing module and a static parameter testing module). Figure 1 (See the test setup shown). For static characteristic characterization, the static parameter test module employs a hardware architecture combining a Source Measure Unit (SMU) and an impedance measurement unit with a switch matrix board. The switch matrix board controls the signal / power path, enabling automatic switching between different port connection methods, ranges, and test functions. On the static side, the system can perform DC parameter tests such as output characteristics (Ids–Vds–Vgs), transfer characteristics (Ids–Vgs), and threshold voltage (Vth), as well as small-signal characterization under DC bias (such as input / output / reverse transfer capacitance Ciss / Coss / Crss). For dynamic characteristic characterization, the dynamic double-pulse test module constructs dynamic transient test loops (e.g., double-pulse test, DPT, DoublePulse Test loop, reverse recovery test loop, and short-circuit test loop) based on a DC source, driver, pulse signal generator board, and oscilloscope. The system acquires the transient waveforms of the device under test on the dynamic side, calculates key dynamic characteristic indicators, and then uploads the original waveforms and extracted features to the host computer for archiving.

[0047] The core feature of this invention in the hardware testing chain is that, unlike the traditional physically separated and segmented process where static testing is done on one device and dynamic testing on another, the static parameter testing module and the dynamic dual-pulse testing module in this system share the same device-under-test (DUT) bearer and security interface module at the physical hardware level (i.e., ...). Figure 1 (The image shows the support fixture unit). In conjunction with the system bus's test task scheduling, the system can continuously and automatically complete the entire static-dynamic testing process for the same device under test (DUT) without changing the test socket, maintaining the same connection boundaries, the same lead parasitic environment, and the same temperature conditions. This unified hardware test link fundamentally eliminates the differences in contact resistance and port parasitic inductance caused by physical transfer of the device between different test devices, as well as the characteristic differences caused by temperature drift. This provides high-quality basic data that is strictly aligned in both the time and physical domains for subsequent modeling modules.

[0048] like Figure 3 As shown, this invention implements a one-click modeling process through a parasitic consistency simulation and modeling module: after completing static and dynamic tests, the system automatically loads the required curves and waveform data, performs parameter extraction and generates an initial model, and outputs a model file (e.g., a SPICE sub-circuit / library file) that can be used for circuit simulation. The initial model includes at least: a static current model, a nonlinear capacitance / charge model, and a reverse conduction branch related model (e.g., a body diode). The parameters of the initial model can be directly calculated or fitted from static IV / CV parameters, and together with the key features extracted from the dynamic waveform, constitute the initial constraints of the model. Furthermore, a model-measurement closed-loop automatic optimization mechanism is constructed to ensure that the final generated device model can accurately approximate the characteristics of real applications. This closed-loop optimization mechanism uses the difference in dynamic results as the basis for correction. In each optimization cycle, the system performs dynamic behavior correction based on the above-mentioned difference results. Through this closed-loop correction mechanism, the system gradually improves the consistency between simulation and measurement results until the preset accuracy requirements are met, thereby outputting the final high-precision power device electrothermal model.

[0049] The integrated system for dynamic and static testing and modeling of power devices provided in the above embodiments of the present invention: An integrated dynamic and static testing and data connectivity architecture was adopted: static and dynamic testing were integrated within the same testing platform to ensure that the same device under test was characterized under consistent physical contact and temperature control conditions; an automatic correlation and transfer mechanism for dynamic and static data was established to provide a truth data source with strictly aligned states for subsequent modeling.

[0050] A dynamic test subsystem for real-world operating condition characterization is provided. Specifically, it is reflected in the collaborative work of the dynamic dual-pulse test module, the device under test (DPT) support and safety interface module, and the test task scheduling and instrument control module. The dynamic dual-pulse test module is responsible for constructing the DPT power loop, drive link, and high-bandwidth sampling link. The DPT support and safety interface module is responsible for maintaining a unified device access boundary and parasitic environment. The test task scheduling and instrument control module is responsible for switching between static and dynamic processes and synchronous triggering, thereby acquiring transient waveforms containing ringing, overshoot, and loss information under real-world application boundaries.

[0051] A consistent construction technique between the physical and simulation environments has been achieved. This is specifically reflected in the fusion of the parasitic parameter network of the test hardware by the model's transient simulation unit, and the equivalent mapping of parasitic parameters resulting from the PCB circuitry and measurement circuitry access methods during the modeling stage. Consistent construction not only includes "fusion of the test hardware parasitic parameter network," but also the construction of an equivalent simulation circuit template consistent with the measured boundary based on the test board, busbars, fixtures, interconnect traces, probe access, and package leads, enabling comparison of simulated and measured waveforms under the same parasitic boundary conditions. Furthermore, in the implementation, this test subsystem further collaborates with a temperature regulation and control module to support comparisons of electrical behavior under the same temperature boundary.

[0052] A closed-loop automatic correction modeling technique based on the model, measured operating conditions, and simulation was developed: a closed-loop iterative modeling algorithm based on the measured operating condition waveform. In the simulation circuit described above, the differences between the simulation and measured results are automatically compared, and the model parameters are corrected accordingly until the model meets the preset accuracy requirements, achieving one-click generation of the model that matches the measured result.

[0053] It achieves end-to-end fully automated modeling: a software architecture that coordinates and schedules instrument control, environmental parameter calls, simulation execution and model updates, breaks down the data barriers between physical testing and virtual simulation, and realizes fully automated operation from issuing test commands with one click to generating high-precision models.

[0054] The feasibility of the technical solution provided in the above embodiments of the present invention is verified below with specific verification examples through prototype system experiments, simulations, and actual use. The verification results are presented in three levels: static testing, dynamic testing, and closed-loop modeling application. Firstly, in terms of static testing, the system comprehensively characterized the static parameters of SiC MOSFETs and other devices under test on the prototype platform. The testing scope covered multiple dimensions of static indicators, including leakage current characteristics (such as gate-source leakage current Igss, drain-source leakage current Idss, etc.), conduction and blocking characteristics (such as gate threshold voltage Vgs_th, on-resistance Rds(on), breakdown voltage VBR_ds, etc.), and small-signal parasitic parameter characteristics (such as internal gate resistance Rg(int), input / output / reverse transfer capacitance Ciss / Coss / Crss, etc.). Cross-comparison of the above static measured data with the baseline curves in the device manufacturer's datasheet showed that the overall trend, key inflection points, and magnitudes of the curves remained highly consistent. Figure 4 The comparison results of capacitance characteristics shown demonstrate that this system has high-precision static measurement capabilities, providing reliable data input for the extraction of initial model parameters and subsequent dynamic correction.

[0055] In terms of dynamic testing, the system in this invention automatically performs double-pulse testing, reverse recovery testing, and short-circuit testing under complex boundary conditions such as multiple bus voltages, load currents, and gate drive resistances. The system successfully captures transient waveforms and accurately extracts dynamic characteristic parameters covering four major categories (taking SiC MOSFETs as an example): Turn-on characteristic parameters include turn-on delay time (Tdon), turn-on energy (Eon), turn-on current change rate (di / dt), and peak current (Idspk). Turn-off characteristic parameters include turn-off delay time (Tdoff), turn-off energy (Eoff), turn-off voltage change rate (dv / dt), and peak voltage (Vdspk). Body diode reverse recovery characteristic parameters include reverse recovery time (trr), reverse recovery charge (Qrr), and reverse recovery energy (Erec). Short-Circuit Safe Operating Area (SCSOA) parameters include short-circuit current (Isc) and short-circuit peak voltage. Through comparative repeatability tests under the same operating conditions, the system demonstrated excellent waveform consistency and repeatability in extracting dynamic characteristic indicators, providing a stable and convergent calibration basis for subsequent model-test closed-loop optimization.

[0056] Finally, at the model output level, this system incorporates a standardized model quality verification process (covering model completeness, accuracy, and rule compliance checks) to ensure the output model possesses reliable engineering verification value. The specific verification and judgment methods are as follows: First, perform a qualitative visual verification of the waveform. For example... Figure 5The comparative embodiments of the single-condition turn-on and turn-off processes shown in (a) and (b) involve superimposing the optimized simulation waveforms with the measured waveforms. The results show that the simulation model is highly consistent with the measured data in terms of curve trends. It should be noted that... Figure 5 This is only a single embodiment of visual verification. In practice, the system supports importing a multi-dimensional test condition matrix and automatically traversing and verifying the waveform accuracy of the device within the complete safe operating area.

[0057] Secondly, quantitative verification of the trend of characteristics under all operating conditions is conducted. For example... Figure 6 The comparison chart showing the trend of switching energy changing with current under different operating conditions (one of the judgment methods among many verification benchmarks of this system) demonstrates the system's quantitative judgment logic for the model's dynamic indicators: the system extracts measured and simulated characteristic indicators (such as Eon and Eoff) under multiple preset current gradients, without relying on single-point errors, but comparing the trend of the entire characteristic curve; when the simulation and measured trends under continuous operating conditions are highly consistent, and the errors at each point fall within the preset tolerance threshold, the system is judged to have met the standard. Finally, when the internal optimization loop makes the model meet the preset qualification standards in the above multi-dimensional comprehensive verification, the system judges the optimization to have converged, automatically generates and exports a high-precision electrothermal model (such as a SPICE model file) of the target device.

[0058] Finally, verification is performed on a system-level platform, such as... Figure 7 As shown, the device model generated by the system is exported and applied to system-level simulation scenarios such as external three-phase inverters. Verification of the system current waveform and key indicators demonstrates the excellent engineering application usability of the established model. It should be noted that this step is only a demonstration of the downstream extended application of the established device model (to verify the model's accuracy) and is not a necessary verification function within the testing and modeling device of this invention.

[0059] It should be noted that, without deviating from the core logic of <experiment-driven - real modeling - closed-loop verification>, this invention supports equivalent substitutions at the following levels: 1. Universal replacement of hardware platforms (1) Instruments and equipment: No specific brand or model is required. Any combination of instruments that can achieve static (IV / CV) and dynamic (DPT) acquisition and have synchronous triggering function (such as various source meters, oscilloscopes, acquisition cards, pulse power supplies, etc.) can be used as a substitute.

[0060] (2) Fixtures and environment: The clamping method is not limited to Socket, but can be replaced by probe, crimping or welding, etc.; the insulation is not limited to nitrogen filling, but can be replaced by oil bath, potting or other inert gas environment, as long as the high voltage insulation and consistency requirements are met; the heating method in the heating and temperature control module is not limited to heating table, chunk, mica sheet, infrared heating and other devices that can be heated in real line, and the temperature acquisition method is not limited to thermocouple, NTC, PT1000 and other temperature control devices such as PID control.

[0061] (3) Topology: The capacitor / inductor form and busbar structure of the DPT power circuit can be changed, as long as its parasitic parameters can be extracted and mapped to the simulation environment.

[0062] 2. Tool replacement for simulation and environment construction Parasitic extraction tools (such as various 3D electromagnetic field solvers) and circuit simulators (such as SPICE-type and behavioral simulation platforms) are not limited to specific software; any software capable of performing parameter extraction and time-domain simulation is acceptable. Similarly, thermal impedance extraction tools are not limited to specific equipment or implementation methods; any software capable of performing thermal impedance extraction, thermal network parameter acquisition, or thermal boundary modeling is acceptable, including but not limited to thermal impedance testing equipment, finite element thermal simulation platforms, and thermal parameter identification methods.

[0063] 3. Algorithm and Model Architecture Strategy Replacement (1) Optimization algorithm: The closed-loop optimization and error correction module is not limited to a specific algorithm. It can adopt genetic algorithm (GA), particle swarm optimization (PSO), gradient descent, Bayesian optimization or a hybrid strategy thereof, and neural network (ANN). It can be replaced by any data-driven model such as support vector machine (SVM), regression tree, lookup table (LUT) or spline interpolation.

[0064] (2) Model structure: "physical model + AI correction", "behavioral model" or "complete data-driven model" can be adopted, as long as dynamic waveform alignment can be achieved through closed-loop iteration.

[0065] 4. Path substitution in software implementation The host computer and algorithm implementation are not limited by language (LabVIEW / Python / C++, etc.) or architecture, and the data storage and interaction are not limited by format (local file / database / cloud), as long as it can realize automatic association and traceable archiving of dynamic and static data.

[0066] Based on the above-mentioned integrated system for dynamic and static testing and modeling of power devices, an embodiment of the present invention also provides an integrated method for dynamic and static testing and modeling of power devices using the above-mentioned system.

[0067] Specifically, such as Figure 8As shown, the integrated method for dynamic and static testing and modeling of power devices provided in this embodiment may include: S1. Using the above-mentioned integrated system for dynamic and static testing and modeling of power devices, static and dynamic unified testing of power devices are performed on the same platform to obtain static and dynamic test data at a set temperature point. S2 generates an initial model based on static and dynamic test results, performs transient characteristic simulation of the model, optimizes the initial model in a closed loop, and finally outputs a target high-precision device electrothermal model with consistent operating conditions.

[0068] It should be noted that the steps in the method provided by the present invention can be implemented using corresponding modules, devices, units, etc. in the system. Those skilled in the art can refer to the technical solution of the system to implement the steps and flow of the method. That is, the embodiments in the system can be understood as preferred examples of the method, and will not be elaborated here.

[0069] An embodiment of the present invention also provides a computer terminal, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it can be used to run any of the systems described in the above embodiments of the present invention.

[0070] Optionally, the memory is used to store programs; the memory may include volatile memory, such as random-access memory (RAM), such as static random-access memory (SRAM), double data rate synchronous dynamic random-access memory (DDR SDRAM), etc.; the memory may also include non-volatile memory, such as flash memory. The memory is used to store computer programs (such as application programs and functional modules that implement the above methods), computer instructions, etc., and the aforementioned computer programs and computer instructions can be partitioned and stored in one or more memories. Furthermore, the aforementioned computer programs, computer instructions, data, etc., can be accessed by the processor.

[0071] A processor is used to execute computer programs stored in memory to implement the various steps of the methods or various modules of the systems involved in the above embodiments. For details, please refer to the relevant descriptions in the preceding method and system embodiments.

[0072] The processor and memory can be separate structures or integrated structures. When the processor and memory are separate structures, they can be coupled together via a bus.

[0073] An embodiment of the present invention also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, can be used to run a system according to any of the above embodiments of the present invention.

[0074] Computer-readable media include computer storage media and communication media, wherein communication media include any medium that facilitates the transfer of computer programs from one place to another. Storage media can be any available medium accessible to a general-purpose or special-purpose computer. An exemplary storage medium is coupled to a processor, enabling the processor to read information from and write information to the storage medium. Of course, the storage medium can also be a component of the processor. The processor and storage medium can reside in an ASIC. Alternatively, the ASIC can reside in a user device. Of course, the processor and storage medium can also exist as discrete components in a communication device.

[0075] The integrated system and method for dynamic and static testing and modeling of power devices provided in the above embodiments of the present invention are achieved through the following technical means: First, on the testing side, parasitic parameters of the dynamic test power board, carrier fixture, busbar, interconnection traces, probe access position, and package leads are extracted or calibrated to obtain parasitic resistance, parasitic inductance, and parasitic capacitance parameters corresponding to the actual board; simultaneously, the device under test or its carrier structure is heated, its temperature is measured, and its temperature is controlled in a closed loop through a heating and temperature control module, enabling static and dynamic testing to be performed under one or more set temperature conditions to obtain static parameters and dynamic waveform data at different temperature points; second, on the modeling side, the above parasitic parameters are mapped according to the actual connection relationship. To simulate the circuit template, the transient simulation unit operates under boundary conditions consistent with actual measurements, and the thermal boundary of the device is characterized using a thermal impedance model or thermal network model. Next, an initial model is generated based on IV / CV data under different static temperature conditions, and a closed-loop optimization process (<model-circuit simulation-measured results>) is constructed using dynamic waveforms as constraints. Subsequently, the model closed-loop automatic optimization unit iteratively corrects the model parameters based on the waveforms until the preset accuracy requirements are met. Finally, the test task scheduling and instrument control module completes the unified scheduling of test execution, temperature setting and control, data archiving, simulation calls, and model export, thereby achieving integrated automatic operation of testing, modeling, and verification. Through these technical means, the system can reproduce the dynamic characteristics of measured overshoot, ringing, dv / dt, di / dt, and losses under real parasitic environments. It can also characterize the electrothermal coupling behavior under different temperature conditions and improve the consistency, traceability, and engineering usability of the model.

[0076] Any matters not covered in the above embodiments of the present invention are well-known in the art.

[0077] The specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various modifications or variations within the scope of the claims, which do not affect the essence of the present invention.

Claims

1. An integrated system for dynamic and static testing and modeling of power devices, characterized in that, include: The device under test (DUT) carries a security interface module, which receives power devices used for testing and modeling. These power devices are either bare power chips or packaged devices. The dynamic double-pulse test module is used to perform dynamic testing of power devices and output dynamic test results. The static parameter testing module is used to perform static tests on power devices and output the static test results. The heating and temperature control module is used to heat, measure and control the temperature of the power device so that the static parameter test module and the dynamic double pulse test module can perform tests under the set temperature conditions. Parasitic consistency simulation and modeling module, which is used to generate an initial model based on the dynamic test results and the static test results, perform transient characteristic simulation of the model, and output the electrothermal model of the target high-precision device; The test task scheduling and instrument control module is used to coordinate the test process of the static parameter test module and the dynamic double pulse test module, as well as the model generation and simulation output of the parasitic consistency simulation and modeling module. The hardware data interaction module serves as the underlying hardware data interaction channel, performing configuration, triggering, and reading operations on the hardware devices of the dynamic double-pulse test module and the static parameter test module through standard interfaces.

2. The integrated system for dynamic and static testing and modeling of power devices according to claim 1, characterized in that, The device under test (DUT) bearer and security interface module includes: The safety interface unit provides electrical isolation, overvoltage and overcurrent protection, port multiplexing and switching, and safety interlock between static parameter testing and dynamic double-pulse testing, so that the reference port definition remains consistent when the same device under test switches between different test modes. The bearing fixture unit is used to mechanically support, position and press the device under test, lead out the Kelvin terminal, and fix the power terminal and signal terminal, while maintaining the physical contact interface and lead parasitic boundary shared by static parameter testing and dynamic dual-pulse testing. The loading interface unit is used to realize the manual or automatic clamping, positioning and import of the device under test. It works with the bearing fixture unit and the safety interface unit to enable the static parameter test module and the dynamic dual-pulse test module to share the same device under test access path without changing the test socket, thereby forming a unified dynamic and static hardware test link.

3. The integrated system for dynamic and static testing and modeling of power devices according to claim 1, characterized in that, The static parameter testing module and the dynamic dual-pulse testing module share the device under test (DUT) carrier and safety interface module. In conjunction with the test task scheduling of the test task scheduling and instrument control module, the same DUT can continuously and automatically complete the entire static-dynamic process test at a set temperature point under the action of the heating and temperature control module, without changing the test socket, maintaining the same connection boundary and the same lead parasitic environment.

4. The integrated system for dynamic and static testing and modeling of power devices according to claim 3, characterized in that, The static parameter testing module includes: a measurement source unit, a measurement impedance unit, a switch matrix board, and a lower-level control board. The switch matrix board receives coordination signals from the test task scheduling and instrument control module via the lower-level control board, controlling the measurement source unit, the measurement impedance unit, and the power path. It automatically switches between different port connection methods, ranges, and test functions to achieve DC parameter testing at a set temperature and AC small-signal characterization of device capacitance or impedance parameters under DC bias conditions.

5. The integrated system for dynamic and static testing and modeling of power devices according to claim 3, characterized in that, The dynamic dual-pulse test module includes a DC source, a driver, a pulse signal generator board, and an oscilloscope. It is used to form a dynamic transient test circuit to acquire the transient waveforms of the gate-source voltage, drain-source voltage, and drain or collector current of the device under test at a set temperature. By performing synchronous trigger alignment, effective switching interval division, threshold determination, extreme value search, slope calculation, and energy integration on the original transient waveform, it automatically calculates key dynamic characteristic features. Then, it uploads the original transient waveform and key dynamic characteristic features to the host computer for archiving. and / or The dynamic double-pulse test module is also used to perform reverse recovery tests and / or short-circuit tests on power devices.

6. The integrated system for dynamic and static testing and modeling of power devices according to claim 1, characterized in that, The parasitic consistency simulation and modeling module includes: The modeling unit is used to acquire the required curves and waveforms after completing static and dynamic tests. It directly calculates, empirically maps, or fits the electrical parameters and temperature-dependent parameters of the initial model using static parameter data measured under different temperature conditions. It also uses the key dynamic characteristics extracted from the dynamic waveform as dynamic constraints to generate the initial model and output a model file for circuit simulation. The model transient simulation unit, based on the initial model and incorporating the parasitic parameter network of the test hardware, performs electrothermal coupling transient characteristic simulation to obtain the simulation waveform. It then uses the measured waveform as a benchmark for error quantification and evaluation to obtain the comprehensive error of the dynamic waveform. The parasitic parameter network of the test hardware is an equivalent network constructed based on the parasitic resistance, inductance, and capacitance of the dynamic test power board, busbars, fixtures, interconnect traces, probe access, and package leads. This network is obtained through at least one of parasitic parameter extraction, impedance measurement, calibration experiments, and three-dimensional electromagnetic field simulation, and is provided to the model transient simulation unit as a simulation boundary condition consistent with the actual board. Simultaneously, the model transient simulation unit also combines a thermal impedance model or a thermal network model to jointly simulate the changes in temperature-related electrical parameters of the device. The model closed-loop automatic optimization unit uses the difference in dynamic results as the basis for correction. It performs feature correction based on the difference results, gradually improving the consistency between simulation and actual measurement until the preset accuracy requirements are met, and outputs the target high-precision power device electrical model.

7. The integrated system for dynamic and static testing and modeling of power devices according to any one of claims 1-6, characterized in that, Also includes: The user interaction module provides a test configuration interface and visualizes test results and generated models. The data management and storage module adopts a unified data structure to manage and store the entire data chain, including device information, test conditions, raw waveforms, feature extraction, model version, and error evaluation. The test task scheduling and instrument control module coordinates the parameter configuration of the user interaction module and the data acquisition and archiving of the data management and storage module.

8. A method for integrating dynamic and static testing and modeling of power devices using the system described in any one of claims 1-7, characterized in that, include: Perform unified static and dynamic tests on power devices on the same platform to obtain static and dynamic test data at a set temperature point; Based on the static and dynamic test results, an initial model is generated, and transient characteristic simulation of the model is performed. Finally, a high-precision target electrothermal device model with consistent operating conditions is output, completing the dynamic and static testing and modeling of the power device.

9. A computer terminal, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it can be used to run the system according to any one of claims 1-7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When executed by a processor, the computer program can be used to run the system according to any one of claims 1-7.

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