Semiconductor structure and method of forming the same

Abstract

Embodiments of the present application provide a semiconductor structure and a forming method thereof; wherein the semiconductor structure comprises: a substrate comprising a trench extending along a first direction; N-1 protruding structures arranged along a second direction on a surface of the substrate; heights of the N-1 protruding structures decrease successively along a direction close to the trench; N is greater than or equal to 2; a capacitor structure comprising N electrode plates successively covering surfaces inside the trench and extending along the second direction on the surface of the substrate, and dielectric layers between adjacent electrode plates; wherein an i-th electrode plate extends along the second direction to a surface of an N-i-th protruding structure; a topmost electrode plate on each protruding structure surface has a same height as an N-th electrode plate in the first direction.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and to, but is not limited to, a semiconductor structure and a method for forming the same. Background Technology

[0002] As the dimensions of devices in semiconductor structures continue to shrink, Moore's Law is approaching its physical limits, and 3D integration technology has become an important direction for overcoming Moore's Law. Among these technologies, deep trench capacitors (DTCs) have become the preferred solution for integrating passive devices in processes such as 2.5D silicon interposers due to their ability to achieve high capacitance density per unit area.

[0003] However, in deep trench capacitors, the height difference between the multiple electrode plates makes the electrode plate connection process more complicated, which in turn makes the electrode plates prone to short circuits or leakage, thus reducing process stability and product yield. Summary of the Invention

[0004] This application provides a semiconductor structure and a method for forming the same.

[0005] The technical solution of this application embodiment is implemented as follows: In a first aspect, embodiments of this application provide a semiconductor structure, including: The substrate includes trenches extending along a first direction; N-1 protrusions are located on the surface of the substrate and are spaced apart along the second direction; the height of the N-1 protrusions decreases sequentially along the direction close to the trench; N≥2; The capacitor structure includes N layers of electrode plates that sequentially cover the inner side of the trench and extend along the second direction on the substrate surface, and a dielectric layer located between adjacent electrode plates; Wherein, the i-th layer of electrode plates extends along the second direction to the surface of the Ni-th protrusion structure; the topmost electrode plate on the surface of each protrusion structure has the same height as the N-th layer of electrode plates in the first direction; the first direction is perpendicular to the plane where the substrate is located, and the second direction is parallel to the plane where the substrate is located.

[0006] In some embodiments, the height of the Nith protrusion is equal to (Ni)*(d1+d2), where d1 and d2 represent the thickness of the electrode plate and the dielectric layer, respectively.

[0007] In some embodiments, the semiconductor structure further includes: A first isolation structure covers the surfaces of the substrate and the capacitor structure; The second isolation structure is located between the substrate and the capacitor structure, and between the protrusion structure and the capacitor structure.

[0008] In some embodiments, the semiconductor structure further includes: N contact structures are located in the first isolation structure and extend along the first direction; The Nth contact structure is connected to the topmost electrode plate on the surface of the Nith protrusion structure, and the Nth contact structure is connected to the Nth layer of electrode plates.

[0009] Secondly, embodiments of this application provide a method for forming a semiconductor structure, the method comprising: A substrate is provided; the substrate includes trenches extending along a first direction; N-1 protrusions are formed on the surface of the substrate and spaced apart along a second direction; the height of the N-1 protrusions decreases sequentially along the direction close to the trench; N≥2; A capacitor structure is formed; the capacitor structure includes N layers of electrode plates that sequentially cover the inner side of the trench and extend along the second direction on the substrate surface, and a dielectric layer located between adjacent electrode plates; Wherein, the i-th layer of electrode plates extends along the second direction to the surface of the Ni-th protrusion structure; the topmost electrode plate on the surface of each protrusion structure has the same height as the N-th layer of electrode plates in the first direction; the first direction is perpendicular to the plane where the substrate is located, and the second direction is parallel to the plane where the substrate is located.

[0010] In some embodiments, N-1 protrusion structures are formed on the surface of the substrate and spaced apart along a second direction, including: Provide initial substrate; The initial substrate is etched to form N-1 protrusion structures spaced apart along the second direction; the height of the Nith protrusion structure is equal to (Ni)*(d1+d2), where d1 and d2 represent the thickness of the electrode plate and the dielectric layer, respectively. The remaining surface of the initial substrate is etched to form the trench; the trench is located on one side of the direction in which the heights of the N-1 protrusion structures decrease sequentially; the remaining initial substrate constitutes the substrate.

[0011] In some embodiments, N-1 protrusion structures are formed on the surface of the substrate and spaced apart along a second direction, including: A filler material layer is formed on the surface of the substrate; The filling material layer is etched to form N-1 protrusion structures spaced apart along the second direction; Wherein, the height of the Nith protrusion is equal to (Ni)*(d1+d2), and d1 and d2 represent the thickness of the electrode plate and the dielectric layer, respectively.

[0012] In some embodiments, forming a capacitor structure includes: An initial electrode plate and an initial dielectric layer are sequentially and alternately formed on the exposed surfaces of the substrate and the trench. The initial electrode plate and the adjacent initial dielectric layer are etched layer by layer so that the electrode plate exposed on the surface of the Nith protrusion structure is the i-th electrode plate.

[0013] In some embodiments, the method further includes: A first isolation structure is formed covering the surfaces of the substrate and the capacitor structure; N contact structures are formed that penetrate the first isolation structure and extend along the first direction; The Nith contact hole is connected to the topmost electrode plate on the surface of the Nith protrusion structure, and the Nth contact hole is connected to the Nth layer electrode plate.

[0014] In some embodiments, prior to forming the capacitor structure, the method further includes: A second isolation structure is formed on the surface of the substrate and the protrusion structure.

[0015] This application provides a semiconductor structure and a method for forming the same; wherein the semiconductor structure includes: a substrate, N-1 bump structures, and a capacitor structure. The substrate includes trenches extending along a first direction; the N-1 bump structures are located on the surface of the substrate and are spaced apart along a second direction; the heights of the N-1 bump structures decrease sequentially along the direction near the trench; N ≥ 2; the capacitor structure includes N electrode plates that sequentially cover the surfaces inside the trenches and extend along the second direction on the substrate surface, and a dielectric layer located between adjacent electrode plates; wherein the i-th electrode plate extends along the second direction to the surface of the Ni-th bump structure; the topmost electrode plate on the surface of each bump structure has the same height as the N-th electrode plate in the first direction.

[0016] Here, since the protrusion structure is located on the substrate surface and its height decreases sequentially along the direction close to the trench, and the i-th electrode plate extends to the Ni-th protrusion surface, the connection area of ​​each electrode plate can be raised according to actual needs, thereby reducing the process difficulty when connecting each electrode plate, improving the reliability of the electrode plate electrical connection, reducing the risk of electrode plate short circuit or leakage, and resulting in high process stability and product yield. Attached Figure Description

[0017] In the accompanying drawings (which are not necessarily drawn to scale), similar reference numerals may describe similar parts in different views. Similar reference numerals with different letter suffixes may indicate different examples of similar parts. The drawings illustrate, by way of example and not limitation, the various embodiments discussed herein.

[0018] Figure 1 Schematic diagram of the semiconductor structure provided in the embodiments of this application Figure 1 ; Figure 2 Schematic diagram of the semiconductor structure provided in the embodiments of this application Figure 2 ; Figure 3 This is a schematic diagram of a partial semiconductor structure provided in the embodiments of this application; Figure 4 A schematic flowchart illustrating the semiconductor structure fabrication method provided in this application embodiment; Figures 5 to 15 This is a schematic diagram of the semiconductor structure formation process provided in the embodiments of this application; Figure 16 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0019] Exemplary embodiments of this application will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of this application are shown in the drawings, it should be understood that this application can be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of this application and to fully convey the scope of this application to those skilled in the art.

[0020] In the following description, numerous details are set forth in order to provide a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, to avoid confusion with this application, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0021] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0022] In the following description, the terms "first," "second," and "third" are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first," "second," and "third" may be interchanged in a specific order or sequence where permissible, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein. In the drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0023] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this application.

[0024] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0025] Currently, with the technological advancements in the semiconductor industry, the continuous miniaturization of device dimensions per unit area and the increasing density of devices are pushing Moore's Law close to its physical limits. Therefore, 3D integration technology has become a crucial direction for overcoming Moore's Law. Among these technologies, 2.5D silicon interposer technology is a significant branch of artificial intelligence chip integration, and its deep trench capacitor technology is a key indicator for evaluating the performance of silicon interposer technology.

[0026] However, in deep trench capacitors, the connection depth of the electrode plate connecting metal (corresponding to the contact structure in the following text) varies due to the height difference of the connection areas of each electrode plate. This not only significantly increases the difficulty of process control and manufacturing cost, but also easily leads to reliability problems such as leakage risk.

[0027] Based on this, embodiments of this application provide a semiconductor structure and a method for forming the same; the semiconductor structure and method for forming the same in the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0028] Before introducing the embodiments of this application, let's define two directions that may be used in the following embodiments to describe the three-dimensional structure. The two directions may include the X-axis (first) and the Y-axis (second). The X-axis direction can be a direction perpendicular to the plane where the substrate is located; the Y-axis direction is parallel to the plane where the substrate is located.

[0029] This application provides a semiconductor structure; please refer to [reference needed]. Figure 1 The semiconductor structure 100 includes a substrate 110, N-1 bump structures 120, and a capacitor structure 130. The substrate 110 includes a trench 111 extending along the X-axis direction; the N-1 bump structures 120 are located on the surface of the substrate 110 and are spaced apart along the Y-axis direction; the height of the N-1 bump structures 120 decreases sequentially along the direction close to the trench 111; N ≥ 2; the capacitor structure 130 includes N layers of electrode plates 131 that sequentially cover the surface inside the trench 111 and extend along the Y-axis on the surface of the substrate 110, and a dielectric layer 132 located between adjacent electrode plates 131.

[0030] Among them, the i-th layer electrode plate 131 extends along the Y-axis to the surface of the Ni-th protrusion structure 120; the topmost electrode plate 131 on the surface of each protrusion structure 120 has the same height as the N-th layer electrode plate 131 in the X-axis direction.

[0031] In this embodiment, the substrate 110 may be a silicon substrate or a silicon-on-insulator (SOI) structure. The substrate 110 may also include other semiconductor elements, such as germanium (Ge), or semiconductor compounds, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), or indium antimonide (InSb), or other semiconductor alloys, such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium indium arsenide phosphide (GaInAsP) or combinations thereof.

[0032] Please refer to this section. Figure 1 The trench 111 in the substrate 110 is used to accommodate the capacitor structure 130 and provide mechanical support for the capacitor structure 130; wherein, since the capacitor structure 130 is formed inside the trench 111, the area of ​​the inner side (i.e., the inner wall) of the trench 111 determines the effective area of ​​the capacitor structure 130; for example, the larger the area of ​​the inner side of the trench 111, the larger the effective area of ​​the capacitor structure 130.

[0033] Please refer to the embodiments in this application. Figure 1 The protrusions 120 are located on the surface of the substrate 110 and are spaced apart along the Y-axis. Their height decreases sequentially in the direction close to the trench, forming a stepped gradient distribution. This allows the connection area of ​​each electrode plate 131 (i.e. the area above the protrusions) to be raised as needed, making the height of each electrode plate 131 flush, which is beneficial for connecting each electrode plate 131 from the same plane.

[0034] Furthermore, the number of protrusions 120 can be determined by the number of electrode plates 131; specifically, when there are N electrode plates 131, there can be N-1 protrusions 120. For example, Figure 1 There are three electrode plates 131 and two protruding structures 120; or there are four electrode plates 131 and three protruding structures 120, and so on.

[0035] In this embodiment, the material of the protrusion structure 120 can be a semiconductor material such as silicon or germanium; or it can be an insulating material such as silicon oxide. The material of the protrusion structure 120 and the material of the substrate 110 can be the same or different; for example, both the protrusion structure 120 and the substrate 110 can be silicon, or the protrusion structure 120 can be silicon oxide and the substrate 110 can be silicon.

[0036] Please refer to the embodiments in this application. Figure 1N electrode plates 131 sequentially cover the inner surface of the trench 111 and extend along the Y-axis on the surface of the substrate 110. The number of electrode plate layers 131 (i.e., the value of N) can be set according to actual needs; the more electrode plate layers 131 there are, the larger the total charge storage capacity of the capacitor structure 130. For example, the number of electrode plate layers 131 can be 2 or 3 (e.g., ...). Figure 1 (As shown), 4 layers, etc. The electrode plate 131 material can be conductive materials such as titanium nitride, tantalum nitride, and tungsten.

[0037] Additionally, the i-th electrode plate 131 extends to the top of the Ni-th protrusion structure; wherein, the i-th electrode plate 131 refers to the i-th electrode plate 131 extending from the bottom up on the surface of the substrate 110, and the Ni-th protrusion structure 120 refers to the Ni-th protrusion structure 120 extending from the direction away from the trench 111 (e.g., the opposite direction of the Y-axis). For example, please refer to... Figure 1 The first electrode plate 131 extends to the second protrusion structure 120, and the second electrode plate 131 extends to the first protrusion structure 120.

[0038] In this embodiment, the dielectric layer 132 is located between two adjacent electrode plates 131, so that when the number of electrode plates 131 is N, the number of dielectric layers 132 is N-1; for example, please refer to Figure 1 The electrode plate 131 has 3 layers, and the dielectric layer 132 has 2 layers. The dielectric layer 132 is made of high dielectric constant dielectric materials such as silicon dioxide, silicon nitride, aluminum oxide, hafnium oxide, and zirconium oxide. The dielectric layer 132 can prevent short circuits between adjacent electrode plates 131 and store electrical energy through its dielectric properties.

[0039] Furthermore, the i-th electrode plate 131, the (i+1)-th electrode plate 131, and the dielectric layer 132 between adjacent electrode plates 131 constitute a capacitor unit, and two adjacent capacitor units can share an electrode plate 131, thereby enabling each capacitor structure 130 to be composed of N-1 capacitor units (e.g., Figure 1 It consists of two capacitor units, which makes the capacitor structure 130 have a high storage density.

[0040] In this way, because of the height difference between different electrode plates in the capacitor structure in the traditional process, the number of stacked electrode plates is reduced in order to reduce the difficulty of connecting different electrode plates; however, in the embodiment of this application, since each electrode plate can be connected through the same height, the process difficulty of connecting each electrode plate is reduced. Therefore, the protrusion structure in this application can increase the number of stacked electrode plates, thereby increasing the storage density in the capacitor structure.

[0041] In this embodiment, on the one hand, since the protrusion structure is located on the substrate surface and its height decreases sequentially along the direction close to the trench, and the i-th electrode plate extends to the Ni-th protrusion surface, the connection area of ​​each electrode plate can be raised according to actual needs. This reduces the process difficulty of connecting each electrode plate, thereby improving the reliability of the electrode plate electrical connection, reducing the risk of electrode plate short circuits or leakage, and resulting in higher process stability and product yield. On the other hand, since the protrusion structure can raise the corresponding electrode plate, the area of ​​each electrode plate above the protrusion structure surface increases, thereby increasing the effective area of ​​the electrode plate and thus improving the capacitance density.

[0042] Next, please refer to Figures 2 to 3 The semiconductor structure 100 will be described in detail.

[0043] In some embodiments, please refer to Figure 2 The semiconductor structure 100 further includes a first isolation structure 140 and a second isolation structure 150. The first isolation structure 140 covers the surfaces of the substrate 110 and the capacitor structure 130; the second isolation structure 150 is located between the substrate 110 and the capacitor structure 130, and between the bump structure 120 and the capacitor structure 130.

[0044] In this embodiment, by filling the interior of the trench 111 and the surface of the capacitor structure 130 with the first isolation structure 140, the entire structure surface can be made relatively flat. Simultaneously, the first isolation structure 140 can protect the capacitor structure 130, preventing damage and resulting in a higher yield of the semiconductor structure. The material of the first isolation structure 140 includes silicon oxide, silicon nitride, silicon oxynitride, and carbon-doped silicon nitride, etc.

[0045] In addition, the thickness distribution of the first isolation structure 140 along the X-axis direction can be set according to actual needs. By setting the first isolation structure 140, electrical breakdown or signal interference can be effectively prevented.

[0046] In this embodiment, the second isolation structure 150 is filled between the bottom surface of the capacitor structure 130 and the substrate 110, the protrusion structure 120, and the trench 111. The second isolation structure 150 can isolate the capacitor structure 130 from the substrate 110 and the protrusion structure 120, ensuring the stability of the capacitor performance. The material of the second isolation structure 150 includes silicon oxide, silicon nitride, silicon oxynitride, and carbon-doped silicon nitride.

[0047] In some embodiments, please refer to Figure 2The semiconductor structure 100 further includes: N contact structures 160 located in the first isolation structure 140 and extending along the X-axis direction; wherein the Nth contact structure 160 is connected to the top electrode plate 131 on the surface of the Nith protrusion structure 120, and the Nth contact structure 160 is connected to the Nth layer electrode plate 131.

[0048] Please refer to the embodiments in this application. Figure 2 The contact structure 160 extends through the first isolation structure 140 along the X-axis and forms a surface contact with the corresponding electrode plate 131, used to lead out the corresponding electrode plate for electrical connection with the peripheral circuit. The material of the contact structure 160 includes conductive materials such as tungsten and copper.

[0049] In this embodiment, the semiconductor structure 100 further includes a barrier layer (not shown) disposed around the contact structure 160 to prevent material diffusion in the contact structure 160 and to enhance the interfacial adhesion strength between the contact structure 160 and the surrounding first isolation structure 140. The barrier layer may be made of materials such as titanium nitride, tantalum tantalum nitride, or tantalum nitride.

[0050] Furthermore, the N contact structures 160 are identical in structure and material, differing mainly in their lateral placement along the Y-axis and their connection to different electrode plates 131. Specifically, from the direction away from the trench 111 (e.g., the opposite direction of the Y-axis), for the Nth contact structure 160, its lateral position along the Y-axis is aligned with the Nith protrusion 120, and it extends along the X-axis to the top electrode plate 131 on the surface of the Nith protrusion 120; for example, the third contact structure 160, its lateral position along the Y-axis is aligned with the second protrusion 120, and it extends along the X-axis to the top electrode plate 131 on the surface of the second protrusion 120; the third contact structure 160 is connected to the third electrode plate 131.

[0051] In this embodiment, the contact structures 160 are isolated from each other by a first isolation structure 140 to avoid leakage current.

[0052] In this embodiment, because each electrode plate 131 in the capacitor structure 130 is at a different position in the Y-axis direction, it is raised to the same height by the protrusion structure 120, thereby ensuring that the penetration depth of each contact structure 160 is the same, reducing the fabrication difficulty of the contact structure 160. Simultaneously, the contact structure 160 extends along the X-axis direction, allowing the corresponding electrode plate 131 to be led out vertically, eliminating the need to increase the lateral layout area of ​​the semiconductor structure and improving the integration density of the semiconductor structure. Furthermore, each contact structure 160 is electrically connected to its corresponding electrode plate 131, ensuring that each layer of electrode plates 131 in the capacitor structure 130 can be independently accessed and controlled, thus meeting the circuit requirements for multiple capacitors connected in series or parallel.

[0053] Next, combined Figure 2 and Figure 3 The height of the N-1 protruding structures, each 120, is described in detail. Figure 3 Only the protrusion structure 120, the second isolation structure 150, and the capacitor structure 130 extending along the Y-axis are shown; the substrate 110, capacitor structure 130, etc., are not shown.

[0054] In some embodiments, please refer to Figure 2 and Figure 3 The height of the Nith protrusion 120 (i.e. the dimension along the X-axis) is equal to (Ni)*(d1+d2), where d1 and d2 represent the thicknesses of the electrode plate 131 and the dielectric layer 132, respectively.

[0055] In this embodiment, the height of the Nth electrode plate 131 (i.e., the top electrode plate 131) is the sum of the thickness of the second isolation structure 150, the thickness of N electrode plates 131, and the thickness of (N-1) dielectric layers 132; similarly, the height of the Nith electrode plate is the sum of the height of the i-th protrusion 120, the thickness of the second isolation structure, the thickness of (Ni) electrode plates 131, and the thickness of (Ni-1) dielectric layers 132. For example, the height of the second electrode plate (i.e., the second-to-top layer) is the sum of the height of the first protrusion 120, the thickness of the second isolation structure, the thickness of two electrode plates 131, and the thickness of one dielectric layer 132.

[0056] Here, in order to make the height of the Nth electrode plate equal to the height of the Nith electrode plate, the height of the Nith protrusion 120 is set to be equal to (Ni)*(d1+d2), where d1 and d2 represent the thicknesses of the electrode plate 131 and the dielectric layer 132, respectively. The values ​​of d1 and d2 can be set according to actual needs.

[0057] In the embodiments of this application, please refer to Figure 2 and Figure 3In the capacitor structure 130 with 3 electrode plates 131, the thickness of the electrode plate 131 can be 25-35 nanometers, and the thickness of the dielectric layer 132 can be 5-8 nanometers. For example, taking the electrode plate 131 thickness as 30 nanometers and the dielectric layer 132 thickness as 6 nanometers, from the direction away from the trench 111 (e.g., the opposite direction of the Y-axis), the top layer on the surface of the first protrusion structure 120 includes the second electrode plate, and its height is calculated as 36 nanometers by (3-2)*(30+6); the top layer on the surface of the second protrusion structure 120 includes the first electrode plate, and its height is calculated as 72 nanometers by (3-1)*(30+6).

[0058] In addition, such as Figure 3 As shown, the height difference D between adjacent protrusions 120 in the X-axis direction is a constant value, wherein the height difference D is equal to the sum of the thickness d1 of the single-layer electrode plate 131 and the thickness d2 of the single-layer dielectric layer 132; for example, the height difference D is equal to 36 nanometers.

[0059] In this embodiment, by designing the height of the protrusion structure 120 to be (Ni)*(d1+d2), it is ensured that the height of each electrode plate 131 is the same in the X-axis direction, which facilitates the lead-out of the corresponding electrode plate 131 through the contact structure 160.

[0060] In this embodiment, by forming trenches on the substrate surface and placing the capacitor structure 130 in the trenches 111, a larger effective capacitor area can be achieved within a limited area. In addition, when the i-th electrode plate extends to the surface of the Ni-th protrusion structure, each electrode plate maintains a high degree of consistency in the X-axis direction, which reduces the difficulty of the process and makes the semiconductor structure more reliable and has a higher yield.

[0061] In addition, this disclosure also provides a method for forming a semiconductor structure. Figure 4 This is a schematic flowchart of the semiconductor structure fabrication method provided in the embodiments of this application, as shown below. Figure 4 As shown, the method for forming a semiconductor structure includes the following steps: steps S110 to S130.

[0062] Step S110, providing a substrate 110; the substrate 110 includes a trench 111 extending along the X-axis direction.

[0063] In step S120, N-1 protrusion structures 120 are formed on the surface of the substrate 110 and spaced apart along the Y-axis; the height of the N-1 protrusion structures 120 decreases sequentially along the direction close to the trench 111; N≥2.

[0064] Step S130: A capacitor structure 130 is formed. The capacitor structure 130 includes N layers of electrode plates 131 that sequentially cover the inner side of the trench 111 and extend along the Y-axis direction on the surface of the substrate 110, and a dielectric layer 132 located between adjacent electrode plates 131. The i-th electrode plate 131 extends along the Y-axis direction to the surface of the (N-i)-th protrusion structure 120. The topmost electrode plate 131 on the surface of each protrusion structure 120 has the same height as the N-th electrode plate 131 in the X-axis direction.

[0065] In this embodiment, by providing a raised structure with progressively decreasing height along the direction close to the substrate trench below the capacitor structure, the connection area of ​​each electrode plate can be raised according to actual needs, thereby achieving the effect that the topmost electrode plate 131 on the surface of each raised structure 120 has the same height as the Nth electrode plate 131 in the X-axis direction. This reduces the process difficulty when connecting each electrode plate, thereby improving the reliability of the electrode plate electrical connection, reducing the risk of electrode plate short circuit or leakage, and resulting in higher process stability and product yield.

[0066] Next, combined Figures 5 to 15 The method for forming a semiconductor structure is described in detail. Steps S110 and S120 can be formed in the following two ways.

[0067] The first method includes steps S110 and S120, specifically steps S11 to S13.

[0068] Step S11, provide as follows Figure 5 The initial substrate 110a is shown.

[0069] Step S12: Etch the initial substrate 110a to form N-1 protrusion structures 120 spaced apart along the Y-axis; the height of the N-i-th protrusion structure 120 is equal to (N-i)*(d1+d2), where d1 and d2 represent the thickness of the electrode plate and the dielectric layer, respectively.

[0070] In implementation, firstly, the number of protrusions 120 is set according to the required number of electrode plates 131; where the number of electrode plates 131 is N (e.g., 3), the number of protrusions 120 is set to N-1 (e.g., 2); simultaneously, the height of the protrusions 120 is set according to the thickness of the electrode plates 131 and the dielectric layer 132; where the thicknesses of the electrode plates 131 and the dielectric layer 132 are d1 and d2 respectively, the height of the (N-i)th protrusion 120 is set to be equal to (N-i)*(d1+d2). Next, for example... Figure 5 The initial substrate 110a shown is etched multiple times to form N-1 protrusion structures 120 arranged at intervals along the Y-axis with decreasing heights.

[0071] The etching processes in this application include, but are not limited to, dry etching, wet etching, and combinations thereof.

[0072] Step S13, for example Figure 6 The remaining surface of the initial substrate 110a is etched to form trenches 111, which are located on one side of the direction in which the heights of the N-1 protrusions 120 decrease sequentially; the remaining initial substrate 110a is configured as shown in the figure. Figure 7 The substrate 110 shown.

[0073] In practice, the remaining initial substrate 110a region on one side of the direction in which the height of the (N-1)th protrusion 120 decreases sequentially along the Y-axis is etched to form a trench 111 on one side of the (N-1)th protrusion 120. Here, the etching depth of the trench 111 can be set according to the actual height of the formed capacitor structure (the dimension along the X-axis direction). Simultaneously, the depth of the trench 111 must be less than the thickness of the initial substrate 110a to prevent the trench 111 from penetrating the initial substrate 110a. Furthermore, the width of the trench 111 (e.g., the dimension along the Y-axis direction) can be set according to the actual width of the formed capacitor structure.

[0074] In this embodiment, since the substrate 110 and the protrusion structure 120 are formed through the same initial substrate 110a, the substrate 110 and the protrusion structure 120 are made of the same material and are an integral structure.

[0075] The second method, step S110, specifically includes steps S21 to S22.

[0076] Step S21, provide as follows Figure 5 The initial substrate 110a is shown.

[0077] Step S22, the initial substrate 110a is etched to form as shown in the figure. Figure 8 The substrate 110 shown includes a trench 111 extending along the X-axis direction.

[0078] Step S120 specifically includes steps S31 to S32.

[0079] Step S31, as follows Figure 8 On the surface of substrate 110, a structure such as Figure 9 The filling material layer 120a is shown.

[0080] In this embodiment, a filling material layer 120a is formed on the exposed surfaces of the substrate 110 and the trench 111. The material of the filling material layer 120a may be different from the material of the substrate 110. For example, the material of the filling material layer 120a may be any suitable material such as polysilicon, silicon oxide, or silicon nitride. Alternatively, the material of the filling material layer 120a may be the same as that of the substrate 110. For example, the material of the filling material layer 120a may be silicon.

[0081] The deposition processes involved in the embodiments of this application include, but are not limited to: chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD), sputtering, metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), and combinations thereof.

[0082] Step S32, as follows Figure 9 The filler material layer 120a is etched to form a shape such as Figure 10 The diagram shows N-1 protrusions 120 spaced apart along the Y-axis; the height of the (N-i)th protrusion 120 is equal to (N-i)*(d1+d2), where d1 and d2 represent the thicknesses of the electrode plate 131 and the dielectric layer 132, respectively.

[0083] In this embodiment, the filling material layer 120a is etched multiple times to remove part of the surface of the substrate 110 and the filling material layer 120a in the trench 111, forming N-1 protrusion structures 120 that are spaced apart along the Y-axis and whose height decreases sequentially along the direction close to the trench 111.

[0084] In this embodiment, the number N of electrode plates 131, the thickness d1 of electrode plates 131, and the thickness d2 of dielectric layer 132 are set according to actual needs. By controlling the etching depth, the height of the Ni-th protrusion 120 is made equal to (Ni)*(d1+d2). In addition, since the protrusion 120 and the substrate 110 are formed in steps, the process is more flexible and it is easier to select materials with better interface characteristics with the subsequent capacitor structure.

[0085] Next, with Figure 7 The following steps will be explained using the 120 protrusion and 110 shown as examples.

[0086] In some embodiments, prior to forming the capacitor structure 130, the method further includes forming a second isolation structure 150 on the surfaces of the substrate 110 and the protrusion structure 120.

[0087] For details, please refer to Figure 11 A second isolation structure 150 is deposited on the exposed surfaces of the substrate 110, the protrusion structure 120, and the trench 111. The second isolation structure 150 isolates the subsequently formed capacitor structure from the substrate 110 and the protrusion structure 120, effectively blocking the leakage path of the capacitor structure. Step S130 is executed to form a capacitor structure 130. The capacitor structure 130 includes N layers of electrode plates 131 that sequentially cover the inner side of the trench 111 and extend along the Y-axis direction on the surface of the substrate 110, and a dielectric layer 132 located between adjacent electrode plates 131. The i-th electrode plate 131 extends along the Y-axis direction to the surface of the (N-i)-th protrusion structure 120. The topmost electrode plate 131 on the surface of each protrusion structure 120 has the same height as the N-th electrode plate 131 in the X-axis direction.

[0088] In some embodiments, step S130 includes steps S131 to S132.

[0089] In step S131, an initial electrode plate 131a and an initial dielectric layer 132a are sequentially and alternately formed on the exposed surfaces of the substrate 110 and the trench 111.

[0090] In the embodiments of this application, in such Figure 11 On the surface of the structure shown (i.e., the second isolation structure 150), N initial electrode plates 131a and N-1 initial dielectric layers 132a located between adjacent initial electrode plates 131a are sequentially and alternately deposited. The thickness of the initial electrode plates 131a and the initial dielectric layers 132a is determined according to the capacitor design requirements. Figure 12 The diagram shows three initial electrode plates 131a and two initial dielectric layers 132a alternately formed on the surface of the second isolation structure 150. Step S132: Etch the initial electrode plate 131a and the adjacent initial dielectric layer 132a layer by layer, so that the electrode plate 131 exposed on the surface of the Nith protrusion structure 120 is the i-th electrode plate 131.

[0091] Specifically, the first etching is performed on the initial electrode plate 131a and the initial dielectric layer 132a above the N-1th (i.e., the highest) protrusion 120 in a direction away from the trench 111 (e.g., the opposite direction of the Y-axis) until the first electrode plate 131 (i.e., the bottom electrode plate 131) is exposed. The second etching is performed on the initial electrode plate 131a and the initial dielectric layer 132a above the N-2th protrusion 120 in a direction away from the trench 111 (e.g., the opposite direction of the Y-axis) until the second electrode plate 131 is exposed. And so on, the i-th etching is performed on the surface above the N-ith protrusion 120 so that the i-th electrode plate 131 is just exposed until the N-1th etching is completed.

[0092] For example, please refer to Figure 13 The first etching is performed on the initial electrode plate 131a and the initial dielectric layer 132a above the second (i.e., the leftmost) protrusion structure 120 until the first electrode plate 131 (i.e., the bottom electrode plate 131) is exposed; the second etching is performed on the initial electrode plate 131a and the initial dielectric layer 132a above the first protrusion structure 120 until the second electrode plate 131 is exposed.

[0093] In this embodiment, since the etching region is only for the area on the substrate 110 with the protrusion structure 120, the final capacitor structure 130 has N fully stacked electrode plates 131 and N-1 dielectric layers 132 formed on the other areas of the substrate 110 and the inner surface of the trench 111. In addition, a stepped extension structure is formed on the surface of the protrusion structure 120, which increases the storage capacity of the capacitor structure. Furthermore, since all the protrusion structures 120 are designed with equal height, each electrode plate 131 is flush with the corresponding protrusion structure 120, which facilitates the lead-out of the electrode plates 131 on the same plane in subsequent processes.

[0094] In some embodiments, after forming the capacitor structure 130, the method for forming the semiconductor structure 100 further includes: forming a first isolation structure 140 covering the surface of the substrate 110 and the capacitor structure 130; forming N contact structures 160 extending through the first isolation structure 140 and along the X-axis direction; wherein the Nith contact hole 161 is connected to the top electrode plate 131 on the surface of the Nith protrusion structure 120, and the Nth contact hole 161 is connected to the Nth electrode plate 131.

[0095] In implementation, firstly, in situations such as Figure 12 The surfaces of the structures shown (i.e., the second isolation structure 150 and the capacitor structure 130) are formed as follows: Figure 13 The first isolation structure 140 is shown. The surface of the first isolation structure 140 can then be planarized using a chemical mechanical polishing (CMP) process.

[0096] Next, for example Figure 13 The first isolation structure 140 shown is etched to form a shape as shown. Figure 14 The diagram shows multiple contact holes 161; each etched hole 161 exposes a corresponding electrode plate 131. For example, from the direction away from the trench 111 (e.g., the opposite direction of the Y-axis), the Ni-th contact hole 161 exposes the topmost electrode plate 131 on the surface of the Ni-th protrusion structure 120, and the N-th contact hole 161 exposes the Nth layer electrode plate 131. Here, since each electrode plate 131 is flush with the corresponding protrusion structure 120, the etching depth of the multiple contact holes 161 is the same, thereby allowing the multiple contact holes 161 to be formed simultaneously, simplifying the process steps.

[0097] Finally, regarding... Figure 15 The contact holes 161 shown are filled to form N contact structures 160 that penetrate the first isolation structure 140 and extend along the X-axis.

[0098] In other embodiments, before forming the contact structure 160, the method of forming the semiconductor structure further includes forming a barrier layer (not shown) on the sidewall of the contact hole 161. The barrier layer can prevent material diffusion of the contact structure 160, while enhancing the interfacial adhesion strength between the contact structure 160 and the surrounding first isolation structure 140.

[0099] In this embodiment, after the N contact structures 160 are formed, their bottom ends are electrically connected to each of the N electrode plates 131. Specifically, from the direction away from the trench 111 (e.g., the opposite direction of the Y-axis), the Nth contact structure 160 is connected to the top electrode plate 131 on the surface of the Nith protrusion 120, and the Nth contact structure 160 is connected to the Nth electrode plate 131, thereby realizing the independent lead-out of each electrode plate 131 of the capacitor structure 130. For example, please refer to... Figure 15 From a direction away from trench 111 (e.g., the opposite direction of the Y-axis), the second contact structure 160 is connected to the top electrode plate 131 on the surface of the first protrusion structure 120, and the third contact structure 160 is connected to the third electrode plate 131. The lateral spacing between each contact structure 160 is isolated by a first isolation structure 140 to prevent short circuits and signal crosstalk between electrode plates at different potentials. At the same time, the first isolation structure 140 also isolates the capacitor structure 130 from subsequent wiring layers and the external environment, avoiding electrical short circuits and protecting the capacitor structure 130 from physical and chemical damage caused by subsequent processes.

[0100] In this embodiment, by providing raised structures with progressively decreasing heights along the direction approaching the trench below the capacitor structure, the electrical connection terminals of each electrode plate are raised in a stepped manner, ultimately making the top electrode plate of all raised structures flush with the upper surface of the Nth (i.e., the topmost) electrode plate. This reduces the etching difficulty when creating vertical contact holes for each electrode plate, thereby improving the reliability of electrical connections, reducing the risk of short circuits or leakage due to process alignment or depth control deviations, and contributing to improved process stability and product yield.

[0101] The semiconductor structure formed by the semiconductor structure formation method provided in this application embodiment is similar to the semiconductor structure in the above embodiments. For technical features not disclosed in detail in this application embodiment, please refer to the above embodiments for understanding, and will not be repeated here.

[0102] This application also provides an electronic device. Figure 16 This is a schematic diagram of the structure of an electronic device 200 provided in an embodiment of this application, as shown below. Figure 16 As shown, the electronic device 200 includes any of the semiconductor structures 100 described in the above embodiments.

[0103] It should be noted that for electronic devices, this can be such as Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SDRAM), Double Data Rate SDRAM (DDRSDRAM), etc., and no specific limitation is made here.

[0104] Furthermore, in some embodiments, the electronic device may include a DRAM chip. The DRAM chip may conform to memory specifications such as DDR, DDR2, DDR3, DDR4, DDR5, and DDR6, as well as LPDDR, LPDDR2, LPDDR3, LPDDR4, LPDDR5, and LPDDR6; no specific limitation is made here.

[0105] In the several embodiments provided in this application, it should be understood that the disclosed structures and methods can be implemented in a non-target manner. The structural embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components can be combined, or integrated into another system, or some features can be ignored or not executed. In addition, the various components shown or discussed are coupled to each other or directly coupled.

[0106] The features disclosed in the several method or structural embodiments provided in this application can be arbitrarily combined without conflict to obtain new method or structural embodiments.

[0107] The above are merely some embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the above-described scope.

Claims

1. A semiconductor structure, characterized in that, include: The substrate includes trenches extending along a first direction; N-1 protrusions are located on the surface of the substrate and are spaced apart along the second direction; the height of the N-1 protrusions decreases sequentially along the direction close to the trench; N≥2; The capacitor structure includes N layers of electrode plates that sequentially cover the inner side of the trench and extend along the second direction on the substrate surface, and a dielectric layer located between adjacent electrode plates; Wherein, the i-th layer of electrode plates extends along the second direction to the surface of the Ni-th protrusion structure; the topmost electrode plate on the surface of each protrusion structure has the same height as the N-th layer of electrode plates in the first direction; the first direction is perpendicular to the plane where the substrate is located, and the second direction is parallel to the plane where the substrate is located.

2. The semiconductor structure according to claim 1, characterized in that, The height of the Nith protrusion is equal to (Ni)*(d1+d2), where d1 and d2 represent the thickness of the electrode plate and the dielectric layer, respectively.

3. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure also includes: A first isolation structure covers the surfaces of the substrate and the capacitor structure; The second isolation structure is located between the substrate and the capacitor structure, and between the protrusion structure and the capacitor structure.

4. The semiconductor structure according to claim 3, characterized in that, The semiconductor structure also includes: N contact structures are located in the first isolation structure and extend along the first direction; The Nth contact structure is connected to the topmost electrode plate on the surface of the Nith protrusion structure, and the Nth contact structure is connected to the Nth layer of electrode plates.

5. A method for forming a semiconductor structure, characterized in that, The method includes: A substrate is provided; the substrate includes trenches extending along a first direction; N-1 protrusions are formed on the surface of the substrate and spaced apart along a second direction; the height of the N-1 protrusions decreases sequentially along the direction close to the trench; N≥2; A capacitor structure is formed; the capacitor structure includes N layers of electrode plates that sequentially cover the inner side of the trench and extend along the second direction on the substrate surface, and a dielectric layer located between adjacent electrode plates; Wherein, the i-th layer of electrode plates extends along the second direction to the surface of the Ni-th protrusion structure; the topmost electrode plate on the surface of each protrusion structure has the same height as the N-th layer of electrode plates in the first direction; the first direction is perpendicular to the plane where the substrate is located, and the second direction is parallel to the plane where the substrate is located.

6. The method according to claim 5, characterized in that, Forming N-1 protrusion structures located on the surface of the substrate and spaced apart along a second direction, including: Provide initial substrate; The initial substrate is etched to form N-1 protrusion structures spaced apart along the second direction; the height of the Nith protrusion structure is equal to (Ni)*(d1+d2), where d1 and d2 represent the thickness of the electrode plate and the dielectric layer, respectively. The remaining surface of the initial substrate is etched to form the trench; the trench is located on one side of the direction in which the heights of the N-1 protrusion structures decrease sequentially; the remaining initial substrate constitutes the substrate.

7. The method according to claim 5, characterized in that, Forming N-1 protrusion structures located on the surface of the substrate and spaced apart along a second direction, including: A filler material layer is formed on the surface of the substrate; The filling material layer is etched to form N-1 protrusion structures spaced apart along the second direction; Wherein, the height of the Nith protrusion is equal to (Ni)*(d1+d2), and d1 and d2 represent the thickness of the electrode plate and the dielectric layer, respectively.

8. The method according to claim 5, characterized in that, Forming a capacitor structure includes: An initial electrode plate and an initial dielectric layer are sequentially and alternately formed on the exposed surfaces of the substrate and the trench. The initial electrode plate and the adjacent initial dielectric layer are etched layer by layer so that the electrode plate exposed on the surface of the Nith protrusion structure is the i-th electrode plate.

9. The method according to claim 5, characterized in that, The method further includes: A first isolation structure is formed covering the surfaces of the substrate and the capacitor structure; N contact structures are formed that penetrate the first isolation structure and extend along the first direction; The Nith contact hole is connected to the topmost electrode plate on the surface of the Nith protrusion structure, and the Nth contact hole is connected to the Nth layer electrode plate.

10. The method according to claim 5, characterized in that, Before forming the capacitor structure, the method further includes: A second isolation structure is formed on the surface of the substrate and the protrusion structure.

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