A node flip self-recovery latch with low area and low power consumption

Abstract

The application discloses a node flip self-recovery latch with low area and low power consumption, comprising a transmission gate, an error tolerance module, a clock control-based recovery module and the like; when a clock signal is CLK=1 and a reverse clock signal is CLKB=0, the latch is in a transparent mode, at this time, the transmission gate is turned on, the clock-controlled transistor in the recovery module is turned off, the input node D supplies values to nodes I1, I2(Q) and I3 through the transmission gate, and then the nodes I1, I2(Q) and I3 provide driving to nodes A0, A1, P and N through the error tolerance module, so as to complete node initialization; conversely, when CLK=0 and CLKB=1, the latch is in a holding mode, the transmission gate is turned off, the clock-controlled transistor in the recovery module is turned on, and the nodes A0, A1, P and N supply values to the nodes I1, I2(Q) and I3 through the recovery module, so as to form a feedback loop to complete latching of a logic value, the latch reduces power consumption overhead caused by step-by-step driving and current competition, and simultaneously reduces the number of sensitive nodes.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit anti-interference technology, specifically to a node-flipping self-recovering latch that combines low area and low power consumption. Background Technology

[0002] In nanoscale CMOS technology, as transistor feature sizes shrink, node capacitance and supply voltage continuously decrease, leading to a critical charge at circuit nodes. As the frequency of power loss continues to decline, the sensitivity of circuits and systems to soft errors is increasing. Against this backdrop, soft errors caused by high-energy particles (such as neutrons, protons, or heavy ions) bombarding sensitive areas of circuits have become a major threat to circuit reliability. When a high-energy particle strikes the diffusion region of the reverse-biased transistor in a memory module, the resulting charge can be captured by neighboring nodes through drift and diffusion mechanisms, leading to a voltage transient known as a single-node-upset (SNU). Furthermore, due to the drastic reduction in node spacing, a single particle impact may affect multiple nodes, resulting in a double-node-upset (DNU). As a critical component of sequential logic circuits, the reliability of latches directly affects the stable operation of the entire system. Therefore, researching ruggedized latch structures capable of tolerating double-node-upsets has significant theoretical and practical value.

[0003] In the current research context, DNU (Distributed Null Null) has become a typical soft error problem affecting circuit reliability. To achieve effective fault tolerance for DNU, scholars both domestically and internationally have proposed various radiation-hardened latch structures. However, existing mainstream hardening schemes generally rely on multi-stage filtering structures and multiple feedback loops to suppress the propagation and diffusion of soft errors. While this design approach improves fault tolerance, it also brings significant drawbacks: it not only causes a significant increase in circuit power consumption but also introduces more sensitive nodes. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a latch that reduces the power consumption overhead caused by step-by-step driving and current competition, while reducing the number of sensitive nodes.

[0005] To solve the above-mentioned technical problems, the present invention provides the following technical solution:

[0006] A node-flipping self-recovering latch with both low area and low power consumption includes: transmission gates TG1, TG2, TG3 and mutually redundant error-tolerant modules, and a clock-controlled recovery module. When the clock signal CLK=1 and the reverse clock signal CLKB=0, the latch is in transparent mode. At this time, transmission gates TG1, TG2, and TG3 are turned on, and the clock-controlled transistors in the recovery module are turned off. Input node D supplies values ​​to nodes I1, I2(Q), and I3 through transmission gates TG1, TG2, and TG3 respectively. Then, nodes I1, I2(Q), and I3 provide drive to nodes A0, A1, P, and N through the error-tolerant module to complete node initialization. Conversely, when the clock signal CLK=0 and the reverse clock signal CLKB=1, the latch is in hold mode, the transmission gates TG1, TG2, and TG3 are turned off, the clock-controlled transistors in the recovery module are turned on, and nodes A0, A1, P, and N supply values ​​to nodes I1, I2(Q), and I3 through the recovery module, thereby forming a feedback loop to complete the latching of the logic value.

[0007] In this embodiment, the error tolerance module includes an OSC unit and a polarity stacked structure; wherein, the OSC unit outputs nodes A0 and A1, and applies nodes A0 and A1 to the polarity stacked structure, so that the output nodes P and N in the polarity stacked structure isolate and attenuate single-node flips, and tolerate double-node flips.

[0008] In this embodiment, the OSC unit includes transistors P1, P2, P3, P4, P5, N1, N2, N3, N4 and N5; the inputs are nodes I1, I2(Q) and I3, and the OSC unit outputs are nodes A0 and A1. The pull-up network of node A0 consists of transistors P1, P2 and P3 connected in series, and the pull-down network consists of transistors N4 and N5 connected in series. The pull-up network of node A1 consists of transistors P4 and P5 connected in series, and the pull-down network consists of transistors N1, N2 and N3 connected in series.

[0009] In this embodiment, the polarity stacking structure includes a first polarity stacking structure and a second polarity stacking structure; The first polarity stacked structure includes transistors P6, P7, P8, P9, P10, N18, N19, and N20; its inputs are nodes I1, I2(Q), I3, A0, and A1, and its output is node P; the pull-up network of node P is P6, P7, and P8 connected in series, and the pull-down network consists of two parallel paths, mainly composed of transistors P9, P10, and N18 and transistors P9, N19, and N20; transistor P9 is shared by both paths; transistors P10 and N19 are in parallel, and the source of thyristor P10 and the drain of thyristor N19 are connected to the drain of transistor P9; transistors N18 and N20 are in parallel, and their sources are connected to GND. The second polarity stacked structure includes transistors P18, P19, P20, N6, N7, N8, N9, and N10; its inputs are nodes I1, I2(Q), I3, A0, and A1, and its output is node N. The pull-down network of node N consists of transistors N8, N9, and N10 connected in series, and the pull-up network consists of two parallel paths, mainly composed of transistors N7, N6, and P18, and transistors N7, P20, and P19; among them, transistor N7 is shared by both paths; transistors N6 and P20 are in parallel, and the source of transistor N6 and the drain of transistor P20 are connected to the drain of transistor N7; transistors P18 and P19 are in parallel, and their sources are connected to VDD. The transistors immediately above and below node N are all NMOS transistors, therefore it is an N-polarity node. Its characteristic is that it is an insensitive node when storing logic 0.

[0010] In this embodiment, node A1 controls the gate of transistor P9 to provide hardening protection for node P, preventing node P from flipping from 1 to 0; node A0 controls the gate of transistor N7 to provide hardening protection for node N, preventing node N from flipping from 0 to 1.

[0011] In this embodiment, the recovery module is used to achieve self-recovery after nodes I1, I2(Q) and I3 are disturbed.

[0012] In this embodiment, the recovery module includes a recovery structure mainly composed of transistors P11, P12, P13, P14, P15, N21, and N22, which is used to protect node I1 and provide a recovery path. The pull-up network of node I1 consists of two parallel paths. Path one is composed of transistors P11, P12, and P13 connected in series, and path two is composed of transistors P14 and P15 connected in series. Both paths are connected to its pull-down network. The pull-down network of node I1 is composed of N21 and N22 connected in series. The recovery structure ensures that node I1 is not affected by the simultaneous flipping of any two nodes among nodes A0, A1, P, and N, and provides a recovery path for node I1 when it flips.

[0013] In this embodiment, the recovery module includes a recovery structure two mainly composed of transistors P21, P22, N11, N12, N13, N14 and N15, which is used to provide protection and recovery paths for node I3; The pull-up network of node I3 includes transistors P21 and P22, which are connected in series; the pull-down network of node I3 consists of two parallel paths, one of which is composed of transistors N11, N12, and N13 connected in series, and the other of which is composed of transistors N14 and N15 connected in series. The recovery structure 2 protects node I3 from the simultaneous flipping of any two nodes among nodes A0, A1, P, and N, and provides a recovery path for node I3.

[0014] In this embodiment, the recovery module includes a dual-input clock-controlled inverter mainly composed of transistors P16, P17, N16 and N17, which serves as the third recovery structure and provides a protection and recovery path for node I2(Q). The pull-up network of node I2(Q) is composed of transistors P16 and P17 connected in series, and the pull-down network is composed of transistors N16 and N17 connected in series. The recovery structure protects node I2(Q) from being affected by the simultaneous flipping of any two nodes among nodes A0, A1, P, and N, and provides a recovery path for node I2(Q).

[0015] In this embodiment, the clock-controlled transistors in the recovery module are thyristors P15, P17, P22, N14, N16, and N21.

[0016] Compared with the prior art, the beneficial effects of the present invention are: The OSPSL latch proposed in this invention is initialized by nodes I1, I2(Q), and I3 in the error-tolerant module for nodes A0, A1, P, and N. In the recovery module, nodes A0, A1, P, and N provide feedback values ​​to nodes I1, I2(Q), and I3, thus forming a feedback loop. This invention uses only a single feedback loop, reducing internal current contention and unnecessary conduction paths, thereby reducing power consumption and area.

[0017] In this invention, nodes P and N are P-polarity nodes and N-polarity nodes, respectively. Taking the N-polarity node as an example, it is constructed by stacking an NMOS transistor through the pull-up pin of the output node N. Due to the built-in electric field distribution in the depletion layer of the drain-substrate PN junction of the NMOS transistor, the N-polarity node exhibits significant selectivity for charge carriers. The N-polarity node only absorbs negative charges and undergoes a 1-to-0 flip. When node N stores logic 0, it is a non-sensitive node. Therefore, the number of sensitive nodes can be effectively reduced through the polarity stacking structure.

[0018] The OSPSL latch proposed in this paper consists of only one feedback loop, thereby reducing the power consumption overhead caused by step-by-step driving and current contention, and also reducing the number of sensitive nodes. Specifically, in the error-tolerant module, the proposed OSPSL latch is initialized by nodes I1, I2(Q), and I3, which drive nodes A0, A1, P, and N. In the recovery module, nodes A0, A1, P, and N then provide feedback values ​​to nodes I1, I2(Q), and I3, thus forming a feedback loop.

[0019] This invention is designed with two modules: an error-tolerant module and a recovery module. The error-tolerant module is mainly used to isolate and attenuate particle flip pulses, while the recovery module is mainly used to achieve self-recovery after a node is disturbed.

[0020] The latch of this invention has a smaller area overhead and the lowest power consumption compared to existing typical rugged latches.

[0021] This invention is insensitive to fluctuations in temperature, power supply voltage, and threshold voltage, and can maintain stable operation even under harsh conditions. Attached Figure Description

[0022] Figure 1 This is a circuit diagram of a node-flipping self-recovering latch with both low area and low power consumption, as described in an embodiment of the present invention.

[0023] Figure 2 The embodiments of the present invention include single-node and dual-node flip-over fault injection diagrams. Detailed Implementation

[0024] To facilitate understanding of the technical solution of the present invention by those skilled in the art, the technical solution of the present invention will now be further described in conjunction with the accompanying drawings.

[0025] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0026] Please see Figure 1 As shown, the present invention provides an Output-Separated Polarity-Stacked Latch (OSPSL) with both low area and low power consumption, including transmission gates TG1, TG2, TG3 and mutually redundant error-tolerant modules, and a clock-controlled recovery module.

[0027] When the clock signal CLK=1 and the reverse clock signal CLKB=0, the latch is in transparent mode. At this time, transmission gates TG1, TG2, and TG3 are turned on, and the clock-controlled transistors in the recovery module are turned off. Input node D supplies values ​​to nodes I1, I2(Q), and I3 through transmission gates TG1, TG2, and TG3, respectively. Then, nodes I1, I2(Q), and I3 provide drive to nodes A0, A1, P, and N through the error-tolerant module, thereby completing node initialization.

[0028] Conversely, when the clock signal CLK=0 and the reverse clock signal CLKB=1, the latch is in hold mode, the transmission gates TG1, TG2, and TG3 are turned off, the clock-controlled transistors in the recovery module are turned on, and nodes A0, A1, P, and N supply values ​​to nodes I1, I2(Q), and I3 through the recovery module, thereby forming a feedback loop to complete the latching of the logic value.

[0029] In one embodiment of the present invention, the error-tolerant module includes an OSC unit and a polarity stacked structure; wherein, the OSC unit outputs nodes A0 and A1, and applies nodes A0 and A1 to the polarity stacked structure, so that the output nodes P and N in the polarity stacked structure isolate and attenuate single-node flips, and tolerate double-node flips.

[0030] In this embodiment, the OSC unit includes transistors P1, P2, P3, P4, P5, N1, N2, N3, N4, and N5, and inputs I1, I2(Q), and I3 nodes. The OSC unit outputs nodes A0 and A1. Specifically, the pull-up network of node A0 consists of three transistors P1, P2, and P3 connected in series, and the pull-down network consists of two transistors N4 and N5 connected in series. It can be seen that when any two nodes of I1, I2(Q), and I3 simultaneously flip from 1 to 0, node A0 will not be directly connected to VDD, that is, node A0 will not be affected and will flip to 1. Only when nodes I2(Q) and I3 simultaneously flip from 0 to 1 will A0 be affected and flip to 0. Similarly, node A1 has similar characteristics. The pull-up network of A1 consists of two transistors P4 and P5 connected in series, and the pull-down network consists of three transistors N1, N2, and N3 connected in series. As can be seen, when any two nodes among I1, I2(Q), and I3 simultaneously undergo a flip from 0 to 1, node A1 is unaffected. Only when nodes I1 and I3 simultaneously flip from 1 to 0 will node A1 be affected and flipped to 1. In summary, when any two nodes among I1, I2(Q), and I3 undergo arbitrary flips simultaneously, it will not cause A0 to flip to 1, nor will it cause A1 to flip to 0, nor will it cause A0 and A1 to flip simultaneously.

[0031] In this embodiment, the polarity stacking structure includes a first polarity stacking structure and a second polarity stacking structure. The first polarity stacking structure includes transistors P6, P7, P8, P9, P10, N18, N19, and N20, with input nodes I1, I2(Q), I3, A0, and A1, and output node P. The pull-up network of node P is mainly composed of P6, P7, and P8 connected in series. The pull-down network can be considered as two parallel paths, each composed of transistors P9, P10, and N18, and transistors P9, N19, and N20, respectively. Transistor P9 is shared by both paths. Transistors P10 and N19 are parallel, and the source of P10 and the drain of N19 are both connected to the drain of transistor P9. Transistors N18 and N20 are parallel, and their sources are both connected to GND. Therefore, the transistors immediately above and below node P are all PMOS transistors, making it a P-polarity node. This special structure ensures that when node P is affected by high-energy particles, it only undergoes a 0-to-1 flip. Therefore, when node P stores logic 1, it will not flip, making it an insensitive node. Furthermore, a hardened node A1 controls the gate of transistor P9 to protect node P. From the above analysis, we can conclude that when any two of nodes I1, I2(Q), and I3 flip simultaneously, node A1 will not flip to 0, thus preventing transistor P9 from conducting and preventing node P from flipping to 0. In summary, node P will not undergo a 1-to-0 flip.

[0032] In this embodiment, the second polarity stacked structure includes transistors P18, P19, P20, N6, N7, N8, N9, and N10. Its inputs are nodes I1, I2(Q), I3, A0, and A1, and its output is node N. The pull-down network of node N is mainly composed of N8, N9, and N10 connected in series. The pull-up network can be considered as two parallel paths, composed of transistors N7, N6, and P18, and transistors N7, P20, and P19, respectively. Transistor N7 is shared by both paths. Transistor N6 is parallel to P20, and the source of N6 and the drain of P20 are both connected to the drain of transistor N7. Transistors P18 and P19 are parallel, and their sources are both connected to VDD. The transistors immediately above and below node N are all NMOS transistors, therefore it is an N-polarity node. Its characteristic is that it is an insensitive node when node N stores logic 0. In addition, a hardened node A0 is used as the gate of the control transistor N7 to provide hardened protection for node N, so that node N will not flip from 0 to 1.

[0033] In one embodiment of the present invention, a recovery module is used to achieve self-recovery after nodes I1, I2(Q), and I3 are disturbed. Specifically, the recovery module includes a recovery structure one mainly composed of transistors P11, P12, P13, P14, P15, N21, and N22, used to protect node I1 and provide a recovery path. The pull-up network of node I1 consists of two parallel paths: path one is composed of transistors P11, P12, and P13 connected in series, and path two is composed of transistors P14 and P15 connected in series. Both paths are connected to its pull-down network. The pull-down network of node I1 is composed of N21 and N22 connected in series. The recovery structure one ensures that node I1 is not affected by the simultaneous flipping of any two nodes among A0, A1, P, and N (note that nodes P and N will not flip simultaneously), and provides a recovery path for node I1 when it flips.

[0034] In this embodiment, the recovery module includes a second recovery structure, mainly composed of transistors P21, P22, N11, N12, N13, N14, and N15, which provides a protection and recovery path for node I3. The pull-up network of node I3 is formed by transistors P21 and P22 connected in series, and the pull-down network of node I3 consists of two parallel paths: path one is formed by transistors N11, N12, and N13 connected in series, and path two is formed by transistors N14 and N15 connected in series. Similarly, the second recovery structure protects node I3 from the simultaneous flipping of any two nodes among nodes A0, A1, P, and N (nodes P and N will not flip simultaneously), and provides a recovery path for I3.

[0035] In this embodiment, the recovery module includes a dual-input clock-controlled inverter mainly composed of transistors P16, P17, N16, and N17, serving as recovery structure three to provide protection and recovery paths for node I2(Q). The pull-up network of node I2(Q) is composed of transistors P16 and P17 connected in series, and the pull-down network is composed of transistors N16 and N17 connected in series. From the previous analysis, it can be concluded that node P will not undergo a flip from 1 to 0, and node N will not undergo a flip from 0 to 1. Therefore, the simultaneous flipping of any two nodes among A0, A1, P, and N (nodes P and N will not flip simultaneously) will not affect node I2. Furthermore, this structure also provides a recovery path for node I2.

[0036] In one embodiment of the present invention, the clock-controlled transistors in the recovery module are thyristors P15, P17, P22, N14, N16, and N21. More specifically, the clock signal CLK controls thyristors P15, P17, and P22, and the reverse clock signal CLKB controls thyristors N14, N16, and N21.

[0037] In one embodiment of the present invention, due to the symmetry of the latch, this embodiment takes the storage of logic value 0 in the latch (i.e., D=I1=I2(Q)=I3=0, A0=A1=P=N=1) as an example to analyze the latch recovery principle. Similarly, it is undoubtedly applicable when the storage of logic value 1 is also true. Since node P remains at a logic high level (i.e., P=1) when the latch is in logic 0, node P is a non-sensitive node at this time. Therefore, in the node flipping analysis, only the cases where nodes I1, I2(Q), I3, A0, A1, and N flip are considered.

[0038] SNU scenarios can be divided into the following three categories: SNU-case1: A single node flips at I1, I2(Q), or I3. Taking node I1 as an example, when I1 flips from 0 to 1, since this node is not acting as the driving node for any pull-up or pull-down network, the transient error cannot propagate to other nodes, and the remaining nodes remain stable. Subsequently, under the action of transistors N21 and N22, node I1 is pulled back to the correct logic value of 0, achieving self-recovery.

[0039] SNU-case2: A single node flip occurs in node A0 or A1. Taking node A0 as an example, when node A0 flips from 1 to 0, the flip does not affect the logic state of the other nodes. Subsequently, under the action of transistors P1, P2, and P3, node A0 returns to the correct logic value of 1.

[0040] SNU-case 3: A single-node flip occurs at the N-polarity node N. When node N flips from 1 to 0, since this node only drives the NMOS transistors in other cells, and the NMOS transistors are turned off when the drive is 0, the error will not be propagated further. Finally, with the combined conduction of transistors P18, P19, P20, N6, and N7, node N is pulled back to the correct logic value of 1.

[0041] In one embodiment of the present invention, due to the symmetry of the latch, this embodiment takes the storage of logic value 0 in the latch (i.e., D=I1=I2(Q)=I3=0, A0=A1=P=N=1) as an example to analyze the recovery principle of the latch. Similarly, it is undoubtedly applicable when the storage of logic value 1 is also true. In addition, since node P remains at a high level (P=1) when the latch stores logic 0, and this node is a P-polarity node, it has a natural inhibitory effect on the collection of negative charges and is not easy to absorb negative charges and thus does not undergo a "1→0" flip. Therefore, in the node flip analysis, only the cases where nodes I1, I2(Q), I3, A0, A1, and N flip need to be considered. DNU scenarios can be divided into the following five categories: DNU-case 1: Any two of nodes I1, I2(Q), and I3 simultaneously flip. Consider the worst-case scenario (node ​​pair).<I2(Q),I3> For example, when nodes I2(Q) and I3 simultaneously flip from 0 to 1, transistors N4 and N5 turn on, causing node A0 to flip to logic 0, while the remaining nodes retain their correct logic values. In the clocked dual-input inverter, transistors P16 and P17 are turned off, and thyristors N16 and N17 are turned on, pulling node I2(Q) back to the correct logic value 0. Simultaneously, in the recovery module, transistors P21 and P22 are turned off, and transistors N12, N13, N14, and N15 are turned on. Node I3 is connected to GND through transistors N14 and N15, thus restoring it to the correct logic value 0. As nodes I2(Q) and I3 recover, transistors N4 and N5 turn off, and transistors P1, P2, and P3 turn on, ultimately restoring node A0 to 1.

[0042] DNU-case 2: Nodes A0 and A1 are simultaneously impacted by particles and flip, meaning both nodes A0 and A1 change from 1 to 0. The pull-up and pull-down networks of node N are both off, keeping it in a high-impedance state and maintaining its original correct logic value. This flip does not affect other nodes. Subsequently, in the OSC cell, transistors P1, P2, P3, P4, and P5 are turned on, while transistors N1, N2, N3, N4, and N5 are turned off, causing nodes A0 and A1 to return to their logic value of 1.

[0043] DNU-case 3: Any one of nodes I1, I2(Q), and I3, and any one of nodes A0 and A1, are simultaneously flipped. The worst-case scenario is determined by the node pair...<I1,A1> For example, node I1 flips from 0 to 1, and node A1 flips from 1 to 0. Transistor P9 turns on, and node P will show a downward pulse glitch. However, because transistors P10, N18, and N20 are turned off, node P will not completely flip, and other nodes are unaffected. Subsequently, because transistors P11, P12, P14, and P15 are turned off, and transistors N21 and N22 are turned on, node I1 returns to its logic value of 0. Finally, transistors P4 and P5 turn on, and transistors N1, N2, and N3 are turned off, and node A1 returns to its logic value of 1.

[0044] DNU-case4: Any one of nodes I1, I2(Q), and I3 is simultaneously affected along with node N. The worst-case scenario is considered as the node pair...<I2(Q),N> For example, node I2(Q) flips from 0 to 1, and node N flips from 1 to 0, causing the pull-up and pull-down networks of nodes I1 and I3 to be in the off state. Nodes I1 and I3 enter a high-impedance state, maintaining their original correct logic values. Subsequently, due to the conduction of transistors P19, P20, and N7, transistors N8 and N9 are turned off, and N returns to its logic value of 1. Finally, transistors N16 and N17 are turned on, and node I2(Q) returns to its logic value of 0.

[0045] DNU-case5: Any one node in A0 or A1, along with N nodes, is simultaneously affected, with node pairs...<A0,N> For example, nodes A0 and N simultaneously flip from logic 1 to 0, causing transistor P12 to turn on and transistors N11, N15, N17, and N22 to turn off. This puts nodes I1, I2(Q), and I3 in a high-impedance state while maintaining their original correct logic values. Subsequently, nodes I1, I2(Q), and I3 turn on transistors P1, P2, and P3, and turn off transistors N4 and N5, restoring node A0 to logic 1. Afterward, node A0 turns on transistor N7, and the pull-up network of node N turns on, restoring it to logic 1.

[0046] In one embodiment of the present invention, please refer to Figure 2, which shows the injection results of single-node and dual-node flip-over faults. As can be seen from the figure, representative single-node and dual-node flip-over scenarios can be recovered.

[0047] Please refer to Table 1, which shows a comparison of reliability and performance with typical latches. Column 2 lists the publication year of the compared structures, and columns 3 and 4 demonstrate the latch's ruggedization capabilities, proposing that the latch can achieve self-recovery during dual-node flip-over. Column 5 shows the area comparison (×10). -2 (um²), proposing that the latch has good comparability. Columns 6 to 8 are the static power consumption P. static (nW), dynamic power consumption P dynamic (uW) and total power consumption P total (uW) comparison shows that the latch has the lowest power consumption. Columns 9 and 10 represent the setup time T. setup (ps) and holding time T hold (ps) In comparison, a relatively small value indicates that the latch has good performance. Columns 11, 12, and 13 represent the time T from data input change to output response, respectively. DQ (ps) Time T from clock trigger to output response CQ (ps) and their average time T Avg.(ps). The last column, APDP, represents the product of area, power consumption, and delay, indicating a comparison of overall overhead. It can be seen that the proposed latch still has the lowest overall overhead.

[0048] Table 1. Comparison of reliability and performance with typical latches

[0049] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention, and no reference numerals in the claims should be construed as limiting the scope of the claims.

[0050] The above embodiments are merely examples of implementation methods of the invention. The scope of protection of the present invention is not limited to the above embodiments. For those skilled in the art, several modifications and improvements can be made without departing from the concept of the present invention, and these all fall within the scope of protection of the present invention.

Claims

1. A node-flip self-recovery latch that combines low area and low power consumption, characterized in that, include: It includes transmission gates TG1, TG2, and TG3, as well as mutually redundant error-tolerant modules and clock-controlled recovery modules; When the clock signal CLK=1 and the reverse clock signal CLKB=0, the latch is in transparent mode. At this time, transmission gates TG1, TG2, and TG3 are turned on, and the clock-controlled transistors in the recovery module are turned off. Input node D supplies values ​​to nodes I1, I2(Q), and I3 through transmission gates TG1, TG2, and TG3 respectively. Then, nodes I1, I2(Q), and I3 provide drive to nodes A0, A1, P, and N through the error-tolerant module to complete node initialization. Conversely, when the clock signal CLK=0 and the reverse clock signal CLKB=1, the latch is in hold mode, the transmission gates TG1, TG2, and TG3 are turned off, the clock-controlled transistors in the recovery module are turned on, and nodes A0, A1, P, and N supply values ​​to nodes I1, I2(Q), and I3 through the recovery module, thereby forming a feedback loop to complete the latching of the logic value.

2. The node-flipping self-recovering latch with both low area and low power consumption according to claim 1, characterized in that, The error-tolerant module includes an OSC unit and a polarity stack structure. The OSC unit outputs nodes A0 and A1, which are applied to the polarity stack structure. This allows the output nodes P and N in the polarity stack structure to isolate and attenuate single-node flips and tolerate double-node flips.

3. The node-flip self-recovering latch with both low area and low power consumption according to claim 2, characterized in that, The OSC unit includes transistors P1, P2, P3, P4, P5, N1, N2, N3, N4, and N5; the inputs are nodes I1, I2(Q), and I3, and the OSC unit outputs are nodes A0 and A1. The pull-up network of node A0 consists of transistors P1, P2 and P3 connected in series, and the pull-down network consists of transistors N4 and N5 connected in series. The pull-up network of node A1 consists of transistors P4 and P5 connected in series, and the pull-down network consists of transistors N1, N2 and N3 connected in series.

4. The node-flip self-recovering latch with both low area and low power consumption according to claim 2, characterized in that, The polarity stacking structure includes a first polarity stacking structure and a second polarity stacking structure; The first polarity stacked structure includes transistors P6, P7, P8, P9, P10, N18, N19, and N20; its inputs are nodes I1, I2(Q), I3, A0, and A1, and its output is node P; the pull-up network of node P is P6, P7, and P8 connected in series, and the pull-down network consists of two parallel paths, mainly composed of transistors P9, P10, and N18 and transistors P9, N19, and N20; transistor P9 is shared by both paths; transistors P10 and N19 are in parallel, and the source of thyristor P10 and the drain of thyristor N19 are connected to the drain of transistor P9; transistors N18 and N20 are in parallel, and their sources are connected to GND. The second polarity stacked structure includes transistors P18, P19, P20, N6, N7, N8, N9, and N10; its inputs are nodes I1, I2(Q), I3, A0, and A1, and its output is node N. The pull-down network of node N consists of transistors N8, N9, and N10 connected in series, and the pull-up network consists of two parallel paths, mainly composed of transistors N7, N6, and P18, and transistors N7, P20, and P19; among them, transistor N7 is shared by both paths; transistors N6 and P20 are in parallel, and the source of transistor N6 and the drain of transistor P20 are connected to the drain of transistor N7; transistors P18 and P19 are in parallel, and their sources are connected to VDD. The transistors immediately above and below node N are all NMOS transistors, therefore it is an N-polarity node. Its characteristic is that it is an insensitive node when storing logic 0.

5. The node-flip self-recovering latch with both low area and low power consumption according to claim 4, characterized in that, Node A1 controls the gate of transistor P9, providing hardening protection for node P so that node P will not flip from 1 to 0; Node A0 controls the gate of transistor N7, providing hardening protection for node N so that node N will not flip from 0 to 1.

6. The node-flip self-recovering latch with low area and low power consumption according to claim 1, characterized in that, The recovery module is used to enable self-recovery of nodes I1, I2(Q), and I3 after they have been disturbed.

7. The node-flip self-recovering latch with low area and low power consumption according to claim 6, characterized in that, The recovery module includes a recovery structure consisting mainly of transistors P11, P12, P13, P14, P15, N21, and N22, which is used to protect node I1 and provide a recovery path. The pull-up network of node I1 consists of two parallel paths. Path one is composed of transistors P11, P12, and P13 connected in series, and path two is composed of transistors P14 and P15 connected in series. Both paths are connected to its pull-down network. The pull-down network of node I1 is composed of N21 and N22 connected in series. The recovery structure ensures that node I1 is not affected by the simultaneous flipping of any two nodes among nodes A0, A1, P, and N, and provides a recovery path for node I1 when it flips.

8. The node-flip self-recovering latch with low area and low power consumption according to claim 6, characterized in that, The recovery module includes recovery structure two, which is mainly composed of transistors P21, P22, N11, N12, N13, N14 and N15, and is used to provide protection and recovery paths for node I3; The pull-up network of node I3 includes transistors P21 and P22, which are connected in series; the pull-down network of node I3 consists of two parallel paths, one of which is composed of transistors N11, N12, and N13 connected in series, and the other of which is composed of transistors N14 and N15 connected in series. The recovery structure 2 protects node I3 from the simultaneous flipping of any two nodes among nodes A0, A1, P, and N, and provides a recovery path for node I3.

9. The node-flip self-recovering latch with low area and low power consumption according to claim 6, characterized in that, The recovery module includes a dual-input clock-controlled inverter mainly composed of transistors P16, P17, N16 and N17, which serves as the third recovery structure and provides a protection and recovery path for node I2(Q). The pull-up network of node I2(Q) is composed of transistors P16 and P17 connected in series, and the pull-down network is composed of transistors N16 and N17 connected in series. The recovery structure protects node I2(Q) from being affected by the simultaneous flipping of any two nodes among nodes A0, A1, P, and N, and provides a recovery path for node I2(Q).

10. The node-flip self-recovering latch with low area and low power consumption according to claim 6, characterized in that, The clock-controlled transistors in the recovery module are thyristors P15, P17, P22, N14, N16, and N21.

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