A mask pattern optimization method, device, medium and program product

Abstract

The application discloses a mask layout optimization method, device, medium and program product, and relates to the technical field of semiconductor manufacturing. The method comprises the following steps: identifying a target vertex of a pattern end region in an original mask layout; determining a placement parameter of an additional pattern, and performing mask manufacturing rule detection on the mask layout under the condition that the additional pattern is placed according to the placement parameter; in the case that the detection fails, adjusting the placement parameter and performing mask manufacturing rule detection on the adjusted mask layout until the detection passes; and in the case that the detection passes, obtaining a target mask layout according to the original mask layout and the additional pattern corresponding to the placement parameter when the detection passes. The application adjusts the placement parameter of the additional pattern, ensures that the pre-placed additional pattern meets the mask manufacturing process requirement, compensates for the lithography imaging deviation of the end region, and improves the consistency of the silicon wafer imaging profile and the design profile.

Description

Technical Field

[0001] This application belongs to the field of semiconductor manufacturing technology, and in particular relates to a mask layout optimization method, apparatus, medium and process product. Background Technology

[0002] In semiconductor manufacturing, due to physical and chemical effects such as optical diffraction and etching processes, deviations occur between the actual contour of the silicon wafer image formed by the mask pattern during photolithography and the designed contour. If these deviations exceed the process tolerance, they will affect the chip's circuit functionality and yield. Mask layout optimization involves using various techniques to specifically correct and adjust the mask layout, compensating for pattern distortion during photolithography, and making the actual contour of the silicon wafer image more closely match the designed contour. This is a crucial step in semiconductor photolithography.

[0003] Currently, mask layout optimization is generally achieved through optical proximity correction (OPC). However, after OPC optimization, the mask layout may exhibit shrinkage and distortion in the silicon wafer imaging profile after exposure and etching, affecting the lithography imaging accuracy and chip manufacturing yield. Summary of the Invention

[0004] This application provides a mask layout optimization method, device, medium, and program product that can compensate for imaging deviations in the end region during photolithography and improve the consistency between the silicon wafer imaging profile and the design profile.

[0005] A first aspect of this application provides a mask layout optimization method, including: Identify target vertices in the end regions of the graphic in the original mask layout; Determine the placement parameters for the additional graphic to be placed, the placement parameters including the graphic size of the additional graphic and its relative position to the target vertex; Perform mask manufacturing rule detection on the mask layout when the additional graphics are placed according to the placement parameters; If the test fails, adjust the placement parameters and perform mask manufacturing rule testing on the adjusted mask layout until the test passes. The target mask pattern is obtained based on the original mask pattern and the additional graphic corresponding to the placement parameters when the detection passes.

[0006] A second aspect of this application provides a mask layout optimization apparatus, comprising: The end-point recognition module is used to identify target vertices in the end regions of the graphic in the original mask layout. The placement parameter module is used to determine the placement parameters of the additional graphic to be placed, the placement parameters including the graphic size of the additional graphic and its relative position to the target vertex; The pre-placement module is used to perform mask manufacturing rule detection on the mask layout when the additional graphics are placed according to the placement parameters; The parameter adjustment module is used to adjust the placement parameters and perform mask manufacturing rule detection on the adjusted mask pattern when the detection fails, until the detection passes. The target module is used to obtain a target mask pattern based on the original mask pattern and the additional pattern corresponding to the placement parameters when the detection passes.

[0007] A third aspect of the embodiments of this application provides a computer device, the device comprising: a memory and a program or instructions stored in the memory and executable on a processor, wherein when the program or instructions are executed by the processor, they implement a mask layout optimization method as provided in any of the embodiments of this application described above.

[0008] A fourth aspect of the embodiments of this application provides a readable storage medium on which a program or instructions are stored, and when the program or instructions are executed by a processor, implement a mask layout optimization method as provided in any of the embodiments of this application described above.

[0009] A fifth aspect of the embodiments of this application provides a computer program product in which instructions, when executed by a processor of an electronic device, cause the electronic device to perform a mask layout optimization method as provided in any of the embodiments of this application described above.

[0010] The technical solution provided in this application has at least the following beneficial effects: This application provides a mask layout optimization method that identifies target vertices in the end regions of patterns in the original mask layout; determines placement parameters for additional patterns; and performs mask manufacturing rule detection on the mask layout with additional patterns placed according to these parameters. If the detection fails, the placement parameters are adjusted, and the adjusted mask layout is subjected to mask manufacturing rule detection until the detection passes. If the detection passes, the target mask layout is obtained based on the original mask layout and the additional patterns corresponding to the placement parameters when the detection passed. This application ensures that the pre-placed additional patterns meet the mask manufacturing process requirements by adjusting the placement parameters of the additional patterns, compensates for photolithographic imaging deviations in the end regions, and improves the consistency between the silicon wafer imaging contour and the design contour. Attached Figure Description

[0011] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 This is a schematic flowchart of a mask layout optimization method provided in an embodiment of this application; Figure 2 This is a schematic diagram of the end region provided in the embodiments of this application; Figure 3 This is a schematic diagram of the horizontal and vertical side lengths of the additional graphics provided in the embodiments of this application; Figure 4 This is a schematic diagram of the horizontal and vertical offsets of the additional graphics provided in the embodiments of this application; Figure 5 This is a schematic diagram illustrating mask manufacturing rule detection of the mask layout after placing additional graphics, as provided in an embodiment of this application. Figure 6a This is a schematic diagram of native vertices and manufacturable vertices provided in the embodiments of this application; Figure 6b This is a schematic diagram of the target vertex provided in an embodiment of this application; Figure 6c This is a schematic diagram of the protruding vertex provided in an embodiment of this application; Figure 6d This is a schematic diagram of a corner vertex provided in an embodiment of this application; Figure 7a This is a schematic diagram of the original mask layout corresponding to the ideal photolithographic imaging profile provided in the embodiments of this application; Figure 7b This is a schematic diagram of the actual photolithographic imaging contour corresponding to the original mask pattern provided in the embodiments of this application; Figure 7c This is a schematic diagram of the lithographic imaging contour corresponding to the original mask pattern after OPC correction provided in the embodiments of this application; Figure 7d This is a schematic diagram of the lithographic imaging contour after placing additional graphics in the original mask pattern, as provided in the embodiments of this application. Figure 7e This is a schematic diagram of the lithographic imaging contour corresponding to the additional graphics provided in the embodiments of this application after OPC correction; Figure 8a This is a schematic diagram of the target vertices and additional graphics provided in the embodiments of this application; Figure 8b This is a schematic diagram illustrating the movement of additional graphics as the marked target vertex is provided in the embodiments of this application; Figure 9This is a schematic diagram of the structure of a mask layout optimization device provided in an embodiment of this application; Figure 10 This is a schematic diagram of a mask layout optimization device provided in an embodiment of this application. Detailed Implementation

[0013] The features and exemplary embodiments of various aspects of this application will be described in detail below. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain this application and not to limit it. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples.

[0014] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0015] It should be noted that the acquisition, storage, use, and processing of data in the technical solution of this application all comply with the relevant provisions of national laws and regulations. In the embodiments of this application, certain existing industry solutions such as software, components, and models may be mentioned. These should be considered exemplary, intended only to illustrate the feasibility of implementing the technical solution of this application, and do not imply that the applicant has already used or necessarily used such solutions.

[0016] First, the terms and concepts involved in one or more embodiments of this application will be explained.

[0017] Optical proximity correction refers to a lithography resolution enhancement technique that pre-corrects the pattern of a photomask to compensate for imaging deviations caused by factors such as optical diffraction and process fluctuations during photolithography, so that the final pattern outline formed on the silicon wafer is closer to the design outline.

[0018] A mask pattern is a pattern used for photolithography exposure, serving as an exposure template for the photolithography process in chip manufacturing.

[0019] Additional graphics refer to graphics that are placed additionally to compensate for lithographic imaging deviations and assist in optimizing the imaging contours of the end region.

[0020] Mask Rule Check (MRC) is a compliance verification at the mask manufacturing level. It is used to check whether the geometric parameters of the mask pattern, such as graphic size, spacing, and shape, meet the process requirements of the mask manufacturing equipment.

[0021] Design Rule Check (DRC) is a compliance check at the chip layout design level. It is used to check whether the geometric parameters such as graphic size, spacing, and overlap in the mask layout meet the design constraints specified by the chip manufacturing process.

[0022] In semiconductor manufacturing, due to physical and chemical effects such as optical diffraction and etching processes, deviations occur between the actual contour of the silicon wafer image formed by the mask pattern during photolithography and the designed contour. If these deviations exceed the process tolerance, they will affect the chip's circuit functionality and yield. Mask layout optimization involves using various techniques to specifically correct and adjust the mask layout, compensating for pattern distortion during photolithography, and making the actual contour of the silicon wafer image more closely match the designed contour. This is a crucial step in semiconductor photolithography.

[0023] Currently, mask layout optimization is generally achieved through optical proximity correction (OPC). However, after OPC optimization, the mask layout may exhibit shrinkage and distortion in the silicon wafer imaging profile after exposure and etching, affecting the lithography imaging accuracy and chip manufacturing yield.

[0024] To address the aforementioned technical problems, this application provides a mask layout optimization method, apparatus, medium, and program product. In the mask layout optimization method provided in this application, firstly, target vertices in the end regions of the original mask layout are identified to determine graphic vertices where additional graphics can be placed; secondly, placement parameters for the additional graphics are determined in the original mask layout, and the mask layout after placing the additional graphics according to the placement parameters is subjected to mask manufacturing rule detection. If the detection fails, the placement parameters are repeatedly adjusted until the detection passes, ensuring that the additional graphics meet the mask manufacturing process requirements; finally, a target mask layout is obtained based on the original mask layout and the detected additional graphics to compensate for imaging deviations during the photolithography process and improve the consistency between the silicon wafer imaging contour and the design contour.

[0025] The mask layout optimization method provided in this application embodiment is described below. In practical applications, the execution subject of the mask layout optimization method in this application embodiment can be a terminal device, such as a desktop computer, laptop computer, etc., or a remote device like a server. Of course, this application embodiment can also adopt an execution subject in the form of software, such as a client or software program installed on a terminal device. The specific type of execution subject corresponding to the technical solution provided in this application embodiment is not strictly limited here, and can be flexibly selected according to the actual application scenario and actual needs.

[0026] The following describes specific embodiments of the mask layout optimization method, apparatus, electronic device, storage medium, and computer program product provided in this application. First, a mask layout optimization method is introduced.

[0027] Figure 1 This is a schematic flowchart illustrating a mask layout optimization method provided in an embodiment of this application. Figure 1 As shown, the method includes steps S100 to S104.

[0028] S100: Identify target vertices in the end region of the graphic in the original mask pattern.

[0029] S101: Determine the placement parameters of the additional graphic to be placed, the placement parameters including the graphic size of the additional graphic and its relative position to the target vertex.

[0030] S102: Perform mask manufacturing rule detection on the mask layout when the additional graphic is placed according to the placement parameters; if the detection fails, proceed to S103; if the detection passes, proceed to S104.

[0031] S103: Adjust the placement parameters and perform mask manufacturing rule detection on the adjusted mask layout until the detection passes, then execute S104.

[0032] S104: Obtain the target mask pattern based on the original mask pattern and the additional graphic corresponding to the placement parameters when the detection passes.

[0033] In the above-mentioned mask layout optimization method, this application first identifies the target vertices of the end region of the pattern in the original mask layout, then determines the placement parameters of the additional pattern and performs mask manufacturing rule detection. By repeatedly adjusting the placement parameters until the detection is passed, it ensures that the additional pattern meets the mask manufacturing process requirements. The target mask layout is obtained by combining the original mask layout and the compliant additional pattern, thereby accurately compensating for the photolithography imaging deviation in the end region during the photolithography process and improving the consistency between the silicon wafer imaging contour and the design contour.

[0034] For example, the mask layout optimization method provided in this application can be applied to the production line of a semiconductor manufacturing company to optimize the original mask layout output during the chip design stage, compensating for the shrinkage of the imaging contour in the end region. In practical applications, after importing the original mask layout, the mask layout optimization method of this application completes the identification of target vertices in the end region, the determination of additional graphic placement parameters, the detection of mask manufacturing rules, and the iterative optimization of placement parameters to obtain a target mask layout that meets the requirements of the mask manufacturing process. This target mask layout is then stored in a data storage device. Operators can then perform mask manufacturing, photolithography exposure, process parameter calibration, and other process flows based on this target mask layout.

[0035] It should be noted that the application scenarios described in the above embodiments of this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided by the embodiments of this application. Those skilled in the art will understand that with the emergence of new application scenarios, the technical solutions provided by the embodiments of this application are also applicable to similar technical problems. The mask layout optimization method provided by the embodiments of this application can be applied to various application scenarios that require compensation for lithographic imaging deviations and improvement of silicon wafer imaging accuracy.

[0036] In step S100, in order to accurately locate the placement position of the additional pattern and ensure that the additional pattern can act on the end region that is prone to lithographic imaging deviation, this application needs to traverse and identify the pattern structure of the original mask pattern and filter out the target vertices belonging to the end region.

[0037] Specifically, this application can analyze the graphic outline, endpoints and extension direction in the original mask pattern based on the shape features of the end region, and extract the target vertices of the end region.

[0038] It should be noted that this application does not limit the specific method of identifying target vertices. It can be set according to actual needs, such as filtering endpoints based on the coordinate information of the graphic, identifying end vertices based on the curvature changes of the graphic edges, or using a preset feature recognition algorithm to extract vertices from the end region. During photolithography imaging, the light field distribution at the edge of the graphic depends on the optical interference and light field coupling of the surrounding graphics; in non-end regions, there are other graphics or line segments on both sides of the graphic edge, forming a uniformly distributed light field; however, the end region refers to the area within a preset range of the graphic extension end in the mask pattern where there are no other graphics or line segments, making it impossible to form a uniformly distributed light field, causing the photolithography imaging to deviate from the ideal state and resulting in inward shrinkage of the imaging contour. For example... Figure 2As shown, the graphic belonging to the end region is a graphic consisting of at least three sequentially connected line segments; wherein, the first line segment 201 and the third line segment 202 extend in the same direction as the reference direction 203, and the second line segment 204 is located between the endpoints on the same side of the first line segment and the third line segment, constituting the end line segment of the graphic belonging to the end region, and there are no other graphics or line segments within its preset range; the target vertex 205 of the end region is connected only to a second line segment with a length less than a preset length threshold, and a first or third line segment with a length not less than the preset length threshold. In this application, the specific size of the preset length threshold is not limited, and it can be set according to actual needs, such as the preset length threshold being determined based on the design dimensions of the original mask pattern, photolithography process accuracy requirements, mask manufacturing rule limitations, etc.

[0039] In step S101, in order to adapt the additional pattern to the end region and accurately compensate for the lithographic imaging deviation at the end region of the target vertex, a clear verification benchmark is provided for subsequent mask manufacturing rule detection. This application needs to determine the placement parameters of the additional pattern.

[0040] Specifically, this application allows for custom settings of the size of the additional graphic and its relative position to the target vertex, provided that the original graphic structure of the original mask pattern and the additional graphic accurately correspond to the target vertex. The graphic size can be set based on the size of the end region where the target vertex is located and the lithographic deviation compensation requirements; this application does not limit this setting. The relative position can be configured in conjunction with the extension direction of the end region and the graphic layout of the original mask pattern to ensure that the additional graphic can achieve targeted lithographic imaging deviation compensation for the end region where the target vertex belongs.

[0041] It should be noted that this application does not limit the specific type of shape, size, and relative position of the additional graphic. These can be set according to actual needs. For example, the shape of the additional graphic may include rectangles, trapezoids, polygons, etc.; the size may include length, width, corner radius, etc.; and the relative position may include horizontal offset distance, vertical offset distance, included angle, etc. To facilitate the parameterization of the additional graphic, accurately control its relative position to the target vertex, and simplify the verification process of mask manufacturing rules, in one or more embodiments of this application, the additional graphic is a rectangle. The graphic size includes the horizontal and vertical side lengths of the additional graphic, and the relative position includes the horizontal and vertical offsets of the center point of the additional graphic relative to the target vertex.

[0042] Figure 3 A schematic diagram showing the horizontal and vertical side lengths of the additional graphics provided for embodiments of this application. For example... Figure 3 As shown, the horizontal side length With vertical side length The graphic size of the additional graphic 302 pre-placed in the original mask layout 301 is determined, with the horizontal side length represented by W and the vertical side length represented by H.

[0043] Figure 4 A schematic diagram illustrating the horizontal and vertical offsets of the additional graphics provided for embodiments of this application. For example... Figure 4 As shown, the lateral offset With vertical offset The distance between the additional graphic center point 401 and the target vertex 402 is determined, with the horizontal offset represented by dW and the vertical offset represented by dH.

[0044] In step S102, in order to avoid the situation where the mask pattern cannot be produced due to unreasonable placement parameters, this application needs to perform compliance verification on the mask pattern after placing additional graphics according to the placement parameters based on the preset mask manufacturing rules.

[0045] It should be noted that the mask layout when placing the additional graphics according to the placement parameters can be implemented using methods such as simulated placement or actual placement, and this application is not limited in this regard. In some embodiments, this application can simulate the placement of the additional graphics based on the placement parameters, that is, simulated placement is only performed during the mask manufacturing rule verification stage to complete the compliance check, and no actual corresponding layout is generated; in the subsequent OPC, the additional graphics are then actually placed in real time according to the placement parameters that have passed the check, to ensure the compliance of the mask graphics and improve the efficiency of mask manufacturing rule detection.

[0046] In step S103, in order to ensure that the mask layout after placing additional graphics according to the placement parameters meets the mask manufacturing rules and to ensure that the generated mask layout is manufacturable, this application needs to iteratively adjust the placement parameters that do not conform to the mask manufacturing rules and re-verify them until the detection passes.

[0047] Specifically, this application can gradually modify the graphic size or relative position of additional graphics, and then re-perform mask manufacturing rule detection based on the updated placement parameters until the virtually placed mask layout meets the manufacturing process requirements.

[0048] It should be noted that this application does not limit the specific method of iterative adjustment, which can be set according to actual needs, such as adjusting the size by a fixed step size, gradually correcting the position by the offset direction, or adjusting the placement parameters based on the error information of the mask manufacturing rules. When the additional graphic is a rectangle, the iterative adjustment of the placement parameters includes: adjusting at least one of the following placement parameters in each iteration: horizontal side length, vertical side length, horizontal offset, and vertical offset.

[0049] Figure 5This is a schematic diagram illustrating mask manufacturing rule detection for a mask layout after placing additional graphics, as provided in an embodiment of this application. Figure 5 As shown, the distance between the edges of the graphic must be greater than the set edge-to-edge value, indicated by a solid arrow; the distance between the corners of the graphic must be greater than the set corner-to-corner value, indicated by a dashed arrow.

[0050] In step S104, in order to obtain a target mask pattern that meets the mask manufacturing rules and can compensate for lithographic imaging deviations, this application needs to generate a usable target mask pattern based on the additional graphics corresponding to the placement parameters when the detection passes and the original mask pattern.

[0051] It should be noted that this application does not limit the specific method of obtaining the target mask pattern. It can be set according to actual needs, such as merging the original mask pattern and the additional graphics corresponding to the placement parameters when the detection passes to obtain the target mask pattern; or merging the original mask pattern and the additional graphics corresponding to the placement parameters when the detection passes, and then optimizing the mask pattern through OPC to obtain the target mask pattern.

[0052] Furthermore, in step S100, in order to accurately locate the vertices of the end region that need to be compensated for photolithographic imaging deviation, in one or more embodiments of this application, this application can identify the original vertices of the original mask pattern, and then select target vertices that meet the length and shape conditions corresponding to the end region from each original vertices.

[0053] It should be noted that this application does not limit the specific method of filtering target vertices. It can be set according to actual needs, such as filtering based on graphic structure features like line segment extension direction, line segment connection relationship, and line segment length, or filtering based on the end contour shape and spatial distribution of the end region. The end contour shape refers to whether the graphic to which the vertex belongs is an outwardly extending end structure, and the spatial distribution refers to whether there are other graphic elements or line segments within a preset range of the end line segment. To improve the accuracy and reliability of target vertex filtering and avoid misjudging vertices in non-end regions as target vertices, in one or more embodiments of this application, for each native vertex, the lengths of the two adjacent edges connected to the native vertex can be obtained. If the lengths of both adjacent edges are both less than or greater than a preset length threshold, the native vertex does not meet the length condition, and is excluded as a target vertex. Conversely, if only one of the two adjacent edges has a length less than the preset length threshold, the native vertex meets the length condition, and it is necessary to further determine whether the graphic to which the native vertex belongs meets a preset shape condition. If yes, the native vertex is used as a target vertex; otherwise, the native vertex does not meet the shape condition, and is excluded as a target vertex. Among them, the length condition is that only one of the two adjacent edges connected to the vertex has a length less than a preset length threshold; the shape condition is that the original vertex belongs to the end of the graph that extends outward from the graph.

[0054] Since the vertices generated by the interruption operation during the OPC process are process-specific vertices rather than the original vertices of the mask layout, they need to be excluded, such as... Figure 6a As shown, native vertex 601 is the vertex of the graphic in the original mask pattern, and process vertex 602 is the vertex after the edge of the graphic in the original mask pattern has been broken. This application divides native vertices into target vertices, jog vertices, and corner vertices; as... Figure 6b As shown, target vertex 603 is a native vertex that satisfies both the length and shape conditions; as Figure 6c As shown, convex vertex 604 is a native vertex that satisfies the length condition but not the shape condition; as Figure 6d As shown, corner vertex 605 is a native vertex that does not meet the length condition but meets the shape condition.

[0055] To ensure that the additional graphic is always aligned with the target vertex during the optical proximity correction process and to avoid the failure of deviation compensation due to graphic movement, in one or more embodiments of this application, the additional graphic can be associated and bound to the target vertex according to the placement parameters when the detection passes, so that the additional graphic moves synchronously with the target vertex during the optical proximity correction process; the bound additional graphic and the original mask pattern are imported into the optical proximity correction model for iterative mask correction until the preset termination condition is met, and the target mask pattern is obtained.

[0056] It should be noted that this application does not limit the specific content of the preset termination conditions, which can be set according to actual needs, such as the number of iterations reaching a preset iteration threshold, the lithography imaging simulation error being less than a preset error threshold, and the key dimensions of the graphic meeting the design size requirements.

[0057] To achieve the functionality of the designed circuit, the end region of the original photomask layout must have sufficient contact area after photolithography. Simply modifying the original photomask layout using OPC is insufficient to ensure that the photolithographic imaging contour of the end region meets the contact area requirements of the designed circuit. Figure 7a As shown, the original mask pattern 301 is represented by a rectangle, and 702 is a simulated image pattern after the original mask pattern has undergone photolithography. The outer contour of this image pattern is the ideal photolithographic imaging contour 703, representing the reference imaging shape that meets the circuit functional requirements. Figure 7b As shown, due to the influence of the photolithography process, the actual imaging contour 704 in the end region is significantly reduced compared to the ideal photolithographic imaging contour, resulting in insufficient contact area and failing to meet the circuit functional requirements. Figure 7c As shown, the edge of the graphic in the original mask pattern is corrected based on OPC, forming a stepped correction structure 705. Although the corrected lithographic imaging contour 706 compensates for the lithographic imaging deviation in the end region to some extent, the correction amount of OPC is difficult to eliminate the lithographic imaging deviation in the end region due to the limitations of mask manufacturing rules.

[0058] Therefore, in this embodiment, by pre-setting an associated and bound additional graphic at the target vertex and making the additional graphic move synchronously with the target vertex during the optical proximity effect correction process, this application can maintain compensation for the imaging deviation of the end region while completing the overall layout correction, and avoid misalignment between the additional graphic and the target vertex due to the optical proximity effect correction.

[0059] Figure 7d This is a schematic diagram illustrating the lithographic imaging contour corresponding to the placement of additional graphics in the original mask pattern, as provided in an embodiment of this application. Figure 7d In this application, additional graphics 707 are placed at the target vertex in the end region, which is equivalent to pre-implementing a certain degree of OPC optimization.

[0060] Figure 7e This is a schematic diagram showing the lithographic imaging contour corresponding to the additional graphics provided for embodiments of this application after OPC correction. Figure 7e In the middle, additional graphics follow Figure 7c After OPC optimization, the position of the target vertex 708 changes synchronously.

[0061] To ensure that the additional pattern moves synchronously with the target vertex during optical proximity correction and to guarantee the consistency and accuracy of imaging deviation compensation, in one or more embodiments of this application, the target mask pattern can be generated by combining iterative correction and associative binding, as follows: This application first sets the target vertex's marking information in the original mask pattern, so that the target vertex and the additional graphics are associated and bound through the marking information. Then, for each round of mask correction, the mask pattern after the previous round of mask correction is used as the current mask pattern. Next, the current mask pattern and the additional graphics corresponding to the target vertex's marking information are input into the optical proximity effect correction model to obtain the correction amount of the current mask pattern. Then, the current mask pattern and the additional graphics are updated according to the correction amount to obtain the mask pattern after the current round of mask correction. Finally, after obtaining the mask pattern after the current round of mask correction, it is determined whether a preset termination condition is met. If not, the next round of mask correction is executed; if so, the mask pattern after the current round of mask correction is used as the target mask pattern.

[0062] Figure 8a A schematic diagram of the target vertices and additional graphics provided in the embodiments of this application.

[0063] Figure 8b A schematic diagram showing the movement of additional graphics as the marked target vertex is provided for embodiments of this application.

[0064] like Figures 8a to 8b As shown, the target vertex is marked as 801, the process vertex generated by the interruption operation is 802, and the additional pattern is 803. The process vertex generated by the interruption operation has been excluded and is not involved in the association binding of the additional pattern. Only the marked target vertex is associated with the additional pattern. Therefore, during the OPC correction process, when the target vertex moves, the additional pattern bound to it will move synchronously, avoiding misalignment between the additional pattern and the target vertex and ensuring the stability of the additional pattern for lithographic imaging compensation in the end region.

[0065] Based on a mask layout optimization method, this application also provides specific embodiments of a mask layout optimization apparatus.

[0066] like Figure 9 As shown, a mask layout optimization device 900 provided in this application embodiment includes an end recognition module 901, a placement parameter module 902, a pre-placement module 903, a parameter adjustment module 904, and a target module 905.

[0067] End-point recognition module 901 is used to identify target vertices in the end region of the graphic in the original mask layout; The placement parameter module 902 is used to determine the placement parameters of the additional graphic to be placed, the placement parameters including the graphic size of the additional graphic and its relative position to the target vertex; The pre-placement module 903 is used to perform mask manufacturing rule detection on the mask layout when the additional graphics are placed according to the placement parameters; The parameter adjustment module 904 is used to adjust the placement parameters and perform mask manufacturing rule detection on the adjusted mask pattern when the detection fails, until the detection passes. The target module 905 is used to obtain a target mask pattern based on the original mask pattern and the additional pattern corresponding to the placement parameters when the detection passes.

[0068] In some embodiments, the target module is specifically used to associate and bind the additional graphic with the target vertex according to the placement parameters when the detection passes, so that the additional graphic moves synchronously with the movement of the target vertex during the optical proximity effect correction process; and to import the bound additional graphic and the original mask pattern into the optical proximity effect correction model for iterative mask correction.

[0069] In some embodiments, the target module described above can also be used to set the marker information of the target vertex in the original mask pattern, so that the target vertex and the additional graphic are associated and bound through the marker information; for each round of mask correction iteration, the mask pattern after the mask correction of the previous round of iteration is used as the current mask pattern; for each round of mask correction iteration, the current mask pattern and the additional graphic corresponding to the marker information of the target vertex are input into the optical proximity effect correction model to obtain the correction amount of the current mask pattern; for each round of mask correction iteration, after updating the current mask pattern and the additional graphic according to the correction amount to obtain the mask pattern after the mask correction of the current round of iteration, it is determined whether a preset termination condition is met; if not, the next round of mask correction iteration is executed; if so, the mask pattern after the mask correction of the current round of iteration is used as the target mask pattern.

[0070] In some embodiments, the additional graphic is a rectangle; the graphic size includes the horizontal and vertical side lengths of the additional graphic, and the relative position includes the horizontal and vertical offsets between the center point of the additional graphic and the target vertex.

[0071] In some embodiments, the parameter adjustment module is specifically used to adjust at least one of the horizontal side length, the vertical side length, the horizontal offset, and the vertical offset.

[0072] In some embodiments, the above-described end-point recognition module is specifically used to identify the native vertices of the original mask layout; and to filter out the native vertices that satisfy the length and shape conditions corresponding to the end region as the target vertices.

[0073] In some embodiments, the above-described end-point identification module can also be used to obtain the lengths of the two adjacent edges connected to each native vertex; if the lengths of both adjacent edges are less than or greater than a preset length threshold, then the native vertex does not satisfy the length condition; if only one of the two adjacent edges has a length less than the preset length threshold, then the native vertex satisfies the length condition; if the native vertex satisfies the length condition, it is determined whether the graphic to which the native vertex belongs satisfies a preset shape condition; if yes, then the native vertex is taken as the target vertex; if no, then the native vertex does not satisfy the shape condition.

[0074] Based on a mask layout optimization method, this application also provides a specific embodiment of a mask layout optimization device.

[0075] Figure 10 This illustration shows a schematic diagram of the hardware structure of a mask layout optimization device provided in an embodiment of this application.

[0076] The mask layout optimization device may include a processor 1001 and a memory 1002 storing computer program instructions.

[0077] Specifically, the processor 901 may include a central processing unit (CPU), an application-specific integrated circuit (ASIC), or one or more integrated circuits that can be configured to implement the embodiments of this application.

[0078] Memory 1002 may include mass storage for data or instructions. For example, and not limitingly, memory 1002 may include a hard disk drive (HDD), floppy disk drive, flash memory, optical disk, magneto-optical disk, magnetic tape, or Universal Serial Bus (USB) drive, or a combination of two or more of these. Where appropriate, memory 1002 may include removable or non-removable (or fixed) media. Where appropriate, memory 1002 may be internal or external to the integrated gateway disaster recovery device. In a particular embodiment, memory 1002 is non-volatile solid-state memory.

[0079] The processor 1001 reads and executes computer program instructions stored in the memory 1002 to implement any of the mask layout optimization methods in the above embodiments.

[0080] In one example, the electronic device may also include a communication interface 1003 and a bus 1010. Wherein, as... Figure 9 As shown, the processor 1001, memory 1002, and communication interface 1003 are connected through bus 1010 and complete communication with each other.

[0081] The communication interface 1003 is mainly used to realize communication between various modules, devices, units and / or equipment in the embodiments of this application.

[0082] Bus 1010 includes hardware, software, or both, that couples the components of the electronic device together. For example, and not limitingly, the bus may include an Accelerated Graphics Port (AGP) or other graphics bus, an Enhanced Industry Standard Architecture (EISA) bus, a Front Side Bus (FSB), HyperTransport (HT) interconnect, an Industry Standard Architecture (ISA) bus, an Infinite Bandwidth Interconnect, a Low Pin Count (LPC) bus, a memory bus, a Microchannel Architecture (MCA) bus, a Peripheral Component Interconnect (PCI) bus, a PCI-Express (PCI-X) bus, a Serial Advanced Technology Attachment (SATA) bus, a Video Electronics Standards Association Local (VLB) bus, or other suitable buses, or combinations of two or more of these. Where appropriate, bus 1010 may include one or more buses. Although specific buses are described and illustrated in embodiments of this application, this application contemplates any suitable bus or interconnect.

[0083] Furthermore, in conjunction with the mask layout optimization methods in the above embodiments, this application embodiment can provide a computer storage medium for implementation. The computer storage medium stores computer program instructions; when these computer program instructions are executed by a processor, they implement any of the mask layout optimization methods in the above embodiments.

[0084] In addition, in conjunction with the mask layout optimization method in the above embodiments, this application embodiment can provide a computer program product for implementation. When the instructions in the computer program product are executed by the processor of an electronic device, the electronic device performs a mask layout optimization method as provided in any aspect of the above embodiments of this application.

[0085] It should be clarified that this application is not limited to the specific configurations and processes described above and shown in the figures. For the sake of brevity, detailed descriptions of known methods are omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method process of this application is not limited to the specific steps described and shown. Those skilled in the art can make various changes, modifications, and additions, or change the order of steps, after understanding the spirit of this application.

[0086] The functional blocks shown in the above-described structural diagram can be implemented as hardware, software, firmware, or a combination thereof. When implemented in hardware, they can be, for example, electronic circuits, application-specific integrated circuits (ASICs), appropriate firmware, plug-ins, function cards, etc. When implemented in software, the elements of this application are programs or code segments used to perform the required tasks. Programs or code segments can be stored on a machine-readable medium or transmitted over a transmission medium or communication link via data signals carried on a carrier wave. "Machine-readable medium" can include any medium capable of storing or transmitting information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, fiber optic media, radio frequency (RF) links, etc. Code segments can be downloaded via computer networks such as the Internet, intranets, etc.

[0087] It should also be noted that the exemplary embodiments mentioned in this application describe methods or systems based on a series of steps or apparatus. However, this application is not limited to the order of the above steps; that is, the steps can be performed in the order mentioned in the embodiments, or in a different order, or several steps can be performed simultaneously.

[0088] The aspects of this disclosure have been described above with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It should be understood that each block in the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that these instructions, executable via the processor of the computer or other programmable data processing apparatus, enable the implementation of the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams. Such a processor can be, but is not limited to, a general-purpose processor, a special-purpose processor, a special application processor, or a field-programmable logic circuit. It is also understood that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can also be implemented by special-purpose hardware performing the specified functions or actions, or can be implemented by a combination of special-purpose hardware and computer instructions.

[0089] The above description is merely a specific implementation of this application. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, modules, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here. It should be understood that the protection scope of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the protection scope of this application.

Claims

1. A mask layout optimization method, characterized in that, include: Identify target vertices in the end regions of the graphic in the original mask layout; Determine the placement parameters for the additional graphic to be placed, the placement parameters including the graphic size of the additional graphic and its relative position to the target vertex; Perform mask manufacturing rule detection on the mask layout when the additional graphics are placed according to the placement parameters; If the test fails, adjust the placement parameters and perform mask manufacturing rule testing on the adjusted mask layout until the test passes. The target mask pattern is obtained based on the original mask pattern and the additional graphic corresponding to the placement parameters when the detection passes.

2. The method as described in claim 1, characterized in that, Based on the original mask layout and the additional graphic corresponding to the placement parameters when the detection passes, a target mask layout is obtained, including: According to the placement parameters when the detection is passed, the additional graphic is associated and bound to the target vertex, so that the additional graphic moves synchronously with the target vertex during the optical proximity effect correction process; The bound additional graphic and the original mask pattern are imported into the optical proximity effect correction model for iterative mask correction.

3. The method as described in claim 2, characterized in that, Associating and binding the additional graphics with the target vertex includes: In the original mask layout, mark information for the target vertices is set so that the target vertices are associated and bound to the additional graphics through the mark information; The bound additional graphic and the original mask pattern are imported into the optical proximity effect correction model for iterative mask correction until a preset termination condition is met, resulting in the target mask pattern, including: For each iteration of mask correction, the mask layout after the mask correction in the previous iteration is used as the current mask layout; For each iteration of mask correction, the additional graphics corresponding to the current mask layout and the marker information of the target vertex are input into the optical proximity effect correction model to obtain the correction amount of the current mask layout; For each round of mask correction, after updating the current mask layout and the additional graphics according to the correction amount to obtain the mask layout after the round of mask correction, it is determined whether the preset termination condition is met. If not, proceed with the next round of mask correction. If so, the mask layout after the mask correction in this round of iterations shall be used as the target mask layout.

4. The method as described in claim 1, characterized in that, The additional graphic is a rectangle; the graphic size includes the horizontal and vertical side lengths of the additional graphic, and the relative position includes the horizontal and vertical offsets between the center point of the additional graphic and the target vertex.

5. The method as described in claim 4, characterized in that, Adjusting the placement parameters includes: Adjust at least one of the horizontal side length, the vertical side length, the horizontal offset, and the vertical offset.

6. The method as described in claim 1, characterized in that, Identify target vertices in the end regions of the graphic in the original mask layout, including: Identify the native vertices of the original mask layout; The original vertices that satisfy the length and shape conditions corresponding to the end region are selected as the target vertices.

7. The method as described in claim 6, characterized in that, Selecting native vertices that satisfy the length and shape conditions corresponding to the end region as target vertices includes: For each native vertex, obtain the lengths of the two adjacent edges connected to that native vertex; If the lengths of the two adjacent sides are both less than or both greater than the preset length threshold, then the original vertex does not satisfy the length condition. If only one of the two adjacent edges has a length less than the preset length threshold, then the original vertex satisfies the length condition. If the original vertex meets the length condition, determine whether the graph to which the original vertex belongs meets the preset shape condition; if yes, then the original vertex is taken as the target vertex; if no, then the original vertex does not meet the shape condition.

8. A computer device, characterized in that, The computer device includes a memory and a program or instructions stored in the memory and executable on a processor, wherein the program or instructions, when executed by the processor, implement the mask layout optimization method as described in any one of claims 1-7.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a program or instructions that, when executed by a processor, implement the mask layout optimization method as described in any one of claims 1-7.

10. A computer program product, characterized in that, When the instructions in the computer program product are executed by the processor of the electronic device, the electronic device performs the mask layout optimization method as described in any one of claims 1-7.

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