Display panel and method of manufacturing the same

Abstract

The present application relates to a display panel and a manufacturing method thereof, and a display panel according to one embodiment of the present application includes: a substrate having a plurality of pixels disposed thereon, each of the plurality of pixels having a first pattern area and a second pattern area surrounding the first pattern area; an insulating layer disposed on the substrate and including a first recessed pattern disposed in the first pattern area; and a pair of light emitting elements disposed on the first recessed pattern of the insulating layer, wherein the first recessed pattern can have a length in a first direction and a length in a second direction different from the first direction, and respective light emitting areas of the pair of light emitting elements can be offset in different directions with respect to an extension line in the first direction or the second direction from a center of the first recessed pattern.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2024-0194284, filed on December 23, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] This application relates to a display panel and a method for manufacturing the same, and more specifically, to a display panel and a method for manufacturing the same that can improve the productivity of pairs of light-emitting elements (e.g., micro LEDs) arranged in different directions and prevent defects (or spots) caused by defective light-emitting elements from becoming visible. Background Technology

[0003] With the advent of the information age, the field of display devices for visually displaying electrical information signals is rapidly developing. Therefore, research is underway to improve aspects including thinning, weight reduction, and low power consumption in various display devices.

[0004] Specific examples of display devices may include liquid crystal display (LCD) devices, light-emitting display (LED) devices, quantum dot display devices, etc.

[0005] Among these display devices, light-emitting display devices may include organic light-emitting diode (OLED) display devices or micro light-emitting diode (micro LED) display devices, wherein organic light-emitting diode (OLED) display devices include organic materials as light-emitting layers, and micro light-emitting diode (micro LED) display devices include inorganic materials as light-emitting layers.

[0006] Here, the micro-LED display device uses an inorganic material resistant to moisture and oxygen as its light-emitting layer, thus being less affected by external environmental factors, thereby ensuring high reliability and providing a longer lifespan compared to OLED display devices. Furthermore, the micro-LED display device has the advantage of enabling flexible display devices while having a thinner structure than OLED display devices.

[0007] Micro-LED transfer technology is a process that transfers micro-LED chips (light-emitting element chips) grown on a growth substrate onto a panel substrate. As micro-LED chips become smaller and smaller, research is underway on technologies for transferring micro-LED chips onto panel substrates with high precision. Summary of the Invention

[0008] A display panel including micro light-emitting diodes (micro LEDs) may include one or more sub-pixel units in each pixel. The one or more sub-pixel units may include a first light-emitting element (first sub-pixel) and a second light-emitting element (second sub-pixel) to prepare (or prepare) for defective chips during the process of properly transferring the respective light-emitting elements onto the substrate of the panel.

[0009] Here, when a defective light-emitting element appears in each sub-pixel unit, the defect may become visible due to the distance difference between the first and second light-emitting elements.

[0010] In addition, depending on the uniformity of the adhesive layer, problems may arise such as non-transfer defects where the light-emitting element fails to transfer to the panel or over-transfer defects where the light-emitting element is over-transferred to the panel.

[0011] Therefore, embodiments of this application are intended to improve the productivity of paired light-emitting elements (e.g., micro LEDs) arranged in different directions, while preventing defects caused by defective light-emitting elements from becoming visible.

[0012] The problems to be solved in this application are not limited to the above-mentioned technical problems, and those skilled in the art to which the technical concept of this application pertains can clearly understand other unmentioned technical problems from the following description.

[0013] According to one aspect of the present invention, a display panel is provided, comprising: a substrate having a plurality of pixels thereon, each of the plurality of pixels having a first patterned area and a second patterned area surrounding the first patterned area; an insulating layer disposed on the substrate and including a first recessed (or intaglio) pattern disposed in the first patterned area; and a pair of light-emitting elements disposed on the first recessed pattern of the insulating layer, wherein the first recessed pattern may have a length in a first direction and a length in a second direction different from the first direction, and the respective light-emitting areas of the pair of light-emitting elements may be offset in different directions relative to (or about) an extension line extending from the center of the first recessed pattern in the first direction or the second direction.

[0014] According to another aspect of the present invention, a method for manufacturing a display panel is provided, comprising: The first step of preparing a substrate having an insulating layer including a first recessed pattern thereon; The second step is to form a first adhesive layer on the first recessed pattern; The third step is to prepare a donor on which a first light-emitting element and a second light-emitting element are disposed; The fourth step of bonding the donor to the substrate such that the first light-emitting element and the second light-emitting element are bonded to the first recessed pattern; and The fifth step is to detach the donor from the substrate. The first recessed pattern has a length in a first direction and a length in a second direction different from the first direction, and The respective light-emitting areas of the first light-emitting element and the second light-emitting element are offset in different directions relative to the extension line from the center of the first recessed pattern in the first direction or the second direction. Attached Figure Description

[0015] The above and other objects, features, and advantages of the present invention will become more apparent to those skilled in the art from the detailed description of exemplary embodiments of the invention with reference to the accompanying drawings, in which: Figure 1 This is a schematic plan view of a display panel according to one embodiment of the present application; Figure 2 This is a schematic plan view of pixels according to an embodiment of this application; Figure 3 This is a plan view of a portion of the display panel according to the first embodiment of this application; Figure 4 For along Figure 3 A sectional view taken by line I-I'; Figure 5 For along Figure 3 A sectional view taken from line II-II'; Figure 6 This is a first variation example of a display panel according to the first embodiment of this application; Figure 7 This is a second variation example of a display panel according to the first embodiment of this application; Figure 8 This is a plan view of a portion of the display panel according to the second embodiment of this application; Figure 9 For along Figure 8 A sectional view taken from line III-III'; Figure 10 This is a first variant example of a display panel according to the second embodiment of this application; Figure 11A A plan view of a portion of a display panel according to a third embodiment of this application; Figure 11B To show Figure 11A A plan view comparing the first recessed pattern and the second recessed pattern; Figure 12 For along Figure 11A A sectional view taken by line IV-IV'; Figure 13 A plan view of a portion of a display panel according to the fourth embodiment of this application; Figure 14 This is a first variant example of a display panel according to the fourth embodiment of this application; Figure 15 A plan view of a portion of a display panel according to the fifth embodiment of this application; Figure 16 This is a first variant example of a display panel according to the fifth embodiment of this application; Figure 17 A plan view of a portion of a display panel according to the sixth embodiment of this application; Figures 18A to 18E A process plan view according to the first embodiment of this application; and Figures 19A to 19F This is a process cross-sectional view according to the first embodiment of this application. Detailed Implementation

[0016] The advantages and features of this application, as well as the methods for implementing this application, should become clear from the embodiments described in detail below with reference to the accompanying drawings. However, this application is not limited to the embodiments described below and can be implemented using various different variations. The embodiments are provided only to allow those skilled in the art to fully understand the scope of this application, and this application is defined only by the scope of the claims.

[0017] The shapes, sizes, ratios, angles, quantities, etc., disclosed in the accompanying drawings for describing embodiments of this application are merely illustrative and are not limited to the content shown in this application. Furthermore, in describing this application, detailed descriptions of well-known technologies will be omitted where it is determined that they may unnecessarily obscure the essence of this application.

[0018] Terms such as “including (or comprising),” “having,” and “consisting of” as used herein are intended to allow for the addition of other elements, unless these terms are used in conjunction with the term “only.” Unless otherwise expressly stated, any reference to the singular may include the plural.

[0019] The component is interpreted as including a normal tolerance range, even if such a margin is not explicitly stated.

[0020] When using terms such as “on,” “above,” “below,” and “near” to describe the positional relationship between two parts, one or more parts may be located between the two parts, unless the term is used in conjunction with the terms “tight” or “direct (or positive).”

[0021] When a device or layer is referred to as being “on” another device or layer, it includes situations where one device or layer is located directly on another device or layer, or where another device or layer is inserted between the two devices or layers.

[0022] Furthermore, although the terms "first," "second," etc., may be used herein to describe various components, the components are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, within the scope of this application, the first component described below may be the second component.

[0023] Throughout the application, the same (or similar) reference numerals denote the same (or similar) elements.

[0024] The dimensions and thicknesses of each component shown in the accompanying drawings are for ease of description and are not necessarily limited to the dimensions and thicknesses of the components shown in this application.

[0025] Features of the various embodiments of this application can be combined with each other in part or in whole. The embodiments can be technically related and operate in various ways, and can be performed independently or in conjunction with each other.

[0026] As used herein, the term "device" can include display devices such as liquid crystal modules (LCMs) and organic light-emitting display modules (OLED modules) that include a display panel and a driving portion for driving the display panel. Furthermore, display devices can include notebook computers, televisions, computer monitors, vehicle equipment, automotive equipment, equipment including one or more components or portions for a vehicle, and assemblies of electronic devices (or assemblies or assemblies of equipment), including mobile electronic devices such as smartphones and electronic boards, which are complete products or end products including LCMs, OLED modules, etc.

[0027] Therefore, the display devices used in this article may include the display devices themselves, such as LCMs and OLED modules, as well as application products including LCMs and OLED modules or setting devices for end consumers.

[0028] Furthermore, in some embodiments, an LCM or OLED module including a display panel, driving components, etc., may be referred to as a "display device," and an electronic device that includes an LCM or OLED module as a complete product may be referred to as a "package." For example, a display device may include a liquid crystal display (LCD) or OLED display panel, and a source printed circuit board (PCB) serving as a controller for driving the display panel. A package may also include a package PCB, which is a package controller for controlling the entire package and electrically connected to the source PCB.

[0029] The display panels used in the embodiments of this application may include all types of display panels, such as LCD panels, organic light-emitting diode (OLED) display panels, and electroluminescent display panels. However, the embodiments of this application are not limited thereto.

[0030] As will be fully understood by those skilled in the art, the features of the various embodiments of this application may be coupled or combined with each other in part or in whole, and may operate on and be technically driven in various ways. Embodiments of this application may be implemented independently of each other, or may be implemented together in a related relationship.

[0031] In the following description, various embodiments of the invention will be described in detail with reference to the accompanying drawings. For ease of description, the proportions of the components shown in the drawings may differ from the actual proportions, and therefore, the invention is not limited to the proportions shown in the drawings.

[0032] Figure 1 This is a schematic plan view of a display panel according to one embodiment of the present application, and Figure 2 This is a schematic plan view of pixels according to an embodiment of this application.

[0033] Reference Figure 1 and Figure 2 The horizontal direction X and vertical direction Y of the display panel 1 can be the longitudinal direction and width direction of the display panel 1, respectively. Furthermore, the horizontal direction X and vertical direction Y of the display panel 1 can also be represented as the row direction and column direction, respectively. The thickness direction Z can refer to the direction perpendicular to the plane having the horizontal direction X and vertical direction Y of the display panel 1. Additionally, the display panel 1 can have a cross-section in the thickness direction Z.

[0034] Reference Figure 1 and Figure 2 According to one embodiment of this application, the display panel 1 may include: a substrate 10 (see...) Figure 4 ), which includes a plurality of pixels P (specifically, a plurality of pixels P are disposed thereon), each of the plurality of pixels P including a first pattern region IA1 and a second pattern region IA2 surrounding the first pattern region IA1; insulating layer 40 (see Figure 4 ), which is disposed on substrate 10 and includes a first recessed pattern IP1 disposed in the first pattern area IA1 (see Figure 3 ); and a pair (e.g., a pair, but not limited to) of light-emitting elements LD, disposed on a first recessed pattern IP1 of insulating layer 40. The first recessed pattern IP1 has a length in a first direction (e.g., the longitudinal direction of the display panel) and a length in a second direction different from the first direction (e.g., the width direction of the display panel), and the light-emitting areas E of the pair of light-emitting elements LD (see Figure 4It can be offset relative to the extension line from the center of the first recessed pattern IP1 in a first direction or a second direction in a different direction (e.g., in the opposite direction).

[0035] Display panel 1 can display information, video, and / or images provided to the user. For example, display panel 1 may include a display area AA and a non-display area NA. For example, substrate 10 (see...) Figure 4 This can include the display area AA and the non-display area NA.

[0036] The substrate 10 can be formed of an insulating material. For example, the substrate 10 can be formed of glass, resin, or the like. Alternatively, the substrate 10 can be formed of a flexible material. For example, the substrate 10 can be formed of a flexible plastic material such as polyimide (PI). However, the embodiments of this application are not limited to these.

[0037] The display area AA can be an area for displaying an image. The display area AA of the substrate 10 or the display panel 1 can be configured into various shapes depending on the design of the display device. For example, the display area AA can be configured as a rectangular shape with four rounded corners, but the embodiments of this application are not limited to this. As another example, the display area AA can be configured as a rectangle, a circle, etc. with four right-angled corners, but the embodiments of this application are not limited to this.

[0038] The display area AA may include multiple pixels P. Each of the multiple pixels P may consist of multiple sub-pixel units SP (SP1, SP2, and SP3). Multiple light-emitting elements LD (LD1-1, LD1-2, LD2-1, LD2-2 or LD3-1 and LD3-2) may be disposed in each of the multiple sub-pixel units SP. The multiple light-emitting elements LD may be configured differently depending on the type of display device. For example, when the display device is an inorganic light-emitting display device, the light-emitting elements may be light-emitting diodes (LEDs), micro light-emitting diodes (micro-LEDs), or miniature light-emitting diodes (miniature LEDs), but the embodiments of this application are not limited to these.

[0039] The non-display area NA can be an area where no image is displayed. Various lines, circuits, etc., used to drive the multiple pixels P of the display area AA can be set in the non-display area NA. For example, various lines and driving circuits can be installed in the non-display area NA, and pad portions connected to integrated circuits, printed circuits, etc. can be provided, but the embodiments of this application are not limited thereto.

[0040] For example, the driving circuit may be a data driving circuit and / or a gate driving circuit, but embodiments of this application are not limited thereto. Lines supplying control signals for controlling the driving circuit can be disposed on the display panel. For example, the control signals may include various timing signals such as clock signals, input data enable signals, and synchronization signals, but embodiments of this application are not limited thereto. Control signals can be received through pad portions. For example, link lines for transmitting signals can be disposed in the non-display area NA. For example, driving components such as flexible circuit boards and printed circuit boards can be connected to the pad portions.

[0041] Each of the plurality of pixels P may include one or more sub-pixel units and may be included in the display area AA. The plurality of pixels P may be arranged in a matrix to form multiple rows and multiple columns, but the display panel of this application is not limited thereto.

[0042] Each of the plurality of pixels P may include a first sub-pixel unit SP1, a second sub-pixel unit SP2, and a third sub-pixel unit SP3. The plurality of sub-pixel units SP (SP1, SP2, and SP3) may be arranged in various ways. For example, the first to third sub-pixel units SP1, SP2, and SP3 may be arranged side-by-side in the X-axis direction. The arrangement of the sub-pixel units SP will be specifically described in the following embodiments. However, the number of sub-pixel units SP constituting a pixel P is exemplary, and the embodiments of this application are not limited thereto.

[0043] The first to third sub-pixel units SP1, SP2, and SP3 can emit light of different colors. For example, one of the first sub-pixel unit SP1, the second sub-pixel unit SP2, and the third sub-pixel unit SP3 can be a red sub-pixel unit, another can be a green sub-pixel unit, and the remaining one can be a blue sub-pixel unit. The types of the plurality of sub-pixel units are exemplary, and the embodiments of this application are not limited thereto.

[0044] Each of the first to third sub-pixel units SP1, SP2, and SP3 may include one or more light-emitting elements (LDs). The light-emitting elements may constitute a sub-pixel of each sub-pixel unit. For example, the first sub-pixel unit SP1 may include a pair of light-emitting elements, namely 1-1 light-emitting element LD1-1 and 1-2 light-emitting element LD1-2; the second sub-pixel unit SP2 may include a pair of light-emitting elements, namely 2-1 light-emitting element LD2-1 and 2-2 light-emitting element LD2-2; and the third sub-pixel unit SP3 may include a pair of light-emitting elements, namely 3-1 light-emitting element LD3-1 and 3-2 light-emitting element LD3-2. However, the number of light-emitting elements included in a sub-pixel unit is exemplary, and embodiments of this application are not limited thereto.

[0045] Multiple signal lines can be disposed in the region between the plurality of sub-pixel units SP. The multiple signal lines can extend along the column direction between the plurality of sub-pixel units SP. The multiple signal lines can be derived from the pixel driving circuit PD (see...). Figure 4 The output pixel voltage is transmitted to the lines of the plurality of sub-pixel units SP.

[0046] For example, the multiple signal lines can be electrically connected to multiple pixel driving circuits PD and multiple sub-pixel units SP, such as the first pixel electrode 55a and the second pixel electrode 55b (see...). Figure 4 The pixel electrode is the first pixel electrode 55a and the second pixel electrode 55b of the plurality of sub-pixel units SP. The pixel voltage output from the pixel driving circuit PD can be transmitted through the plurality of signal lines to the first pixel electrode 55a and the second pixel electrode 55b of the plurality of sub-pixel units SP. For example, the first pixel electrode 55a and the second pixel electrode 55b can be the first electrodes 93a and 93b electrically connected to the light-emitting element LD (see [link to relevant documentation]). Figure 4 The pixels are electrodes of the light-emitting element LD. Therefore, the pixel voltage transmitted through the signal line can be transmitted to the first electrodes 93a and 93b of the light-emitting element LD via the first pixel electrode 55a and the second pixel electrode 55b (see [reference]). Figure 4 ).

[0047] Therefore, the structure of the display panel 1 can be simplified by using a pixel driving circuit that integrates multiple pixel circuits (instead of forming multiple transistors and storage capacitors in each of the multiple sub-pixel units SP). Furthermore, since the circuitry in each of the multiple sub-pixel units SP is integrated into a single pixel driving circuit PD, high-efficiency and low-power operation is possible.

[0048] According to one embodiment, each of the plurality of pixels P may include one or more first pattern regions IA1 (IA1-1, IA1-2, and IA1-3) and a second pattern region IA2 surrounding the first pattern region IA1. The first pattern region IA1 and the second pattern region IA2 may be formed on the insulating layer 40 (see [link to documentation]). Figure 4 The recessed pattern (in other words, the recessed pattern) in the insulating layer 40, 140, or 240. Here, the recessed pattern can be formed by removing a certain thickness from the upper surface of the insulating layer 40, 140, or 240.

[0049] According to one embodiment, each first pattern region IA1 may correspond to each sub-pixel unit SP. That is, according to one embodiment, each first pattern region IA1 may include each sub-pixel unit SP. When multiple sub-pixel units SP are provided, the one or more first pattern regions IA1 may also be provided as multiple. For example, the one or more first pattern regions IA1 may include pattern region IA1-1 (1-1), pattern region IA1-2 (1-2), and pattern region IA1-3 (1-3).

[0050] Each first pattern region IA1 may contain one sub-pixel unit SP. A first pattern region IA1 may include a pair of light-emitting elements (e.g., a pair of light-emitting elements, but not limited thereto). For example, pattern region IA1-1 may include light-emitting elements LD1-1 and LD1-2 of the first sub-pixel unit SP1. For example, pattern region IA1-2 may include light-emitting elements LD2-1 and LD2-2 of the second sub-pixel unit SP2. For example, pattern region IA1-3 may include light-emitting elements LD3-1 and LD3-2 of the third sub-pixel unit SP3.

[0051] The second pattern area IA2 may include one or more second recessed patterns IP2 (see...). Figure 3 The one or more second recessed patterns IP2 may be configured to correspond at least to each of the plurality of sub-pixel units SP. For example, when three sub-pixel units are included (e.g., first to third sub-pixel units SP1, SP2 and SP3), at least three second recessed patterns IP2 may be configured to correspond to each of the three sub-pixel units (e.g., first to third sub-pixel units SP1, SP2 and SP3).

[0052] The second recessed pattern IP2 can be used as a space where the light-emitting elements LD are temporarily transferred during the imprinting process of the paired light-emitting elements LD. Therefore, the second recessed pattern IP2 can be disposed adjacent to the first pattern area IA1 in which the light-emitting elements LD are disposed, while maintaining a predetermined distance from it.

[0053] The second patterned area IA2 may also include one or more first dummy patterns DP1 and one or more second dummy patterns DP2. The first dummy patterns DP1 and the second dummy patterns DP2 may be dummy areas where the light-emitting element LD is not temporarily placed during the imprinting process. Therefore, the first dummy patterns DP1 and the second dummy patterns DP2 can improve the design freedom of the light-emitting element LD and can improve the uniformity of the adhesive layer in contact with the light-emitting element LD.

[0054] In the following embodiments, the first pattern area IA1 and the second pattern area IA2 will be described in detail.

[0055] Figure 3 This is a plan view of a portion of a display panel according to a first embodiment of this application. Figure 4 For along Figure 3 A cross-sectional view taken by line I-I'. Figure 5 For along Figure 3 The sectional view taken from line II-II'.

[0056] Reference Figures 3 to 5 The display panel according to the first embodiment of this application may include a plurality of pixels P located on a substrate 10. The display panel according to the first embodiment of this application may include a first recessed pattern IP1 (IP1-1, IP1-2, or IP1-3) in a first pattern region IA1 of each of the plurality of pixels P, and a plurality of second recessed patterns IP2 in a second pattern region IA2 surrounding the first pattern region IA1. Pairs of light-emitting elements LD (LD1-1 and LD1-2, LD2-1 and LD2-2, or LD3-1 and LD3-2) may be disposed on each of the first recessed patterns IP1.

[0057] The plurality of pixels P can be arranged in a matrix to form multiple rows and multiple columns. However, this application is not limited thereto.

[0058] The distance between adjacent pixels P can form a first pitch (or spacing) PP. The first pitch PP can be measured as the distance between the centers of the light-emitting elements LD at corresponding positions of two adjacent pixels P in the vertical or width direction. However, the measurement standard of the first pitch PP in this application is not limited to this. For example, the first pitch PP can also be measured as the distance between the centers of two adjacent pixels P in the vertical or width direction (in other words, the shortest distance).

[0059] Each pixel P may contain multiple sub-pixel units SP (SP1, SP2, and SP3). The multiple sub-pixel units SP may include a first sub-pixel unit SP1, a second sub-pixel unit SP2, and a third sub-pixel unit SP3.

[0060] The plurality of sub-pixel units SP can be arranged in various ways. According to the first embodiment, the plurality of sub-pixel units SP can be spaced apart from each other by a predetermined distance in the row direction. The second recessed pattern IP2 can be disposed between the plurality of spaced-apart sub-pixel units SP.

[0061] The distance between adjacent sub-pixel units SP can form a second pitch SPP. The second pitch SPP can be measured as the distance between the centers of adjacent sub-pixel units SP. The second pitch SPP can also be measured as the shortest distance between the centers of adjacent first recessed patterns IP1. However, in this application, the measurement standard for the second pitch SPP is not limited to these. For example, the second pitch SPP can also be measured as the distance between the leftmost edge of the first sub-pixel unit SP1 and the leftmost edge of the second sub-pixel unit SP2.

[0062] The first to third sub-pixel units SP1, SP2, and SP3 may each include a pair of light-emitting elements (LDs) (LD1-1 and LD1-2, LD2-1 and LD 2-2, or LD3-1 and LD3-2). Each pair of light-emitting elements (LDs) can constitute a sub-pixel. For example, the first sub-pixel unit SP1 may include 1-1 light-emitting element LD1-1 and 1-2 light-emitting element LD1-2, the second sub-pixel unit SP2 may include 2-1 light-emitting element LD2-1 and 2-2 light-emitting element LD 2-2, and the third sub-pixel unit SP3 may include 3-1 light-emitting element LD3-1 and 3-2 light-emitting element LD3-2.

[0063] When using micro-LEDs as light-emitting elements (LDs), multiple micro-LEDs can be formed on a wafer and transferred to the substrate 10 of the display panel 1 to manufacture the display panel 1. During the process of transferring multiple light-emitting elements (LDs) with micro-sized dimensions from the wafer (or die) to the substrate 10, various defects may occur.

[0064] For example, in some sub-pixels, transfer failures may occur where the light-emitting element (LD) is not transferred, or defects may occur where the LD is transferred out of its intended position due to misalignment. Furthermore, even if the transfer process proceeds normally, the transferred LD itself may be defective. Therefore, considering the potential defects that may occur during the transfer of multiple LDs, multiple LDs of the same type can be transferred to a single sub-pixel. Illumination tests can be performed on multiple LDs, and ultimately, only the single LD determined to be functioning correctly can be used.

[0065] In a pair of light-emitting elements (LDs), one can be a primary (or main) LD, and the other can be a redundant LD. The redundant LD can be a backup LD transferred in preparation for a defective LD. When the primary LD is defective, the redundant LD can be used as a replacement. Therefore, by transferring both the primary and redundant LDs to a single subpixel unit (SP), the degradation of display quality due to the failure of either the primary or redundant LD can be minimized. Since color expression within the subpixel unit is possible even when only one of the primary and redundant subpixels is driven, yield (or output) can be improved.

[0066] For example, 1-1 light-emitting element LD1-1, 2-1 light-emitting element LD2-1 and 3-1 light-emitting element LD3-1 can be used as main light-emitting elements (or main sub-pixels), and 1-2 light-emitting element LD1-2, 2-2 light-emitting element LD2-2 and 3-2 light-emitting element LD3-2 can be used as redundant light-emitting elements (or redundant sub-pixels).

[0067] The paired light-emitting elements (LDs) can be arranged in various ways. According to the first embodiment, the paired light-emitting elements (LDs) can be arranged side by side in the Y-axis direction.

[0068] The light-emitting areas of the paired light-emitting elements LD can be arranged (or oriented) in different directions. For example, when the first recessed pattern IP1 (IP1-1, IP1-2, or IP1-3) has a length in a first direction and a length in a second direction different from the first direction, the light-emitting areas of the paired light-emitting elements LD can be arranged to be offset relative to the extension line from the center of the first recessed pattern IP1 in the first or second direction in different directions (e.g., in opposite directions, but not limited thereto). The paired light-emitting elements LD according to the first embodiment can be arranged such that their light-emitting areas E face each other.

[0069] The light-emitting region E can be biased towards one side of the light-emitting element LD. The light-emitting region E of the light-emitting element LD can be biased towards the side where the active layers 96a and 96b are located. The active layers 96a and 96b of the light-emitting element LD can overlap with the first electrodes 93a and 93b of the light-emitting element LD, respectively. Therefore, the light-emitting region E according to this application can overlap with the first electrodes 93a and 93b of the light-emitting element LD.

[0070] In the display panel according to the first embodiment of this application, the light-emitting areas E of a pair of light-emitting elements LD can be arranged to face each other. When the pair of light-emitting elements LD are arranged side by side in the Y-axis direction, the light-emitting areas E of the pair of light-emitting elements LD can also be arranged adjacent to each other in the Y-axis direction. For example, the pair of light-emitting elements LD according to the first embodiment can be arranged such that their light-emitting areas E face each other, and can be vertically symmetrical with respect to (or about) any X-axis direction.

[0071] The display panel according to the first embodiment of this application can have uniform color wavelength dispersion. When the light-emitting regions E of the paired light-emitting elements LD are arranged adjacent to each other, color shift in the paired light-emitting elements LD can be significantly reduced. Therefore, the display panel of this application can have the effect of preventing defects in the embossed area units from becoming visible. Here, defects in the embossed area units can refer to color differences caused by various factors such as non-uniform color wavelength dispersion.

[0072] The paired light-emitting elements LD can be spaced apart by a first distance D1. The first distance D1 can be measured as the distance between the centers of the paired light-emitting elements (in other words, the shortest distance). However, the measurement standard of the first distance D1 in this application is not limited to this. For example, the first distance D1 can also be measured as the distance between the upper end of light-emitting element LD1-1 (1-1) and the upper end of light-emitting element LD1-2 (1-2).

[0073] According to this application, the first distance D1 of the display panel can be configured to be less than the binocular resolution based on the pixel distance of the viewing distance. The first distance D1 can be derived by calculating the minimum perceptible pixel interval at the viewing distance. Binocular resolution can also be referred to as binocular acuity, binocular resolution capability, etc. Binocular resolution can refer to the visual ability to accurately distinguish details when both eyes work together to identify objects. The binocular resolution of pixel distance can be measured as the angle between the nearest perceptible pixels on a vertical line, assuming that the pixels are located along the vertical line between the viewer and the screen.

[0074] For example, for a viewer with visual acuity of 1.0, the binocular resolution at pixel distance could be 1 / 60°. As another example, for a viewer with visual acuity of 2.0, the binocular resolution at pixel distance could be 1 / 120°.

[0075] The minimum perceptible pixel spacing α at the viewing distance can be calculated using binocular resolution (BR) and viewing distance (VD). Viewing distance VD refers to the vertical distance between the viewer and the screen. The minimum perceptible pixel spacing α at the viewing distance VD can be calculated using Equation 1 below. [Equation 1] α = 2 × VD × tan (radians ((BR) × (1 / 2))) .

[0076] For example, when the viewing distance is 3 m and the binocular resolution is 1 / 60° based on visual acuity of 1.0, the minimum perceptible pixel spacing α at the viewing distance is derived to be approximately 872.6646 by substituting VD = 3 and BR = 1 / 60 into Equation 1.

[0077] The minimum perceptible pixel spacing α at the viewing distance can determine the first pitch PP, and based on the determined first pitch PP, a first distance D1 can be determined, where the first distance D1 is the distance between a pair of light-emitting elements.

[0078] To ensure that the viewer cannot perceive the distance difference between pixels P, the first pitch PP can be configured to be less than the minimum perceptible pixel interval α at the viewing distance. For example, the first pitch PP can be configured to be less than 1 / 2 of the minimum perceptible pixel interval α at the viewing distance.

[0079] The first distance D1 between the paired light-emitting elements can be set to a value less than the first pitch PP. For example, the first distance D1 can be at most 1 / 2 of the first pitch PP. Alternatively, the first distance D1 can be less than or equal to 1 / 10 of the first pitch PP. However, the first distance D1 in the display panel of this application is not limited to this and can be set to a distance less than 1 / 10 of the first pitch PP, such as 1 / 11, 1 / 12, 1 / 13, ... or 1 / n of the first pitch PP (where n is a number greater than 10). The first distance D1 between the paired light-emitting elements can be set to position the first light-emitting element and the second light-emitting element as close to each other as possible.

[0080] In the display panel of this application, a two-step imprinting method (in other words, an imprinting method including a first imprinting process and a second imprinting process) can be used to transfer paired light-emitting elements (LDs), thereby allowing a first distance D1 to be formed to be less than the binocular resolution. The achieved first distance D1 can be set to be less than or equal to 1 / 2 of the first pitch PP, and preferably less than or equal to 1 / 10 of the first pitch PP. Alternatively, the first distance D1 can be set to be less than or equal to 1 / 2 of the first pitch PP and greater than or equal to 1 / 10 of the first pitch PP. Therefore, in the display panel of this application, even when defects occur consecutively in the subpixels of each subpixel unit, the viewer cannot perceive the flaws caused by the defects.

[0081] By employing a two-stage imprinting method, the productivity of paired light-emitting elements (LDs) set (or oriented) in different directions can be improved (restraining capacity reduction). In the second (or secondary) imprinting method, the distance (second distance D2) between each first recessed pattern IP1 (IP1-1, IP1-2, or IP1-3) and the second recessed pattern IP2 can be set to a predetermined distance to prevent cluster defects during the first imprinting process (or process).

[0082] Combination Figure 2 Reference Figure 3 According to the first embodiment of this application, the display panel can be located in the plurality of first pattern areas IA1-1, IA1-2 and IA1-3 (see... Figure 2 The pattern includes recessed pattern IP1-1 (1-1), recessed pattern IP1-2 (1-2), and recessed pattern IP1-3 (1-3), and can be found in the second pattern area IA2 (see...). Figure 2 The ) includes multiple second recessed patterns IP2.

[0083] The plurality of first recessed patterns IP1 may include recessed pattern IP1-1 (1-1), recessed pattern IP1-2 (1-2), and recessed pattern IP1-3 (1-3). Recessed patterns IP1-1, IP1-2, and IP1-3 may be spaced apart from each other, with a second recessed pattern IP2 interposed between them. The second recessed pattern IP2 may be located on one side of each of the recessed patterns IP1-1, IP1-2, and IP1-3 (1-1 to 1-3). (Refer to...) Figure 4 and Figure 5 The cross-sectional view is described in detail as an example of recessed pattern IP1-1 and second recessed pattern IP2.

[0084] Reference Figure 4 and Figure 5 According to one embodiment of this application, a display panel may include a plurality of insulating layers (e.g., first to sixth insulating layers 20, 30, 40, 50, 60, and 70) located on a substrate 10, a driving circuit including at least one transistor T located between the plurality of insulating layers (e.g., first to sixth insulating layers 20, 30, 40, 50, 60, and 70), adhesive layers (e.g., first and second adhesive layers 45 and 47), and a pair of light-emitting elements LD (LD1-1 and LD1-2). The plurality of insulating layers (e.g., first to sixth insulating layers 20, 30, 40, 50, 60, and 70) may sequentially include a first insulating layer 20, a second insulating layer 30, a third insulating layer 40, a fourth insulating layer 50, a fifth insulating layer 60, and a sixth insulating layer 70 located on the substrate 10.

[0085] The at least one transistor T may include a gate electrode 11, a semiconductor layer 21, an ohmic contact layer 23, a source electrode 31, and a drain electrode 33.

[0086] The gate electrode 11 can be disposed on the substrate 10. The gate electrode 11 can be formed on the same layer as the reflective layer 13 and the common power line 15 on the substrate 10. For example, the gate electrode 11 can be a single layer or multiple layers formed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or their alloys.

[0087] The semiconductor layer 21 may be disposed on the first insulating layer 20 to overlap with the gate electrode 11. For example, the semiconductor layer 21 may be formed of a semiconductor material composed of any one of amorphous silicon, polycrystalline silicon, oxide and organic materials, but this application is not limited thereto.

[0088] The ohmic contact layer 23 may be disposed on the semiconductor layer 21. The ohmic contact layer 23 is configured to form an ohmic contact between the semiconductor layer 21 and the source electrode 31 and the drain electrode 33, and may be omitted.

[0089] The source electrode 31 can be disposed on the ohmic contact layer 23, overlapping one side of the semiconductor layer 21. The drain electrode 33 can be disposed on the other side of the ohmic contact layer 23, spaced apart from the source electrode 31. The source electrode 31 and the drain electrode 33 can be formed together. For example, the source electrode 31 and the drain electrode 33 can be formed as a single layer of a metallic material such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), or alloys thereof, or as a multilayer structure using these materials.

[0090] The reflective layer 13 on the substrate 10 may be disposed below the light-emitting area of ​​at least each of the light-emitting elements LD1-1 and LD1-2. For example, the reflective layer 13 may overlap with both light-emitting elements LD1-1 and LD1-2 and may be formed as a single pattern. However, this application is not limited thereto.

[0091] A common power line 15 on substrate 10 can extend from the non-display area NA to the display area AA. The common power line 15 can supply pixel driving power from the pad portion of the non-display area NA to the paired light-emitting elements LD.

[0092] The first insulating layer 20 may cover the gate electrode 11, reflective layer 13, common power line 15, etc., formed on the substrate 10. The first insulating layer 20 may be formed at least over the entire display area AA. The first insulating layer 20 may refer to a commonly used gate insulating layer. For example, the first insulating layer 20 may be formed as a single layer or multiple layers of inorganic materials, and may include silicon oxide (SiO2).x Silicon nitride (SiN) x However, this application is not limited to these.

[0093] The second insulating layer 30 may cover the driving circuit including at least one transistor T on the first insulating layer 20. The second insulating layer 30 may be formed at least over the entire display area AA and may be in contact with the first insulating layer 20 in some areas. The second insulating layer 30 may refer to a commonly used interlayer insulating layer. For example, the second insulating layer 30 may be made of materials such as silicon oxide (SiO2). x ) or silicon nitride (SiN) x The second insulating layer 30 may be formed from an inorganic material, or from an organic material such as benzocyclobutene or photocurable acrylic. The second insulating layer 30 may be omitted. However, this application is not limited thereto.

[0094] The third insulating layer 40 may be disposed on the second insulating layer 30. The third insulating layer 40 may be formed at least over the entire display area AA. For example, the third insulating layer 40 may be formed of an organic material such as benzocyclobutene or a photocurable acrylic substance. However, this application is not limited thereto.

[0095] The third insulating layer 40 may include at least one first recessed pattern IP1 (IP1-1, IP1-2, or IP1-3) and at least one second recessed pattern IP2. The first and second recessed patterns IP1 and IP2 may be formed by partially removing a portion of the thickness of the third insulating layer 40 from its upper surface. The first and second recessed patterns IP1 and IP2 may be spaces in which multiple light-emitting elements (LDs) are disposed during the imprinting process (i.e., placement spaces). The term "placement space" does not necessarily refer to a space in which the light-emitting elements (LDs) are fixed. For example, a placement space may include a space where the light-emitting elements (LDs) are temporarily disposed and then separated during the imprinting process, as well as a space where the light-emitting elements (LDs) are transferred and fixed.

[0096] The first recessed pattern IP1 and the second recessed pattern IP2 can guide the position of the plurality of light-emitting elements LD during the transfer process of transferring the plurality of light-emitting elements LD to the display panel 1. During the transfer process of transferring the plurality of light-emitting elements LD, the plurality of light-emitting elements LD can be transferred onto the first recessed pattern IP1 and the second recessed pattern IP2.

[0097] For example, a pair of light-emitting elements LD1-1 and LD1-2 can be disposed on the 1-1 recessed pattern IP1-1, with a first adhesive layer 45 inserted between them. The 1-1 recessed pattern IP1-1 can have a predetermined area sufficient to accommodate the pair of light-emitting elements LD1-1 and LD1-2 spaced apart by a first distance D1. For example, when each light-emitting element LD is formed such that its length in the Y-axis direction is greater than its length in the X-axis direction, and the pair of light-emitting elements LD1-1 and LD1-2 are arranged side by side in the Y-axis direction, the 1-1 recessed pattern IP1-1 can be formed such that its length in the Y-axis direction is greater than its length in the X-axis direction.

[0098] A second adhesive layer 47 may be formed on each of the second recessed patterns IP2. In the display panel according to the first embodiment of this application, a second recessed pattern IP2 may be formed to correspond to each 1-1 recessed pattern IP1-1. The second recessed pattern IP2 may be an area where one of the pair of light-emitting elements LD1-1 and LD2-1 formed on the 1-1 recessed pattern IP1-1 is temporarily disposed during the imprinting process. Therefore, the second recessed pattern IP2 according to this embodiment may have a smaller area in the plane of the display panel than the 1-1 recessed pattern IP1-1.

[0099] The recessed pattern IP1-1 and the second recessed pattern IP2 can be spaced apart by a second distance D2. In the two-stage imprinting method, during the first imprinting process, multiple LED chips can be transferred onto the recessed pattern IP1-1 and the second recessed pattern IP2. The second distance D2 can be a predetermined distance used to prevent cluster defects of the light-emitting elements during the first imprinting process. For example, the second distance D2 can be less than or equal to half of the second pitch SPP (which is the shortest distance between adjacent sub-pixel units SP).

[0100] The first adhesive layer 45 and the second adhesive layer 47 can be respectively disposed on the first recessed pattern IP1 and the second recessed pattern IP2 of the third insulating layer 40. The first adhesive layer 45 and the second adhesive layer 47 may include the first adhesive layer 45 disposed on the first recessed pattern IP1 and the second adhesive layer 47 disposed on the second recessed pattern IP2. For example, the first adhesive layer 45 and the second adhesive layer 47 may include optically transparent adhesive (OCA), optically transparent resin (OCR), pressure-sensitive adhesive (PSA), etc. However, this application is not limited thereto.

[0101] A first adhesive layer 45 may be disposed on the first recessed pattern IP1. The first adhesive layer 45 may be formed along the side surface and bottom surface of the recessed pattern IP1-1. The first adhesive layer 45 may include a lower surface Ca1 in contact with the bottom surface of the recessed pattern IP1-1, an upper surface Ca2 in contact with the first light-emitting element LD1-1 and the second light-emitting element LD1-2, and a groove H. The groove H of the first adhesive layer 45 may include a bottom surface Ca3 that is closer to the substrate 10 than the upper surface Ca2, and a side surface Ca4 between the upper surface Ca2 and the bottom surface Ca3.

[0102] To improve the contact capability of the first electrodes 93a and 93b and the second electrodes 91a and 91b of the first light-emitting element LD1-1 and the second light-emitting element LD1-2, an etching process can be performed after the first light-emitting element LD1-1 and the second light-emitting element LD1-2 are transferred onto the adhesive layer. In this process, as the adhesive layer in the area that does not overlap with the first light-emitting element LD1-1 and the second light-emitting element LD1-2 is etched, a groove H of the first adhesive layer 45 can be formed.

[0103] Therefore, a thickness difference may occur in the first adhesive layer 45. In the first adhesive layer 45, a first thickness t1 can be formed between the lower surface Ca1 and the bottom surface Ca3 of the groove H, and a second thickness t2 can be formed between the upper surface Ca2 and the lower surface Ca1. As a result of the etching process, the first thickness t1 can be formed to be smaller than the second thickness t2.

[0104] A second adhesive layer 47 may be disposed on the second recessed pattern IP2. The second adhesive layer 47 may be formed along the side surface and bottom surface of the second recessed pattern IP2. The second recessed pattern IP2 may include a lower surface Cb1 in contact with the third insulating layer 40 and an upper surface Cb2 opposite to the lower surface Cb1. A third thickness t3 may be formed between the upper surface Cb2 and the lower surface Cb1 of the second recessed pattern IP2. When the first adhesive layer 45 and the second adhesive layer 47 are formed in the same process, as a result of the etching process, the third thickness t3 may be similar to (e.g., equal to) the first thickness t1 and less than the second thickness t2.

[0105] Prior to the etching process, the first adhesive layer 45 and the second adhesive layer 47 can be disposed on the entire third insulating layer 40, including the recessed pattern IP1-1 and the second recessed pattern IP2. Except for the recessed pattern IP1-1 and the second recessed pattern IP2, the adhesive layers disposed on the upper surface of the third insulating layer 40 can be removed by the etching process. However, the display panel of this application is not limited to this, and the adhesive layer material may be partially present on the upper surface of the third insulating layer 40.

[0106] A pair of 1-1 and 1-2 light-emitting elements LD1-1 and LD1-2 can be disposed on the first adhesive layer 45. According to one embodiment, the 1-1 and 1-2 light-emitting elements LD1-1 and LD1-2 can respectively include a light-emitting layer, a first electrode (or anode terminal) 93a and 93b, and a second electrode (or cathode terminal) 91a and 91b.

[0107] The light-emitting layer can emit light by recombination of electrons and holes caused by the current flowing between the first electrodes 93a and 93b and the second electrodes 91a and 91b. According to one embodiment, the light-emitting layer may include first semiconductor layers 94a and 94b, active layers 96a and 96b, and second semiconductor layers 98a and 98b.

[0108] The first semiconductor layers 94a and 94b can provide electrons to the active layers 96a and 96b. For example, the first semiconductor layers 94a and 94b can be formed of an n-type GaN-based semiconductor material, and the n-type GaN-based semiconductor material can include GaN, AlGaN, InGaN, AlInGaN, etc. Here, the impurities used to dope the first semiconductor layers 94a and 94b can include Si, Ge, Se, Te, C, etc.

[0109] An active layer 96a may be disposed on one side of the first semiconductor layer 94a, and an active layer 96b may be disposed on one side of the first semiconductor layer 94b. Active layers 96a and 96b may have a multiple quantum well (MQW) structure, comprising a well layer and a barrier layer having a higher bandgap than the well layer. For example, active layers 96a and 96b may have a multiple quantum well (MQW) structure such as InGaN / GaN.

[0110] Second semiconductor layers 98a and 98b can be disposed on active layers 96a and 96b, respectively, and holes can be supplied to active layers 96a and 96b, respectively. For example, second semiconductor layers 98a and 98b can be formed of a p-type GaN-based semiconductor material, and the p-type GaN-based semiconductor material can include GaN, AlGaN, InGaN, AlInGaN, etc. Here, impurities used to dope the second semiconductor layers 98a and 98b can include Mg, Zn, Be, etc.

[0111] First electrodes 93a and 93b can be disposed on second semiconductor layers 98a and 98b, respectively. First electrodes 93a and 93b can be connected to the source electrode 31 of at least one transistor T.

[0112] The second electrode 91a can be disposed on the other side of the first semiconductor layer 94a to be electrically isolated from the active layer 96a and the second semiconductor layer 98a, and the second electrode 91b can be disposed on the other side of the first semiconductor layer 94b to be electrically isolated from the active layer 96b and the second semiconductor layer 98b. The second electrodes 91a and 91b can be connected to the common power line 15.

[0113] For example, each of the first electrodes 93a and 93b and each of the second electrodes 91a and 91b may be formed of one or more metallic materials including Au, W, Pt, Si, Ir, Ag, Cu, Ni, Ti, or Cr or alloys thereof. As another example, each of the first electrodes 93a and 93b and each of the second electrodes 91a and 91b may be formed of a transparent conductive material, and the transparent conductive material may include indium tin oxide (ITO) or indium zinc oxide (IZO), but this application is not limited thereto.

[0114] The light-emitting elements LD1-1 and LD1-2 (1-1 and 1-2) can emit light through the recombination of electrons and holes generated by the current flowing between the respective first electrodes 93a and 93b and the respective second electrodes 91a and 91b. For example, the light emitted from the light-emitting elements LD1-1 and LD1-2 can pass through the respective first electrodes 93a and 93b and the respective second electrodes 91a and 91b, and can be emitted to the outside. The light emitted from the light-emitting elements LD1-1 and LD1-2 can pass through the respective first electrodes 93a and 93b and the respective second electrodes 91a and 91b in a second direction opposite to a first direction toward the bottom surface of the recessed pattern IP1-1 (1-1) to display an image.

[0115] The fourth insulating layer 50 may be disposed on the first adhesive layer 45 and the second adhesive layer 47, and on the third insulating layer 40 on which the light-emitting element LD is formed. The fourth insulating layer 50 may be formed on the entire display area AA excluding the upper surface of the light-emitting element LD. The fourth insulating layer 50 may expose the upper surface of the light-emitting element LD to allow contact with the first and second electrodes 91a, 91b, 93a and 93b on the upper surface of the light-emitting element LD.

[0116] The fourth insulating layer 50 can be formed of a black organic pigment as a photoresist material. The fourth insulating layer 50 can have a structure surrounding the light-emitting region of the light-emitting element LD, and can be formed of a material including the black pigment. For example, the fourth insulating layer 50 can be formed of a material such as silicon dioxide (SiO2) including the black pigment. x ) or silicon nitride (SiN) xIt can be formed from inorganic materials or organic materials such as benzocyclobutene or photocurable acrylics. However, this application is not limited thereto.

[0117] A fifth insulating layer 60 may be disposed on a portion of the fourth insulating layer 50, and may be disposed at least between the first electrode 93a and the second electrode 91a of the 1-1 light-emitting element LD1-1, and at least between the first electrode 93b and the second electrode 91b of the 1-2 light-emitting element LD1-2. The fifth insulating layer 60 can prevent short circuits between the first electrodes 93a and 93b and the second electrodes 91a and 91b. The upper surface of the fifth insulating layer 60 disposed on a portion of the fourth insulating layer 50 may be higher than the upper surface of the light-emitting element LD in the Z-axis direction relative to the substrate 10. For example, the fifth insulating layer 60 may protrude beyond the light-emitting element LD in the Z-axis direction relative to the substrate 10.

[0118] For example, the fifth insulating layer 60 can be formed of an organic material such as benzocyclobutene or a photocurable acrylic substance. However, this application is not limited thereto.

[0119] The first pixel electrode 55a and the second pixel electrode 55b, as well as the first common electrode 51a and the second common electrode 51b, can be disposed on a substrate 10 on which a fifth insulating layer 60 is formed.

[0120] The first pixel electrode 55a, which contacts the light-emitting element LD1-1 (1-1), and the second pixel electrode 55b, which contacts the light-emitting element LD1-2 (1-2), can be integrally formed and connected in series. However, this application is not limited to this. For example, the first pixel electrode 55a and the second pixel electrode 55b can be formed separately and connected in parallel.

[0121] The first pixel electrode 55a and the second pixel electrode 55b can be connected in series, and therefore, the two first electrodes 93a and 93b can be connected to the source electrode 31 of at least one transistor T. The first pixel electrode 55a and the second pixel electrode 55b can be defined as anodes. For example, the first and second pixel electrodes 55a and 55b can be disposed on the upper and side surfaces of the fifth insulating layer 60 that overlap with the first electrodes 93a and 93b of the 1-1 and 1-2 light-emitting elements LD1-1 and LD1-2, and on the side and bottom surfaces of the fourth insulating layer 50 disposed between the 1-1 and 1-2 light-emitting elements LD1-1 and LD1-2.

[0122] A portion of the first pixel electrode 55a and the second pixel electrode 55b can be electrically connected to the source electrode 31 of at least one transistor T through contact holes disposed through the second insulating layer 30 and the third insulating layer 40. The first pixel electrode 55a can be connected to the first electrode 93a of the 1-1 light-emitting element LD1-1 exposed between the fourth insulating layer 50 and the fifth insulating layer 60. The second pixel electrode 55b can be electrically connected to the first electrode 93b of the 1-2 light-emitting element LD1-2 exposed between the fourth insulating layer 50 and the fifth insulating layer 60.

[0123] Therefore, the first electrodes 93a and 93b can be electrically connected to the source electrode 31 of at least one transistor T via the first pixel electrode 55a and the second pixel electrode 55b. For example, when the display device adopts a top-emitting scheme, the first pixel electrode 55a and the second pixel electrode 55b can be formed of a transparent conductive material. For example, when the display device adopts a bottom-emitting scheme, the first pixel electrode 55a and the second pixel electrode 55b can be formed of a reflective conductive material.

[0124] Transparent conductive materials may include indium tin oxide (ITO), indium zinc oxide (IZO), etc., but this application is not limited to these. Reflective conductive materials may include Al, Ag, Au, Pt, Cu, etc., but this application is not limited to these. When the first pixel electrode 55a and the second pixel electrode 55b are formed of reflective conductive materials, the first pixel electrode 55a and the second pixel electrode 55b may be formed as a single layer including the reflective conductive material or as a multilayer wherein the single layer is stacked.

[0125] The first common electrode 51a and the second common electrode 51b can be electrically connected to each other. For example, the first common electrode 51a and the second common electrode 51b can be integrally formed on the exterior of the 1-1 light-emitting element LD1-1 and the 1-2 light-emitting element LD1-2. However, this application is not limited to this. Furthermore, the first common electrode 51a and the second common electrode 51b can be formed of the same material as the first pixel electrode 55a and the second pixel electrode 55b.

[0126] The first and second common electrodes 51a and 51b can electrically connect the corresponding second electrodes 91a and 91b of the 1-1 and 1-2 light-emitting elements LD1-1 and LD1-2 to the common power line 15. Depending on the situation, the first common electrode 51a and the second common electrode 51b can be defined as cathodes. The first common electrode 51a and the second common electrode 51b can be disposed along the upper surface, side surface, and bottom surface of the fourth insulating layer 50 and along the side surface and upper surface of the fifth insulating layer 60.

[0127] For example, the first common electrode 51a may overlap with the second electrode 91a exposed between the fourth insulating layer 50 and the fifth insulating layer 60. For example, the second common electrode 51b may overlap with the second electrode 91b exposed between the fourth insulating layer 50 and the fifth insulating layer 60.

[0128] According to one embodiment, one side of the second common electrode 51b can be electrically connected to the common power line 15 through contact holes provided through the first to fourth insulating layers 20, 30, 40 and 50. According to one embodiment, one side of the first common electrode 51a can be electrically connected to the second electrode 91a of the 1-1 light-emitting element LD1-1, and the other side of the second common electrode 51b can be electrically connected to the second electrode 91b of the 1-2 light-emitting element LD1-2. Therefore, the second electrodes 91a and 91b of the 1-1 light-emitting element LD1-1 and the 1-2 light-emitting element LD1-2 can be electrically connected to the common power line 15 through the first common electrode 51a and the second common electrode 51b, respectively.

[0129] According to one embodiment, the first pixel electrode 55a and the second pixel electrode 55b, as well as the first common electrode 51a and the second common electrode 51b, can be formed simultaneously by a deposition process for depositing electrode materials and an electrode patterning process using photolithography and etching. Therefore, in the display panel according to this embodiment, the first pixel electrode 55a and the second pixel electrode 55b, as well as the first common electrode 51a and the second common electrode 51b, which connect the light-emitting element LD to the pixel driving circuit PD, can be formed simultaneously. Furthermore, the display panel according to this embodiment allows for a simplified electrode connection process. Additionally, the display panel according to this embodiment allows for a significant reduction in the processing time for connecting the light-emitting element LD to the pixel driving circuit PD, thereby improving the productivity of the display panel.

[0130] A sixth insulating layer 70 may be disposed on a substrate 10 on which the first pixel electrode 55a and the second pixel electrode 55b, as well as the first common electrode 51a and the second common electrode 51b, are formed. The sixth insulating layer 70 may be disposed around the paired light-emitting elements LD1-1 and LD1-2. For example, as... Figure 4 As shown, in some areas, the sixth insulating layer 70 can contact the upper surfaces of the first pixel electrode 55a and the second pixel electrode 55b, as well as the first common electrode 51a and the second common electrode 51b. For example, as Figure 5 As shown, in some areas, the sixth insulating layer 70 may contact the ends of the first pixel electrode 55a and the second pixel electrode 55b, as well as the first common electrode 51a and the second common electrode 51b. However, the display panel of this application is not limited to this.

[0131] The sixth insulating layer 70 may overlap with the fifth insulating layer 60, which is partially disposed on the fourth insulating layer 50. Therefore, the sixth insulating layer 70 disposed on the protruding fifth insulating layer 60 can prevent color mixing between adjacent sub-pixel units SP.

[0132] For example, the sixth insulating layer 70 can be formed of a material including black pigment. For example, the sixth insulating layer 70 can be formed of a material such as silicon oxide (SiO2). x ) or silicon nitride (SiN) x It can be formed from inorganic materials, or from organic materials such as benzocyclobutene or photocurable acrylics. The sixth insulating layer 70 can be omitted. However, this application is not limited thereto.

[0133] A transparent buffer layer 80 may be disposed on the sixth insulating layer 70. The transparent buffer layer 80 may be disposed on the substrate 10, on which the sixth insulating layer 70 is formed to provide a flat surface. The transparent buffer layer 80 may at least cover the entire display area AA of the substrate 10. The transparent buffer layer 80 may protect the light-emitting element LD and circuitry formed on the substrate 10 from external impacts. For example, the transparent buffer layer 80 may comprise an optically transparent adhesive (OCA) or an optically transparent resin (OCR), but this application is not limited thereto.

[0134] In the following embodiments, the description of the same configuration as the display panel according to the first embodiment will be omitted.

[0135] Figure 6 This is a first variation example of a display panel according to the first embodiment of this application. Figure 6 A schematic planar view of one pixel P out of a plurality of pixels P.

[0136] Combination Figure 2 Reference Figure 6 According to a first variant example of the first embodiment of this application, the display panel can be in multiple first pattern areas IA1 (see... Figure 2 The first recessed pattern IP1 is included in the second pattern area IA2, and the second pattern area IA2 may include a plurality of second recessed patterns IP2. Here, a sub-pixel unit SP including a pair of first light-emitting elements LD1 and second light-emitting elements LD2 may be included in each first recessed pattern IP1.

[0137] According to this embodiment, the plurality of first recessed patterns IP1 can be arranged to be spaced apart from each other in the X-axis direction. The distance between the first recessed patterns IP1 can be set to a predetermined distance to prevent cluster defects during the first imprinting process. For example, the distance between the first recessed patterns IP1 can be set to 2 chip pitches or greater.

[0138] Each first recessed pattern IP1 can be formed to have a greater length in the Y-axis direction than in the X-axis direction, such that a pair of first light-emitting elements LD1 and second light-emitting elements LD2 are arranged inside the first recessed pattern IP1 in the Y-axis direction. Furthermore, each first recessed pattern IP1 can be configured such that the pair of first light-emitting elements LD1 and second light-emitting elements LD2 are spaced apart by a predetermined first distance D1.

[0139] According to this embodiment, each of the plurality of second recessed patterns IP2 can be configured to correspond to a first recessed pattern IP1. A second recessed pattern IP2 can be disposed on one side of each of the plurality of first recessed patterns IP1 in the Y-axis direction. Furthermore, in the two-stage imprinting method, each second recessed pattern IP2 can be spaced from its corresponding first recessed pattern IP1 in the Y-axis direction by at least a predetermined second distance D2 to prevent clustering defects during the first imprinting process. For example, the second distance D2 can be less than or equal to half of the second pitch SPP.

[0140] The second recessed pattern IP2 may be an area that is temporarily transferred to one of the paired first light-emitting elements LD1 and second light-emitting elements LD2 during the first imprinting process. Therefore, the second recessed pattern IP2 may have an area corresponding to at least one light-emitting element.

[0141] Each sub-pixel unit SP according to this embodiment may be included within each first recessed pattern IP1. Each sub-pixel unit SP may include a pair of first light-emitting elements LD1 and second light-emitting elements LD2. The pair of first light-emitting elements LD1 and second light-emitting elements LD2 may be arranged side by side in the Y-axis direction.

[0142] The paired first light-emitting elements LD1 and second light-emitting elements LD2 can be configured such that their light-emitting regions face each other. Here, the light-emitting region may include the area where the first electrode E1 of each of the paired first light-emitting elements LD1 and second light-emitting elements LD2 is located. Therefore, in the display panel of this application, by arranging the light-emitting regions of the paired first light-emitting elements LD1 and second light-emitting elements LD2 adjacent to each other, the dispersion of color wavelengths can be stabilized.

[0143] Each of the first light-emitting element LD1 and the second light-emitting element LD2 may include a first electrode E1 and a second electrode E2. Here, the first electrode E1 is the region that overlaps with the active layer of the light-emitting element and may overlap with most of the light-emitting region. Therefore, in the display panel of this application, by arranging the first electrodes E1 facing each other, the dispersion of color wavelengths can be stabilized.

[0144] The first light-emitting element LD1 and the second light-emitting element LD2 can be spaced apart by a first distance D1. According to this application, the first distance D1 of the display panel can be less than the binocular resolution. For example, the first distance D1 can be set to be less than or equal to 1 / 2 of the first pitch PP, and preferably less than or equal to 1 / 10 of the first pitch PP.

[0145] In the display panel of this application, the paired first light-emitting elements LD1 and second light-emitting elements LD2 can be transferred by a two-step imprinting method, thereby allowing the first distance D1 to be configured to be less than the minimum perceptible pixel spacing at the viewing distance. Therefore, even when defects occur consecutively in the subpixels of each subpixel unit, the display panel of this application can prevent the viewer from perceiving defects caused by them. When the two-step imprinting method is used, the productivity for transferring the paired first light-emitting elements LD1 and second light-emitting elements LD2 arranged in different directions can be improved.

[0146] Figure 7 This is a schematic diagram of a second variation example of a display panel according to the first embodiment of this application. Figure 7 A schematic planar view of one pixel P out of a plurality of pixels P.

[0147] Combination Figure 2 Reference Figure 7 According to a second variant example of the first embodiment of this application, the display panel can be in multiple first pattern areas IA1 (see... Figure 2 The pattern includes multiple first recessed patterns IP1, and can be in the second pattern area IA2 (see Figure 2 The first recessed pattern IP1 includes multiple second recessed patterns IP2. Sub-pixel units SP, including pairs of first light-emitting elements LD1 and second light-emitting elements LD2, may be included in each first recessed pattern IP1.

[0148] According to this embodiment, the plurality of first recessed patterns IP1 can be arranged to be spaced apart from each other in the X-axis direction. A second recessed pattern IP2 can be disposed between the plurality of spaced-apart first recessed patterns IP1.

[0149] Each first recessed pattern IP1 can be formed to have a greater length in the X-axis direction than in the Y-axis direction, such that a pair of first light-emitting elements LD1 and second light-emitting elements LD2 are arranged inside the first recessed pattern IP1 in the X-axis direction. Each first recessed pattern IP1 can be configured such that the pair of first light-emitting elements LD1 and second light-emitting elements LD2 can be spaced apart by a predetermined first distance D1.

[0150] According to this embodiment, the plurality of second recessed patterns IP2 can each be configured to correspond to each first recessed pattern IP1. Each second recessed pattern IP2 can be disposed on one side of each first recessed pattern IP1 in the X-axis direction. In the two-stage imprinting method, each second recessed pattern IP2 can be spaced apart from the corresponding first recessed pattern IP1 by a predetermined second distance D2 in the X-axis direction to prevent clustering defects during the first imprinting process. For example, the second distance D2 can be less than or equal to 1 / 2 of the second pitch SPP.

[0151] The second recessed pattern IP2 may be an area that is temporarily transferred to one of the paired first light-emitting elements LD1 and second light-emitting elements LD2 during the first imprinting process. Therefore, the second recessed pattern IP2 may have an area corresponding to at least one light-emitting element.

[0152] According to this embodiment, the sub-pixel unit SP may include a pair of first light-emitting elements LD1 and second light-emitting elements LD2. The pair of first light-emitting elements LD1 and second light-emitting elements LD2 may be arranged side by side in the X-axis direction. The pair of first light-emitting elements LD1 and second light-emitting elements LD2 may be configured such that their light-emitting areas are oriented in opposite directions relative to (or about) the Y-axis direction. Therefore, in the display panel of this application, by arranging the light-emitting areas of the pair of first light-emitting elements LD1 and second light-emitting elements LD2 adjacent to each other relative to (or about) the X=Y axis direction (diagonal direction), the dispersion of color wavelengths can be stabilized.

[0153] Each of the first light-emitting element LD1 and the second light-emitting element LD2 may include a first electrode E1 and a second electrode E2. The first electrode E1 is a region that overlaps with the active layer of the light-emitting element and may overlap with most of the light-emitting region.

[0154] The first light-emitting element LD1 and the second light-emitting element LD2 can be spaced apart by a first distance D1. According to this application, the first distance D1 of the display panel can be less than the binocular resolution. For example, the first distance D1 can be set to be less than or equal to 1 / 2 of the first pitch PP, and preferably less than or equal to 1 / 10 of the first pitch PP.

[0155] In the display panel of this application, the paired first light-emitting elements LD1 and second light-emitting elements LD2 can be transferred by a two-step imprinting method, thereby allowing the first distance D1 to be configured to be less than the minimum perceptible pixel spacing at the viewing distance. Therefore, even when defects occur consecutively in the subpixels of each subpixel unit, the display panel of this application can prevent the viewer from perceiving defects caused by them. When the two-step imprinting method is used, the productivity for transferring the paired first light-emitting elements LD1 and second light-emitting elements LD2 arranged in different directions can be improved.

[0156] Figure 8 This is a plan view of a display panel according to a second embodiment of this application, and Figure 9 For along Figure 8 The sectional view taken from line III-III'. Figure 8 A schematic planar view of one pixel P out of a plurality of pixels P.

[0157] Reference Figure 8 and Figure 9 The display panel according to this embodiment of the present application may include 1-1 and 1-2 recessed patterns IP11 and IP12 on the third insulating layer 140, a first adhesive layer 145a and 145b and a second adhesive layer (not shown) on the third insulating layer 140, a fourth insulating layer 150 covering the first adhesive layer 145a and 145b and the second adhesive layer (not shown) and exposing the first light-emitting element LD1 and the second light-emitting element LD2, a fifth insulating layer 160 disposed on a portion of the fourth insulating layer 150, a first pixel electrode 155a and a second pixel electrode 155b in contact with the first electrodes 93a and 93b of the first light-emitting element LD1 and the second light-emitting element LD2, a first common electrode 151a and a second common electrode 151b in contact with the second electrodes 91a and 91b, a sixth insulating layer 170 disposed around the light-emitting elements LD1 and LD2, and a transparent buffer layer 180 configured to planarize the uneven surface on the substrate 10.

[0158] Combination Figure 2 Reference Figure 8 and Figure 9 According to the second embodiment of this application, the display panel can be in multiple first pattern areas IA1-1, IA1-2 and IA1-3 (see... Figure 2 Each of the above includes 1-1 recessed pattern IP11, 1-2 recessed pattern IP12 and raised pattern EP, and may be in the second pattern area IA2 (see Figure 2 The ) includes multiple second recessed patterns IP2.

[0159] The plurality of first pattern regions, each comprising a recessed pattern IP11, a recessed pattern IP12, and a protruding pattern EP, can be configured to be spaced apart from each other in the X-axis direction. Furthermore, a second recessed pattern IP2 can be disposed in a second pattern region between the first pattern regions.

[0160] The recessed patterns IP11 and IP12 (1-1 and 1-2) can be spaced apart from each other in the Y-axis direction. A first light-emitting element LD1 can be disposed within the recessed pattern IP11 (1-1), and a second light-emitting element LD2 can be disposed within the recessed pattern IP12 (1-2). The recessed patterns IP11 and IP12 (1-1 and 1-2) can each be provided with a size corresponding to the area of ​​at least one light-emitting element. For example, when the length of the light-emitting element in the Y-axis direction is greater than its length in the X-axis direction, each of the recessed patterns IP11 and IP12 (1-1 and 1-2) can be formed such that its length in the Y-axis direction is greater than its length in the X-axis direction.

[0161] A raised pattern EP can be disposed between recessed patterns IP11 and IP12 of 1-1 and 1-2. The raised pattern EP can be formed along the length of each of the recessed patterns IP11 and IP12 of 1-1 and 1-2 in the X-axis direction. The raised pattern EP can be integrally formed with the third insulating layer 140. When the recessed patterns IP11 and IP12 of 1-1 and 1-2 are formed in the third insulating layer 140, the raised pattern EP can be formed together with the recessed patterns IP11 and IP12 of 1-1 and 1-2.

[0162] Reference Figure 9 The protruding pattern EP may have a shape that protrudes from the bottom surfaces of the recessed patterns IP11 and IP12 of 1-1 and 1-2 along the Z-axis direction (away from the substrate 10). The protruding pattern EP may include the side surface of each of the adjacent recessed patterns IP11 and IP12 of 1-1 and 1-2. The protruding pattern EP may partially overlap with the recessed patterns IP11 and IP12 of 1-1 and 1-2.

[0163] The raised pattern EP can prevent interference between two light-emitting elements during the process of transferring the light-emitting elements to the recessed patterns IP11 and IP12 of 1-1 and 1-2. The recessed patterns IP11 and IP12 of 1-1 and 1-2 can guide the position of the multiple light-emitting elements LD during the transfer process of transferring the multiple light-emitting elements LD to the display panel 1.

[0164] Along with the formation of the protruding pattern EP, this embodiment may also include a protrusion 100a located on the protruding pattern EP. The protrusion 100a may include a first protrusion 150a of the fourth insulating layer 150, a second protrusion 160a of the fifth insulating layer 160, and a third protrusion 170a of the sixth insulating layer 170. Due to the protruding shape of the protruding pattern EP, the first protrusion 150a, the second protrusion 160a, and the third protrusion 170a may be formed naturally when the insulating layers of the corresponding layers are formed. In some cases, the first protrusion 150a, the second protrusion 160a, and the third protrusion 170a may not be formed, or may be selectively formed.

[0165] As the protruding pattern EP is formed, a first adhesive layer can be disposed in each of the recessed patterns IP11 and IP12 of 1-1 and 1-2. Therefore, the first adhesive layer of this embodiment may include a first adhesive layer 145a disposed in the recessed pattern IP11 of 1-1 and a first adhesive layer 145b disposed in the recessed pattern IP12 of 1-2. The plurality of second recessed patterns IP2 according to this embodiment can be configured to correspond to one of the recessed patterns IP11 and IP12 of 1-1 and 1-2. Each second recessed pattern IP2 can be disposed on one side of the 1-1 or 1-2 recessed pattern IP11 or IP12 in the X-axis direction. Furthermore, in the two-stage imprinting method, each second recessed pattern IP2 can be spaced apart from the corresponding 1-1 or 1-2 recessed pattern IP11 or IP12 by a predetermined second distance D2 in the X-axis direction to prevent cluster defects during the first imprinting process. For example, the second distance D2 can be formed to be less than or equal to 1 / 2 of the second pitch SPP.

[0166] The second recessed pattern IP2 may be an area that is temporarily transferred to one of the paired first light-emitting elements LD1 and second light-emitting elements LD2 during the first imprinting process. Therefore, the second recessed pattern IP2 may have an area corresponding to at least one light-emitting element.

[0167] A first light-emitting element LD1 can be disposed on a recessed pattern IP11 (1-1), and a second light-emitting element LD2 can be disposed on a recessed pattern IP12 (1-2). The paired first light-emitting elements LD1 and LD2 can constitute a sub-pixel unit SP. The paired first light-emitting elements LD1 and LD2 can be configured such that their first electrodes E1 face each other. The first electrode E1 of the light-emitting element is the region overlapping with the active layer of the light-emitting element, and can largely overlap with the light-emitting area. Therefore, the display panel of this application can have uniform color wavelength dispersion.

[0168] The first light-emitting element LD1 and the second light-emitting element LD2 can be spaced apart by a first distance D1. The first distance D1 of the display panel according to this application can be less than the binocular resolution. For example, the first distance D1 can be set to be less than or equal to 1 / 2 of the first pitch PP, and preferably less than or equal to 1 / 10 of the first pitch PP. Therefore, even when defects occur consecutively in the subpixels of each subpixel unit, the display panel of this application can still prevent the viewer from perceiving flaws caused by defects. Furthermore, by employing a double-imprinting method, the productivity for transferring the pairs of first light-emitting elements LD1 and second light-emitting elements LD2 arranged in different directions can be improved.

[0169] Figure 10This is a schematic diagram of a first variant example of a display panel according to a second embodiment of this application. Figure 10 A schematic planar view of one pixel P out of a plurality of pixels P.

[0170] Combination Figure 2 Reference Figure 10 According to the first variant example of the second embodiment of this application, the display panel can be in multiple first pattern areas IA1-1, IA1-2 and IA1-3 (see Figure 2 Each of the above includes 1-1 recessed pattern IP11, 1-2 recessed pattern IP12 and raised pattern EP, and may be in the second pattern area IA2 (see Figure 2 The ) includes multiple second recessed patterns IP2.

[0171] The plurality of first pattern regions, each comprising a recessed pattern IP11, a recessed pattern IP12, and a protruding pattern EP, can be configured to be spaced apart from each other in the X-axis direction. A second recessed pattern IP2 can be disposed in a second pattern region between the first pattern regions.

[0172] The recessed patterns IP11 and IP12 (1-1 and 1-2) can be spaced apart from each other in the X-axis direction. The first light-emitting element LD1 can be disposed inside the recessed pattern IP11 (1-1). The second light-emitting element LD2 can be disposed inside the recessed pattern IP12 (1-2).

[0173] The recessed patterns IP11 and IP12 of 1-1 and 1-2 can each be provided with a size corresponding to the area of ​​at least the light-emitting element. For example, when the length of the light-emitting element in the Y-axis direction is greater than its length in the X-axis direction, each of the recessed patterns IP11 and IP12 of 1-1 and 1-2 can be formed such that its length in the Y-axis direction is greater than its length in the X-axis direction.

[0174] A raised pattern EP can be disposed between recessed patterns IP11 and IP12 in 1-1 and 1-2. The raised pattern EP can be formed along the length of each of the recessed patterns IP11 and IP12 in the Y-axis direction. The raised pattern EP can be integrally formed with the third insulating layer 140 (see [reference]). Figure 9 The highlighted pattern EP is not limited to Figure 10 The contents shown can partially overlap with the adjacent side surfaces of the recessed patterns IP11 and IP12 in 1-1 and 1-2.

[0175] According to this embodiment, the plurality of second recessed patterns IP2 can be configured to correspond to recessed patterns IP11 and IP12 of 1-1 and 1-2. Each second recessed pattern IP2 can be disposed on one side of recessed pattern IP11 or IP12 of 1-1 or 1-2 in the X-axis direction. In the two-stage imprinting method, each second recessed pattern IP2 can be spaced apart from the corresponding recessed pattern IP11 or IP12 of 1-1 or 1-2 in the X-axis direction by a predetermined second distance D2 to prevent clustering defects during the first imprinting process. For example, the second distance D2 can be less than or equal to 1 / 2 of the second pitch SPP.

[0176] The second recessed pattern IP2 may be an area that is temporarily transferred to one of the paired first light-emitting elements LD1 and second light-emitting elements LD2 during the first imprinting process. Therefore, the second recessed pattern IP2 may have an area corresponding to at least one light-emitting element.

[0177] The first light-emitting element LD1 can be disposed on the 1-1 recessed pattern IP11, and the second light-emitting element LD2 can be disposed on the 1-2 recessed pattern IP12. The paired first light-emitting elements LD1 and second light-emitting elements LD2 can constitute a sub-pixel unit SP. In this case, the paired first light-emitting elements LD1 and second light-emitting elements LD2 can be configured such that their light-emitting areas are oriented in opposite directions relative to the Y-axis. Therefore, in the display panel of this application, by arranging the light-emitting areas of the paired first light-emitting elements LD1 and second light-emitting elements LD2 adjacent to each other relative to the X=Y axis direction, the dispersion of color wavelengths can be stabilized.

[0178] The first light-emitting element LD1 and the second light-emitting element LD2 can be spaced apart by a first distance D1. The first distance D1 of the display panel according to this application can be less than the binocular resolution. For example, the first distance D1 can be set to be less than or equal to 1 / 2 of the first pitch PP, and preferably less than or equal to 1 / 10 of the first pitch PP. Therefore, even when defects occur consecutively in the subpixels of each subpixel unit, the display panel of this application can still prevent the viewer from perceiving flaws caused by defects. Furthermore, by employing a double-imprinting method, the productivity for transferring the pairs of first light-emitting elements LD1 and second light-emitting elements LD2 arranged in different directions can be improved.

[0179] Figure 11A This is a plan view of a display panel according to a third embodiment of this application, and Figure 11B To show Figure 11A A plan view comparing the first and second recessed patterns. Figure 12 For along Figure 11A A sectional view taken along line IV-IV'. Here, Figure 11AA schematic planar view of one pixel P out of a plurality of pixels P.

[0180] Reference Figures 11A to 12 The display panel according to this embodiment of the present application may include recessed patterns IP11 and IP12 of 1-1 and 1-2 on the third insulating layer 240, a first adhesive layer 245 and a second adhesive layer 247 on the third insulating layer 240, a fourth insulating layer 250 covering the first adhesive layer 245 and the second adhesive layer 247 and exposing the first light-emitting element LD1 and the second light-emitting element LD2, a fifth insulating layer 260 disposed on a portion of the fourth insulating layer 250, a common electrode 251b in contact with the second electrode 91b of the second light-emitting element LD2, a sixth insulating layer 270 disposed around the first light-emitting element LD1 and the second light-emitting element LD2, and a transparent buffer layer 280 configured to planarize the uneven surface on the substrate 10.

[0181] Combination Figure 2 Reference Figure 11A According to the third embodiment of this application, the display panel can be in multiple first pattern areas IA1-1, IA1-2 and IA1-3 (see... Figure 2 Each of the above includes 1-1 recessed pattern IP11, 1-2 recessed pattern IP12 and raised pattern EP, and may be in the second pattern area IA2 (see Figure 2 The ) includes multiple second recessed patterns IP2.

[0182] Reference Figure 11A and Figure 11B In the display panel according to this embodiment, the first area A1 of each of the recessed patterns IP11 and IP12 (1-1 and 1-2) can be larger than the second area A2 of the second recessed pattern IP2. (Refer to...) Figure 12 The first length A1-a of the recessed patterns IP11 and IP12 in the X-axis direction can be greater than the second length A2-a of the second recessed pattern IP2 in the X-axis direction.

[0183] The recessed patterns IP11 and IP12 in 1-1 and 1-2 can be areas where the first light-emitting element LD1 and the second light-emitting element LD2 are transferred and attached during the imprinting process. Conversely, the second recessed pattern IP2 can be a non-transfer area in which one of the paired first light-emitting elements LD1 and second light-emitting elements LD2 is temporarily placed after being transferred during the imprinting process, but is not ultimately transferred.

[0184] Since each of the recessed patterns IP11 and IP12 in 1-1 and 1-2 is formed to be sufficiently larger than the area of ​​each of the first and second light-emitting elements LD1 and LD2, a relatively strong pressure can be applied. Forming an area larger than each of the first and second light-emitting elements LD1 and LD2 can mean that each of the recessed patterns IP11 and IP12 in 1-1 and 1-2 is formed to be larger than the second recessed pattern IP2. Applying a relatively strong pressure can mean applying a greater pressure to the recessed patterns IP11 and IP12 in 1-1 and 1-2 than to the second recessed pattern IP2. Therefore, even when the adhesive layer is substantially non-uniformly formed on the recessed patterns IP11 and IP12 in 1-1 and 1-2, or when a pressure difference exists in the donor, the light-emitting elements are transferred with a relatively strong force, thereby reducing the defect rate of untransferred light-emitting elements.

[0185] Figure 13 This is a plan view of a portion of a display panel according to a fourth embodiment of this application. Figure 13 A schematic planar view of one pixel P out of a plurality of pixels P.

[0186] Combination Figure 2 Reference Figure 13 According to the fourth embodiment of this application, the display panel can be in multiple first pattern areas IA1-1, IA1-2 and IA1-3 (see... Figure 2 Each of the above includes a first recessed pattern IP1, and may be in a second pattern area IA2 (see Figure 2 The device includes multiple second recessed patterns IP2 and multiple first dummy recessed patterns DP1. For example, the first dummy recessed patterns DP1 can be formed in the same manner as the second recessed patterns IP2.

[0187] The second recessed pattern IP2 and the first dummy recessed pattern DP1 can be disposed on one side of each first recessed pattern IP1. The second recessed pattern IP2 and the first dummy recessed pattern DP1 can be configured to correspond to each pair of first light-emitting elements LD1 and second light-emitting elements LD2 disposed in the first recessed pattern IP1. For example... Figure 13 As shown, when the pair of first light-emitting elements LD1 and second light-emitting elements LD2 are arranged side by side in the Y-axis direction, the second recessed pattern IP2 and the first dummy recessed pattern DP1 can also be arranged side by side in the Y-axis direction.

[0188] For example, the first dummy recessed pattern DP1 can be configured to correspond to one side of the first light-emitting element LD1, and the second recessed pattern IP2 can be configured to correspond to one side of the second light-emitting element LD2. Compared to the previous embodiment, the display panel according to this embodiment may further include the first dummy recessed pattern DP1, which has a configuration corresponding to the light-emitting element. Therefore, the display panel of this embodiment can have improved freedom of movement in the transfer direction. Furthermore, the first dummy recessed pattern DP1 may also accommodate an adhesive layer, thereby allowing the adhesive layer within the recessed pattern to be formed with a more uniform thickness.

[0189] Figure 14 This is a first variant example of a display panel according to the fourth embodiment of this application. Figure 14 A schematic planar view of one pixel P out of a plurality of pixels P.

[0190] Combination Figure 2 Reference Figure 14 According to the first variant example of the fourth embodiment of this application, the display panel can be in multiple first pattern areas IA1-1, IA1-2 and IA1-3 (see... Figure 2 Each of the above includes a first recessed pattern IP1, and may be in a second pattern area IA2 (see Figure 2 The ) includes multiple second recessed patterns IP2 and multiple first dummy recessed patterns DP1.

[0191] The second recessed pattern IP2 and the first dummy recessed pattern DP1 can be disposed on one side of each first recessed pattern IP1. The first dummy pattern DP1 can be further disposed on the other side of the first recessed pattern IP1 located at the edge of pixel P in the area where the second recessed pattern IP2 is not disposed.

[0192] For example, the first dummy recessed pattern DP1 and the second recessed pattern IP2 can be arranged side by side in the Y-axis direction on one side of each of the first recessed patterns IP1 arranged in the first, second, and third columns. Alternatively, the two first dummy recessed patterns DP1 can be arranged side by side in the Y-axis direction on the other side of the first recessed pattern IP1 arranged in the first column.

[0193] The display panel according to this embodiment may further include a first dummy recessed pattern DP1, thereby further improving the degree of freedom in the transfer direction. Furthermore, the first dummy recessed pattern DP1 may also accommodate an adhesive layer, thereby allowing the adhesive layer within the recessed pattern to form with a more uniform thickness.

[0194] Figure 15 This is a plan view of a portion of a display panel according to the fifth embodiment of this application. Figure 15A schematic planar view of one pixel P out of a plurality of pixels P.

[0195] Combination Figure 2 Reference Figure 15 According to the fifth embodiment of this application, the display panel can have multiple first pattern areas IA1-1, IA1-2 and IA1-3 (see... Figure 2 Each of the above includes a first recessed pattern IP1, and may be in a second pattern area IA2 (see Figure 2 The ) includes multiple second recessed patterns IP2, multiple first dummy recessed patterns DP1 and multiple second dummy recessed patterns DP2.

[0196] The second recessed pattern IP2 and the first dummy recessed pattern DP1 can be disposed on one side of each first recessed pattern IP1. The first dummy pattern DP1 can be further disposed on the other side of the first recessed pattern IP1 located at the edge of pixel P in the area where the second recessed pattern IP2 is not disposed.

[0197] The second dummy recessed pattern DP2 can be respectively positioned in the Y-axis direction corresponding to the plurality of first recessed patterns IP1, the plurality of second recessed patterns IP2, and the plurality of first dummy recessed patterns DP1. The first dummy recessed patterns DP1 and the second dummy recessed patterns DP2 can have an arrangement structure surrounding the first recessed pattern IP1.

[0198] For example, seven second dummy recessed patterns DP2 can be arranged side by side in the first row. For example, in the second row, the first dummy recessed patterns DP1, IP1, IP1, DP1, IP1, DP1, IP1, IP1, IP1, IP1, IP1, IP1, and DP1 can be arranged sequentially from the left, corresponding to the seven second dummy recessed patterns DP2 respectively.

[0199] For example, in the third row, the first dummy recessed pattern DP1, the first recessed pattern IP1, the second recessed pattern IP2, the first recessed pattern IP1, the second recessed pattern IP2, the first recessed pattern IP1, the first recessed pattern IP1, and the second recessed pattern IP2 can be arranged sequentially from the left, each corresponding to one of the seven second dummy recessed patterns DP2. For example, in the fourth row, the seven second dummy recessed patterns DP2 can be arranged to correspond to the seven second dummy recessed patterns DP2.

[0200] Compared to the previous embodiment, the display panel according to this embodiment can improve the degree of freedom in the transfer direction and improve the uniformity of the thickness of the adhesive layer by further including a second dummy recessed pattern DP2.

[0201] Figure 16 This is a first variant example of a display panel according to the fifth embodiment of this application. Figure 16 A schematic planar view of one pixel P out of a plurality of pixels P.

[0202] Combination Figure 2 Reference Figure 16 According to a first variant example of the fifth embodiment of this application, the display panel can be in multiple first pattern areas IA1-1, IA1-2 and IA1-3 (see... Figure 2 Each of the above includes a first recessed pattern IP1, and may be in a second pattern area IA2 (see Figure 2 The ) includes multiple second recessed patterns IP2, multiple first dummy recessed patterns DP1 and multiple second dummy recessed patterns DP2.

[0203] The second recessed pattern IP2 and the first dummy recessed pattern DP1 can be disposed on one side of each first recessed pattern IP1. In addition, the first dummy pattern DP1 can be further disposed on the other side of the first recessed pattern IP1 (opposite to the side of the first recessed pattern IP1 located at the edge of pixel P) in the area where the second recessed pattern IP2 is not disposed.

[0204] The second dummy recessed pattern DP2 can be disposed on both the X-axis and Y-axis, corresponding to the plurality of first recessed patterns IP1, the plurality of second recessed patterns IP2, and the plurality of first dummy recessed patterns DP1, respectively. That is, the second dummy recessed pattern DP2 can have an arrangement structure surrounding the plurality of first recessed patterns IP1, the plurality of second recessed patterns IP2, and the plurality of first dummy recessed patterns DP1.

[0205] For example, nine second virtual recessed patterns DP2 can be arranged side by side in the first row. For example, in the second row, the second virtual recessed pattern DP2, the first virtual recessed pattern DP1, the first virtual recessed pattern IP1, the first virtual recessed pattern DP1, the first virtual recessed pattern IP1, the first virtual recessed pattern IP1, the first virtual recessed pattern DP1, the first virtual recessed pattern IP1, the first virtual recessed pattern DP1, the first virtual recessed pattern DP1, the first virtual recessed pattern DP1, and the second virtual recessed pattern DP2 can be arranged sequentially from the left, each corresponding to one of the nine second virtual recessed patterns DP2. For example, in the third row, the second dummy recessed pattern DP2, the first dummy recessed pattern DP1, the first recessed pattern IP1, the second recessed pattern IP2, the first recessed pattern IP1, the second recessed pattern IP2, the first recessed pattern IP2, the first recessed pattern IPP1, the second recessed pattern IP2, the second recessed pattern IP2, and the second dummy recessed pattern DP2 can be arranged sequentially from the left, each corresponding to nine second dummy recessed patterns DP2. For example, in the fourth row, the nine second dummy recessed patterns DP2 can be arranged to correspond to nine second dummy recessed patterns DP2.

[0206] The second dummy recessed pattern DP2, disposed at both ends of the first recessed pattern IP1 in the X-axis direction, allows for a uniform thickness of the adhesive layer within the second recessed pattern IP2, which is the area where the light-emitting element is temporarily transferred during the first imprinting process. Therefore, the display panel according to this application can prevent the light-emitting element from being over-transferred to the second recessed pattern IP2 during the first imprinting process. Reference is made here. Figure 16 The second dummy recessed pattern DP2 set in the X-axis direction relative to the first recessed pattern IP1 can refer to the four second dummy recessed patterns DP2 set at both ends of the second and third rows.

[0207] Figure 17 This is a plan view of a portion of a display panel according to the sixth embodiment of this application. Figure 17 A schematic planar view of one pixel P out of a plurality of pixels P.

[0208] Combination Figure 2 Reference Figure 17 According to the sixth embodiment of this application, the display panel can be in multiple first pattern areas IA1-1, IA1-2 and IA1-3 (see... Figure 2 Each of the above includes 1-1 recessed pattern IP11, 1-2 recessed pattern IP12 and raised pattern EP, and may be in the second pattern area IA2 (see Figure 2The ) includes multiple second recessed patterns IP2, multiple first dummy recessed patterns DP1 and multiple second dummy recessed patterns DP2.

[0209] This embodiment relates to the arrangement structure of a first dummy recessed pattern DP1 and a second dummy recessed pattern DP2 when multiple first pattern regions, each including a 1-1 recessed pattern IP11, a 1-2 recessed pattern IP12 and a protruding pattern EP, are spaced apart from each other in the X-axis direction.

[0210] The second recessed pattern IP2 may be disposed on one side of each of the recessed patterns IP11 and IP12 in 1-1 and 1-2 along the X-axis direction. The first dummy recessed pattern DP1 may be disposed on the other side of each of the recessed patterns IP11 and IP12 in 1-1 and 1-2 along the X-axis direction (where the second recessed pattern IP2 is not disposed).

[0211] The second dummy recessed pattern DP2 can be set around the 1-1 and 1-2 recessed patterns IP11 and IP12, the second recessed pattern IP2 and the first dummy recessed pattern DP1.

[0212] For example, twelve second dummy recessed patterns DP2 can be arranged side-by-side in the first row. For example, in the second row, the second dummy recessed pattern DP2, the first dummy recessed pattern DP1, the 1-1 recessed pattern IP11, the 1-2 recessed pattern IP12, the second recessed pattern IP2, the 1-1 recessed pattern IP11, the 1-2 recessed pattern IP12, the second recessed pattern IP2, the 1-1 recessed pattern IP11, the 1-2 recessed pattern IP12, the second recessed pattern IP2, and the second dummy recessed pattern DP2 can be arranged sequentially from the left, each corresponding to one of the twelve second dummy recessed patterns DP2. For example, in the third row, the twelve second dummy recessed patterns DP2 can be arranged corresponding to one of the twelve second dummy recessed patterns DP2.

[0213] Therefore, the display panel according to this embodiment can have the effect of improving the degree of freedom in the transfer direction and improving the uniformity of the adhesive layer thickness.

[0214] Figures 18A to 18E and Figures 19A to 19F These are a process plan view and a process cross-sectional view according to the first embodiment of this application, respectively.

[0215] Figure 18A Corresponding to Figure 19A The same process operation (or steps). Figure 18B Corresponding to Figure 19B The same process operation, Figure 18C Corresponding to Figure 19CThe same process operations (or steps), and Figure 18E Corresponding to Figure 19D The same process operation (or steps).

[0216] exist Figures 18A to 18E and Figures 19A to 19F For ease of description, Figures 3 to 5 The recessed patterns IP1-1, IP1-2, and IP1-3 shown in the diagram are shown and described as the first recessed pattern IP1, the light-emitting elements LD1-1, LD2-1, and LD3-1 shown in the diagram are shown and described as the first light-emitting element LD1, and the light-emitting elements LD1-2, LD2-2, and LD3-2 shown in the diagram are shown and described as the second light-emitting element LD2. Figure 19F The first electrodes 93a and 93b and Figures 18A to 18E The first electrode E1 in the middle is the same, and Figure 19F The second electrodes 91a and 91b with Figures 18A to 18E The second electrode E2 is the same.

[0217] exist Figures 19A to 19F In the diagram, the cross-sectional view along line II' (on the left) is a cross-sectional view of pixel P along the Y-axis, and the cross-sectional view along line II-II' (on the right) is a cross-sectional view of pixel P along the X-axis. Furthermore, refer to... Figures 18A to 19F The XY coordinate system on the panel and the x′y′ coordinate system on the donor are considered to be independent of each other.

[0218] Reference Figure 18A and Figure 19A The first recessed pattern IP1 and the second recessed pattern IP2 can be alternately disposed on the substrate 10 of the panel in the X-axis direction.

[0219] The first adhesive layer 1145 can be completely disposed on the primary third insulating layer 40'. Due to the fluidity of the first adhesive layer 1145, it can flow into the first recessed pattern IP1 and the second recessed pattern IP2 located at relatively lower positions. Therefore, apart from the first recessed pattern IP1 and the second recessed pattern IP2, the first adhesive layer 1145 can be formed on the upper part of the primary third insulating layer 40' with a relatively small thickness.

[0220] The first recessed pattern IP1 can be the area where light-emitting elements LD1 and LD2 are transferred and attached. The second recessed pattern IP2 can be the area where light-emitting elements LD1 and LD2 are temporarily placed and separated after the first imprinting process. The primary second adhesive layer 1145b formed on the second recessed pattern IP2 can have lower surface adhesion than the primary first adhesive layer 1145a formed on the first recessed pattern IP1. For this purpose, the primary second adhesive layer 1145b can be in a surface-hardened state.

[0221] On the donor, a plurality of first light-emitting elements LD1 and a plurality of second light-emitting elements LD2 can be arranged alternately in the x' axis direction. Each second light-emitting element LD2 on the donor can be configured to correspond to a first recessed pattern IP1, and each first light-emitting element LD1 on the donor can be configured to correspond to a second recessed pattern IP2. Alternatively, each first light-emitting element LD1 on the donor can be configured to correspond to a first recessed pattern IP1, and each second light-emitting element LD2 on the donor can be configured to correspond to a second recessed pattern IP2.

[0222] The first electrode E1 of each of the plurality of first and second light-emitting elements LD1 and LD2 can be aligned (or aligned) in the same direction. That is, the light-emitting area of ​​each of the plurality of first and second light-emitting elements LD1 and LD2 can be aligned in the same direction along an extension line in the longitudinal or width direction of the donor. For example, the light-emitting area of ​​each of the plurality of first and second light-emitting elements LD1 and LD2 can be aligned in the y′ axis direction of the donor.

[0223] The primary first insulating layer 20', primary second insulating layer 30', and primary third insulating layer 40' can be in a state where no contact holes are formed for exposing the pixel driving circuit PD and the common power line 15.

[0224] Reference Figure 18B and Figure 19B The panel and the donor can be aligned, and a first imprinting process (or procedure) can be performed. Multiple first and second light-emitting elements LD1 and LD2 can be transferred from the donor to the panel. For example, the second light-emitting element LD2 can be transferred to the primary first adhesive layer 1145a of the first recessed pattern IP1, and the first light-emitting element LD1 can be placed on the primary second adhesive layer 1145b of the second recessed pattern IP2.

[0225] Reference Figure 18C and Figure 19CThe first light-emitting element LD1, transferred to the primary second adhesive layer 1145b, can be bonded to the donor. This is because the adhesion of the primary second adhesive layer 1145b is relatively low. In the panel, due to the adhesion of the primary first adhesive layer 1145a, the second light-emitting element LD2 can be retained on the primary first adhesive layer 1145a of the first recessed pattern IP1.

[0226] Reference Figure 18D The donor can remain parallel to the panel and rotate 180 degrees counterclockwise. The positions of the first electrode E1 and the second electrode E2 of each first light-emitting element LD1 on the donor can be reversed.

[0227] Reference Figure 18E and Figure 19D The first light-emitting element LD1 can be transferred onto the panel. Each first light-emitting element LD1 can be transferred onto the primary first adhesive layer 1145a of the first recessed pattern IP1, while being spaced apart from the second light-emitting element LD2 by a first distance D1.

[0228] Reference Figure 19E An etching process can be performed to improve the contact capability of the first electrodes 93a, 93b and the second electrodes 91a, 91b. In addition to the first recessed pattern IP1 and the second recessed pattern IP2, the first adhesive layer 1145 located above the primary third insulating layer 40' can be removed. The first light-emitting element LD1 and the second light-emitting element LD2 can be used as masks to remove the area of ​​the primary first adhesive layer 1145a that does not overlap with the light-emitting elements LD1 and LD2, thereby forming the first adhesive layer 45.

[0229] The first adhesive layer 45 may have a groove H formed in a region that does not overlap with the first light-emitting element LD1 and the second light-emitting element LD2. The primary second adhesive layer 1145b may be etched to a thickness similar to that of the first adhesive layer 45 to form the second adhesive layer 47.

[0230] Reference Figure 19F A fourth insulating layer 50 and a fifth insulating layer 60 can be formed on a substrate 10 on which a first adhesive layer 45 and a second adhesive layer 47 are formed. A contact hole CH configured to expose a portion of a common power line 15 and a portion of a pixel driving circuit PD can be formed through the first insulating layer 20, the second insulating layer 30, the fourth insulating layer 40, and the fourth insulating layer 50. Next, a first pixel electrode 55a and a second pixel electrode 55b, a first common electrode 51a and a second common electrode 51b, a sixth insulating layer 70, and a transparent buffer layer 80 can be sequentially formed on the substrate 10 on which the fifth insulating layer 60 is formed.

[0231] As described above, the display panel of this application can employ a two-stage imprinting method to transfer pairs of light-emitting elements LD1 and LD2 that are set (or oriented) in different directions by configuring a second recessed pattern IP2.

[0232] If, for a pair of light-emitting elements including a first light-emitting element and a second light-emitting element, the first light-emitting element disposed on the wafer along a first direction is aligned on the donor and then transferred to the panel, and the second light-emitting element disposed on the wafer along a second direction is aligned on the donor and then transferred to the panel, then the alignment process from the wafer to the donor may take a relatively long time.

[0233] In this application, by configuring the second recessed pattern IP2, all light-emitting elements on the wafer can be aligned on the donor at one time (or simultaneously), and pairs of light-emitting elements can be arranged in different directions. Therefore, the display panel of this application can have improved productivity (suppressing capacity decline). In other words, the display panel of this application can allow for an increase in the number of panels that can be produced within a specific time period.

[0234] By employing a double-imprinting method, the display panel of this application allows pairs of light-emitting elements arranged in different directions to be arranged close together at a first distance, which is less than the binocular resolution at the viewing distance, thereby preventing the viewer from perceiving defects caused by flaws.

[0235] According to one embodiment of this application, the display panel can prevent the viewer from perceiving defects caused by flaws.

[0236] Furthermore, the display panel according to one embodiment of this application can improve productivity during the process of transferring light-emitting elements.

[0237] Furthermore, the display panel according to one embodiment of this application can prevent the light-emitting elements from being excessively transferred onto the panel.

[0238] The effects of this application are not limited to those described above, and those skilled in the art to which the technical concept of this application pertains can clearly understand from the following description other effects not mentioned.

[0239] Although embodiments of the present invention have been described in detail above with reference to the accompanying drawings, the present invention is not limited to these embodiments and various changes and modifications can be made without departing from the technical spirit of the present invention.

[0240] Therefore, the embodiments disclosed herein are to be considered as descriptions of the technical spirit of the invention rather than as limitations, and the scope of the technical spirit of the invention is not limited by these embodiments.

[0241] Therefore, the above embodiments should be understood as exemplary and not as limiting in any way.

[0242] The scope of this invention should be interpreted by the appended claims, and all technical spirit within the scope of its equivalents should be interpreted as being included within the scope of this invention.

Claims

1. A display panel comprising: A substrate having a plurality of pixels, each of the plurality of pixels having a first pattern area and a second pattern area surrounding the first pattern area; An insulating layer is disposed on the substrate and includes a first recessed pattern disposed in the first pattern region; as well as A pair of light-emitting elements are disposed on a first recessed pattern of the insulating layer. The first recessed pattern has a length in a first direction and a length in a second direction different from the first direction, and The respective light-emitting areas of the paired light-emitting elements are offset in different directions relative to the extension line from the center of the first recessed pattern in the first direction or the second direction.

2. The display panel according to claim 1, wherein, The display panel has a plane with a longitudinal direction and a width direction, and a cross-section in the thickness direction. The shortest distance between the centers of adjacent pixels in the vertical or width direction of the display panel is set as the first pitch. The shortest distance between the centers of the paired light-emitting elements is set as a first distance, and The first distance is less than or equal to 1 / 2 of the first pitch.

3. The display panel according to claim 2, wherein, The first distance is less than or equal to 1 / 10 of the first pitch.

4. The display panel according to claim 2, wherein, The paired light-emitting elements are arranged side by side along the width direction of the display panel, and The respective light-emitting areas of the paired light-emitting elements are arranged to face each other.

5. The display panel according to claim 4, wherein, The insulating layer includes a plurality of first recessed patterns in a plurality of first pattern regions and a plurality of second recessed patterns in a second pattern region, the plurality of first recessed patterns being spaced apart from each other in the longitudinal direction and a second recessed pattern being provided on one side of each of the plurality of first recessed patterns in the width direction.

6. The display panel according to claim 2, wherein, The paired light-emitting elements are arranged side by side in the longitudinal direction of the display panel, and The corresponding light-emitting areas of the paired light-emitting elements are arranged along a diagonal direction.

7. The display panel according to claim 6, wherein, The insulating layer includes a plurality of first recessed patterns in a plurality of first pattern regions and a plurality of second recessed patterns in a second pattern region, the plurality of first recessed patterns being spaced apart from each other in the longitudinal direction, and a second recessed pattern being provided between the plurality of spaced-apart first recessed patterns.

8. The display panel according to claim 1, further comprising a first adhesive layer disposed between the first recessed pattern of the insulating layer and the paired light-emitting elements, in, The first adhesive layer includes: The upper surface that is in contact with the paired light-emitting elements; The lower surface in contact with the insulating layer; and A recess, located around the paired light-emitting elements, includes a bottom surface between the upper and lower surfaces and a side surface between the upper and bottom surfaces. A first thickness is formed between the lower surface and the bottom surface, and A second thickness greater than the first thickness is formed between the upper surface and the lower surface.

9. The display panel according to claim 8, wherein, The insulating layer also includes a second recessed pattern disposed on one side of the first recessed pattern in the second pattern region.

10. The display panel according to claim 9, wherein, The paired light-emitting elements are miniature light-emitting diodes, and the second recessed pattern serves as a space where the paired light-emitting elements are temporarily transferred during the imprinting process of the paired light-emitting elements.

11. The display panel according to claim 9, wherein, The first recessed pattern is provided as a plurality of first recessed patterns. The shortest distance between the centers of the plurality of first recessed patterns is set as the second pitch. The shortest distance between the centers of the first recessed pattern and the second recessed pattern is set as the second distance, and The second distance is less than or equal to 1 / 2 of the second pitch.

12. The display panel of claim 9, further comprising a second adhesive layer located on the second recessed pattern of the insulating layer, in, The second adhesive layer includes: a lower surface in contact with the insulating layer; and an upper surface opposite to the lower surface of the second adhesive layer, and A third thickness, less than the second thickness, is formed between the lower surface and the upper surface of the second adhesive layer.

13. The display panel according to claim 9, wherein, The first recessed pattern includes a 1-1 recessed pattern and a 1-2 recessed pattern. The insulating layer further includes a protruding pattern disposed between the 1-1 recessed pattern and the 1-2 recessed pattern in the first pattern area, and The paired light-emitting elements are respectively disposed in the 1-1 recessed pattern and the 1-2 recessed pattern.

14. The display panel according to claim 13, wherein, The protruding pattern is integrally formed with the insulating layer.

15. The display panel according to claim 13, wherein, The area of ​​each of the 1-1 recessed pattern and the 1-2 recessed pattern is greater than the area of ​​the second recessed pattern.

16. The display panel according to claim 9, wherein, The insulating layer further includes a first dummy recessed pattern disposed in the second pattern region, and The second recessed pattern and the first dummy recessed pattern are disposed on one side of the first recessed pattern to correspond to each pair of light-emitting elements.

17. The display panel according to claim 16, wherein, The display panel has a plane with a longitudinal direction and a width direction, and a cross-section in the thickness direction. The insulating layer further includes a second dummy recessed pattern disposed in the second pattern region, and The second dummy recessed pattern is disposed on the plane to surround the first recessed pattern, the second recessed pattern and the first dummy recessed pattern.

18. A method for manufacturing a display panel, comprising: The first step of preparing a substrate having an insulating layer including a first recessed pattern thereon; The second step is to form a first adhesive layer on the first recessed pattern; The third step is to prepare a donor on which a first light-emitting element and a second light-emitting element are disposed; The fourth step is to combine the donor to the substrate so that the first light-emitting element and the second light-emitting element are combined to the first recessed pattern; as well as The fifth step is to detach the donor from the substrate. The first recessed pattern has a length in a first direction and a length in a second direction different from the first direction, and The respective light-emitting areas of the first light-emitting element and the second light-emitting element are offset in different directions relative to the extension line from the center of the first recessed pattern in the first direction or the second direction.

19. The method of claim 18, wherein: In the first step, a substrate having an insulating layer having a first recessed pattern and a second recessed pattern formed thereon is prepared. In the second step, a first adhesive layer is formed on the first recessed pattern, and a second adhesive layer is formed on the second recessed pattern, wherein the second adhesive layer has lower adhesion than the first adhesive layer. The fourth step also includes: The first sub-step involves aligning the donor with the substrate such that the first light-emitting element corresponds to the first adhesive layer and the second light-emitting element corresponds to the second adhesive layer. Perform the second sub-step of the first imprinting of the donor onto the substrate; The third sub-step involves detaching the donor from the substrate while keeping the second light-emitting element attached to the donor; The fourth sub-step involves rotating the donor 180 degrees while maintaining its orientation toward the substrate. Perform a second imprinting of the donor, rotated 180 degrees, onto the substrate to space the second light-emitting element from the first light-emitting element and correspond to the fifth sub-step of the first adhesive layer; and The sixth sub-step involves detaching the donor from the substrate.

20. The method according to claim 19, wherein, In the third step, the respective light-emitting areas of the first and second light-emitting elements are offset in the same direction relative to the extension line in the longitudinal or width direction of the donor.

21. The method according to claim 19, wherein, The display panel is formed as a plane having a vertical and a width direction, and a cross-section in the thickness direction, and also includes multiple pixels. Each of the plurality of pixels includes the first recessed pattern and the second recessed pattern. The shortest distance between the centers of adjacent pixels in the longitudinal or width direction of the display panel is set as the first pitch. The shortest distance between the centers of the first light-emitting element and the second light-emitting element is set as the first distance, and The first distance is less than or equal to 1 / 2 of the first pitch.

22. The method according to claim 21, wherein, The first light-emitting element and the second light-emitting element are arranged in the width direction of the display panel, and The corresponding light-emitting areas of the first light-emitting element and the second light-emitting element are arranged to face each other.

23. The method according to claim 21, wherein, The first light-emitting element and the second light-emitting element are arranged in the longitudinal direction of the display panel, and The corresponding light-emitting areas of the first light-emitting element and the second light-emitting element are arranged along a diagonal direction.

24. The method according to claim 21, wherein, The first recessed pattern is provided as a plurality of first recessed patterns. The shortest distance between the centers of the plurality of first recessed patterns is set as the second pitch. The shortest distance between the centers of the first recessed pattern and the second recessed pattern is set as the second distance, and The second distance is less than or equal to 1 / 2 of the second pitch.

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