A method for preparing and analyzing a high-power bare chip failure analysis sample

Abstract

This application relates to the field of semiconductor technology and provides a method for preparing and analyzing high-power bare chip failure analysis samples. The method includes: fixing the back surface of the high-power bare chip under test to the patch area of ​​a carrier substrate; wire bonding the functional electrode area on the amorphous back surface of the chip to the lead pads of the carrier substrate; preparing a polymer encapsulation layer on the amorphous back surface to obtain a molded high-power bare chip; peeling the molded high-power bare chip from the patch area of ​​the carrier substrate; grinding, fine polishing, and thinning the back surface to obtain the target failure analysis sample; powering the target failure analysis sample by connecting the lead pads outside the back surface area; observing the back surface area of ​​the target failure analysis sample to determine the failure location. This application not only avoids high-power bare chips being broken down or burned by high voltage and high current in failure analysis scenarios, but also significantly improves the sample preparation efficiency and quality of high-power bare chip failure samples.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a method for preparing and analyzing samples for failure analysis of high-power bare chips. Background Technology

[0002] High-power semiconductor devices, as core components of power electronic equipment, are widely used in new energy vehicles, smart grids, wind power generation, photovoltaic power generation and industrial control, and are key components for achieving efficient conversion and utilization of electrical energy.

[0003] For failure analysis of conventional packaged high-power semiconductor devices, the device's packaging structure can withstand high voltage and current stress, providing a certain degree of protection for the internal chip. However, for unpackaged high-power bare chips, directly applying high voltage and high current during failure analysis can easily lead to permanent failures such as chip breakdown and burnout, severely affecting the accuracy and validity of the failure analysis results.

[0004] Therefore, how to prevent high-power bare chips from being broken down and burned by high voltage and high current during failure analysis, while ensuring that the constructed temporary test system does not introduce additional failure factors, does not interfere with the electrical signal transmission, temperature field distribution and failure point observation required for failure analysis, and can be adapted to typical failure analysis scenarios such as parameter testing, thermal imaging analysis and optical emission microscopy detection, has become one of the technical problems that urgently need to be solved in this field. Summary of the Invention

[0005] In view of this, this application provides a method for preparing and analyzing samples for failure analysis of high-power bare chips. The aim is to avoid breakdown or burnout of high-power bare chips due to high voltage and current during the failure analysis process, while ensuring that the constructed temporary test system does not introduce additional failure factors, does not interfere with the electrical signal transmission, temperature field distribution and failure point observation required for failure analysis, and can be adapted to typical failure analysis scenarios such as parameter testing, thermal imaging analysis and optical emission microscopy detection.

[0006] To achieve the above-mentioned objectives, this application provides a method for preparing and analyzing high-power bare chip failure analysis samples, including: The back side of the high-power bare chip under test is fixed in the patch area of ​​the carrier substrate; The functional electrode area on the amorphous back side of the high-power bare chip under test is wire-connected to the lead pads of the carrier substrate. A polymer encapsulation layer is prepared on the amorphous back side of the high-power bare chip to be tested after wire bonding to obtain a plastic-encapsulated high-power bare chip; wherein, the polymer encapsulation layer completely covers the amorphous back side, and the thickness of the polymer encapsulation layer exceeds the highest point of the lead wire arc between the electrode area and the lead pad, and the amorphous back side is set opposite to the crystal back side. The plastic-encapsulated high-power bare chip is peeled off from the mounting area of ​​the carrier substrate; The back side of the plastic-encapsulated high-power bare chip is ground, finely polished, and thinned to obtain the target failure analysis sample. The target failure analysis sample includes the back side region and the adhesive layer region. The back side region meets the preset flatness and thickness requirements, and the lead solder joints in the outer region of the back side are exposed. The lead solder joints connecting the outer region of the crystal back are used to power the target failure analysis sample. The crystal back region of the target failure analysis sample is observed using an infrared microscope to determine the failure location of the target failure analysis sample.

[0007] The beneficial effects of the technical solution provided in this application include at least the following: fixing the back surface of the high-power bare chip under test to the patch area of ​​the carrier substrate; connecting the functional electrode area on the amorphous back surface of the high-power bare chip under test to the lead pads of the carrier substrate via wire bonding; and preparing a polymer encapsulation layer on the amorphous back surface of the high-power bare chip under test after wire bonding to obtain a molded high-power bare chip; wherein the polymer encapsulation layer completely covers the amorphous back surface, and the thickness of the polymer encapsulation layer exceeds the highest point of the lead wire arc between the electrode area and the lead pad, and the amorphous back surface... The die and back sides are positioned opposite each other. The high-power molded die is peeled off from the mounting area of ​​the substrate. The back side of the high-power molded die is ground, finely polished, and thinned to obtain the target failure analysis sample. The target failure analysis sample includes a back surface area and a binder layer area. The back surface area meets the preset flatness and thickness requirements, and the lead solder joints in the outer area of ​​the back surface are exposed. The lead solder joints in the outer area of ​​the back surface are connected to power the target failure analysis sample. The back surface area of ​​the target failure analysis sample is observed using an infrared microscope to determine the failure location. Using the above method, the high-power molded die can be peeled off from the mounting area of ​​the substrate as a whole, and the back surface of the die can be directly ground, finely polished, and thinned, eliminating the grinding step of the substrate and significantly shortening the sample preparation time. At the same time, it can avoid problems such as uneven silicon substrate thickness, scratches on the back surface, and even chip breakage caused by manual grinding, which is beneficial to ensuring the subsequent electrical testing and microscopic observation results. In addition, the process of peeling the plastic-encapsulated high-power bare chip from the mounting area of ​​the carrier substrate will not damage the carrier substrate, enabling the carrier substrate to be recycled and reused, reducing the consumption of polishing consumables, and effectively reducing the sample preparation cost. Attached Figure Description

[0008] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0009] Figure 1 This is a schematic flowchart of a high-power bare chip failure analysis sample preparation and analysis method provided in an embodiment of this application; Figure 2 This is a schematic diagram of the structure of a carrier substrate provided in an embodiment of this application; Figure 3 This is a physical diagram of a carrier substrate provided in one embodiment of this application; Figure 4 This is a schematic diagram of the adhesive layer area and the location of the lead solder joints in a specific embodiment of this application. Figure 5 This is a physical image of the target failure analysis sample provided in one embodiment of this application; Figure 6 This is a partial structural image of a target failure analysis sample that was successfully prepared according to an embodiment of this application, under an infrared microscope. Figure 7 This is the failure analysis result of a target failure analysis sample that was successfully prepared according to an embodiment of this application; Figure 8 This is a partial structural image of a target failure analysis sample with sample preparation failure provided in an embodiment of this application under an infrared microscope; Figure 9 This is a schematic diagram of coating black adhesive on the amorphous back surface of the high-power bare chip under test in Embodiment 1 of this application; Figure 10 This is a schematic diagram of manually bending the substrate by hand in Embodiment 1 of this application; Figure 11 This is a schematic diagram of obtaining a plastic-encapsulated high-power bare chip from a carrier substrate according to Embodiment 1 of this application; Figure 12 This is a physical image of the first sample prepared in Example 1 of this application; Figure 13 This is a photograph of the polished sample obtained in Example 1 of this application; Figure 14 This is a schematic diagram of cutting a plastic-encapsulated high-power bare chip in Comparative Example 1; Figure 15 This is a surface state diagram of the crystal back region of the target failure analysis sample prepared in Comparative Example 2. Figure 16 This is a surface state diagram of the crystal back region of the target failure analysis sample prepared in Comparative Example 3. Figure 17 This is a surface state diagram of the crystal back region of the target failure analysis sample prepared in Comparative Example 4. Detailed Implementation

[0010] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with embodiments. It should be understood that the specific embodiments described herein are only for explaining this application, but the implementation of this application is not limited thereto.

[0011] Unless otherwise defined, the technical terms used in the following embodiments have the same meanings as commonly understood by those skilled in the art to which this application pertains. Unless otherwise specified, the experimental reagents used in the following embodiments are conventional biochemical reagents; the amounts of experimental reagents used are, unless otherwise specified, the amounts used in conventional experimental operations; and the experimental methods used are, unless otherwise specified, conventional methods.

[0012] Figure 1 This is a schematic flowchart illustrating a method for preparing and analyzing samples for high-power bare chip failure analysis, as provided in an embodiment of this application. Please refer to... Figure 1 The method includes the following steps: S101. Fix the back side of the high-power bare chip under test to the patch area of ​​the carrier substrate.

[0013] High-power bare dies under test (BBDs) refer to high-power semiconductor devices that exist directly in die form without packaging. They mainly include bare dies for silicon-based power devices (such as IGBT bare dies, power MOSFET bare dies, thyristors, etc.), bare dies for third-generation semiconductor power devices (such as SiC MOSFET bare dies (silicon carbide MOSFETs), SiC SBD bare dies (silicon carbide Schottky diodes), etc.), and other types of high-voltage, high-current semiconductor power bare dies.

[0014] Figure 2 This is a schematic diagram of the structure of a carrier substrate provided in an embodiment of this application. Figure 3 This is a physical diagram of a carrier substrate provided in one embodiment of this application. Please refer to... Figures 2-3 The carrier substrate 200 includes a carrier plate 201 and a patch area 202 disposed on the carrier plate 201. The carrier substrate 200 is preferably a substrate with high thermal conductivity and high insulation properties, such as an aluminum nitride ceramic substrate or a silicon carbide substrate. Such carrier substrates have advantages such as good heat dissipation, good pressure resistance, good mechanical support strength, and the ability to accommodate test samples of different sizes.

[0015] In some embodiments, a temporary adhesive layer 203 can be provided on the bonding area 202 of the carrier substrate 200 to provide adhesive support for subsequent chip bonding, while initially ensuring the insulation between the chip and the carrier board 201, avoiding poor contact or leakage risks after bonding.

[0016] Preferably, the temporary adhesive layer 203 is a UV (ultraviolet) release adhesive layer. This UV release adhesive layer is formed by curing UV release adhesive under specific wavelength ultraviolet light irradiation and specific heating conditions. After curing, it possesses high adhesive strength, meeting the mechanical fixation requirements of chips and other devices during processing and testing. When separation is required, re-irradiation with specific wavelength ultraviolet light and appropriate heating conditions can alter the adhesive layer structure, causing it to become brittle or degraded, thereby achieving non-destructive separation of the device from the substrate and avoiding damage to the device caused by forced disassembly. Simultaneously, the amount of adhesive residue after separation is low, preventing solvent contamination of the substrate and chip surface.

[0017] In some implementations, please refer to Figure 3 The above-mentioned step S101 specifically includes: coating a UV adhesive in the patch area 202 of the carrier substrate 200, placing the back side of the high-power bare chip to be tested on the patch area 202, irradiating it with a UV lamp with a wavelength of 365 nm and an energy density of 2000 mJ / cm², and heating and curing it at 100°C for 60 seconds, so as to form a temporary adhesive layer 203 between the back side of the high-power bare chip to be tested and the patch area 202 of the carrier substrate 200.

[0018] In actual operation, firstly, the back side of the high-power bare chip to be tested is placed on the UV adhesive 2021 of the patch area 202 of the carrier substrate 200; then, the edge of the high-power bare chip to be tested is held with plastic tweezers, and the chip is gently pressed down to allow the UV adhesive 2021 to spread along the bonding surface between the carrier plate 201 and the back side of the chip (it should not overflow too much and cover the chip surface). After being irradiated with a UV lamp with a wavelength of 365 nm and an energy density of 2000 mJ / cm², it is heated and cured at 100 ℃ for 60 seconds to form a temporary adhesive layer between the back side of the high-power bare chip to be tested and the patch area 202 of the carrier substrate 200, thereby fixing the chip in the patch area 202 of the carrier substrate 200.

[0019] S102. Connect the functional electrode area on the amorphous back side of the high-power bare chip under test to the lead pads of the carrier substrate by wire bonding.

[0020] Please see Figure 4The functional electrode region refers to the two core functional electrode regions on the amorphous back side of the high-power bare chip under test. Specifically, it is the pad region 401 of the gate (G) and source (S) of the power device (such as MOSFET, IGBT and other common high-power devices). It is the key part to realize the electrical signal control and current output of the device.

[0021] The functional electrode area is usually located on the amorphous back side (unmounted side) of the bare chip. It exists in the form of metallized pads (mostly conductive materials such as aluminum and copper) and has a clear area boundary, which facilitates subsequent wire bonding interconnection.

[0022] The Gate electrode is used to input control signals, enabling the device to turn on and off; the Source electrode is the main channel for current output / input, and both need to be connected to the pin pads 402 of the carrier plate 201 of the carrier substrate 200 via wire bonding. Figure 4 Only when the number 403 in the diagram represents the lead wire can a complete conductive circuit be formed to meet the requirements of subsequent high-voltage testing.

[0023] S103. A polymer encapsulation layer is prepared on the amorphous back side of the high-power bare chip to be tested after wire bonding to obtain a plastic-encapsulated high-power bare chip; wherein, the polymer encapsulation layer completely covers the amorphous back side, and the thickness of the polymer encapsulation layer exceeds the highest point of the lead wire arc between the electrode area and the pin pad, and the amorphous back side is set opposite to the crystal back side.

[0024] In some embodiments, step S103 specifically includes: A polymer adhesive is coated on the amorphous back side of the high-power bare chip to be tested; The high-power bare chip under test after adhesive coating is defoamed and baked to cure, so that the polymer adhesive on the amorphous back side of the high-power bare chip under test is completely cured to form a polymer encapsulation layer, resulting in a plastic-encapsulated high-power bare chip. The polymer encapsulation layer covers the lead solder joints in the outer area of ​​the crystal back side.

[0025] The polymer encapsulation layer is preferably made of a material with high thermal conductivity, high insulation, and high temperature resistance, such as a modified epoxy resin layer (with added curing agent, insulating filler, etc.), an organosilicon layer, or a polyimide layer.

[0026] As an example, the polymer encapsulating adhesive layer covers the entire pin pad area of ​​the carrier substrate 200 (e.g., Figure 4(The area indicated by the yellow dashed box). Typically, the coverage area of ​​the polymer encapsulation adhesive layer extends to a region 0.25 cm beyond the edge of the high-power bare chip under test. For example, when the chip size is 1cm × 1cm, the coverage area of ​​the polymer adhesive layer is 1.5cm × 1.5cm. This ensures that the adhesive layer completely covers the back side and edge areas of the chip, effectively improving the structural stability and fixation reliability of the chip during subsequent grinding, polishing, and electrical testing, and avoiding chip edge lifting, uneven stress, or edge cracking due to insufficient adhesive layer coverage. At the same time, the moderately extended adhesive layer can evenly disperse mechanical and thermal stress, preventing local stress concentration during chip processing and further reducing the risk of chip breakage. By reasonably controlling the extended size, sufficient coverage and reliable fixation can be ensured without material waste due to excessive adhesive layer area, thus balancing process reliability and economy.

[0027] As another example, the polymer adhesive layer covers at least the lead bonding joints 402 on the outer surface of the chip's back surface, effectively encapsulating and protecting them. This prevents the lead bonding joints from being damaged by external forces, friction, or stress during subsequent machining processes such as grinding, polishing, and thinning, thus ensuring the integrity of the wire bonding structure and the reliability of the electrical connection. Simultaneously, the adhesive layer isolates the solder joints from moisture, dust, and contaminants in the external environment, reducing the risk of oxidation and corrosion, and further ensuring the accuracy of subsequent electrical testing and failure analysis results.

[0028] By forming a polymer encapsulation layer on the amorphous back side of the high-power bare chip under test after wire bonding is completed, the encapsulation protection effect of conventional plastic-encapsulated devices is simulated. This achieves high voltage and high temperature protection for the high-power bare chip under test and its leads, avoiding chip breakdown or lead damage caused by high voltage and high current during subsequent testing. At the same time, the coverage and thickness of the encapsulation layer meet the testing requirements.

[0029] S104. Peel the plastic-encapsulated high-power bare chip from the mounting area of ​​the carrier substrate.

[0030] By utilizing the tough deformation of the carrier plate, combined with the rigidity of the polymer encapsulation layer and the softness of the temporary adhesive layer (UV debonding layer), uniform microcracks can be formed between the polymer encapsulation layer and the carrier substrate by manually or mechanically applying force to bend it. Subsequently, after being irradiated with ultraviolet light of a specific wavelength and kept at a preset temperature under specific heating conditions (usually about 90 seconds), the UV debonding layer can be made brittle or degraded, thereby achieving non-destructive separation of the chip from the carrier substrate.

[0031] This method can obtain independent plastic-encapsulated high-power bare chips, while ensuring that the substrate remains intact and reusable. Only a small amount of UV adhesive remains on the back of the chip, which is easy to remove through subsequent grinding, thus shortening the sample preparation cycle.

[0032] S105. Grind, finely polish, and thin the back side of the plastic-encapsulated high-power bare chip to obtain the target failure analysis sample. The target failure analysis sample includes the back side region and the adhesive layer region. The back side region meets the preset flatness and thickness requirements, and the lead solder joints in the outer region of the back side are exposed.

[0033] As an example, please refer to Figure 5 After the above grinding, fine polishing, and thinning processes, the target failure analysis sample is obtained. The crystal back region 502 of this target failure analysis sample meets the preset flatness and thickness requirements. Figure 5 The gray area in the image represents the adhesive layer area 501. After grinding, fine polishing, and thinning, the wire ends 503 (corresponding to the wire bonding in step S102) are removed. Figure 4 The lead solder joint (shown as number 402) is now exposed.

[0034] In some embodiments, step S105 specifically includes: The back side of the plastic-encapsulated high-power bare chip was ground to remove the temporary adhesive layer remaining between the back side of the chip and the surface mount area, thus obtaining the first sample. The back side of the first sample was finely polished to obtain the second sample; The second sample was thinned to obtain the target failure analysis sample.

[0035] In some embodiments, the back side of the molded high-power bare die is ground to remove residual temporary adhesive layer on the back side, resulting in a first sample, comprising: The back side of the molded high-power bare chip is polished using silicon carbide sandpaper; When the area of ​​the temporary adhesive layer remaining on the back side of the plastic-encapsulated high-power bare chip is reduced to less than 5% of the area of ​​the back side, the grinding process is stopped. Then, the plastic-encapsulated high-power bare chip is ultrasonically cleaned and dried to obtain the first sample.

[0036] The above technical solution removes the residual temporary adhesive layer on the back side of the plastic-encapsulated high-power bare chip by grinding, providing a clean surface for subsequent fine polishing processes. At the same time, it can avoid the residual adhesive layer from interfering with chip thickness measurement and subsequent failure analysis.

[0037] In some embodiments, the back surface of the first sample is finely polished to obtain the second sample, including: The back side of the first sample was polished at a constant speed using diamond polishing slurry, with a polishing speed of 100~150 r / min and a polishing time of 2~3 minutes. During the uniform polishing process, the surface condition of the back side of the first sample is monitored at preset time intervals; When the surface of the back side of the first sample is a uniform mirror finish and there are no scratches or residual impurities, polishing is stopped, and a polished sample is obtained. The polished sample was ultrasonically cleaned and dried to obtain the second sample.

[0038] The above technical solution, by performing fine polishing on the back side of the first sample, can further remove the trace amount of UV adhesive remaining on the back side of the chip, so that the back side of the chip achieves a mirror effect, ensuring the clarity and accuracy of subsequent analysis.

[0039] In some embodiments, the second sample is thinned to obtain the target failure analysis sample, including: The second sample was subjected to automatic grinding, and the thickness of the second sample was monitored in real time during the automatic grinding process. The process parameters for automatic grinding were: grinding speed of 15~65 Kr / min and grinding pressure of 0.8 N. When the thickness of the second sample is reduced to the target thickness, grinding is stopped, and the ground second sample is polished, cleaned, and dried to obtain the target failure analysis sample. The polishing process parameters are: polishing speed of 50~75 Kr / min, polishing pressure of 0.8~1 N, and polishing times of 3~5 times.

[0040] Step S106: Power on the target failure analysis sample by connecting the lead solder joints of the outer region of the crystal back and observe the crystal back region of the target failure analysis sample using an infrared microscope to determine the failure location of the target failure analysis sample.

[0041] As an example, please refer to Figures 6-7 If the crystal back region of the target failure analysis sample meets the preset flatness and thickness requirements, the failure anomaly location can be quickly and accurately located under an infrared microscope.

[0042] As another example, please refer to Figure 8 If the crystal back region of the target failure analysis sample does not meet the preset flatness and thickness requirements, two shadow positions will be seen under an infrared microscope. However, it is not possible to accurately determine whether these two shadow positions are abnormal positions caused by device failure or abnormal positions caused by unevenness or scratches on the crystal back.

[0043] Through the above preparation steps, the obtained failure analysis samples can meet the requirements of failure analysis, enabling rapid and accurate location of abnormal failure sites during the failure analysis process, while effectively improving the preparation efficiency of failure analysis samples. For example, using UV de-adhesive to quickly fix the bare chip to the patch area of ​​the carrier substrate facilitates the bonding of the test point wires on the bare chip to the lead pads of the carrier substrate, and also facilitates the encapsulation protection of the back side of the high-power bare chip under test after bonding. This prevents the high-power bare chip from being broken down or burned due to high voltage and high current when electrical signals are applied to the test points.

[0044] By combining ultraviolet light irradiation with heating, the plastic-encapsulated high-power bare chip can be non-destructively peeled off from the substrate mounting area. This not only improves the overall sample preparation efficiency but also avoids mechanical damage to the sample, ensuring the accuracy and completeness of subsequent failure analysis and observation.

[0045] The preparation method provided in this application can be applied to the preparation of failure analysis samples of high-power bare chips or wafers.

[0046] This application has undergone multiple experiments, and some of the test results are presented here for reference to further describe the invention in detail. The following is a detailed description in conjunction with specific embodiments.

[0047] Example 1 The first step involves attaching the back side of the high-power bare chip to be tested onto the UV adhesive 2021 in the patch area of ​​the carrier substrate. Using plastic tweezers, hold the chip edge and gently press down on the chip to allow the UV adhesive to spread along the bonding surface between the patch area and the back side of the chip (avoid excessive overflow that covers the chip surface). Irradiate the chip with a UV lamp at a wavelength of 365 nm and an energy density of 2000 mJ / cm², and then heat-cur it at 100 °C for 60 seconds to form a temporary adhesive layer between the back side of the high-power bare chip to be tested and the patch area of ​​the carrier substrate, thus fixing the high-power bare chip to be tested in the patch area of ​​the carrier substrate.

[0048] The second step involves connecting the functional electrode regions (gate and source) on the amorphous back side of the high-power bare chip under test to the lead pads of the substrate via wire bonding to form a complete conductive circuit.

[0049] Step 3, please refer to Figure 9After the second step of wire bonding, the high-power bare chip to be tested is placed on a clean workbench, and surface dust is gently blown away with a dust-free air gun. Then, using a precision dispenser, black glue (such as modified epoxy resin) is slowly applied along the edge of the chip, with the coverage area controlled to extend approximately 0.25cm outwards from the chip's perimeter (e.g., for a chip size of 1cm × 1cm, the black glue coverage area is 1.5cm × 1.5cm). During the glue application process, the dispensing speed and glue volume are adjusted to ensure uniform black glue thickness, and the thickness of the polymer encapsulation adhesive layer exceeds the highest point of the lead wire arc between the electrode area and the pin pads, with the adhesive layer thickness controlled at approximately 2 mm (this can be assisted by the height positioning function of the dispensing machine). The aforementioned black glue is a high-temperature resistant, high-insulation semiconductor encapsulation black glue (requiring a breakdown voltage ≥ twice the test voltage, and no softening or deformation at 100℃). Next, the high-power bare chip to be tested after glue application is placed in a vacuum defoaming chamber and evacuated for 5 minutes to remove air bubbles inside the black glue, preventing local electric field concentration caused by air bubbles from affecting high voltage withstand performance. Next, the high-power bare chip to be tested, after removing air bubbles, is placed in a precision oven. The baking temperature is set to 100℃, and the baking time is 1 hour to ensure that the black adhesive is completely cured (avoid oven temperature fluctuations during the curing process to prevent cracking of the black adhesive), forming a polymer encapsulation layer 2022. Finally, the chip is removed, and the surface of the black adhesive is observed to ensure it is smooth, without depressions or cracks, and that the coverage and thickness meet the requirements. The polymer encapsulation layer 2022 is also checked for tight adhesion to the carrier board 201. If the above requirements are met, the fabrication of the plastic-encapsulated high-power bare chip is complete.

[0050] For the fourth step, please refer to [link / reference]. Figures 10-11First, the carrier substrate is manually and slightly bent (e.g., pressing down on the empty spaces at both ends of the carrier substrate with both thumbs and slightly pushing up with the index fingers). Due to the carrier substrate's certain flexibility, it will slightly deform and bend after bending. The polymer encapsulation layer is hard after baking, while the temporary adhesive layer (UV release adhesive layer) between the high-power bare chip and the carrier substrate is slightly soft. After bending, uniform microcracks are formed between the polymer encapsulation layer and the carrier substrate. On this basis, the bending force is slowly increased (still controlled within the carrier substrate's flexibility range), and the arc deformation of the carrier substrate is maintained for 3-5 seconds. The bonding surface between the polymer encapsulation layer and the carrier substrate is observed under a microscope. Under the tensile force of the carrier substrate's deformation, uniform microcracks will gradually appear between the polymer encapsulation layer and the carrier substrate (the width of these microcracks is controlled at 0.1-0.3 mm to facilitate subsequent clamping operations). When the microcracks are observed to be evenly distributed around the polymer encapsulation layer, the bending force is slowly released, allowing the carrier substrate to return to its natural state. At this time, the microcracks will still remain. Next, the sample was irradiated under a UV lamp with a wavelength of 365 nm and an energy density of 4000 mJ / cm², and then subjected to 80°C. Heating at ℃ for 90 seconds to de-adhede the adhesive is followed by using a flat, burr-free plastic pry bar (avoiding scratches on the adhesive or chip with metal tools). Using a microscope, locate the micro-crack between the polymer encapsulation layer and the substrate. Gently insert the tip of the plastic pry bar into the crack (insertion depth controlled at 0.5~1mm, avoiding contact with the chip). Using the pry bar insertion point as a fulcrum, gently apply upward clamping force while slowly moving the pry bar to evenly distribute the clamping force across the bonding surface around the polymer encapsulation layer. Observe the gradual separation of the polymer encapsulation layer from the substrate. When the separation area between the polymer encapsulation layer and the substrate reaches more than 80%, gently pinch the edge of the polymer encapsulation layer and slowly pull upwards to completely peel the high-power molded chip from the mounting area of ​​the substrate. Finally, if there is no residual adhesive in the mounting area of ​​the substrate, it can be reused normally. Inspect the separated high-power molded chip to ensure that the polymer encapsulation layer is undamaged, the wire bonding is unbroken, and only a small amount of UV de-adhesive remains on the back side of the high-power chip.

[0051] In practical applications, one can first manually pry the carrier substrate to create uniform micro-cracks between the polymer encapsulation layer and the carrier substrate, then irradiate it with ultraviolet light, and finally use a pry bar to completely peel the plastic-encapsulated high-power bare chip from the mounting area of ​​the carrier substrate; alternatively, one can first irradiate it with ultraviolet light, then manually pry the carrier substrate to create uniform micro-cracks between the polymer encapsulation layer and the carrier substrate, and finally use a pry bar to completely peel the plastic-encapsulated high-power bare chip from the mounting area of ​​the carrier substrate.

[0052] Step 5: Fix the plastic-encapsulated high-power bare chip obtained in Step 4 onto the grinding fixture, ensuring the back side of the chip faces upwards and the sample is firmly fixed without shaking. Then, select 2000-grit silicon carbide sandpaper (uniform grit, high grinding precision, avoids deep scratches), lay the sandpaper flat on the grinding platform, and wet the sandpaper surface with deionized water. Gently press the fixed sample onto the sandpaper, and move the sample back and forth at a uniform speed along with the arm for grinding. During the grinding process, continuously add deionized water to cool and wash away grinding debris. The grinding time is adjusted according to the amount of UV deadhesive residue (usually about 1 minute). During this time, remove the sample every 5 seconds and observe the UV deadhesive residue on the back side of the chip with a microscope. When the residual UV deadhesive reduces to less than 5% of the chip's back side area, stop the grinding process. Place the ground sample in an ultrasonic cleaner and wash with deionized water for 2 minutes to remove residual grinding debris and UV adhesive residue from the surface. Then place it in an infrared dryer and dry at 60°C for 3 minutes to obtain the first sample (e.g., Figure 12 (As shown).

[0053] Step 6: Fix the first sample on the polishing fixture, ensuring the back side of the chip faces upwards; select diamond polishing slurry (particle size 0.3~0.5μm, selectable according to polishing precision requirements), lay the polishing cloth flat on the polishing machine table, and evenly apply a small amount of diamond polishing slurry; then, turn on the polishing machine, set the polishing speed to 100~150r / min, gently press the sample onto the polishing cloth, and move the sample along an "8" shaped trajectory at a uniform speed for polishing. Continuously replenish the polishing slurry during the polishing process to keep the polishing cloth moist; the polishing time is 2~3 minutes, remove the sample every 30 seconds, gently wipe the back surface of the chip with an alcohol swab, and observe the surface condition under a microscope. When the back surface of the chip exhibits a uniform mirror effect, without any scratches or residual impurities (such as...), the polishing is considered successful. Figure 13 When the time is shown, stop polishing to obtain a polished sample. Finally, place the polished sample in an ultrasonic cleaner and clean it for 5 minutes with a mixture of alcohol and deionized water (volume ratio 1:1) to completely remove polishing solution residue. Then, blow dry the sample surface with a nitrogen gun and place it in a drying oven to dry at room temperature for later use, thus obtaining the second sample.

[0054] Step 7: Measure the initial thickness of the second sample using a precision thickness gauge. Combine this with the target thickness to calculate the required thinning amount. If the chip body of the second sample is confirmed to be undamaged and of uniform thickness, precision grinding can be performed directly. Specifically, fix the chip sample on the special fixture of the X-Prep precision grinding machine, ensuring the second sample is firmly fixed and the target analysis area is directly facing the grinding head. Then, based on the chip material and the required thinning amount, set the grinding speed (generally set to 15~65 Kr / min), grinding pressure (generally set to 0.8 N), and grinding time (calculated from the required thinning amount and grinding rate). Select a high-precision grinding drill bit (such as a 0.7 mm diamond drill) to ensure grinding accuracy. Next, turn on the X-Prep grinding machine and perform automatic precision grinding according to the set parameters. During the grinding process, the equipment will monitor the thickness of the second sample in real time. When the thickness of the second sample reaches the target thickness, grinding will automatically stop. Replace the grinding drill bit with a dedicated polishing head (the drill bit position is a polishing cloth), and set the corresponding polishing parameters (grinding speed of 50~75 Kr / min, grinding pressure of 0.8~1 N). N), polishing 3-5 times, observing the back surface of the second sample under a microscope after each polishing until the back surface of the crystal shows a mirror effect; then, measuring the thickness of the second sample at different locations using a precision thickness gauge (measuring at least 5*5 points) to confirm that the overall thickness is uniform and meets the target requirements; observing the target analysis area under a microscope to ensure there is no grinding damage and the surface is flat; finally, the precision-ground sample is cleaned and dried again to obtain the target failure analysis sample (e.g. Figure 5 (As shown), for later use.

[0055] Comparative Example 1 The first step involves attaching the back side of the high-power bare chip to be tested onto the common adhesive (such as epoxy resin) in the mounting area of ​​the carrier substrate. Using plastic tweezers, hold the edge of the chip and gently press down on it to allow the common adhesive to spread along the bonding surface between the mounting area and the back side of the chip (do not allow excessive overflow to cover the chip surface). Then, heat and cure at 150 °C for 60 min to form a cured adhesive layer between the back side of the high-power bare chip to be tested and the mounting area of ​​the carrier substrate, thus fixing the high-power bare chip to be tested in the mounting area of ​​the carrier substrate.

[0056] The second step is the same as the second step in Example 1.

[0057] The third step is the same as the third step in Example 1.

[0058] For the fourth step, please refer to [link / reference]. Figure 14 The high-power bare chip obtained in the third step is then cut to remove the carrier board area outside the encapsulation range, resulting in a cut sample.

[0059] Fifth, use 400-grit or 1000-grit sandpaper to grind the back side of the cut sample obtained in the fourth step (i.e., the remaining substrate after cutting) to remove the remaining substrate. Then, use 2000-grit sandpaper to continue grinding to remove the residual cured adhesive layer on the back side of the plastic-encapsulated high-power bare chip. Finally, polish the back side of the chip to obtain the target failure analysis sample.

[0060] Using ordinary adhesive to bond and fix the bare high-power chip under test to the patch area of ​​the carrier substrate requires first removing the carrier substrate by grinding, and then polishing the sample. This results in the final failure analysis sample having surface cracks, irregular scratches, and chipping on the crystal back, thus leading to sample preparation failure.

[0061] Comparative Example 2 The first step is the same as the first step in Example 1.

[0062] The second step is the same as the second step in Example 1.

[0063] The third step is the same as the third step in Example 1.

[0064] The fourth step is the same as the fourth step in Example 1.

[0065] The fifth step is basically the same as the fifth step in Example 1, except that: 400-grit sandpaper is used to grind away the residual UV adhesive layer on the back side of the plastic-encapsulated high-power bare chip; finally, the back side of the chip is polished to obtain the target failure analysis sample (e.g., Figure 15 (As shown). From Figure 15 It can be seen that when using 400-grit sandpaper for polishing and removing adhesive, severe mechanical scratches will be generated on the back of the chip; for thinner chips, this process is prone to causing structural failures such as chip breakage.

[0066] Comparative Example 3 The first step is the same as the first step in Example 1.

[0067] The second step is the same as the second step in Example 1.

[0068] The third step is the same as the third step in Example 1.

[0069] The fourth step is the same as the fourth step in Example 1.

[0070] The fifth step is the same as the fifth step in Example 1.

[0071] Step six is ​​essentially the same as step six in Example 1, except that the sample after rough grinding in step five is polished step by step with diamond sandpaper in the order of 3μm, 1μm, and 0.5μm. This process easily produces irregular mechanical scratches on the back of the chip, which adversely affects subsequent microscopic observation (e.g., ...). Figure 16 (As shown).

[0072] Comparative Example 4 The first step is the same as the first step in Example 1.

[0073] The second step is the same as the second step in Example 1.

[0074] The third step is the same as the third step in Example 1.

[0075] The fourth step is the same as the fourth step in Example 1.

[0076] The fifth step is the same as the fifth step in Example 1.

[0077] Step 6 is the same as step 6 in Example 1.

[0078] Step seven is basically the same as step seven in Example 1, except that when grinding the second sample obtained in step six, if the grinding speed is set too high (80 Kr / min) or too low (10 Kr / min), even if the grinding pressure is set to 1 N, chipping defects are still likely to occur on the back of the chip, and in severe cases, chip breakage may occur (e.g. Figure 17 (As shown).

[0079] In summary, the technical solutions provided by the embodiments of this application have at least the following beneficial effects: 1) Improve sample preparation efficiency and analytical accuracy to ensure the quality of failure analysis.

[0080] By eliminating the substrate grinding step and adopting a standardized process of fine polishing and precision grinding for thinning, the preparation time can be shortened, and the problem of uneven thickness of silicon-based samples caused by manual grinding can be avoided, ensuring the subsequent electrical analysis and imaging effects.

[0081] 2) Reduce the risk of sample damage and ensure the reliability of the analytical basis.

[0082] Compared with the traditional grinding process for removing the substrate, the technical solution provided in this application can avoid the risks of chip back being scratched or chip breaking due to factors such as untimely sandpaper replacement, and effectively ensure the integrity of the sample structure.

[0083] 3) Reduce material consumption and lower failure analysis costs.

[0084] During the separation process between the carrier substrate and the high-power chip under test, the carrier substrate will not be damaged. Only a small amount of UV adhesive needs to be removed by light grinding. The carrier substrate can be recycled and reused intact without the need to be ground off as a consumable. At the same time, the grinding process is simplified, the consumption of consumables such as sandpaper is reduced, and the analysis cost is significantly reduced.

[0085] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A method for preparing and analyzing samples for high-power bare chip failure analysis, characterized in that, include: The back side of the high-power bare chip under test is fixed in the patch area of ​​the carrier substrate; The functional electrode area located on the amorphous back side of the high-power bare chip under test is wire-connected to the lead pads of the carrier substrate. A polymer encapsulation layer is prepared on the amorphous back side of the high-power bare chip under test after wire bonding to obtain a plastic-encapsulated high-power bare chip; wherein, the polymer encapsulation layer completely covers the amorphous back side, and the thickness of the polymer encapsulation layer exceeds the highest point of the lead wire arc between the electrode area and the lead pad, and the amorphous back side is disposed opposite to the crystal back side; The plastic-encapsulated high-power bare chip is peeled off from the mounting area of ​​the carrier substrate; The back side of the plastic-encapsulated high-power bare chip is ground, finely polished, and thinned to obtain a target failure analysis sample. The target failure analysis sample includes a crystal back area and an adhesive layer area. The crystal back area meets the preset flatness and thickness requirements, and the lead solder joints of the outer crystal back area are exposed. The lead solder joints connecting the outer region of the crystal back are used to power the target failure analysis sample. The crystal back region of the target failure analysis sample is observed using an infrared microscope to determine the failure location of the target failure analysis sample.

2. The method for preparing and analyzing high-power bare chip failure analysis samples according to claim 1, characterized in that, The back side of the high-power bare chip under test is fixed to the patch area of ​​the carrier substrate, including: A UV adhesive is applied to the patch area of ​​the carrier substrate, and the back side of the high-power bare chip to be tested is placed on the patch area. The chip is then irradiated with a UV lamp with a wavelength of 365 nm and an energy density of 2000 mJ / cm², and heated and cured at 100°C for 60 seconds to form a temporary adhesive layer between the back side of the high-power bare chip to be tested and the patch area of ​​the carrier substrate.

3. The method for preparing and analyzing high-power bare chip failure analysis samples according to claim 1, characterized in that, Peeling the molded high-power bare chip from the mounting area of ​​the carrier substrate includes: Pressure is applied to the carrier substrate to form uniform microcracks between the plastic-encapsulated high-power bare chip and the carrier substrate. Then, it is irradiated under a UV lamp with a wavelength of 365 nm and an energy density of 4000 mJ / cm², and heated at 80 °C for 90 seconds to de-adhere. After that, the plastic-encapsulated high-power bare chip is peeled off from the mounting area of ​​the carrier substrate.

4. The method for preparing and analyzing high-power bare chip failure analysis samples according to claim 1, characterized in that, The coverage area of ​​the polymer encapsulation layer extends to a region 0.25 cm outside the edge of the high-power bare chip under test.

5. The method of claim 1, wherein the method further comprises: A polymer encapsulation layer is prepared on the amorphous back surface of the high-power bare chip under test after wire bonding to obtain a plastic-encapsulated high-power bare chip, including: A polymer adhesive is coated on the amorphous back surface of the high-power bare chip under test; The high-power bare chip under test after coating is defoamed and baked to cure, so that the polymer adhesive on the amorphous back side of the high-power bare chip under test is completely cured to form a polymer encapsulation layer, resulting in a plastic-encapsulated high-power bare chip, wherein the polymer encapsulation layer covers the lead solder joints in the outer region of the crystal back side.

6. The method of claim 1, wherein the method further comprises: The back surface of the plastic-encapsulated high-power bare chip is ground, finely polished, and thinned to obtain the target failure analysis sample, including: The back side of the plastic-encapsulated high-power bare chip is ground to remove the residual temporary adhesive layer on the back side of the chip, thus obtaining the first sample; The back surface of the first sample is finely polished to obtain the second sample; The second sample is thinned to obtain the target failure analysis sample.

7. The method of claim 6, wherein the method further comprises: The back surface of the plastic-encapsulated high-power bare chip is ground to remove the residual temporary adhesive layer on the back surface, resulting in a first sample, comprising: The back side of the plastic-encapsulated high-power bare chip was polished using silicon carbide sandpaper; When the area of ​​the temporary adhesive layer remaining on the back side of the plastic-encapsulated high-power bare chip is reduced to less than 5% of the area of ​​the back side, the grinding process is stopped. Then, the plastic-encapsulated high-power bare chip is ultrasonically cleaned and dried to obtain the first sample.

8. The method of claim 6, wherein the method further comprises, The back surface of the first sample is finely polished to obtain a second sample, comprising: The back surface of the first sample was polished at a constant speed using diamond polishing slurry, wherein the polishing speed was 100~150 r / min and the polishing time was 2~3 minutes. During the uniform polishing process, the surface condition of the back side of the first sample is monitored at preset time intervals; When the surface of the back side of the first sample is a uniform mirror finish and there are no scratches or residual impurities, polishing is stopped to obtain a polished sample. The polished sample was ultrasonically cleaned and dried to obtain a second sample.

9. The method for preparing and analyzing high-power bare chip failure analysis samples according to claim 1, characterized in that, The substrate is an aluminum nitride ceramic substrate or a silicon carbide substrate.

10. The method of claim 1, wherein the method further comprises: The polymer encapsulating adhesive layer is one of a modified epoxy resin layer, an organosilicon layer, or a polyimide adhesive layer; The thickness of the polymer encapsulation layer is 2 mm.

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