Instruction access method and apparatus, electronic device, and storage medium

Abstract

This application proposes an instruction access method, apparatus, electronic device, and storage medium, relating to the field of processor technology. The instruction access method includes: receiving a program counter (PC) to be fetched sent by a branch prediction unit (BPU); determining a first target PC to be fetched and performing a prefetch filtering query on the first target PC to obtain a first query result; caching the first query result in a prefetch filtering query result queue; determining a second target PC to be fetched and obtaining a second query result corresponding to the second target PC from the prefetch filtering query result queue; and retrieving the target instruction corresponding to the second target PC from the instruction cache based on the second query result, thereby improving the access efficiency of the instruction cache.

Description

Technical Field

[0001] This application relates to the field of processor technology, and in particular to an instruction access method, apparatus, electronic device, and storage medium. Background Technology

[0002] To improve processor performance, existing high-performance processor designs employ a decoupled front-end architecture with a branch prediction unit (BPU) and instruction cache (ICache) access. The BPU provides fetch requests, which are written to a decoupled queue, namely the fetch target queue (FTQ). The FTQ queue accesses the instruction cache to fetch instructions, providing instruction supply to the decode unit to form the back end of the pipeline.

[0003] Compared to the coupled front-end designs of the past, the decoupled front-end design has the advantage that the branch prediction unit is not affected by the instruction fetch unit, especially the pipeline wait caused by instruction cache misses does not affect branch prediction. At the same time, the branch prediction unit pipeline can run before the instruction fetch unit pipeline, which can hide the cavitation caused by misprediction of branches; in the decoupled front-end architecture, the branch prediction results can also guide instruction prefetching.

[0004] The problem with decoupling the front end is that branch prediction-guided instruction prefetching, the prefetch filter query initiated by the instruction prefetch queue and the instruction fetch request initiated by FTQ will repeatedly access the instruction cache tag (ITAG) and the instruction translation lookaside buffer (ITLB), wasting the valuable read ports of ITAG and ITLB, affecting access speed and wasting the processor's valuable hardware resources. Summary of the Invention

[0005] This application aims to at least partially address one of the technical problems in the related art.

[0006] Therefore, the first objective of this application is to propose an instruction access method to improve the access efficiency of instruction cache.

[0007] The second objective of this application is to provide an instruction access device.

[0008] The third objective of this application is to propose an electronic device.

[0009] The fourth objective of this application is to provide a computer-readable storage medium.

[0010] The fifth objective of this application is to provide a computer program product.

[0011] To achieve the above objectives, a first aspect of this application proposes an instruction access method, executed by an instruction fetch target queue (FTQ), comprising:

[0012] Receive the program counter PC to be fetched sent by the branch prediction unit (BPU); Determine the first target PC to be prefetched, and perform a prefetch filtering query on the first target PC to be prefetched to obtain the first query result; Cache the first query result to the prefetch filter query result queue; Determine the second target index PC that needs to be retrieved, and obtain the second query result corresponding to the second target index PC from the prefetch filter query result queue; Based on the second query result, retrieve the target instruction corresponding to the second target instruction PC from the instruction cache.

[0013] To achieve the above objectives, a second aspect of this application provides an instruction access device, comprising: The branch prediction unit (BPU) is used to predict the program counter (PC) to be fetched. The instruction fetch target queue (FTQ) is used to receive the program counter (PC) to be fetched from the branch prediction unit (BPU); determine the first target PC to be fetched currently, and perform a prefetch filtering query on the first target PC to obtain a first query result; cache the first query result in the prefetch filtering query result queue; determine the second target PC to be fetched currently, and obtain the second query result corresponding to the second target PC to be fetched from the prefetch filtering query result queue; and retrieve the target instruction corresponding to the second target PC to be fetched from the instruction cache according to the second query result.

[0014] To achieve the above objectives, a third aspect of this application provides an electronic device comprising: A processor, and a memory communicatively connected to the processor; The memory stores computer-executed instructions; The processor executes computer execution instructions stored in the memory to implement the method described in the first aspect embodiment.

[0015] To achieve the above objectives, a fourth aspect of this application provides a computer-readable storage medium storing computer-executable instructions that, when executed by a processor, are used to implement the method described in the first aspect embodiment.

[0016] To achieve the above objectives, a fifth aspect of this application provides a computer program product including a computer program that, when executed by a processor, implements the method described in the first aspect.

[0017] The instruction access method, apparatus, electronic device, and storage medium provided in this application determine the first target PC to be prefetched from the PCs to be fetched sent by the BPU through the instruction fetch target queue (FTQ). A prefetch filtering query is performed on the first target PC to be fetched to obtain a first query result, which can effectively filter duplicate prefetch requests. The first query result is cached in the prefetch filtering query result queue. For the second target PC to be fetched, the second query result corresponding to the second target PC to be fetched is obtained from the prefetch filtering query result queue to retrieve the corresponding target instruction from the instruction cache. This avoids duplicate access to the instruction cache during the prefetch and fetch stages, improving the access efficiency of the instruction cache.

[0018] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0019] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein: Figure 1 A schematic diagram of a conventional decoupled front-end architecture provided in an embodiment of this application; Figure 2 A flowchart illustrating an instruction access method provided in an embodiment of this application; Figure 3 A flowchart illustrating an instruction access method provided in an embodiment of this application; Figure 4 This is a basic architecture diagram of an instruction access method provided in an embodiment of this application; Figure 5 This is a schematic diagram of the structure of an instruction access device provided in an embodiment of this application. Detailed Implementation

[0020] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application, and should not be construed as limiting this application.

[0021] Figure 1 This is a schematic diagram of a conventional decoupled front-end architecture provided in an embodiment of this application; it includes a branch prediction component, a transfer target queue (fetch target queue), an instruction prefetch queue, an instruction translation back buffer, instruction cache tags, and instruction cache data. The branch prediction component provides the branch predictor's prediction result to the transfer target queue. The transfer target queue initiates an instruction prefetch request to the instruction prefetch queue. The instruction prefetch queue caches the fetch requests to be prefetched and sends a prefetch filtering query to the instruction translation back buffer and the instruction cache tags to filter duplicate or invalid fetch requests. The transfer target queue initiates an instruction fetch request to the instruction translation back buffer, the instruction cache tags, and the instruction cache data. The instruction translation back buffer completes the translation from virtual address to physical address. The instruction cache tags perform tag comparisons based on the physical address to determine a cache hit. Finally, the instruction cache data retrieves the target instruction based on the hit determination result.

[0022] The instruction access method, apparatus, electronic device, and storage medium of this application are described below with reference to the accompanying drawings.

[0023] Figure 2 This is a flowchart illustrating an instruction access method provided in an embodiment of this application. Figure 2 As shown, the method, executed by the instruction fetch target queue (FTQ), includes the following steps: S201, Receive the program counter PC to be fetched sent by the branch prediction unit (BPU).

[0024] The Branch Prediction Unit (BPU) is a core hardware module in the front end of the Central Processing Unit (CPU). Its core function is to predict the direction and target address of program branches, allowing the pipeline to prefetch instructions without interruption, thus significantly increasing the number of instructions per cycle.

[0025] In some embodiments, the BPU can predict the current instruction to be fetched (PC) based on the historical program counter (PC) and send the current instruction to be fetched (PC) to the instruction fetch target queue (FTQ). It can be understood that the instruction to be fetched (PC) is the instruction address of the instruction to be fetched.

[0026] The Fetch Target Queue (FTQ) is the core buffer and control structure of the CPU front end. It is located between the Branch Prediction Unit (BPU) and the Instruction Fetch Unit (IFU). Essentially, it is a circular buffer that decouples the BPU and IFU, temporarily stores the predicted address, and manages pipeline rollback.

[0027] FTQ includes four pointers, belonging to branch prediction, guidance prefetch, instruction fetch, and commit respectively. The branch prediction pointer is at the front and is the enqueue pointer; the commit pointer is the dequeue pointer; the guidance prefetch pointer is before the instruction fetch pointer. In this embodiment, the guidance prefetch pointer is used to prefetch instructions into the instruction cache to improve instruction access efficiency.

[0028] S202, determine the first target PC to be prefetched, and perform a prefetch filtering query on the first target PC to be prefetched to obtain the first query result.

[0029] In some embodiments, the first target PC to be prefetched can be the PC that the prefetch pointer is currently pointing to, which is the address of the instruction to be prefetched.

[0030] After determining the first target PC to be prefetched, a prefetch filtering query is performed on the first target PC to be prefetched, that is, the first target PC to be prefetched is prefetched, filtered and queried.

[0031] In this embodiment, prefetching the first target instruction PC means prefetching the currently used instruction into the instruction cache; filtering the first target instruction PC can be done by checking whether the instruction corresponding to the current first target instruction PC already exists in the instruction cache, so as to avoid duplicate caching of the instruction corresponding to the first target instruction PC; querying the first target instruction PC can be done by querying the translation back buffer (ITLB) and the instruction cache tag (ITAG) to obtain the query results in the ITLB and ITAG, thereby obtaining the first query result of the prefetch filtering query.

[0032] S203, cache the first query result to the prefetch filter query result queue.

[0033] In some embodiments, the prefetch filter query result queue includes at least a first target index PC and a first query result of the first target index PC.

[0034] It is understood that there may be one or more PCs to be retrieved. In this embodiment, each PC to be retrieved and its corresponding query result are cached sequentially in the prefetch filter query result queue according to the order of the prefetch filter query, so that FTQ can perform the query.

[0035] S204, determine the second target PC to be retrieved, and obtain the second query result corresponding to the second target PC from the prefetch filter query result queue.

[0036] In some embodiments, the second target PC to be fetched can be the PC currently pointed to by the instruction fetch pointer, which is the address of the instruction to be fetched.

[0037] In some embodiments, during the instruction query process, the first target PC and the second target PC corresponding to the prefetch instruction and the fetch instruction in the same round can be the same PC. For example, assuming that the PC currently pointed to by the prefetch pointer is A, after performing a prefetch filtering query on A and caching the first query result corresponding to A, the PC currently pointed to by the fetch pointer is still A. After fetching the instruction on A, one instruction access process is completed. Further, the PC pointed to by the prefetch pointer is the next PC, and so on, until all instructions corresponding to all PCs to be fetched are retrieved.

[0038] In other embodiments, during the instruction lookup process, the first target instruction PC and the second target instruction PC corresponding to the same round of prefetching and fetching instructions can be different PCs. For example, suppose the PC currently pointed to by the prefetch pointer is B and the PC currently pointed to by the fetch pointer is A. At this time, the prefetch pointer performs prefetch filtering lookup on instructions with PC B in advance to meet the instruction requirements of the future pipeline, while the fetch pointer is still processing instructions with PC A earlier and has not yet fetched instructions with PC B.

[0039] In other embodiments, during the instruction lookup process, the prefetched instructions may be canceled due to branch prediction errors or abnormal interruptions. In this case, the instruction fetch pointer will jump to a new target address based on the actual execution result and will not read the prefetched instructions again.

[0040] Furthermore, a matching search is performed from the prefetched filter query result queue to obtain the second query result corresponding to the current second target PC to be retrieved.

[0041] S205, based on the second query result, retrieve the target instruction corresponding to the second target instruction PC from the instruction cache.

[0042] Understandably, the second query result can at least indicate whether the instruction corresponding to the current second target instruction PC exists in the instruction cache. When the second query result indicates that the instruction corresponding to the second target instruction PC exists in the instruction cache, the instruction is read from the instruction cache according to the second target instruction PC in the second query result, and the target instruction corresponding to the second target instruction PC is retrieved, thereby improving the access efficiency of the instruction cache.

[0043] In this embodiment, the instruction fetch target queue (FTQ) receives the instruction PC to be fetched sent by the BPU and performs a prefetch filtering query on the first target instruction PC to be fetched, obtaining a first query result. This effectively filters duplicate prefetch requests. The first query result is cached in the prefetch filtering query result queue. For the second target instruction PC to be fetched, the second query result corresponding to the second target instruction PC is directly obtained from the prefetch filtering query result queue. Based on the second query result, the corresponding target instruction is retrieved from the instruction cache. This avoids redundant access to the instruction cache during the prefetch and fetch stages, improving the access efficiency of the instruction cache.

[0044] Based on the above embodiments, Figure 3 This is a flowchart illustrating an instruction access method provided in an embodiment of this application. Figure 3 As shown, the method, executed by the instruction fetch target queue (FTQ), includes the following steps: S301 receives the instruction fetch program counter PC sent by the branch prediction unit (BPU).

[0045] In some embodiments, the branch prediction unit (BPU) can also receive prediction information of the program counter (PC) to be fetched, which is used to determine the starting PC for the next prefetch, thereby enabling continuous prefetching.

[0046] In some embodiments, the prediction information may include whether a branch will jump, the target PC for the jump, and the end instruction of the current fetch. The end position of this prefetch can be determined based on the end instruction of the current fetch, thereby determining the starting PC of the next prefetch.

[0047] In this application embodiment, the implementation method of step S301 can be implemented in any of the various embodiments of this disclosure, and no limitation is made here, nor will it be described in detail.

[0048] S302, determine the first target PC to be fetched at the current time.

[0049] Alternatively, the first target pointer to be fetched, PC, can be determined based on the guiding prefetch pointer.

[0050] In this application embodiment, the implementation method of step S302 can be implemented in any of the various embodiments of this disclosure, and no limitation is made here, nor will it be described in detail.

[0051] S303, after querying the instruction translation back buffer (ITLB), obtains the physical address of the first target PC to be fetched.

[0052] The Instruction Translation Backup Buffer (ITLB) is a dedicated address translation cache in the CPU front end, responsible for the fast translation of instruction virtual addresses to physical addresses. In this embodiment, the ITLB is queried to obtain the physical address of the first target instruction PC, that is, the ITLB quickly translates the current first target instruction PC into a physical address so that the instruction can be accessed through the physical address.

[0053] S304: Based on the physical address, query the instruction cache tag ITAG to determine the hit result.

[0054] The instruction cache tag (ITAG) is a tag storage array in the instruction cache used to store the physical address tags of cache lines and their validity status. The physical address is compared with the tag to determine the instruction cache hit result.

[0055] Understandably, the hit result includes both hit and miss.

[0056] When the CPU executes an instruction, it breaks it down into three parts based on the physical address: Tag, Index, and Offset. The Index is used to locate the corresponding cache group. The Tag is compared with the Tag stored in the cache line. If the Tag matches and the valid bit of the cache line is 1, a cache hit occurs. If the Tag does not match or the valid bit is 0, a cache miss occurs.

[0057] S305, based on the physical address and the hit result, obtain the first query result.

[0058] In some embodiments, the first query result may include a first target PC to be fetched, a physical address, and a hit result. The first query result may at least indicate whether the instruction of the currently prefetched first target PC to be fetched exists in the instruction cache.

[0059] S306, cache the first query result to the prefetch filter query result queue.

[0060] In this application embodiment, the implementation method of step S306 can be implemented in any of the various embodiments of this disclosure, and no limitation is made here, nor will it be described in detail.

[0061] S307, determine the second target PC to be retrieved, and obtain the second query result corresponding to the second target PC from the prefetch filter query result queue.

[0062] Optionally, the second target instruction PC to be fetched can be determined based on the instruction fetch pointer; it is understood that during an instruction fetch process, the first target instruction PC and the second target instruction PC can be the same or different, guiding the prefetch pointer to be before the instruction fetch pointer.

[0063] Based on the matching of the second target PC in the prefetch filter query result queue, the first query result of the corresponding first target PC is determined as the second query result of the second target PC.

[0064] In some embodiments, in response to the absence of a second query result corresponding to the second target PC in the prefetch filter query result queue, that is, the query result corresponding to the second target PC is not stored in the prefetch filter query result queue, the ITLB storage and ITAG storage are accessed according to the second target PC to obtain the target query result corresponding to the second target PC. The target query result may include the physical address of the second target PC and the hit result.

[0065] In some embodiments, the target query results may also be cached in the prefetch filter query result queue for synchronization; in other embodiments, the target query results may not be cached in the prefetch filter query result queue.

[0066] Understandably, since the time interval between the instruction prefetch filter query guided by branch prediction and the instruction fetch operation to access the cache is small, and both the instruction prefetch filter query and the instruction cache access request are given by FTQ, the instruction cache line for the instruction prefetch filter query and the cache line for the instruction fetch operation to access the instruction cache are basically the same. Therefore, this embodiment can obtain the required ITAG and ITLB values ​​in the prefetch filter query result queue, avoiding repeated access to the instruction cache tag (ITAG) memory and the instruction translation back buffer (ITLB) memory, reducing the occupation of instruction cache tag memory ports, and reducing access to the instruction cache tag memory also reduces the processor's power consumption. The processor cache tag memory is generally composed of static random-access memory (SRAM). Increasing the number of SRAM ports has a significant impact on the processor's access speed and area. Therefore, reducing access to SRAM can also reduce the processor's power consumption.

[0067] S308: Based on the second query result, retrieve the target instruction corresponding to the second target instruction PC from the instruction cache.

[0068] In some embodiments, in response to a hit indication in the second query result, access to the ITLB and ITAG is omitted, and the target instruction is retrieved directly from the instruction cache.

[0069] In some embodiments, in response to a miss indication in the second query result, the target instruction of the second target fetch instruction PC is prefetched from the lower storage unit into the instruction cache, that is, an instruction prefetch request is initiated to the lower storage unit to prefetch the target instruction of the second target fetch instruction PC into the instruction cache, and further, the target instruction of the second target fetch instruction PC is retrieved from the instruction cache.

[0070] In some embodiments, after prefetching the target instruction of the second target PC from the lower storage unit to the instruction cache, the prefetch filter query result queue can also be updated based on the target instruction of the second target PC, that is, the query result information of the second target PC is synchronized in the prefetch filter query result queue.

[0071] Furthermore, to ensure correctness, this embodiment supports invalidating the corresponding item when it is necessary to invalidate the item in the prefetch filter query result queue; in response to any cache block in the instruction cache meeting the invalidation condition, the query result of the PC corresponding to any cache block in the prefetch filter query result queue is invalidated, wherein the cache block corresponds to one or more PCs.

[0072] Optionally, satisfying an invalid condition includes at least one of the following operations: The processor executes instruction cache synchronization instructions, such as FENCE.I. Instruction cache synchronization instructions are used to synchronize the instruction cache, ensuring that all previously issued read and write operations to memory have been completed and that the data has been flushed from the processor cache to memory before continuing to execute subsequent instructions. This ensures that the processor executes instructions in the expected order.

[0073] The cache block in the instruction cache is replaced for invalidation.

[0074] An external consistency request causes an invalidation operation on the corresponding cache block.

[0075] Understandably, when an operation that satisfies the invalidation condition of a cache block is performed, the prefetch filter query result queue will be queried, and the items in the prefetch filter query result queue corresponding to that cache block will be invalidated.

[0076] In this embodiment, the first target instruction PC to be fetched is determined based on the prefetch pointer, and the translation from virtual address to physical address is completed in the ITLB and a hit judgment is performed in the ITAG to obtain the corresponding first query result. The query result is cached in the prefetch filter query result queue, so that the subsequent instruction fetching stage can directly reuse the query result obtained in the prefetch stage, avoiding repeated access to the ITLB and ITAG, effectively reducing the occupation of the instruction cache tag storage port. For scenarios where the prefetch filter query result queue lacks corresponding query results or is invalid, the correctness of the fetch result and the consistency of the cache are ensured through query completion and result invalidation mechanisms, thereby reducing the processor's power consumption and improving the overall operating efficiency of the processor.

[0077] Figure 4 This is a basic architecture diagram of an instruction access method provided in an embodiment of this application; it includes: a branch prediction unit, a transfer target queue (fetch target queue), an instruction prefetch queue, an instruction translation back buffer, an instruction cache tag, a prefetch filter query result queue, and instruction cache data. The branch prediction unit provides the branch predictor's prediction result to the transfer target queue. The transfer target queue initiates an instruction prefetch request to the instruction prefetch queue. The instruction prefetch queue caches the fetch requests to be prefetched and sends a prefetch filter query to the instruction translation back buffer and the instruction cache tag, caching the result of the prefetch filter query in the prefetch filter query result queue. When the transfer target queue initiates an instruction fetch request, it directly obtains the corresponding query result from the prefetch filter query result queue, reusing the address translation and hit determination results already completed in the prefetch stage, avoiding repeated access to the instruction translation back buffer and the instruction cache tag. Based on the obtained query result, the target instruction is retrieved from the instruction cache data, effectively reducing the occupation of the instruction cache tag storage port.

[0078] To implement the above embodiments, this application also proposes an instruction access device.

[0079] Figure 5 This is a schematic diagram of the structure of an instruction access device provided in an embodiment of this application. Figure 5 As shown, the instruction access device 500 includes: The branch prediction unit (BPU) 501 is used to predict the program counter (PC) to be fetched. The instruction fetch target queue FTQ 502 is used to receive the instruction PC to be fetched sent by the BPU; determine the first target instruction PC to be fetched currently, and perform a prefetch filter query on the first target instruction PC to obtain a first query result; cache the first query result in the prefetch filter query result queue; determine the second target instruction PC to be fetched currently, and obtain the second query result corresponding to the second target instruction PC from the prefetch filter query result queue; and retrieve the target instruction corresponding to the second target instruction PC from the instruction cache according to the second query result.

[0080] In some embodiments, the instruction fetch target queue FTQ 502 is used for: The physical address of the PC to be fetched is obtained by querying the instruction translation back buffer (ITLB). The system queries the instruction cache tag ITAG based on the physical address to determine the hit result, which includes whether the hit result is a hit or a miss. The first query result is obtained based on the physical address and the hit result.

[0081] In some embodiments, the instruction fetch target queue FTQ 502 is used for: In response to a hit indication in the second query result, access to ITLB and ITAG is omitted, and the target instruction is retrieved from the instruction cache; In response to a miss in the second query result, the target instruction of the second target PC is prefetched from the lower storage unit into the instruction cache; Retrieve the target instruction of the second target PC from the instruction cache.

[0082] In some embodiments, the instruction fetch target queue FTQ 502 is used for: The prefetch filter query result queue is updated based on the target instruction of the second target PC.

[0083] In some embodiments, the instruction fetch target queue FTQ 502 is further configured to: The program counter (PC) sent by the branch prediction unit (BPU) provides prediction information for the program counter to be fetched. This prediction information is used to determine the starting PC for the next prefetch, thus enabling continuous prefetching.

[0084] In some embodiments, the instruction fetch target queue FTQ 502 is further configured to: In response to the absence of a second query result corresponding to the second target PC in the prefetch filter query result queue, the ITLB storage and ITAG storage are accessed to obtain the target query result corresponding to the second target PC.

[0085] In some embodiments, the instruction fetch target queue FTQ 502 is used for: The first target pointer to be fetched, PC, is determined based on the guidance prefetch pointer; The second target instruction to be fetched (PC) is determined based on the instruction fetch pointer; The prefetch pointer is used before the instruction pointer is fetched.

[0086] In some embodiments, the instruction fetch target queue FTQ 502 is further configured to: In response to any cache block in the instruction cache meeting the invalidation condition, the query result of the PC corresponding to any cache block in the prefetch filter query result queue is invalidated, wherein the cache block corresponds to one or more PCs.

[0087] In some embodiments, satisfying an invalid condition includes at least one of the following operations: The processor executes instruction cache synchronization instructions; The cache block in the instruction cache is replaced for invalidation. An external consistency request causes an invalidation operation on the corresponding cache block. It should be noted that the foregoing explanation of the instruction access method embodiment also applies to the instruction access apparatus of this embodiment, and will not be repeated here.

[0088] In this embodiment, the first target instruction PC to be fetched is determined based on the prefetch pointer, and the translation from virtual address to physical address is completed in the ITLB and a hit judgment is performed in the ITAG to obtain the corresponding first query result. The query result is cached in the prefetch filter query result queue, so that the subsequent instruction fetching stage can directly reuse the query result obtained in the prefetch stage, avoiding repeated access to the ITLB and ITAG, effectively reducing the occupation of the instruction cache tag storage port. For scenarios where the prefetch filter query result queue lacks corresponding query results or is invalid, the correctness of the fetch result and the consistency of the cache are ensured through query completion and result invalidation mechanisms, thereby reducing the processor's power consumption and improving the overall operating efficiency of the processor.

[0089] To implement the above embodiments, this application also proposes an electronic device, including: a processor and a memory communicatively connected to the processor; the memory stores computer execution instructions; the processor executes the computer execution instructions stored in the memory to implement the method provided in the foregoing embodiments.

[0090] To implement the above embodiments, this application also proposes a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, are used to implement the methods provided in the foregoing embodiments.

[0091] To implement the above embodiments, this application also proposes a computer program product, including a computer program that, when executed by a processor, implements the methods provided in the foregoing embodiments.

[0092] The collection, storage, use, processing, transmission, provision, and disclosure of user personal information involved in this application all comply with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0093] It should be noted that personal information collected from users should be used for legitimate and reasonable purposes and should not be shared or sold outside of these legitimate uses. Furthermore, such collection / sharing should only be conducted after receiving the user's informed consent, including but not limited to notifying the user to read the user agreement / user notice and sign an agreement / authorization that includes authorization of relevant user information before the user uses the function. In addition, any necessary steps must be taken to protect and safeguard access to such personal information data and ensure that others with access to personal information data comply with their privacy policies and procedures.

[0094] This application is intended to provide an implementation scheme for users to selectively prevent the use or access to their personal information data. Specifically, this disclosure is intended to provide hardware and / or software to prevent or block access to such personal information data. Once personal information data is no longer needed, risks can be minimized by restricting data collection and deleting data. Furthermore, where applicable, such personal information is de-identified to protect user privacy.

[0095] In the foregoing descriptions of the embodiments, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0096] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0097] Any process or method description in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more executable instructions for implementing custom logic functions or processes, and the scope of the preferred embodiments of this application includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the functions involved, as should be understood by those skilled in the art to which embodiments of this application pertain.

[0098] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-included system, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include: an electrical connection having one or more wires (electronic device), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Alternatively, the computer-readable medium may be paper or other suitable media on which the program can be printed, since the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in a computer memory.

[0099] It should be understood that various parts of this application can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented using software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0100] Those skilled in the art will understand that all or part of the steps of the methods in the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, the program includes one or a combination of the steps of the method embodiments.

[0101] Furthermore, the functional units in the various embodiments of this application can be integrated into a processing module, or each unit can exist physically separately, or two or more units can be integrated into a module. The integrated module can be implemented in hardware or as a software functional module. If the integrated module is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium.

[0102] The storage medium mentioned above can be a read-only memory, a disk, or an optical disk, etc. Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of this application.

Claims

1. A method for accessing instructions, characterized in that, Executed by the instruction fetch target queue (FTQ), the method includes: Receive the program counter PC to be fetched sent by the branch prediction unit (BPU); Determine the first target PC to be prefetched, and perform a prefetch filtering query on the first target PC to be prefetched to obtain the first query result; Cache the first query result to the prefetch filter query result queue; Determine the second target index PC that needs to be retrieved, and obtain the second query result corresponding to the second target index PC from the prefetch filter query result queue; Based on the second query result, retrieve the target instruction corresponding to the second target instruction PC from the instruction cache; The step of performing a prefetch filtering query on the first target PC to be retrieved to obtain a first query result includes: The physical address of the PC to be fetched from the first target is obtained by querying the instruction translation back buffer (ITLB). The physical address is used to query the instruction cache tag ITAG to determine the hit result, wherein the hit result includes a hit or a miss; The first query result is obtained based on the physical address and the hit result; The step of retrieving the target instruction corresponding to the second target instruction PC from the instruction cache based on the second query result includes: In response to a hit indication in the second query result, access to the ITLB and the ITAG is omitted, and the target instruction is retrieved from the instruction cache; In response to a miss in the second query result, the target instruction of the second target PC is prefetched from the lower storage unit into the instruction cache; Retrieve the target instruction of the second target PC from the instruction cache.

2. The method according to claim 1, characterized in that, After prefetching the target instruction of the second target PC from the lower-level storage unit into the instruction cache, the process includes: The prefetch filter query result queue is updated based on the target instruction of the second target PC.

3. The method according to any one of claims 1-2, characterized in that, The method further includes: The system receives prediction information from the branch prediction unit (BPU) regarding the program counter (PC) to be fetched. This prediction information is used to determine the starting PC for the next prefetch, thus enabling continuous prefetching.

4. The method according to any one of claims 1-2, characterized in that, The method further includes: In response to the absence of a second query result corresponding to the second target PC in the prefetch filter query result queue, the ITLB storage and ITAG storage are accessed to obtain the target query result corresponding to the second target PC.

5. The method according to any one of claims 1-2, characterized in that, The method includes: The first target pointer to be fetched, PC, is determined based on the guidance prefetch pointer; The second target instruction to be fetched (PC) is determined based on the instruction fetch pointer; The prefetch pointer is located before the instruction fetch pointer.

6. The method according to any one of claims 1-2, characterized in that, The method further includes: In response to any cache block in the instruction cache meeting the invalidation condition, the query result of the PC corresponding to any cache block in the prefetch filter query result queue is invalidated, wherein the cache block corresponds to one or more PCs.

7. The method according to claim 6, characterized in that, The condition for invalidity includes at least one of the following operations: The processor executes instruction cache synchronization instructions; The cache block in the instruction cache is replaced for invalidation. An external consistency request causes an invalidation operation on the corresponding cache block.

8. An instruction access device, characterized in that, include: The branch prediction unit (BPU) is used to predict the program counter (PC) to be fetched. The instruction fetch target queue (FTQ) is used to receive the instruction fetching PC sent by the BPU. Determine the first target PC to be prefetched, and perform a prefetch filtering query on the first target PC to be prefetched to obtain the first query result; The first query result is cached in the prefetch filter query result queue; the second target pointer PC to be retrieved is determined, and the second query result corresponding to the second target pointer PC is obtained from the prefetch filter query result queue; Based on the second query result, retrieve the target instruction corresponding to the second target instruction PC from the instruction cache; The step of performing a prefetch filtering query on the first target PC to be retrieved to obtain a first query result includes: The physical address of the PC to be fetched from the first target is obtained by querying the instruction translation back buffer (ITLB). The physical address is used to query the instruction cache tag ITAG to determine the hit result, wherein the hit result includes a hit or a miss; The first query result is obtained based on the physical address and the hit result; The step of retrieving the target instruction corresponding to the second target instruction PC from the instruction cache based on the second query result includes: In response to a hit indication in the second query result, access to the ITLB and the ITAG is omitted, and the target instruction is retrieved from the instruction cache; In response to a miss in the second query result, the target instruction of the second target PC is prefetched from the lower storage unit into the instruction cache; Retrieve the target instruction of the second target PC from the instruction cache.

9. An electronic device, characterized in that, include: A processor, and a memory communicatively connected to the processor; The memory stores computer-executed instructions; The processor executes computer execution instructions stored in the memory to implement the method as described in any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, are used to implement the method as described in any one of claims 1-7.

11. A computer program product, characterized in that, Includes a computer program that, when executed by a processor, implements the method of any one of claims 1-7.

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