An encoder and an encoding method

Abstract

This application discloses an encoding converter and encoding conversion method, relating to the field of digital circuit technology. The encoding converter includes: a trigger signal control circuit and an encoding state generation circuit; the trigger signal control circuit is connected to the encoding state generation circuit; the trigger signal control circuit is used to acquire a first number of encoding states and a first maximum number of encoding states, and sends the judgment result of the numerical relationship between the first number of encoding states and the first maximum number of encoding states to the encoding state generation circuit. By implementing the encoding converter and encoding conversion method described in this application, when the number of states in the state machine is less than the maximum number of Gray codes, a first encoding transition state is generated, causing the Gray code state to transition from the final state to the first state through the transition state, and the operation corresponding to the transition state is set to a no-operation. This avoids metastability caused by the simultaneous flipping of multiple bits in the Gray code, ensuring the security of data operations.

Description

Technical Field

[0001] This invention relates to the field of digital circuit technology, and in particular to an encoding converter and encoding conversion method. Background Technology

[0002] In digital circuit design, a state machine is a sequential logic circuit that performs system functions through state transitions and digital logic outputs. Since Gray code differs from adjacent states by only one bit, using Gray code to label each state effectively reduces metastability. However, when the actual number of states in the state machine is less than the maximum number of Gray code encodings, the transition from the last state to the first state may involve simultaneous flipping of multiple bits. This can lead to asynchronous flipping of multiple registers, resulting in race conditions and metastability, which can cause errors or even data loss during read / write operations. Summary of the Invention

[0003] This application provides an encoding converter and encoding conversion method, which at least solves the metastability phenomenon that exists when the state expressed by Gray code in the prior art transitions from the final state to the first state.

[0004] In a first aspect, this application provides an encoding converter, including: a trigger signal control circuit and an encoding state generation circuit; The trigger signal control circuit is connected to the encoding state generation circuit; A trigger signal control circuit is used to obtain the number of first encoding states and the maximum number of first encoding states, and send the judgment result of the numerical relationship between the number of first encoding states and the maximum number of first encoding states to the encoding state generation circuit. The first encoding has several first encoding states, including: a first encoding start state, several first encoding intermediate states and a first encoding end state. The several first encoding states are transformed from the first encoding start state through several first encoding intermediate states to the first encoding end state. The encoding state generation circuit is used to generate a first encoding transition state in response to the first encoding state number being less than the first encoding maximum number, so that the first encoding end state is transitioned to the first encoding beginning state through the first encoding transition state.

[0005] Secondly, this application also provides an encoding conversion method, including: Obtain the number of first-encoded states and the maximum number of first-encoded states; In response to the fact that the number of first coding states is less than the maximum number of first coding states, a first coding transition state is generated, and the state of the first coding is cyclically transformed in the following manner: from the first coding start state, it sequentially goes through several first coding intermediate states to the first coding end state, and then from the first coding end state through the first coding transition state to the first coding start state; wherein, the first coding transition state corresponds to the execution of a no-operation.

[0006] The beneficial effects of the technical solution provided in this application are as follows: By implementing the encoding converter and encoding conversion method described in this application, when the number of states in the state machine is less than the maximum number of Gray codes, a first encoding connection state is generated, so that the Gray code state is transformed from the end state to the first state through the connection state, and the operation corresponding to the connection state is set to a no operation, which can avoid the metastability caused by the simultaneous flipping of multiple bits of Gray code and ensure the security of data operation; by providing an encoding type conversion circuit for exchanging Gray code and one-hot code, the circuit has the flexibility of encoding selection; by providing a random number generation circuit, random number generation is realized without the need to use an additional circuit to perform random number generation, saving costs. Attached Figure Description

[0007] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0008] Figure 1 This is a schematic diagram of an encoding converter provided in an embodiment of this application; Figure 2 This is a schematic diagram of Gray code state transitions provided in an embodiment of this application; Figure 3 This is a schematic diagram of the first trigger signal control circuit provided in an embodiment of this application; Figure 4 This is a schematic diagram of the encoding state generation logic flow provided in the embodiments of this application; Figure 5 This is a schematic diagram of Gray code state transition containing a first encoded connection state provided in an embodiment of this application; Figure 6 This is a schematic diagram of the second trigger signal control circuit provided in an embodiment of this application; Figure 7 This is another Gray code state transition diagram provided in an embodiment of this application; Figure 8 This is a schematic diagram of the second encoding state generation circuit provided in an embodiment of this application; Figure 9 This is a schematic diagram of the encoding type conversion circuit provided in an embodiment of this application; Figure 10 This is a schematic diagram illustrating the state transition from Gray code to one-hot code provided in an embodiment of this application; Figure 11 This is a schematic diagram illustrating the state transition from one-hot code to Gray code provided in an embodiment of this application; Figure 12 This is a schematic diagram of the function switching component provided in an embodiment of this application; Figure 13 This is a schematic diagram of the random number generation circuit provided in an embodiment of this application; Figure 14 This is a schematic diagram of the state of random number generation provided in the embodiments of this application; Figure 15 This is a schematic diagram of an encoding conversion method provided in an embodiment of this application. Detailed Implementation

[0009] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0010] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The numbers in the accompanying drawings are only used to distinguish individual functional parts or modules and do not indicate logical relationships between parts or modules. The terms “comprising,” “including,” or “including,” and similar terms mean that the element or object preceding the term encompasses the element or object listed following the term and its equivalents, without excluding other elements or objects. The terms “connected,” “linked,” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. “Above,” “below,” “left,” “right,” etc., are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0011] The various embodiments according to this disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that in the drawings, the same reference numerals are assigned to components having substantially the same or similar structure and function, and repeated descriptions of them will be omitted.

[0012] To address the metastability issue that exists in existing technologies using Gray code representation when a state transitions from a final state to a first state, this application provides the following implementation method: In some embodiments, such as Figure 1 As shown, an encoding converter includes: a trigger signal control circuit 100 and an encoding state generation circuit 200; The trigger signal control circuit 100 is connected to the encoding state generation circuit 200; The trigger signal control circuit 100 is used to obtain the number of first encoding states and the maximum number of first encoding states, and send the judgment result of the numerical relationship between the number of first encoding states and the maximum number of first encoding states to the encoding state generation circuit 200. The first encoding has several first encoding states, including: first encoding start state, several first encoding intermediate states and first encoding end state. The several first encoding states are transformed from the first encoding start state through several first encoding intermediate states to the first encoding end state. The encoding state generation circuit 200 is used to generate a first encoding connection state in response to the first encoding state number being less than the first encoding maximum number, so that the first encoding end state is transformed into the first encoding beginning state through the first encoding connection state.

[0013] Preferably, the first encoding is Gray code, and the second encoding is one-hot code.

[0014] In Gray code, two adjacent states differ by only one binary bit. For an n-bit Gray code, it can be encoded as 2^n. n Each state has a unique code value, and the maximum and minimum values ​​differ by only one bit, indicating a cyclic encoding. For example, when n=4, the coded values ​​for the 16 states are as follows: State 1: 0000, State 2: 0001, State 3: 0011, State 4: 0010, State 5: 0110, State 6: 0111, State 7: 0101, State 8: 0100, State 9: 1100, State 10: 1101, State 11: 1111, State 12: 1110, State 13: 1010, State 14: 1011, State 15: 1001, and State 16: 1000.

[0015] As can be seen, only one bit differs between two adjacent Gray code states, thus reducing the occurrence of metastability. Metastability refers to a situation where a trigger cannot reach a verifiable state within a specified period.

[0016] However, in practical designs, the actual number of first encoded states m of the state machine is very likely to be less than the maximum number of Gray code states (i.e., m < 2). n At this point, when transitioning from state m to state 1, more than one bit will differ. For example... Figure 2 As shown, taking m=6 as an example, in the Gray code-encoded state machine, three bits differ during the transition from state 6 (0111) to state 1 (0000). Therefore, there is a risk of multiple registers flipping out of sync, causing timing races and hazards in the circuit, leading to metastability and resulting in errors or even data loss during reading and writing.

[0017] One-hot coding is a coding system where only one bit is valid; each state has only one valid bit. For example, when n=5, the code values ​​for each state using one-hot coding are as follows: State 1: 00001, State 2: 00010, State 3: 00100, State 4: 01000, State 5: 10000.

[0018] This encoding method is suitable for combinational logic circuits and medium-scale circuits.

[0019] In this application, when designing a state machine using Gray code, if the actual number of first encoded states m of the state machine is less than the maximum number of first encoded states of the Gray code (i.e., m < 2), then... n Add a first-encoding connection state m+1, and ensure that state m+1 and state m satisfy Gray code encoding requirements. Change the original jump from state m to state 1 to a jump from state m to state m+1, and then back from state m to state m+1. State m+1 is set to no operation to avoid asynchronous register flipping caused by timing races and hazards, which could lead to state encoding errors and trigger erroneous operations. m and n are both natural numbers.

[0020] When the number of first encoding states is less than the maximum number of Gray codes, a first encoding transition state is generated, which transforms the Gray code state from the end state to the beginning state through the transition state. The operation corresponding to the transition state is set to a no operation, which can avoid the metastability caused by the simultaneous flipping of multiple bits in the Gray code and ensure the security of data operations.

[0021] The first encoding connection state can be implemented in two ways: inserting a new state as the first encoding connection state; or reusing an existing state as the first encoding connection state.

[0022] Accordingly, the trigger signal control circuit 100 includes: a first trigger signal control circuit 100a adapted to insert a new state as the first coded connection state, and a second trigger signal control circuit 100b adapted to reuse an existing state as the first coded connection state.

[0023] The encoding state generation circuit 200 includes: a first encoding state generation circuit 200a adapted to insert a new state as a first encoding connection state, and a second encoding state generation circuit 200b adapted to reuse an existing state as a first encoding connection state.

[0024] The two technical solutions will be described separately below.

[0025] In some embodiments, such as Figure 3 As shown, the first trigger signal control circuit 100a includes: a first comparator 110a, a first NOT gate 120a, a first buffer 131a, a second buffer 132a, and a third buffer 133a; One input of the first comparator 110a is used to obtain the number of first encoded states, and the other input of the first comparator 110a is used to obtain the maximum number of first codes. The output of the first comparator 110a is connected to the input of the first NOT gate 120a, the enable terminal of the first buffer 131a, the enable terminal of the second buffer 132a, and the input of the first encoded state generation circuit 200a. The output of the first NOT gate 120a is connected to the enable terminal of the third buffer 133a. The input terminal of the first buffer 131a is connected to the first trigger signal, the input terminal of the second buffer 132a is connected to the second trigger signal, and the input terminal of the third buffer 133a is connected to the third trigger signal.

[0026] In this embodiment, the first encoding connection state is the m+1 state.

[0027] The function of the first comparator 110a is to compare the number of first encoded states with the maximum number of first encoded states. When the number of first encoded states is greater than or equal to the maximum number of first encoded states, its output terminal outputs a low level; when the number of first encoded states is less than the maximum number of first encoded states, its output terminal outputs a high level. A high level output from the first comparator 110a indicates that a first encoded transition state needs to be added for the state cycle encoded using Gray code.

[0028] The first buffer 131a, the second buffer 132a, and the third buffer 133a are tri-state buffers with an enable terminal. When the enable terminal of the tri-state buffer receives a high level, the tri-state buffer is turned on and outputs the signal received at the input terminal; when the enable terminal of the tri-state buffer receives a low level, the tri-state buffer is blocked and its output terminal cannot output the data received at the input terminal.

[0029] When m=2 n When the first comparator 110a outputs a low level, it becomes a high level through the first NOT gate 120a, thereby enabling the third buffer 133a. The third trigger signal is output from the output terminal of the third buffer 133a. At this time, the enable terminals of the first buffer 131a and the second buffer 132a both receive a low level, exhibiting a blocked state and not outputting a signal.

[0030] When m<2 n When this occurs, it indicates that a first encoding connection state needs to be added. The first comparator 110a outputs a high level, the first buffer 131a and the second buffer 132a are turned on, and the third buffer 133a is blocked. The first trigger signal and the second trigger signal can be output.

[0031] The first encoding state generation circuit 200a has no operation when the first comparator 110a outputs a low level; when the first comparator 110a outputs a high level, it stores the state encoding value into array Str_1 and sets array Str_2; after inverting the least significant bit Str_1[0] of array Str_1, it stores the least significant bit Str_2[0] of array Str_2; bits 1 to n-1 of array Str_1 remain unchanged and are stored in bits 1 to n-1 of array Str_2 accordingly; the value of array Str_2 is the value of state m+1. Figure 4 The logical flow is shown below.

[0032] This embodiment provides an implementation method to ensure that state m+1 and state m satisfy the Gray code requirements. Specifically, the least significant bit of the encoded value of state m is inverted, and this inverted value is used as the encoded value of state m+1. For example, the encoded value of state m, "0011", is changed to "0010" and used as the encoded value of state m+1. Alternatively, other bits of the encoded value of state m can be inverted and used as the encoded value of state m+1. For instance, inverting the second bit of "0011" results in "0001", or inverting the third bit of "0011" results in "0111", etc. This ensures that the encoded values ​​of state m+1 and state m differ by only one bit, thus satisfying the Gray code requirements.

[0033] Figure 5The diagram illustrates the state transition process in a state machine implemented using an FPGA. The state machine includes states 1, 2, ..., and m. After the FPGA powers on and resets, the state machine enters state 1. During the transition from state 1 to state 2, the FPGA system performs data reading, service processing, and other operations. When processing is complete and a trigger signal is valid, the state machine enters state 2, and so on. During the transition between every two adjacent states, the FPGA processes related services, and when a trigger signal is valid, the state machine enters the next state until it returns to state 1, and then the state transition cycle repeats.

[0034] When m<2 n When state m+1 is generated, the encodings of state m+1 and state m satisfy the Gray code conditions. Simultaneously, a first trigger signal is generated for state m+1, a second trigger signal is generated for state m, and a third trigger signal is invalid. A valid first trigger signal indicates that the transition from state m+1 to state 1 is activated; a valid second trigger signal indicates that the transition from state m to state m+1 is activated; and a valid third trigger signal indicates that the transition from state m to state 1 is activated.

[0035] In state m, the state machine cannot transition to state 1 because the third trigger signal is invalid. When the second trigger signal is detected to be valid, the state machine transitions from state m to state m+1. Since state m+1 and state m meet the Gray code conditions, there is no risk of data read / write errors.

[0036] In this embodiment, the first trigger signal is the signal for transitioning from state m+1 to state 1, the second trigger signal is the signal for transitioning from state m to state m+1, and the third trigger signal is the signal for transitioning from state m to state 1.

[0037] It should be noted that the transition from state m+1 to state 1 may not satisfy the Gray code conditions. However, since the system's business processing has already been completed during the transition from state m to state m+1, and the transition from state m+1 to state 1 is a no-operation, it does not involve business processing. Therefore, there is no risk of data processing errors, thus ensuring the system's security.

[0038] In other embodiments, such as Figure 6 As shown, the second trigger signal control circuit 100b includes: a second comparator 110b, a first OR gate 120b, and a first selector 130b; One input of the second comparator 110b is used to obtain the first code state quantity, and the other input of the second comparator 110b is used to obtain the first maximum code quantity. The output of the second comparator 110b is connected to one input of the first OR gate 120b. The other input of the first OR gate 120b is set to the first level, and the output of the first OR gate 120b is used to transmit the third trigger signal. One channel of the first selector 130b is set to the first level, and the other channel is set to the second level. Its channel selection terminal is used to access the encoding cycle state indication signal, and its output terminal outputs the level of the corresponding channel according to the encoding cycle state indication signal.

[0039] The first selector 130b is a dual-channel selector. It receives an encoding cycle status indication signal at its channel selection terminal to determine which input signal to use as the output signal. Schematic, when the encoding cycle status indication signal is high, the input signal of channel "1" is selected as the output signal; when the encoding cycle status indication signal is low, the input signal of channel "0" is selected as the output signal.

[0040] In this embodiment, the first encoding connection state is the m-1 state.

[0041] When m=2 n During the transition from state m to state 1, the system finishes processing the current process and then transitions to state 1.

[0042] When m<2 n When the state machine reaches state m, it jumps back to state m-1. After the system finishes processing the process in state m-1, it jumps back to state 1, as shown below. Figure 7 As shown. Since the encoded values ​​of state m and state m-1 satisfy the Gray code conditions, the integrity and correctness of the data can be guaranteed; and the transition from state m-1 to state 1 does not involve the data processing process, which also ensures that the data meets the security requirements.

[0043] Figure 7 In the code, end_loop represents the encoding loop state indicator signal, CMP_out represents the output signal of the second comparator, sig_m-1=0 indicates a jump from state m-1 to state 1, sig_m-1=1 indicates a jump from state m-1 to state m, and sig_m=1 indicates a jump from state m to state 1.

[0044] The difference between this embodiment and the previous embodiment is that it does not require adding a new state m+1 to the state machine, but it does require adding one data processing step to state m-1. There is no data processing step during the transition from state m-1 to state 1.

[0045] The two processes in state m-1 are described below.

[0046] Process 1: The process of data processing during the transition from state machine to state m-1 when the state machine first runs to state m; Process 2: The state machine jumps from state m back to state m-1, and the system performs the processing of the last process. After the data processing is completed, it jumps from state m-1 to state 1.

[0047] This embodiment achieves cyclical state transitions by adding processes to the existing state, while ensuring data security.

[0048] Accordingly, such as Figure 8 As shown, the corresponding second encoding state generation circuit 200b includes: an input judgment component 210b, a second selector 220b, and a first flip-flop 230b; The input judgment component 210b has: a first judgment component input port 210b_i1, a second judgment component input port 210b_i2, a third judgment component input port 210b_i3, a fourth judgment component input port 210b_i4, a first judgment component output port 210b_o1, a second judgment component output port 210b_o2, a third judgment component output port 210b_o3, and a fourth judgment component output port 210b_o4; The second selector 220b has: a first input port 220b_i1, a second input port 220b_i2, a third input port 220b_i3, a fourth input port 220b_i4, a first enable port 220b_e1, a second enable port 220b_e2, a third enable port 220b_e3, a fourth enable port 220b_e4, and a selector output port 220b_o; The first trigger 230b has: a first digital input port D0, a second digital input port D1, a third digital input port D2, a fourth digital input port D3, and an encoding output port SO2; The first judgment component input port 210b_i1 is used to receive the encoding cycle state indication signal. The second judgment component input port 210b_i2 is connected to the first enable port 220b_e1 and is used to receive the fourth trigger signal. The third judgment component input port 210b_i3 is connected to the comparison result signal generated by the output of the second comparator 110b. The fourth judgment component input port 210b_i4 is used to receive the third trigger signal. The first judgment component output port 210b_o1 is connected to the first digital input port D0. The second judgment component output port 210b_o2 is connected to the second enable port 220b_e2. The third judgment component input port 210b_o1 is connected to the first digital input port D0. The component output port 210b_o3 is connected to the third enable port 220b_e3, the fourth judgment component output port 210b_o4 is connected to the fourth enable port 220b_e4, the first input port 220b_i1 is set to the first level, the second input port 220b_i2 is set to the second level, the third input port 220b_i3 is set to the first level, the fourth input port 220b_i4 is set to the second level, the strobe output port 220b_o is connected to the second digital input port D1 and the third digital input port D2, the fourth digital input port D3 is set to the second level, and the encoding output port SO2 is used to output the status encoding value.

[0049] like Figure 8 As shown, the input judgment component 210b includes: a second NOT gate 2101b, a third NOT gate 2102b, a fourth NOT gate 2103b, a fifth NOT gate 2104b, a sixth NOT gate 2105b, a first AND gate 2106b, a second AND gate 2107b, a third AND gate 2108b, a fourth AND gate 2109b, a fifth AND gate 2110b, and a sixth AND gate 2111b; The input of the second NOT gate 2101b serves as the input port 210b_i1 of the first judgment component. The output of the second NOT gate 2101b is connected to one input of the first AND gate 2106b. The other input of the first AND gate 2106b is connected to the input of the third NOT gate 2102b and serves as the input port 210b_i2 of the second judgment component. The output of the first AND gate 2106b serves as the output port 210b_o1 of the first judgment component. The output of the third NOT gate 2102b is connected to one input of the second AND gate 2107b, one input of the third AND gate 2108b, and one input of the fifth AND gate 2110b. The other input of the second AND gate 2107b is connected to the output of the fourth AND gate 2109b and the input of the fifth NOT gate 2104b. The output of the second AND gate 2107b serves as the output port 210b_o2 of the second judgment component. The other input of the third AND gate 2108b... One input terminal is connected to the output terminal of the sixth AND gate 2111b and the input terminal of the sixth NOT gate 2105b. The output terminal of the third AND gate 2108b serves as the output port 210b_o3 of the third judgment component. The other input terminal of the fifth AND gate 2110b is connected to the output terminal of the fifth NOT gate 2104b. One input terminal of the fifth AND gate 2110b is connected to the output terminal of the sixth NOT gate 2105b. The output terminal of the fifth AND gate 2110b serves as the output port 210b_o4 of the fourth judgment component. The input terminal of the fourth NOT gate 2103b is connected to one input terminal of the sixth AND gate 2111b and then serves as the input port 210b_i3 of the third judgment component. The output terminal of the fourth NOT gate 2103b is connected to one input terminal of the fourth AND gate 2109b. The other input terminal of the fourth AND gate 2109b is connected to the other input terminal of the sixth AND gate 2111b and then serves as the input port 210b_i4 of the fourth judgment component.

[0050] The following is combined with Figure 8 Taking m=6 as an example, we will explain the state transition.

[0051] The second selector 220b is a 4-channel data selector with an enable control terminal. Each input has a corresponding enable port. For example, the first input port 220b_i1 corresponds to the first enable port 220b_e1, the second input port 220b_i2 corresponds to the second enable port 220b_e2, and so on. A high level received by the enable port is a valid level, and a low level is an invalid level. Furthermore, only one of the four enable ports can receive a valid level at a time.

[0052] The first flip-flop 230b is a D flip-flop with a reset port (i.e., the first reset port RST1). The reset signal is active high and inactive low. When the reset port receives a high level, the encoding output port SO2 outputs the state 0000. When the reset port receives a low level, the pulse of the first clock triggers the encoding output port SO2 to output the corresponding state value.

[0053] Wherein, the first clock is the system clock; the second clock is the sampling clock. Preferably, the frequency of the second clock can be set to twice that of the first clock.

[0054] In this embodiment, the first level is a high level and the second level is a low level.

[0055] After the first trigger 230b finishes its reset, the fourth trigger signal (indicating the transition from state 5 to state 6) is high, and when the encoding cycle state indicator signal is low, state 5 jumps to state 6, and the encoding output port SO2 outputs the encoding value corresponding to state 6: 0111.

[0056] When the second comparator 110b detects m<2 n When the output is high, it indicates a jump from state 6 back to state 5. The encoded output port SO2 outputs 0110.

[0057] When state 6 appears, it indicates that the current Gray code cycle has ended, and the encoding cycle status indicator signal is high, indicating a jump from state 5 to state 1.

[0058] In order to reset the initial state of the first flip-flop 230b, the first flip-flop 230b also has a first reset port RST1 and a first clock port CLK1; In response to receiving a valid reset signal at the first reset port RST1, the output of the encoded output port SO2 is set to the initial value; In response to receiving an invalid reset signal at the first reset port RST1, the encoded output port SO2 determines the output status encoded value based on the first clock signal received at the first clock port CLK1 and the signals received at the first digital input port D0, the second digital input port D1, the third digital input port D2, and the fourth digital input port D3.

[0059] The second encoding state generation circuit 200b also includes a seventh NOT gate 2112b; The output of the seventh NOT gate 2112b is connected to the first reset port RST1, and the input of the seventh NOT gate 2112b is used to receive the reset signal.

[0060] By receiving the reset signal through the seventh NOT gate 2112b, the state of the first flip-flop 230b is reset using an effective reset signal in hardware.

[0061] The encoder-converter also includes an encoding type conversion circuit 300; The encoding type conversion circuit 300 is used to convert the first encoding to the second encoding, or the second encoding to the first encoding, according to the conversion signal.

[0062] In other embodiments, such as Figure 9 As shown, the encoding type conversion circuit 300 includes: a logic judgment component 310 and an encoding conversion component 320; The logic judgment component 310 has: a first logic judgment input port 310a, a second logic judgment input port 310b, a third logic judgment input port 310c, a first logic judgment output port 310d, a second logic judgment output port 310e, a third logic judgment output port 310f, and a fourth logic judgment output port 310g. The encoding conversion component 320 has: a first conversion enable port 320a, a second conversion enable port 320b, a third conversion enable port 320c, a fourth conversion enable port 320d, a first encoding input port 320e, a second encoding input port 320f, a first encoding output port 320g, and a second encoding output port 320h; The logic judgment first input port 310a is used to obtain the number of first encoding states, the logic judgment second input port 310b is used to obtain the maximum number of first encodings, the logic judgment third input port 310c is used to obtain the conversion signal, the logic judgment first output port 310d is connected to the first conversion enable port 320a, the logic judgment second output port 310e is connected to the second conversion enable port 320b, the logic judgment third output port 310f is connected to the third conversion enable port 320c, the logic judgment fourth output port 310g is connected to the fourth conversion enable port 320d, the logic judgment first encoding input port 320e is used to obtain the first encoding to be converted, the second encoding input port 320f is used to obtain the second encoding to be converted, the first encoding output port 320g is used to output the second encoding obtained by converting the first encoding to be converted, and the second encoding output port 320h is used to output the first encoding obtained by converting the second encoding to be converted.

[0063] Specifically, the logic judgment component 310 includes: a third comparator 311, a seventh AND gate 312, an eighth AND gate 313, a ninth AND gate 314, and an eighth NOT gate 315; One input of the third comparator 311 serves as the first input port 310a for logic judgment, and the other input of the third comparator 311 serves as the second input port 310b for logic judgment. The output of the third comparator 311 is connected to one input of the seventh AND gate 312, one input of the eighth AND gate 313, and one input of the ninth AND gate 314. The other input of the seventh AND gate 312 is connected to the other input of the eighth AND gate 313, the other input of the ninth AND gate 314, and the input of the eighth NOT gate 315, and then serves as the third input port 310c for logic judgment. The output of the seventh AND gate serves as the first output port 310d for logic judgment, the output of the eighth AND gate 313 serves as the second output port 310e for logic judgment, the output of the ninth AND gate 314 serves as the third output port 310f for logic judgment, and the output of the eighth NOT gate 315 serves as the fourth output port 310g for logic judgment.

[0064] Specifically, the encoding conversion component 320 includes: a fourth buffer 321, a fifth buffer 322, a sixth buffer 323, a seventh buffer 324, and a state machine 325; The state machine 325 has: a first indicator port 325a, a second indicator port 325b, a third indicator port 325c, a fourth indicator port 325d, a first state input port 325e, a second state input port 325f, a first state output port 325g, and a second state output port 325h; The enable terminal of the fourth buffer 321 serves as the first conversion enable port 320a. The input terminal of the fourth buffer 321 is used to input the first digital code, and the output terminal of the fourth buffer 321 is connected to the first indicator port 325a. The enable terminal of the fifth buffer 322 serves as the second conversion enable port 320b. The input terminal of the fifth buffer 322 is used to input the second digital code, and the output terminal of the fifth buffer 322 is connected to the second indicator port 325b. The enable terminal of the sixth buffer 323 serves as the third conversion enable port 320c. The input terminal of the sixth buffer 323 is used to input the third digital code. The output of device 323 is connected to the third indicator port 325c. The enable terminal of the seventh buffer 324 serves as the fourth conversion enable port 320d. The input terminal of the seventh buffer 324 is used to input the fourth digital code. The output terminal of the seventh buffer 324 is connected to the fourth indicator port 325d. The first state input port 325e serves as the first code input port 320e. The second state input port 325f serves as the second code input port 320f. The first state output port 325g serves as the first code output port 320g. The second state output port 325h serves as the second code output port 320h.

[0065] When the conversion signal is high, the conversion from Gray code to one-hot code is performed, such as... Figure 10As shown. Here, m=5 represents the number of states in the Gray code, and k=7 represents the number of states in the one-hot code. The number of states in the Gray code is less than the number of states in the one-hot code. After conversion by the encoding conversion component 320, the following corresponding encoding is obtained: 0000 (Gray code) corresponds to 0000001 (one-hot code), 0001 (Gray code) corresponds to 0000010 (one-hot code), 0011 (Gray code) corresponds to 0000100 (one-hot code), 0010 (Gray code) corresponds to 0001000 (one-hot code), 0110 (Gray code) corresponds to 0010000 (one-hot code), and 0100000 and 1000000 are newly generated one-hot codes.

[0066] When the conversion signal is low, the conversion from one-hot code to Gray code is performed, such as... Figure 11 As shown. At this point, m=5 represents the number of Gray code states, and k=7 represents the number of one-hot codes states. After the encoding conversion component 320, the following corresponding codes are obtained: 0000001 (one-hot code) corresponds to 0000 (Gray code), 0000010 (one-hot code) corresponds to 0001 (Gray code), 0000100 (one-hot code) corresponds to 0011 (Gray code), 0001000 (one-hot code) corresponds to 0010 (Gray code), 0010000 (one-hot code) corresponds to 0110 (Gray code), and 0100000 and 1000000 are skipped by the state machine.

[0067] This embodiment provides an implementation method for converting between Gray code and one-hot code, making the circuit more flexible.

[0068] In order to cooperate with the encoding type conversion circuit 300 to convert the encoding type, the second encoding state generation circuit 200b also includes a function switching component 240b, which disables the function of the encoding state generation circuit when encoding type conversion is required.

[0069] The function switching component 240b is used to acquire the reset signal and the conversion signal, and set the output of the encoding output port SO2 of the first flip-flop 230b in the second encoding state generation circuit 200b to the initial value according to the reset signal and the conversion signal, or make the encoding output port SO2 determine the output state encoding value according to the first clock signal received by the first clock port CLK1 and the signals received by the first digital input port D0, the second digital input port D1, the third digital input port D2 and the fourth digital input port D3.

[0070] like Figure 12 As shown, the function switching component 240b includes: a ninth NOT gate 2113b and a second OR gate 2114b; The input of the ninth NOT gate 2113b is used to receive the reset signal. The output of the ninth NOT gate 2113b is connected to one input of the second OR gate 2114b. The other input of the second OR gate 2114b is used to receive the conversion signal. The output of the second OR gate 2114b is connected to the first reset port RST1 of the first flip-flop 230b.

[0071] When the conversion signal is high, it indicates that the encoding type conversion circuit 300 is enabled. At this time, the second OR gate 2114b outputs a high level, which sets the output of the encoding output port SO2 of the first flip-flop 230b to the initial value, thereby disabling the function of the second encoding state generation circuit 200b.

[0072] In some preferred embodiments, the encoder-converter further includes a random number generation circuit 400; like Figure 13 As shown, the random number generation circuit 400 includes: a second flip-flop 410, a third flip-flop 420, an eighth buffer 430, a tenth AND gate 440, an eleventh AND gate 450, a tenth NOT gate 460, and an eleventh NOT gate 470. The clock port of the second flip-flop 410 is used to receive the first clock signal. One input of the tenth AND gate 440 is used to receive the encoded cycle state indication signal. The input of the tenth NOT gate 460 is used to receive the fourth trigger signal. The output of the tenth NOT gate 460 is connected to the other input of the tenth AND gate 440. The output of the tenth AND gate 440 is connected to the data input of the second flip-flop 410. The reset terminal of the second flip-flop 410 is connected to the reset terminal of the third flip-flop 420 and the output of the eleventh NOT gate 470. The input of the eleventh NOT gate 470 is used to receive the reset signal. The clock port of the third flip-flop 420 is used to receive the second clock signal. One input of the eleventh AND gate 450 is connected to the other input and used to receive the state encoded value. The output of the eleventh AND gate 450 is connected to the data input of the third flip-flop 420. The data output of the second flip-flop 410 is connected to the enable terminal of the eighth buffer 430. The data output of the third flip-flop 420 is connected to the input of the eighth buffer 430. The output of the eighth buffer 430 is used to output the generated random number.

[0073] To ensure the acquisition of metastable signals, the frequency of the second clock signal is higher than the frequency of the first clock signal. For example, the frequency of the first clock signal is 100MHz, and the frequency of the second clock signal is 200MHz.

[0074] During each iteration of the state machine's cycle, as it transitions from state 5 to state 1, it samples one random bit. These sampled random bits are sequentially stored in memory (e.g., RAM) to form a random sequence, which can then be used as random numbers by the system. Figure 14As shown.

[0075] Preferably, for a random sequence, the following formula is used to detect whether the number of bits '1' and bits '0' in a subsequence of arbitrary length in the random sequence are close, thereby determining whether the generated random sequence meets the randomness requirement. The formula is as follows: ; For a random sequence of N bits, take m subsequences zi = randni(z), (i = 1, 2, ..., m), where randn() represents taking any n bits at different positions. randni(z) means taking any ni bits at different positions from the sequence z to form a new subsequence zi. Therefore, each subsequence zi contains ni bits, and 2 ≤ ni ≤ N, that is, the length of each subsequence does not exceed the length of z.

[0076] Calculate the proportion of bits '1' in each subsequence zi: ; Where 1≤i≤m, zij represents the value of the j-th bit ("0" or "1") in the subsequence zi.

[0077] Calculate the cumulative error of all subsequences: ; Calculate the residual error: ; Here, erfc() is the residual error function.

[0078] Set the pass standard base. For example, for 100 subsequences, if you expect more than 90 of them to pass the detection, then base = (100-90) / 100 = 0.1. When detecting a random sequence, the random sequence can be used only if R_value ≥ base; otherwise, the detection fails and the sequence should be discarded. The smaller the base value is set, the higher the detection accuracy.

[0079] The advantage of this method is that the random sequence can be collected and generated during the state machine operation, without the need for a separate process to obtain random numbers or an external physical random number generation module on the FPGA, thus saving costs and improving efficiency.

[0080] In other embodiments, such as Figure 15 As shown, an encoding conversion method includes: S100: Obtain the number of first encoding states and the maximum number of first encodings; S200: In response to the fact that the number of first coded states is less than the maximum number of first codes, a first coded concatenation state is generated, and the states of the first codes are cyclically transitioned in the following manner: The process starts from the first encoding state, goes through several intermediate states of the first encoding, and then transitions to the end state of the first encoding. From the end state of the first encoding, it goes through a first encoding transition state and then back to the first encoding state. The first encoding transition state corresponds to the execution of a no-operation.

[0081] It should be understood that, although Figure 15 The steps in the flowchart shown are displayed sequentially as indicated by the arrows; however, these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise explicitly stated herein, there is no strict order in which these steps are performed, and they can be executed in other orders. Furthermore, Figure 15 At least some of the steps in the process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0082] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0083] Specifically, according to embodiments of this application, the processes described above with reference to the flowcharts can be implemented as steps controlled by a computer software program. For example, embodiments of this application include a computer program product comprising a computer program loaded on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device, or installed from memory, or installed from ROM. When the computer program is executed by an external processor, it performs the functions defined in the methods of embodiments of this application.

[0084] It should be noted that the computer-readable medium in the embodiments of this application can be a computer-readable signal medium or a computer-readable storage medium, or any combination of the two. A computer-readable storage medium can be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In the embodiments of this application, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In the embodiments of this application, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to: wires, optical fibers, RF (Radio Frequency), etc., or any suitable combination thereof.

[0085] The aforementioned computer-readable medium may be included in the aforementioned server; or it may exist independently and not assembled into the server. The aforementioned computer-readable medium carries one or more programs that, when executed by the server, cause the server to: in response to detecting that the peripheral mode of the terminal is not activated, acquire the frame rate of the application on the terminal; when the frame rate meets the screen-off condition, determine whether the user is acquiring the terminal's screen information; and in response to the determination that the user is not acquiring the terminal's screen information, control the screen to enter an immediate dimming mode.

[0086] Computer program code for performing the operations of the embodiments of this application can be written in one or more programming languages ​​or a combination thereof. Programming languages ​​include object-oriented programming languages—such as Java, Smalltalk, and C++—and conventional procedural programming languages—such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0087] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, for system or system embodiments, since they are basically similar to method embodiments, the description is relatively simple, and relevant parts can be referred to the descriptions in the method embodiments. The systems and system embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without creative effort.

[0088] The technical solutions provided in this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only intended to help understand the methods and core ideas of this application. Furthermore, those skilled in the art will recognize that, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of this application.

[0089] The above provides a detailed description of the encoding converter and encoding conversion method provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. These embodiments are merely preferred embodiments of this application, used to help understand the method and core ideas of this application, and are not intended to limit this application. It should be noted that for those skilled in the art, any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application without departing from its principles are also within the protection scope of this application.

Claims

1. An encoding converter, characterized in that, include: Trigger signal control circuit (100) and encoding state generation circuit (200); The trigger signal control circuit (100) is connected to the encoding state generation circuit (200); The trigger signal control circuit (100) is used to obtain the number of first encoding states and the maximum number of first encoding states, and send the judgment result of the numerical relationship between the number of first encoding states and the maximum number of first encoding states to the encoding state generation circuit (200). The first encoding has a plurality of first encoding states, which include: a first encoding start state, a plurality of first encoding intermediate states and a first encoding end state. The plurality of first encoding states are converted from the first encoding start state through the plurality of first encoding intermediate states to the first encoding end state. The encoding state generation circuit (200) is used to generate a first encoding connection state in response to the first encoding state number being less than the first encoding maximum number, so that the first encoding end state is transformed to the first encoding beginning state through the first encoding connection state.

2. The encoder-converter according to claim 1, characterized in that, The trigger signal control circuit (100) includes a first trigger signal control circuit (100a), and the encoding state generation circuit (200) includes a first encoding state generation circuit (200a). The first trigger signal control circuit (100a) includes: a first comparator (110a), a first NOT gate (120a), a first buffer (131a), a second buffer (132a), and a third buffer (133a). One input of the first comparator (110a) is used to obtain the first number of encoded states, and the other input of the first comparator (110a) is used to obtain the first maximum number of encoded states. The output of the first comparator (110a) is connected to the input of the first NOT gate (120a), the enable terminal of the first buffer (131a), the enable terminal of the second buffer (132a), and the input of the first encoded state generation circuit (200a). The output of the first NOT gate (120a) is connected to the enable terminal of the third buffer (133a). The input terminal of the first buffer (131a) is connected to the first trigger signal, the input terminal of the second buffer (132a) is connected to the second trigger signal, and the input terminal of the third buffer (133a) is connected to the third trigger signal.

3. The encoder-converter according to claim 1, characterized in that, The trigger signal control circuit (100) includes a second trigger signal control circuit (100b); The second trigger signal control circuit (100b) includes: a second comparator (110b), a first OR gate (120b), and a first selector (130b); One input of the second comparator (110b) is used to obtain the number of the first encoded states, and the other input of the second comparator (110b) is used to obtain the maximum number of the first encodings. The output of the second comparator (110b) is connected to one input of the first OR gate (120b), and the other input of the first OR gate (120b) is set to a first level. The output of the first OR gate (120b) is used to transmit a third trigger signal. One channel of the first selector (130b) is set to a first level, and the other channel is set to a second level. Its channel selection terminal is used to access the encoding cycle state indication signal, and its output terminal outputs the level of the corresponding channel according to the encoding cycle state indication signal.

4. The encoder-converter according to claim 3, characterized in that, The encoding state generation circuit (200) includes a second encoding state generation circuit (200b); The second encoded state generation circuit (200b) includes: an input judgment component (210b), a second selector (220b), and a first flip-flop (230b); The input judgment component (210b) has: a first judgment component input port (210b_i1), a second judgment component input port (210b_i2), a third judgment component input port (210b_i3), a fourth judgment component input port (210b_i4), a first judgment component output port (210b_o1), a second judgment component output port (210b_o2), a third judgment component output port (210b_o3), and a fourth judgment component output port (210b_o4); The second strobe (220b) has: a first input port (220b_i1), a second input port (220b_i2), a third input port (220b_i3), a fourth input port (220b_i4), a first enable port (220b_e1), a second enable port (220b_e2), a third enable port (220b_e3), a fourth enable port (220b_e4), and a strobe output port (220b_o); The first trigger (230b) has: a first digital input port (D0), a second digital input port (D1), a third digital input port (D2), a fourth digital input port (D3), and an encoded output port (SO2). The first judgment component input port (210b_i1) is used to receive the encoding cycle state indication signal. The second judgment component input port (210b_i2) is connected to the first enable port (220b_e1) and is used to receive the fourth trigger signal. The third judgment component input port (210b_i3) is connected to the comparison result signal generated by the output of the second comparator (110b). The fourth judgment component input port (210b_i4) is used to receive the third trigger signal. The first judgment component output port (210b_o1) is connected to the first digital input port (D0). The second judgment component output port (210b_o2) is connected to the second enable port (220b_e2). The third judgment component output... The port (210b_o3) is connected to the third enable port (220b_e3), the fourth judgment component output port (210b_o4) is connected to the fourth enable port (220b_e4), the first input port (220b_i1) is set to the first level, the second input port (220b_i2) is set to the second level, the third input port (220b_i3) is set to the first level, the fourth input port (220b_i4) is set to the second level, the strobe output port (220b_o) is connected to the second digital input port (D1) and the third digital input port (D2), the fourth digital input port (D3) is set to the second level, and the encoding output port (SO2) is used to output the status encoding value.

5. The encoder-converter according to claim 4, characterized in that, The input judgment component (210b) includes: a second NOT gate (2101b), a third NOT gate (2102b), a fourth NOT gate (2103b), a fifth NOT gate (2104b), a sixth NOT gate (2105b), a first AND gate (2106b), a second AND gate (2107b), a third AND gate (2108b), a fourth AND gate (2109b), a fifth AND gate (2110b), and a sixth AND gate (2111b). The input terminal of the second NOT gate (2101b) serves as the input port (210b_i1) of the first judgment component. The output terminal of the second NOT gate (2101b) is connected to one input terminal of the first AND gate (2106b). The other input terminal of the first AND gate (2106b) is connected to the input terminal of the third NOT gate (2102b) and serves as the input port (210b_i2) of the second judgment component. The output terminal of the first AND gate (2106b) serves as the output port (210b_o1) of the first judgment component. The output of NOT gate (2102b) is connected to one input of the second AND gate (2107b), one input of the third AND gate (2108b), and one input of the fifth AND gate (2110b). The other input of the second AND gate (2107b) is connected to the output of the fourth AND gate (2109b) and the input of the fifth NOT gate (2104b). The output of the second AND gate (2107b) serves as the output port (210b_o2) of the second judgment component. The third AND gate (2108b)... The other input terminal is connected to the output terminal of the sixth AND gate (2111b) and the input terminal of the sixth NOT gate (2105b). The output terminal of the third AND gate (2108b) serves as the output port (210b_o3) of the third judgment component. The other input terminal of the fifth AND gate (2110b) is connected to the output terminal of the fifth NOT gate (2104b). One input terminal of the fifth AND gate (2110b) is connected to the output terminal of the sixth NOT gate (2105b). The output terminal of the fifth AND gate (2110b) serves as the... The fourth judgment component output port (210b_o4) is connected to one input of the sixth AND gate (2111b) and serves as the third judgment component input port (210b_i3). The output of the fourth NOT gate (2103b) is connected to one input of the fourth AND gate (2109b), and the other input of the fourth AND gate (2109b) is connected to the other input of the sixth AND gate (2111b) and serves as the fourth judgment component input port (210b_i4).

6. The encoder-converter according to claim 4, characterized in that, The first flip-flop (230b) also has a first reset port (RST1) and a first clock port (CLK1). In response to the first reset port (RST1) receiving a valid reset signal, the output of the encoded output port (SO2) is set to the initial value; In response to receiving an invalid reset signal at the first reset port (RST1), the encoded output port (SO2) determines the output status encoded value based on the first clock signal received at the first clock port (CLK1) and the signals received at the first digital input port (D0), the second digital input port (D1), the third digital input port (D2), and the fourth digital input port (D3).

7. The encoder-converter according to claim 6, characterized in that, The second encoded state generation circuit (200b) also includes a seventh NOT gate (2112b); The output of the seventh NOT gate (2112b) is connected to the first reset port (RST1), and the input of the seventh NOT gate (2112b) is used to receive the reset signal.

8. The encoding converter according to any one of claims 4-6, characterized in that, The encoder-converter also includes an encoding type conversion circuit (300); The encoding type conversion circuit (300) is used to convert the first encoding to the second encoding, or to convert the second encoding to the first encoding, according to the conversion signal.

9. The encoder-converter according to claim 8, characterized in that, The encoding type conversion circuit (300) includes: a logic judgment component (310) and an encoding conversion component (320); The logic judgment component (310) has: a first logic judgment input port (310a), a second logic judgment input port (310b), a third logic judgment input port (310c), a first logic judgment output port (310d), a second logic judgment output port (310e), a third logic judgment output port (310f), and a fourth logic judgment output port (310g). The encoding conversion component (320) has: a first conversion enable port (320a), a second conversion enable port (320b), a third conversion enable port (320c), a fourth conversion enable port (320d), a first encoding input port (320e), a second encoding input port (320f), a first encoding output port (320g), and a second encoding output port (320h); The first input port (310a) of the logic judgment is used to obtain the number of first encoding states, the second input port (310b) of the logic judgment is used to obtain the maximum number of first encodings, the third input port (310c) of the logic judgment is used to obtain the conversion signal, the first output port (310d) of the logic judgment is connected to the first conversion enable port (320a), the second output port (310e) of the logic judgment is connected to the second conversion enable port (320b), the third output port (310f) of the logic judgment is connected to the third conversion enable port (320c), the fourth output port (310g) of the logic judgment is connected to the fourth conversion enable port (320d), the first encoding input port (320e) is used to obtain the first encoding to be converted, the second encoding input port (320f) is used to obtain the second encoding to be converted, the first encoding output port (320g) is used to output the second encoding obtained by converting the first encoding to be converted, and the second encoding output port (320h) is used to output the first encoding obtained by converting the second encoding to be converted.

10. The encoder-converter according to claim 9, characterized in that, The logic judgment component (310) includes: a third comparator (311), a seventh AND gate (312), an eighth AND gate (313), a ninth AND gate (314), and an eighth NOT gate (315). One input of the third comparator (311) serves as the first input port (310a) of the logic judgment, and the other input of the third comparator (311) serves as the second input port (310b) of the logic judgment. The output of the third comparator (311) is connected to one input of the seventh AND gate (312), one input of the eighth AND gate (313), and one input of the ninth AND gate (314). The other input of the seventh AND gate (312) is connected to the other input of the eighth AND gate (313), and the other input of the ninth AND gate (314). The other input of the 9 AND gate (314) and the input of the 8 NOT gate (315) are connected to serve as the third input port (310c) of the logic judgment. The output of the 7 AND gate serves as the first output port (310d) of the logic judgment. The output of the 8 AND gate (313) serves as the second output port (310e) of the logic judgment. The output of the 9 AND gate (314) serves as the third output port (310f) of the logic judgment. The output of the 8 NOT gate (315) serves as the fourth output port (310g) of the logic judgment.

11. The encoder-converter according to claim 9, characterized in that, The encoding conversion component (320) includes: a fourth buffer (321), a fifth buffer (322), a sixth buffer (323), a seventh buffer (324), and a state machine (325); The state machine (325) has: a first indicator port (325a), a second indicator port (325b), a third indicator port (325c), a fourth indicator port (325d), a first state input port (325e), a second state input port (325f), a first state output port (325g), and a second state output port (325h); The enable terminal of the fourth buffer (321) serves as the first conversion enable port (320a). The input terminal of the fourth buffer (321) is used to input the first digital code. The output terminal of the fourth buffer (321) is connected to the first indicator port (325a). The enable terminal of the fifth buffer (322) serves as the second conversion enable port (320b). The input terminal of the fifth buffer (322) is used to input the second digital code. The output terminal of the fifth buffer (322) is connected to the second indicator port (325b). The enable terminal of the sixth buffer (323) serves as the third conversion enable port (320c). The input terminal of the sixth buffer (323) is used to input the third digital code. The output terminal of the seventh buffer (323) is connected to the third indicator port (325c). The enable terminal of the seventh buffer (324) serves as the fourth conversion enable port (320d). The input terminal of the seventh buffer (324) is used to input the fourth digital code. The output terminal of the seventh buffer (324) is connected to the fourth indicator port (325d). The first state input port (325e) serves as the first code input port (320e). The second state input port (325f) serves as the second code input port (320f). The first state output port (325g) serves as the first code output port (320g). The second state output port (325h) serves as the second code output port (320h).

12. The encoder-converter according to claim 8, characterized in that, The second encoded state generation circuit (200b) also includes a function switching component (240b); The function switching component (240b) is used to acquire a reset signal and a conversion signal, and set the output of the encoding output port (SO2) of the first flip-flop (230b) in the second encoding state generation circuit (200b) to an initial value according to the reset signal and the conversion signal, or, make the encoding output port (SO2) determine the output state encoding value according to the first clock signal received by the first clock port (CLK1) and the signals received by the first digital input port (D0), the second digital input port (D1), the third digital input port (D2) and the fourth digital input port (D3).

13. The encoder-converter according to claim 12, characterized in that, The function switching component (240b) includes: a ninth NOT gate (2113b) and a second OR gate (2114b). The input terminal of the ninth NOT gate (2113b) is used to receive the reset signal, the output terminal of the ninth NOT gate (2113b) is connected to one input terminal of the second OR gate (2114b), the other input terminal of the second OR gate (2114b) is used to receive the conversion signal, and the output terminal of the second OR gate (2114b) is connected to the first reset port (RST1) of the first flip-flop (230b).

14. The encoder-converter according to claim 1, characterized in that, The encoder-converter also includes a random number generation circuit (400). The random number generation circuit (400) includes: a second flip-flop (410), a third flip-flop (420), an eighth buffer (430), a tenth AND gate (440), an eleventh AND gate (450), a tenth NOT gate (460), and an eleventh NOT gate (470). The clock port of the second flip-flop (410) is used to receive the first clock signal. One input of the tenth AND gate (440) is used to receive the encoded cycle state indication signal. The input of the tenth NOT gate (460) is used to receive the fourth trigger signal. The output of the tenth NOT gate (460) is connected to the other input of the tenth AND gate (440). The output of the tenth AND gate (440) is connected to the data input of the second flip-flop (410). The reset terminal of the second flip-flop (410) is connected to the reset terminal of the third flip-flop (420) and the output of the eleventh NOT gate (470). The input terminal of the 0) is used to connect the reset signal. The clock port of the third flip-flop (420) is used to connect the second clock signal. One input terminal of the eleventh AND gate (450) is connected to its other input terminal to connect the status code value. The output terminal of the eleventh AND gate (450) is connected to the data input terminal of the third flip-flop (420). The data output terminal of the second flip-flop (410) is connected to the enable terminal of the eighth buffer (430). The data output terminal of the third flip-flop (420) is connected to the input terminal of the eighth buffer (430). The output terminal of the eighth buffer (430) is used to output the generated random number.

15. An encoding conversion method, characterized in that, include: Obtain the number of first-encoded states and the maximum number of first-encoded states; If the number of the first encoded states is less than the maximum number of the first codes, a first encoded concatenation state is generated, and the states of the first codes are cyclically transitioned in the following manner: The first encoding start state is sequentially transformed into the first encoding end state through several first encoding intermediate states, and then transformed into the first encoding start state through the first encoding connection state; wherein, the first encoding connection state corresponds to the execution of a no-operation.

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