Display device

Abstract

This disclosure relates to a display device. An electroluminescent display device is provided, comprising: a substrate including a display area and a non-display area; a plurality of first signal lines in the display area; a plurality of second signal lines disposed in the display area and extending in a direction perpendicular to the plurality of first signal lines; a plurality of pad electrodes in the non-display area; a plurality of link lines disposed in the non-display area and electrically connected to the plurality of pad electrodes and the plurality of first signal lines; a low power supply voltage contact in the non-display area; and a shielding wire between the plurality of link lines and the low power supply voltage contact.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10-2024-0195066, filed on December 24, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to display devices. Background Technology

[0004] With the development of the information society, the demand for display devices for displaying images is increasing in various forms. Therefore, in recent years, various display devices such as liquid crystal displays (LCDs), plasma display panels (PDPs), and organic light-emitting displays (OLEDs) have been used.

[0005] Among display devices, organic light-emitting diodes (OLEDs) are self-emissive and offer superior viewing angles and contrast compared to liquid crystal displays (LCDs). They are also lightweight and thin due to the elimination of the need for a separate backlight, and their power consumption is advantageous. Furthermore, OLEDs are driven by low-voltage direct current (DC), resulting in fast response times and, most notably, low manufacturing costs.

[0006] Multiple signal lines are arranged in the non-display area of ​​the display device, and low-power supply voltage contacts with relatively large areas are arranged near these signal lines. During the manufacturing process, static electricity may remain in these low-power supply voltage contacts. Therefore, due to static electricity, irregular signals may be applied to the multiple signal lines, causing the threshold voltage Vth of the thin-film transistor in each pixel of the display area to change. In this case, when the completed display device is driven, the shape of blemishes or lines may appear on the display device according to the change in threshold voltage Vth, resulting in problems that impair the user's vision. Summary of the Invention

[0007] This disclosure is made in view of the above-mentioned problems, and one aspect of this disclosure is to provide a display device that has a shielding line between a low power supply voltage line and multiple data lines, and minimizes or eliminates fluctuations in the threshold voltage of the driving thin-film transistors provided in each pixel due to electrostatic discharge generated during the inspection phase.

[0008] According to one aspect of this disclosure, the above and other technical effects can be achieved by providing an electroluminescent display device, which includes: a substrate including a display area and a non-display area; a plurality of first signal lines in the display area; a plurality of second signal lines disposed in the display area and extending in a direction perpendicular to the plurality of first signal lines; a plurality of pad electrodes in the non-display area; a plurality of link lines disposed in the non-display area and electrically connected to the plurality of pad electrodes and the plurality of first signal lines; a low power supply voltage contact in the non-display area; and a shielding wire between the plurality of link lines and the low power supply voltage contact.

[0009] In addition, according to one aspect of this disclosure, the above and other technical effects can be achieved by providing an electroluminescent display device, which includes: a substrate including a display area and a non-display area; a low power supply voltage contact disposed in the non-display area; a low power supply voltage line disposed in the non-display area and connected to the low power supply voltage contact; and a bridging wire disposed in the non-display area and connected to the low power supply voltage contact, wherein the pad electrode is connected to the low power supply voltage line and not connected to the bridging wire.

[0010] It should be understood that both the foregoing general description and the following detailed description are exemplary and illustrative, and are intended to provide further explanation of the claimed inventive concept. Attached Figure Description

[0011] The accompanying drawings are included to provide a further understanding of this disclosure and are incorporated in and constitute a part of this application. The drawings illustrate embodiments of the disclosure and, together with the description, explain the principles of the disclosure. In the drawings:

[0012] Figure 1 This is a schematic perspective view of a display device according to an embodiment of the present disclosure.

[0013] Figure 2 This is a schematic plan view of a display device according to an embodiment of the present disclosure.

[0014] Figure 3 This is a circuit diagram of a pixel provided in a display device according to an embodiment of the present disclosure.

[0015] Figure 4 This is a plan view of a display device according to an embodiment of the present disclosure.

[0016] Figure 5A and Figure 5B This is a processing plan view for manufacturing a display device according to an embodiment of the present disclosure.

[0017] Figure 6 This is a cross-sectional view of a display device according to an embodiment of the present disclosure. In this case, Figure 6 Involving Figure 4 The cross section II′ and the cross section of any pixel.

[0018] Figure 7A and Figure 7B This is a plan view of the display device according to an embodiment of the present disclosure before the cutting process, and Figure 7C and Figure 7D This is a plan view of the display device after cutting according to an embodiment of the present disclosure.

[0019] Figure 7E and Figure 7F This is a plan view of a display device according to another embodiment of the present disclosure.

[0020] Figure 8 This is a plan view of a display device according to another embodiment of the present disclosure.

[0021] Figure 9 This is a plan view of a display device according to another embodiment of the present disclosure.

[0022] Figure 10 This is a cross-sectional view of a display device according to another embodiment of the present disclosure. In this case, Figure 10 Involving Figure 9 Section II-II′.

[0023] Figure 11 This is a plan view of a display device according to another embodiment of the present disclosure.

[0024] Figure 12 This is a cross-sectional view of a display device according to another embodiment of the present disclosure. In this case, Figure 12 Involving Figure 11 Section III-III′.

[0025] Figure 13 This is a plan view of a display device according to another embodiment of the present disclosure.

[0026] Figure 14 This is a plan view of a display device according to another embodiment of the present disclosure.

[0027] Figure 15 This is a plan view of a display device according to another embodiment of the present disclosure.

[0028] Throughout the accompanying drawings and detailed embodiments, unless otherwise described, the same reference numerals should be understood to refer to the same elements, features, and structures. For clarity, illustration, and convenience, the relative dimensions and depictions of these elements may be exaggerated. Detailed Implementation

[0029] Implementations of this disclosure will now be described in detail, examples of which are illustrated in the accompanying drawings. The described progression of processing steps and / or operations is exemplary; however, the order of steps and / or operations is not limited to the order set forth herein, except that they must occur in a specific order, and can be varied as is known in the art. The names of the various elements used in the following description may have been chosen solely for the convenience of writing this specification, and may therefore differ from the names used in actual products.

[0030] The advantages and features of this disclosure and its implementation methods will be illustrated by the following examples described with reference to the accompanying drawings. However, this disclosure may be implemented in various forms and should not be construed as limited to the examples set forth herein. Rather, these examples are provided so that the specification of this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art. Furthermore, the scope of this disclosure is defined only by the appended claims.

[0031] The shapes, dimensions, ratios, angles, and numbers of the examples disclosed in the accompanying drawings to describe the present disclosure are merely illustrative, and therefore, the present disclosure is not limited to the details shown. Like reference numerals refer to like elements throughout the specification, unless otherwise stated. In the following description, detailed descriptions of relevant known functions or configurations will be omitted where such descriptions are deemed unnecessarily obscuring the focus of the present disclosure. Where terms such as “comprising,” “having,” and “including” are used in the present disclosure, an additional part may be added unless “only” is used. Unless otherwise indicated, singular terms may include plural forms.

[0032] When interpreting a component, it is interpreted as including the error range even if there is no separate explicit description of the error range.

[0033] When describing positional relationships, such as "above," "over," "below," and "next to," one or more parts may be positioned between two other parts unless "exactly" or "directly" is used. Terms such as "below," "lower," "above," "upper," etc., may be used herein to describe relationships between elements shown in the accompanying drawings. It should be understood that these terms are spatially relative and based on the orientation depicted in the accompanying drawings.

[0034] The description of time relationships can include cases where time priority is described as "after", "following", or "before", and is not sequential unless "immediately" or "right away" is used.

[0035] Although terms like "first," "second," etc., are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, in the technical concept of this disclosure, the "first component" mentioned below can be the "second component."

[0036] It should be understood that although the terms “first,” “second,” “A,” “B,” “(a),” and “(b)” are used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0037] If a component is described as “connected,” “coupled,” or “attached” to another component, then that component may be directly connected, coupled, or attached to that other component. However, it should be understood that, without any specific description, other components may be inserted between components that may be indirectly connected, coupled, or attached.

[0038] It should be understood that if a component or layer is described as "in contact" or "overlapping" with another component or layer, then the component or layer may be in direct contact or overlap with the other component or layer, but in the absence of an explicit description, other components may be inserted between components that may be in indirect contact or overlap.

[0039] The term “at least one” should be understood to include any and all combinations of one or more of the associated listed items. For example, “at least one of the first element, the second element, or the third element” means all combinations of the three listed elements, combinations of any two of the three elements, and each individual element, namely the first element, the second element, or the third element.

[0040] The terms “first direction,” “second direction,” “third direction,” “X-axis direction,” “Y-axis direction,” and “Z-axis direction” should not be interpreted merely as geometrically perpendicular to each other, but may mean that the configuration of this disclosure has a wider range of directions within the scope to which the configuration of this disclosure can function.

[0041] Features of each of the various examples in this disclosure may be partially or completely coupled or combined with each other, various interoperability and driving are technically possible, and each of the examples may be implemented independently of each other or may be implemented together in a related relationship.

[0042] In the following, one embodiment of the present disclosure will be described in detail with reference to the accompanying drawings.

[0043] Figure 1 This is a schematic perspective view of a display device according to an embodiment of the present disclosure.

[0044] Figure 2 This is a schematic plan view of a display device according to an embodiment of the present disclosure.

[0045] In the following text, the X-axis represents the direction parallel to the gate line, the Y-axis represents the direction parallel to the data line, and the Z-axis represents the height direction of the display device 10.

[0046] Although the display device 10 according to the embodiments of this disclosure is mainly implemented as an organic light-emitting display, it can be implemented as a liquid crystal display (LCD), a plasma display panel (PDP), a quantum dot light-emitting display (QLED), or an electrophoretic display.

[0047] Reference Figure 1 and Figure 2 The display device 10 according to an embodiment of the present disclosure includes a display panel 100, a source driver integrated circuit (hereinafter referred to as "source driver IC") 310, a flexible film 320, a circuit board 330, and a timing control unit (hereinafter also referred to as a timing controller) 340.

[0048] The display panel 100 includes a first substrate 100a and a second substrate 100b facing each other. The second substrate 100b may be an encapsulation substrate. The first substrate 100a may be a plastic film, a glass substrate, or a silicon wafer substrate formed by semiconductor processing. The second substrate 100b may be a plastic film, a glass substrate, or an encapsulation film. The first substrate 100a and the second substrate 100b may be formed of a transparent material.

[0049] The display panel 100 can be divided into a display area DA in which pixels are formed to display images and a non-display area NDA in which no images are displayed.

[0050] Multiple vertical signal lines (hereinafter also referred to as first signal lines) SL1, multiple horizontal signal lines (hereinafter also referred to as second signal lines) SL2, and multiple pixels P can be set in the display area DA, and a pad area PA containing pads and at least one gate driver 305 can be set in the non-display area NDA. Meanwhile, Figure 2 The gate driver 305 is shown disposed on one side and the other side of the display panel 100, but the present disclosure is not limited thereto.

[0051] Multiple vertical signal lines SL1 may extend in a second direction (e.g., the Y-axis direction) and may intersect with multiple horizontal signal lines SL2 in the display area DA. The multiple vertical signal lines SL1 may be, for example, high power supply voltage lines for supplying high power supply voltage to the anode, reference voltage lines for transmitting reference signals to each of the multiple pixels P, data lines for transmitting data signals to each of the multiple pixels P, etc., but are not limited thereto, and the multiple vertical signal lines SL1 may be one of various lines for transmitting signals according to the level of technology in the art.

[0052] Multiple horizontal signal lines SL2 may extend in a first direction (e.g., the X-axis direction) within the display area DA. The multiple horizontal signal lines SL2 may be, for example, gate lines that transmit gate signals to each of a plurality of pixels P, but are not limited thereto, and the multiple horizontal signal lines SL2 may be one of various lines for transmitting signals according to the level of technology in the art.

[0053] Multiple pixels P are set in an area where multiple first signal lines SL1 or multiple first signal lines SL1 and multiple second signal lines SL2 intersect, and emit predetermined light to display an image.

[0054] The source driver IC 310 receives digital video data and source control signals from the timing controller 340. Based on the source control signals, the source driver IC 310 converts the digital video data into analog data voltage and supplies the converted analog data to the data lines. When the source driver IC 310 is manufactured as a driver chip, it can be mounted on the flexible film 320 using a chip-on-film (COF) or chip-on-plastic (COP) approach.

[0055] Lines connecting the pads to the source driver IC 310 and lines connecting the pads to the circuit board 330 can be formed in the flexible film 320. The flexible film 320 is attached to the pads using an anisotropic conductive film, and thus the lines of the flexible film 320 and the pads can be connected.

[0056] The circuit board 330 can be attached to the flexible film 320. Multiple circuits implemented using a driver chip can be mounted on the circuit board 330. For example, a timing controller 340 can be mounted on the circuit board 330. The circuit board 330 can be a printed circuit board or a flexible printed circuit board.

[0057] The timing controller 340 receives digital video data and timing signals from an external system board (not shown). Based on the timing signals, the timing controller 340 generates gate control signals for controlling the operating timing of the gate driver and source control signals for controlling the source driver IC 310. The timing controller 340 supplies the gate control signals to the gate driver 305 and the source control signals to the source driver IC 310.

[0058] Figure 3 This is a circuit diagram of a pixel provided in a display device according to an embodiment of the present disclosure.

[0059] like Figure 3 As shown, a display device according to an exemplary embodiment of the present disclosure includes a first thin-film transistor to a third thin-film transistor T1, T2 and T3 and a capacitor Cst.

[0060] The first thin-film transistor T1 is a driving thin-film transistor, the second thin-film transistor T2 is a switching thin-film transistor, and the third thin-film transistor T3 is a sensing thin-film transistor.

[0061] The first thin-film transistor T1 switches according to the data voltage Vdata supplied from the second thin-film transistor T2, generates a data current according to the driving voltage VDD supplied to the power line PL, and supplies the data current to the organic light-emitting diode OLED.

[0062] The second thin-film transistor T2 is switched according to the gate signal GS supplied to the gate line GL, and the data voltage Vdata supplied to the data line DL is supplied to the first thin-film transistor T1.

[0063] The third thin-film transistor T3 is switched according to the sensing control signal SCS supplied to the sensing control line SCL, and therefore, the threshold voltage of the first thin-film transistor T1 is sensed by using the reference voltage Vref supplied to the reference line REFL.

[0064] The capacitor Cst is used to maintain the data voltage supplied to the first thin-film transistor T1 within one frame, and is disposed between the gate electrode and the source electrode of the first thin-film transistor T1.

[0065] Organic light-emitting diodes (OLEDs) emit predetermined light according to the data current supplied from the first thin-film transistor T1.

[0066] Figure 4 This is a plan view of a display device according to an embodiment of the present disclosure.

[0067] like Figure 4As shown, the display device according to an embodiment of the present disclosure includes a first substrate 100a, a plurality of pad electrodes PE, a plurality of link lines LL, a low power supply voltage contact VSC, a shield line ESL, a first high power supply voltage short circuit bar VDDSa, a second high power supply voltage short circuit bar VDDSb, a plurality of first signal lines SL1, a plurality of second signal lines SL2, and a plurality of pixels P.

[0068] The substrate 100a includes a non-display area NDA and a display area DA.

[0069] The non-display area NDA can be defined as the area on the first substrate 100a other than the display area DA. Various wirings, electrodes, and thin-film transistors can be disposed in the non-display area NDA, and these wirings, electrodes, and thin-film transistors can transmit signals for realizing images or videos in the display area DA.

[0070] The non-display area NDA may include a first non-display area NDAa located on one side of the display area DA, for example, above it, and a second non-display area NDAab located on the other side of the display area DA, for example, below it.

[0071] The first non-display area NDAa and the second non-display area NAb can be positioned so that they face each other relative to the display area DA.

[0072] The first non-display area NDAa may include the pad area PA and the link area LA.

[0073] The pad area PA can include multiple pad electrodes PE. The multiple pad electrodes PE can receive material from a flexible film (see...). Figure 1 (320) sends multiple signals and sends the signals to multiple link lines LL.

[0074] Multiple pad electrodes PE may include, for example, a first pad electrode PE1, a second pad electrode PE2, a third pad electrode PE3, a fourth pad electrode PE4, and a fifth pad electrode PE5.

[0075] In this configuration, the first pad electrode PE1 can apply a data voltage to the data line connected to each of the multiple pixels P, the second pad electrode PE2 can apply a reference voltage to the reference line, the third pad electrode PE3 can apply a high power supply voltage to the first high power supply voltage shorting bar VDDSa, the fourth pad electrode PE4 can apply a low power supply voltage to the low power supply voltage contact VSC, and the fifth pad electrode PE5 can apply a voltage to the shield line ESL.

[0076] The first pad electrode PE1 includes pad electrode PE1a (1-1), pad electrode PE1b (1-2), pad electrode PE1c (1-3), and pad electrode PE1d (1-4). In this case, to emit red (R), green (G), blue (B), and white (W) light in multiple pixels P, each of pad electrodes PE1a to PE1d can be drawn from the flexible film (see...). Figure 1 The data voltage received by (320) is applied to any one of the multiple first signal lines SL1, such as any one of the first data lines DL1 to the fourth data line DL4. Meanwhile, the arrangement of the first-1 pad electrodes PE1a to the first-4 pad electrodes PE1d is not limited thereto.

[0077] The second pad electrode PE2 can be removed from the flexible film 320 (see...) Figure 1 The received reference voltage is applied to other first signal lines, such as the reference line REFL among multiple first signal lines SL1.

[0078] The third pad electrode PE3 can transmit the first power source, for example, from the flexible membrane (see...). Figure 1 The high power supply voltage received by (320) is applied to the first high power supply voltage short-circuit bar VDDSa.

[0079] The fourth pad electrode PE4 can transmit a second power source, for example, from the flexible film (see...). Figure 1 The low power supply voltage received by (320) is applied to the low power supply voltage contact VSC.

[0080] The fourth pad electrode PE4 can be formed in multiple forms, for example, and as follows: Figure 4 As shown, it can be configured as a combination of three left pad electrodes and three right pad electrodes, but the number and arrangement of the fourth pad electrode PE4 and the low power supply voltage contact VSC are not limited thereto, and various changes can be made according to the art.

[0081] The fifth pad electrode PE5 can be transferred from the flexible film (see...) Figure 1 The first voltage received from the flexible film (see 320) is applied to the shielding line ESL. According to embodiments of this disclosure, by... Figure 1 The first voltage received by (320) is sent to the shield line ESL through the fifth pad electrode PE5, which can keep the shield line ESL from floating.

[0082] The link area LA includes multiple link lines LL, a low power supply voltage contact VSC, a shield line ESL, and a first high power supply voltage short-circuit bar VDDSa.

[0083] Multiple link lines LL can transmit signals applied from the pad electrodes PE located in the pad area PA to multiple first signal lines SL1 and / or the first high power supply voltage short-circuit bar VDDSa.

[0084] The multiple link lines LL may include a first link line LL1, a second link line LL2, and a third link line LL3. The first link line LL1, the second link line LL2, and the third link line LL3 may extend in a second direction Y (e.g., the vertical direction) and may extend from the first non-display area NDAa toward the display area DA.

[0085] The first link LL1 may include link LL1a (1-1), link LL1b (1-2), link LL1c (1-3), and link LL1d (1-4).

[0086] Link lines LL1a (1-1) to LL1d (1-4) can be electrically connected to pad electrodes PE1a (1-1) to PE1d (1-4), respectively. For example, to emit red (R), green (G), blue (B), or white (W) light from multiple pixels P, light is emitted from a flexible film (see...). Figure 1 The received data voltage can be transmitted via any one of the first signal lines SL1, such as any one of the first data lines DL1 to the fourth data line DL4, through any one of the first link line LL1a to the first link line LL1d.

[0087] Multiple pixels P can be configured to emit red (R), green (G), and blue (B) light other than white (W), and in this case, the first link line LL1 includes the first-1 link line LL1a, the first-2 link line LL1b, and the first-3 link line LL1c, and the first-1 link line LL1a to the first-3 link line LL1c can be connected to the first data line DL1 to the third data line DL3, respectively.

[0088] The second connection line LL2 can be electrically connected to the second pad electrode PE2. The second connection line LL2 can transfer the material from the flexible film (see...) Figure 1 The reference voltage received by (320) is sent to another first signal line, such as the reference line REFL, among the multiple first signal lines SL1. However, in some cases, the second link line LL2 may not be provided, and in such cases, the second pad electrode PE2 may also not be provided.

[0089] The third link line LL3 can be electrically connected to the third pad electrode PE3. The third link line LL3 can transmit a first power source, for example, from the flexible membrane (see...). Figure 1The high power supply voltage received by (320) is sent to the first high power supply voltage short-circuit bar VDDSa. For example, the third link line LL3 can be electrically connected to the first high power supply voltage short-circuit bar VDDSa through the first contact hole CH1.

[0090] The low power supply voltage contact VSC can be positioned adjacent to multiple link lines LL. The low power supply voltage contact VSC can be formed in a polygonal shape, with one side (e.g., the upper side) being longer and the other side (e.g., the lower side) being shorter, but is not limited thereto. When viewed in a plan view, the low power supply voltage contact VSC is shown as having a hexagonal shape, but is not limited thereto, and can also be formed in the shape of an inverted triangle, an inverted trapezoid, etc.

[0091] The low power supply voltage contact VSC can be connected to the low power supply voltage line VSL extending toward the pad area PA. For example, the low power supply voltage contact VSC can be electrically connected to the low power supply voltage line VSL through the third contact hole CH3.

[0092] The low power supply voltage contact VSC can receive voltage from the source driver IC 310 connected to the pad area PA and send the low power supply voltage to the cathode of the pixel. Specifically, the low power supply voltage contact VSC can receive the low power supply voltage applied to the fourth pad electrode PE4 disposed in the pad area PA through the low power supply voltage line VSL.

[0093] The shielded line ESL can be placed between multiple link lines LL and the low power supply voltage contact VSC.

[0094] According to embodiments of this disclosure, the shield line ESL can be disposed between the multiple link lines LL and the low power supply voltage contact VSC. Therefore, in the manufacturing process of the display device according to embodiments of this disclosure, the influence of the voltage applied to the low power supply voltage contact VSC during the inspection process on the multiple link lines LL can be minimized. For example, the inspection process may be a process of checking whether a signal such as a data voltage is properly applied to the multiple first signal lines SL1, or a process of checking whether the low power supply voltage is properly applied to the low power supply voltage contact VSC, but is not limited thereto.

[0095] Specifically, when a voltage is applied to the low power supply voltage contact VSC, the threshold voltage Vth of the driving thin-film transistor TRd of the pixel connected to the first data line DL1 and the first link line LL1 closest to the low power supply voltage contact VSC may change. However, according to embodiments of this disclosure, the effect of the voltage applied to the low power supply voltage contact VSC during the inspection process on the multiple link lines LL can be minimized or eliminated by the shielding line ESL. Meanwhile, reference will be made later... Figure 5A and Figure 5B Describe the principles in detail.

[0096] Therefore, according to embodiments of this disclosure, by providing a shielding line ESL, fluctuations in the threshold voltage Vth of the plurality of driving thin-film transistors disposed in the plurality of pixels in the display device according to embodiments of this disclosure can be minimized. Thus, the appearance of blemishes or lines can be minimized or prevented when displaying or reproducing an image.

[0097] According to embodiments of this disclosure, the shielding wire ESL can surround the outer side of the low power supply voltage contact VSC within the link region LA. Simultaneously, the interior of the low power supply voltage contact VSC can be defined as the interior of the contact CNT formed based on the boundary of the low power supply voltage contact VSC, and the exterior of the low power supply voltage contact VSC can be defined as the exterior of the boundary of the low power supply voltage contact VSC where no contact CNT is formed.

[0098] The shielded line ESL can be connected to the flexible film attached to the fifth pad electrode PE5 (see...). Figure 1 (320) Receive voltage. By forming it in this way, even when driving the display device, the mutual interference between the low power supply voltage contact VSC and the first link line LL1 can be minimized through the shielding line ESL.

[0099] The first high power supply voltage short-circuit bar VDDSa can extend along the first direction X. The first high power supply voltage short-circuit bars VDDSa can be spaced apart and separated from each other in the first direction X, and can be arranged in a line. However, the present disclosure is not limited thereto, and the first high power supply voltage short-circuit bars VDDSa can be provided on the first substrate 100a in the form of bars in the first direction X.

[0100] The first high power supply voltage shorting bar VDDSa can receive a high power supply voltage sent from the third pad electrode PE3 to apply the high power supply voltage to another first signal line, such as the high power supply voltage line VDDL. In this way, by applying a high power supply voltage using the first high power supply voltage shorting bar VDDSa, a relatively high voltage can be stably applied to the high power supply voltage lines VDDL, which are individually located in multiple pixels P.

[0101] The second non-display area NDAb may include a second high power supply voltage short-circuit bar VDDSb.

[0102] The second high power supply voltage short circuit bar VDDSb can be electrically connected to the first high power supply voltage short circuit bar VDDSa via the high power supply voltage line VDDL among the multiple first signal lines SL1.

[0103] The display area DA is an area containing multiple first signal lines SL1, multiple second signal lines SL2, and multiple pixels P. The display area DA can be an area where images or videos are provided by light emitted from the multiple pixels P.

[0104] Multiple first signal lines SL1 include first data lines DL1 to fourth data lines DL4, reference line REFL, and high power supply voltage line VDDL.

[0105] The first data line DL1 to the fourth data line DL4 can be extended from the first-1 link line LL1a to the first-4 link line LL1d to receive signals transmitted from the first-1 pad electrode PE1a to the first-4 pad electrode PE1d, respectively.

[0106] Specifically, the first data line DL1 can extend from the first-1 link line LL1a to receive signals transmitted from the first-1 pad electrode PE1a. Similarly, the second data line DL2 can extend from the first-2 link line LL1b to receive signals transmitted from the first-2 pad electrode PE1b, and the third data line DL3 can extend from the first-3 link line LL1c to receive signals transmitted from the first-3 pad electrode PE1c, and the fourth data line DL4 can extend from the first-4 link line LL1d to receive signals transmitted from the first-4 pad electrode PE1d. In this case, the first data line DL1 to the fourth data line DL4 can be integrally formed with the first-1 link line LL1a to the first-4 link line LL1d, respectively, but this disclosure is not limited thereto.

[0107] The reference line REFL can be extended from the second link line LL2 to receive the reference voltage sent from the second pad electrode PE2.

[0108] The reference line REFL is connected to each of the multiple pixels P, and the threshold voltage of the driving thin-film transistor (driving TFT) set in the multiple pixels P can be sensed.

[0109] A high power supply voltage line VDDL can be disposed between a first high power supply voltage shorting bar VDDSa and a second high power supply voltage shorting bar VDDSb. For example, one end (e.g., the upper end) of the high power supply voltage line VDDL can be electrically connected to the first high power supply voltage shorting bar VDDSa through the 2-1 contact hole CH2a, and the other end (e.g., the lower end) of the high power supply voltage line VDDL can be electrically connected to the second high power supply voltage shorting bar VDDSb through the 2-2 contact hole CH2b.

[0110] The high power supply voltage line VDDL can be set between the first high power supply voltage shorting bar VDDSa and the second high power supply voltage shorting bar VDDSb, and the high power supply voltage can be applied to each of the plurality of pixels P set in the display area DA to provide power to each of the plurality of pixels P to emit light.

[0111] Multiple second signal lines SL2 include gate line GL.

[0112] The gate line GL can extend along a first direction X, such as a horizontal direction. The gate line GL can overlap or intersect with the first data lines DL1 to the fourth data lines DL4 while extending along the first direction X. In this case, multiple pixels P can be disposed in the area formed by the intersection of the gate line GL and the first data lines DL1 to the fourth data lines DL4.

[0113] Multiple pixels P can be located in the area where multiple first signal lines SL1 and multiple second signal lines SL2 intersect in the display area DA. For example, a data voltage can be supplied to each of the multiple pixels P from any of the first data lines DL1 to the fourth data lines DL4, a gate signal can be supplied from the gate line GL, a reference voltage can be applied from the reference line REFL, and a high power supply voltage can be applied from the high power supply voltage line VDDL.

[0114] Figure 5A and Figure 5B This is a processing plan view for manufacturing a display device according to an embodiment of the present disclosure. Figure 5A and Figure 5B Involving according to Figure 4 The display device of the embodiment is described, and the same reference numerals are assigned to the same configuration, and repeated descriptions are omitted.

[0115] First, such as Figure 5AAs shown, in order to manufacture a display device according to an embodiment of the present disclosure, multiple link lines LL, low power supply voltage contacts VSC, shielding lines ESL, first high power supply voltage short-circuit bars VDDSa, second high power supply voltage short-circuit bars VDDSb, multiple first signal lines SL1, multiple second signal lines SL2, and multiple pixels P can be formed on a first substrate 100a. Figure 5A In the implementation scenario, no pad area is formed (see...). Figure 4 The PA is used to test whether the various lines, electrodes and thin-film transistors set in the display device disclosed herein are operating properly.

[0116] In other words, pad electrodes can be avoided in multiple link lines LL (see...). Figure 4 In the case of PE), an inspection area IA is formed. In this case, the inspection area IA can be set on one side, for example, the upper side, of the first non-display area NDAa.

[0117] The inspection area (IA) includes multiple inspection units (IP) and multiple inspection lines (IL).

[0118] Multiple inspection units (IPs) include the high power supply voltage inspection unit (VDDP), the first data voltage inspection units (DVPa) through the fourth data voltage inspection units (DVPd), the reference voltage inspection unit (REFVP), and the low power supply voltage inspection unit (VSSP).

[0119] The multiple check lines IL include the high power supply voltage check line VDDIL, the first data voltage check lines DILa to the fourth data voltage check lines DILd, the reference voltage check line REFIL, the shield check line ESIL, and the low power supply voltage line VSL.

[0120] The first data voltage check line DILa to the fourth data voltage check line DILd can be formed in the same way as the process of forming the first-1 link line LL1a to the first-4 link line LL1d, the reference voltage check line REFIL can be formed in the same way as the process of forming the second link line LL2, and the high power supply voltage check line VDDIL can be formed in the same way as the process of forming the third link line LL3.

[0121] By applying voltage to various lines, electrodes, and thin-film transistors located in the non-display area NDA and the display area DA, the inspection area IA can check in advance whether each component in the display device is operating properly before completion, thereby reducing the defect rate of the finished product and increasing production output.

[0122] Specifically, each of the inspection units IP located in the inspection area IA can be electrically connected to multiple link lines LL and / or low power supply voltage lines VSL via multiple inspection lines IL. In this case, some of the inspection units IP can check whether the signal is being properly applied to multiple first signal lines SL1 and multiple pixels P located in the display area DA via multiple link lines LL.

[0123] According to embodiments of this disclosure, the shielded test line ESIL can be an extension of the shielded line ESL. Alternatively, the shielded test line ESIL can be integrally formed with the shielded line ESL. In this case, the shielded test line ESIL can be electrically connected to any of the test sections IP. For example, the shielded test line ESIL can extend from the shielded line ESL and can be electrically connected to the first data voltage test section DVPa.

[0124] When the voltage sent from the first data voltage check unit DVPa is applied to the shield line ESL, interference caused by static electricity between the low power supply voltage contact VSC and the first-1 link line LL1a is reduced. Therefore, in some of the pixels P electrically connected to the first data line DL1 integrally formed with the first-1 link line LL1a, interference caused by static electricity generated by the voltage applied to the low power supply voltage contact VSC is reduced.

[0125] Therefore, fluctuations in the threshold voltage Vth of the driving thin-film transistor Td in some of the multiple pixels P electrically connected to the first data line DL1 can be minimized or prevented.

[0126] At the same time, Figure 5A The diagram only shows the shielded test line ESIL connected to the first data voltage check section DVPa, but this disclosure is not limited thereto, and the shielded test line ESIL can be electrically connected to any one of the second data voltage check sections DVPb to the fourth data voltage check section DVPd, the reference voltage check section REFVP, the high power supply voltage check section VDDP, and the low power supply voltage check section VSSP.

[0127] Furthermore, according to embodiments of this disclosure, the shielded inspection line ESIL overlaps with any one of the plurality of inspection sections provided in the inspection area IA to ensure capacitance and thus perform inspection stably.

[0128] Next, as Figure 5B As shown, it can be disconnected or cut. Figure 5AThe display device undergoes inspection processing such that only the display area DA, the first non-display area NDAa, and the second non-display area NDAb are retained along the cutting line CL. After removing a portion of the substrate 100a and the inspection area IA along the cutting line CL, multiple pad electrodes PE can be formed on one side of multiple link lines LL to connect the flexible film (see...). Figure 1 (320). By forming a plurality of pad electrodes PE as described above, a display device according to an embodiment of the present disclosure can be realized.

[0129] Figure 6 This is a cross-sectional view of a display device according to an embodiment of the present disclosure. In this case, Figure 6 Involving Figure 4 The cross section II′ and the cross section of any pixel. Meanwhile, Figure 6 Involving Figure 4 as well as Figure 5A and Figure 5B The implementation methods are described, and the same reference numerals are assigned to the same configurations, and repeated descriptions are omitted.

[0130] like Figure 6 As shown, the display device according to an embodiment of the present disclosure includes a first substrate 100a, a shielding line ESL, a light blocking layer 105, a buffer layer 110, an active layer 120, a gate insulating layer 130, a low power supply voltage contact VSC, a gate electrode 140, an interlayer insulating layer 150, a source electrode 161, a drain electrode 163, a planarization layer 170, a first electrode 200, a dam 210, a light-emitting layer 220, and a second electrode 230.

[0131] The first substrate 100a can be made of glass or plastic. Specifically, the first substrate 100a can be made of a transparent plastic with flexible properties, such as polyimide. When polyimide is used as the first substrate 100a, considering that a high-temperature deposition process is performed on the first substrate 100a, a heat-resistant polyimide that can withstand high temperatures can be used.

[0132] A light-blocking layer 105 can be provided on the first substrate 100a. The light-blocking layer 105 can overlap with the active layer 120. By forming it in this way, light incident from the lower surface of the first substrate 100a can be prevented from flowing into the active layer 120, thereby preventing the degradation of the semiconductor characteristics of the active layer 120 (specifically, the channel portion 121).

[0133] According to embodiments of this disclosure, shielding line ESL can be provided on the first substrate 100a.

[0134] The shielding line ESL can be disposed on the same layer as the light blocking layer 105 using the same material, but is not limited thereto, and depending on the level of skill in the art, the shielding line ESL can be formed on the same layer using the same material as any one of the gate electrode 140, source electrode 161 and drain electrode 163.

[0135] Therefore, as another example, the shielding line ESL can be formed in the same layer on the gate insulating layer 130 using the same material as the gate electrode 140 and the low power supply voltage contact VSC. However, the invention is not limited thereto.

[0136] A buffer layer 110 may be disposed on the first substrate 100a. The buffer layer 110 can protect the active layer 120 by blocking air and moisture. The buffer layer 110 may be formed of an inorganic insulating material such as silicon oxide, silicon nitride or metal oxide, but is not limited thereto, and may also be formed of an organic insulating material.

[0137] An active layer 120 may be disposed on the buffer layer 110. The active layer 120 may comprise any of semiconductor materials, such as amorphous silicon (a-Si), polycrystalline silicon (Poly Si), and oxide semiconductor materials.

[0138] The active layer 120 includes a channel portion 121, a first connecting portion 123a disposed on one side of the channel portion 121 (e.g., on the right side of the channel portion 121), and a second connecting portion 123b disposed on the other side of the channel portion 121 (e.g., on the left side of the channel portion 121).

[0139] The channel portion 121 overlaps with the gate electrode 140. By forming it in this way, the channel portion 121 can be protected by the gate electrode 140 to maintain its semiconductor properties and will not become a conductor during the conductive process of manufacturing the active layer 120.

[0140] The first connection portion 123a and the second connection portion 123b can acquire conductive properties by performing plasma treatment or ion-doping conductive treatment on the semiconductor material using the gate electrode 140 as a mask. The first connection portion 123a and the second connection portion 123b formed by the conductive treatment have excellent conductive properties and can be used as electrodes or wiring.

[0141] A gate insulating layer 130 may be disposed on the active layer 120. The gate insulating layer 130 may be disposed on the entire surface of the first substrate 100a, but is not limited thereto, and a portion of the gate insulating layer 130 may be patterned such that one end of the gate insulating layer 130 and the other end correspond to one end of the gate electrode 140, respectively.

[0142] The gate insulating layer 130 may include, but is not limited to, a silicon nitride layer (SiNx) or a silicon oxide layer (SiOx). The gate insulating layer 130 may be formed of a single layer or multiple layers comprising inorganic insulating materials and / or organic insulating materials.

[0143] A gate electrode 140 can be disposed on the gate insulating layer 130.

[0144] The gate electrode 140 may include at least one of aluminum-based metals such as aluminum (Al) or aluminum alloys, silver-based metals such as silver (Ag) or silver alloys, copper-based metals such as copper (Cu) or copper alloys, molybdenum-based metals such as molybdenum (Mo) or molybdenum alloys, chromium (Cr), tantalum (Ta), neodymium (Nd), and titanium (Ti). The gate electrode 140 may have a structure including a single metal layer or a multilayer structure including at least two metal layers, each with different physical properties.

[0145] A low power supply voltage contact (VSC) can be formed on the gate insulating layer 130. For example, the low power supply voltage contact (VSC) can be formed on the same layer using the same material as the gate electrode 140, but it is not limited to this and can be provided at various locations depending on the level of expertise in the art. For example, as another example, the low power supply voltage contact (VSC) can be formed on the same layer using the same material as the light blocking layer 105, the source electrode 161, or the drain electrode 163.

[0146] An interlayer insulating layer 150 may be disposed on the gate electrode 140. The interlayer insulating layer 150 insulates the gate electrode 140 from the source electrode 161 and also insulates the gate electrode 140 from the drain electrode 163. The interlayer insulating layer 150 may be formed of a single layer or multiple layers comprising inorganic insulating materials and / or organic insulating materials.

[0147] Contact holes can be provided in the interlayer insulating layer 150. Therefore, a portion of the upper surface of the first connection portion 123a of the active layer 120 can be exposed through either contact hole, and in addition, a portion of the upper surface of the second connection portion 123b of the active layer 120 can be exposed through the other contact hole.

[0148] According to embodiments of this disclosure, a contact CNT can be provided in the interlayer insulation layer 150 to electrically connect the low power supply voltage contact VSC and the second electrode 230. Since the contact CNT is provided in the interlayer insulation layer 150, a portion of the upper surface of the low power supply voltage contact VSC can be exposed, thereby electrically connecting the low power supply voltage contact VSC and the second electrode 230.

[0149] A source electrode 161 and a drain electrode 163 can be disposed on the interlayer insulating layer 150.

[0150] The source electrode 161 can be electrically connected to the first connection portion 123a of the active layer 120 through a contact hole, and the drain electrode 163 can be electrically connected to the second connection portion 123b of the active layer 120 through a contact hole.

[0151] The source electrode 161 and the drain electrode 163 may be formed of the same material as the gate electrode 140, but are not limited thereto, and may be formed of materials according to knowledge in the art.

[0152] A planarization layer 170 can be provided on the interlayer insulating layer 150, the source electrode 161, and the drain electrode 163. The planarization layer 170 can be provided on the source electrode 161 and the drain electrode 163 to planarize the upper surface of the planarization layer 170.

[0153] Contact holes can be provided in the planarization layer 170, and a portion of the upper surface of the source electrode 161 can be exposed through the contact holes. However, in some cases, a portion of the upper surface of the drain electrode 163 can be exposed through the contact holes.

[0154] The planarization layer 170 can be formed of an organic insulating material. For example, the planarization layer 170 can be formed of an organic insulating material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0155] A first electrode 200 can be disposed on the planarization layer 170, and the first electrode 200 can be electrically connected to the source electrode 161 through a contact hole disposed in the planarization layer 170. The first electrode 200 can be used as an anode.

[0156] The first electrode 200 can be patterned on the planarization layer 170, and patterned to correspond to multiple sub-pixels (e.g. Figure 3 The pixel P may include sub-pixels SP1 to SP4. Therefore, for example, the first electrode 200 may be patterned to correspond to the first sub-pixel SP1 and the second sub-pixel SP2.

[0157] A dam 210 can be provided on the first electrode 200. In this case, the part of the upper surface of the first electrode 200 that is not covered by the dam 210 and is exposed becomes the light-emitting area.

[0158] Dike 210 can be formed from an organic film such as acrylic resin, epoxy resin, phenolic resin, polyamide resin or polyimide resin.

[0159] A light-emitting layer 220 may be disposed on the first electrode 200. The light-emitting layer 220 may include red, green, and blue light-emitting layers patterned for each sub-pixel, or it may be formed by a white light-emitting layer connected to all pixels. When the light-emitting layer 220 is formed by a white light-emitting layer, the light-emitting layer 220 may include, for example, a first stack including a blue light-emitting layer, a second stack including a yellow-green light-emitting layer, and a charge generation layer disposed between the first stack and the second stack, but is not limited thereto.

[0160] A second electrode 230 can be disposed on the light-emitting layer 220. The second electrode 230 can be used as a cathode.

[0161] On the other hand, although not specifically shown, an encapsulation layer may be provided on the second electrode 230 to prevent moisture or air from entering the light-emitting layer 220 from the outside of the display device.

[0162] Figure 7A and Figure 7B This is a plan view of the display device according to an embodiment of the present disclosure before the cutting process, and Figure 7C and Figure 7D This is a plan view of the display device according to an embodiment of the present disclosure after the cutting process. In the following description, the device will be primarily described in relation to... Figure 5A and Figure 5B Different configurations can be implemented.

[0163] First, such as Figure 7A and Figure 7B As shown, in order to manufacture a display device according to an embodiment of the present disclosure, multiple link lines LL, low power supply voltage contacts VSC, shielding lines ESL, first high power supply voltage short-circuit bars VDDSa, second high power supply voltage short-circuit bars VDDSb, multiple first signal lines SL1, multiple second signal lines SL2, and multiple pixels P can be formed on a first substrate 100a. In this case, according to Figure 7A and Figure 7B In some embodiments, a guide ring GR may be additionally provided around the outer surface of the first substrate 100a. For example, the guide ring GR may be provided on the first substrate 100a along the outer periphery of the first substrate 100a.

[0164] The guide ring GR can connect all the multiple link lines LL, low power supply voltage contact VSC, shield line ESL, first high power supply voltage shorting bar VDDSa, second high power supply voltage shorting bar VDDSb, multiple first signal lines SL1 and multiple second signal lines SL2 to the same potential, thereby reducing the problem of static electricity flowing into the thin film transistors in each pixel.

[0165] The first data voltage check line DILa to the fourth data voltage check line DILd extend to the guide ring GR and are electrically connected to the guide ring GR, so that multiple link lines LL, data lines DL1, DL2, DL3, DL4 constituting multiple first signal lines SL1, and shield line ESL can be electrically connected to the guide ring GR.

[0166] In addition, since the reference voltage checking section REFVP extends to and is electrically connected to the guide ring GR, the reference line REFL that constitutes multiple first signal lines SL1 can be electrically connected to the guide ring GR.

[0167] In addition, the high power supply voltage check line VDDIL extends to the guide ring GR and is electrically connected to the guide ring GR, so that the first high power supply voltage short-circuit bar VDDSa and the second high power supply voltage short-circuit bar VDDSb, as well as the high power supply voltage line VDDL constituting the multiple first signal lines SL1, can be electrically connected to the guide ring GR.

[0168] In addition, multiple second signal lines SL2 can be directly connected to the guide ring GR, connected to the guide ring GR through contact holes, or electrically connected to the guide ring GR through separate transistors.

[0169] Alternatively, the low power supply voltage check section VSSP can extend to the guide ring GR to electrically connect the low power supply voltage contact section VSC to the guide ring GR. However, the low power supply voltage check section VSSP may not extend to the guide ring GR, so that the low power supply voltage contact section VSC may not be electrically connected to the guide ring GR.

[0170] According to embodiments of this disclosure, the low power supply voltage contact VSC and the guide ring GR can be connected via a separate bridge wire BR.

[0171] The bridging cable BR can connect the low power supply voltage contact VSC and the guide ring GR through various paths.

[0172] For example, such as Figure 7A As shown, the bridging wire BR can be connected to the left side of the guide ring GR by extending upward from the low power supply voltage contact VSC and then to the left, while crossing the multiple link lines LL, the shield line ESL, and the low power supply voltage line VSL. In this case, the bridging wire BR can be placed on a different layer than the multiple link lines LL, the shield line ESL, and the low power supply voltage line VSL.

[0173] In some cases, the bridging wire BR can be connected to the lower left of the guide ring GR by crossing multiple link wires LL, shield wire ESL and low power supply voltage line VSL, extending downwards and then returning to extend to the left.

[0174] The bridging wire BR can be formed in the same layer as the low power supply voltage contact VSC, but is not limited thereto, and can be formed in a different layer than the low power supply voltage contact VSC by a different material, and connected to the low power supply voltage contact VSC through a contact hole.

[0175] As another example, such as Figure 7B As shown, the bridging line BR can extend upward from the low power supply voltage contact VSC and can cross with the data voltage check lines DILa to DILd, the reference voltage check line REFVP, and the high power supply voltage check line VDDIL to connect to the upper part of the guide ring GR. In this case, the bridging line BR can be formed on the same layer with any of the multiple link lines LL, the shield line ESL, and the low power supply voltage line VSL, but is not limited thereto.

[0176] The bridging wire BR can be made of a different material than the material of the low power supply voltage contact VSC in a different layer than the low power supply voltage contact VSC, and can be connected to the low power supply voltage contact VSC through contact holes, but is not limited thereto.

[0177] In some cases, the bridging line BR includes a first part and a second part. The first part may be the lower part of the bridging line BR that does not intersect with the data voltage check lines DILa to DILd, the reference voltage check section REFVP, or the high power supply voltage check line VDDIL. The second part may be the upper part of the bridging line BR that intersects with the data voltage check lines DILa to DILd, the reference voltage check section REFVP, or the high power supply voltage check line VDDIL. Furthermore, the first and second parts may be formed on different layers.

[0178] Additionally, although not shown, when the low power supply voltage check section VSSP extends to the upper guide ring GR and the low power supply voltage contact section VSC is electrically connected to the guide ring GR, the bridging wire BR can be connected to the low power supply voltage check section VSSP and then electrically connected to the guide ring GR via the low power supply voltage check section VSSP.

[0179] Next, as Figure 7C As shown, cutting along the cutting line CL has been completed. Figure 7A The display device in the inspection step retains only the display area DA, the first non-display area NDAa, and the second non-display area NDAb.

[0180] In addition, such as Figure 7D As shown, cutting along the cutting line CL has been completed. Figure 7BThe display device in the inspection step retains only the display area DA, the first non-display area NDAa, and the second non-display area NDAb.

[0181] like Figure 7C and Figure 7D As shown, after removing a portion of the substrate 100a and the inspection area IA along the cutting line CL, a portion of the first substrate 100a can be disconnected or cut to remove the remaining portion of the guide ring GR. Subsequently, multiple pad electrodes PE can be formed on one side of the multiple link lines LL to connect to the flexible film (see...). Figure 1 (320).

[0182] By removing the guide ring GR in this manner and forming multiple pad electrodes PE, a display device according to an embodiment of the present invention can be realized.

[0183] In this configuration, the bridging wire BR extends from the low power supply voltage contact VSC in one direction, for example, upward. One end of the bridging wire BR can be connected to the low power supply voltage contact VSC, while the other end of the bridging wire BR can coincide with the end of the substrate 100a.

[0184] Additionally, since external signals must be applied to lines such as the shield line ESL, the link line LL, and the low power supply voltage line VSL, these lines are connected to pad electrodes PE1, PE2, PE3, PE4, and PE5. Specifically, the fourth pad electrode PE4 is connected to the low power supply voltage line VSL to supply the externally applied low power supply voltage to the low power supply voltage contact VSC. Therefore, the externally applied low power supply voltage can be transmitted through the fourth pad electrode PE4 to the low power supply voltage line VSL, and then supplied to the low power supply voltage contact VSC through the third contact hole CH3.

[0185] In contrast, no external signal needs to be applied to the bridging wire BR. Therefore, the bridging wire BR is connected directly or through contact holes to the low power supply voltage contact VSC, but the individual pad electrodes are not connected to the bridging wire BR.

[0186] In this way, the low power supply voltage line VSL and the bridging line BR can be arranged parallel to each other in the same direction (e.g., in the upward direction) within the low power supply voltage contact VSC. Furthermore, one end of each of the low power supply voltage line VSL and the bridging line BR is connected to the low power supply voltage contact VSC, while the other end of each of the low power supply voltage line VSL and the bridging line BR coincides with one end of the substrate 100a (e.g., the upper end of the substrate 100a).

[0187] In this configuration, the fourth pad electrode PE4 is connected to the other end of the low power supply voltage line VSL, while the pad electrode is not connected to the other end of the bridging line BR.

[0188] For example, the low power supply voltage line (VSL) and the bridging line (BR) can be formed on different layers, such as... Figure 7C As shown, or they can be formed from the same material in the same layer, such as Figure 7D As shown. That is to say, as Figure 7C As shown, the low power supply voltage line VSL is connected to the low power supply voltage contact VSC through the third contact hole CH3, and the bridging wire BR can be integrally formed with the low power supply voltage contact VSC, and as... Figure 7D As shown, the low power supply voltage line VSL can be connected to the low power supply voltage contact VSC through the third contact hole CH3, and the bridging wire BR can also be connected to the low power supply voltage contact VSC through the contact hole.

[0189] Figure 7E and Figure 7F This is a plan view of a display device according to another embodiment of the present disclosure.

[0190] Figure 7E It shows from Figure 7C Excluding the shielded line ESL and the fifth pad electrode PE5, and Figure 7F It shows from Figure 7D The shielded line ESL and the fifth pad electrode PE5 are excluded.

[0191] like Figure 7E and Figure 7F As shown, according to another embodiment of this disclosure, static electricity in the low power supply voltage contact VSC can be eliminated by connecting the bridging wire BR to the guide ring GR without configuring the shielding wire ESL.

[0192] Figure 8 This is a plan view of a display device according to another embodiment of the present disclosure. In addition to the arrangement of the electrostatic discharge pattern, Figure 8 Implementation methods and Figure 4 The implementation methods are the same, and therefore the different configurations will be mainly described below.

[0193] like Figure 8As shown, a display device according to another embodiment of the present disclosure includes a first substrate 100a, a plurality of pad electrodes PE, a plurality of link lines LL, a low power supply voltage contact VSC, a shield line ESL, a first high power supply voltage short circuit bar VDDSa, a second high power supply voltage short circuit bar VDDSb, a plurality of first signal lines SL1, a plurality of second signal lines SL2, an electrostatic discharge pattern ESDP, and an electrostatic discharge signal line ESDL.

[0194] According to another embodiment of this disclosure, the second non-display area NAb may further include an electrostatic discharge pattern ESDP and an electrostatic discharge signal line ESDL.

[0195] The electrostatic discharge pattern ESDP can be connected to one end of multiple first signal lines SL1, such as the lower end. For example, the electrostatic discharge pattern ESDP can be electrically connected to any end of the first data line DL1, the second data line DL2, the third data line DL3, the fourth data line DL4, and the reference line REFL.

[0196] The electrostatic discharge pattern ESDP can be electrically connected to the electrostatic discharge signal line ESDL. The ESDP can be positioned between the electrostatic discharge signal line ESDL and a portion of multiple first signal lines SL1, thereby preventing the generation of static electricity in multiple pixels P. Simultaneously, Figure 8 Only the electrostatic discharge pattern ESDP disposed in the second non-display area NDAb is shown, but the present disclosure is not limited thereto, and the electrostatic discharge pattern ESDP can be disposed in the display area DA, and can be disposed in various arrangements in accordance with common knowledge in the art.

[0197] The electrostatic discharge signal line ESDL can extend in a first direction X (e.g., horizontal direction) and can receive a predetermined voltage.

[0198] Figure 9 This is a plan view of a display device according to another embodiment of the present disclosure. In addition to the arrangement of the shielding wires, Figure 9 Implementation methods and Figure 4 The implementation methods are the same, and therefore the different configurations will be mainly described below.

[0199] like Figure 9 As shown, a display device according to another embodiment of the present disclosure includes a first substrate 100a, a plurality of pad electrodes PE, a plurality of link lines LL, a low power supply voltage contact VSC, a shield line ESL, a first high power supply voltage short circuit bar VDDSa, a second high power supply voltage short circuit bar VDDSb, a plurality of first signal lines SL1, a plurality of second signal lines SL2, and a plurality of pixels P.

[0200] According to another embodiment of this disclosure, with Figure 4 The implementation methods differ, flexible membranes (see...) Figure 1 (320) can be electrically connected to the fourth pad electrode PE4 used to apply signals to the shielded line ESL.

[0201] According to another embodiment of this disclosure, the shielding line ESL includes a protrusion ESLp that protrudes (e.g., downwards) on one side and extends.

[0202] The protrusion ESLp can be electrically connected to the first high power supply voltage shorting bar VDDSa through the fourth contact hole CH4. Therefore, the shielded wire ESL can be supplied with a high power supply voltage through the first high power supply voltage shorting bar VDDSa. By forming it in this way, the shielded wire ESL can be positioned between the low power supply voltage contact VSC and the first-1 link wire LL1a in a non-floating state.

[0203] Figure 10 This is a cross-sectional view of a display device according to another embodiment of the present disclosure. In this case, Figure 10 Involving Figure 9 The cross section II-II′. Meanwhile... Figure 10 Involving Figure 9 The implementation methods are described, and the same reference numerals are assigned to the same configurations, and repeated descriptions are omitted.

[0204] like Figure 10 As shown, a display device according to another embodiment of the present disclosure includes a first substrate 100a, a shielding line ESL, a protrusion ESLp, a buffer layer 110, a gate insulating layer 130, a low power supply voltage contact VSC, a first high power supply voltage short-circuit bar VDDSa, an interlayer insulating layer 150, and a second electrode 230.

[0205] The shielded wire ESL can be electrically connected to the first high power supply voltage short-circuit bar VDDSa via a protrusion ESLp that protrudes and extends in the second direction Y. In this case, the first high power supply voltage short-circuit bar VDDSa and the shielded wire ESL can be electrically connected to each other via the fourth contact hole CH4.

[0206] According to another embodiment of this disclosure, the shielded wire ESL can be electrically connected to the first high power supply voltage short-circuit bar VDDSa via the protrusion ESLp to receive a predetermined voltage without floating. Therefore, it is possible to prevent contact between the low power supply voltage contact VSC and the first-1 link wire (see [link to documentation]). Figure 4 Interference caused by static electricity between LL1a and LL1a.

[0207] Figure 11This is a plan view of a display device according to another embodiment of the present disclosure. On the other hand, due to the arrangement of the shielding line and the additional horizontal line, Figure 11 Implementation methods and Figure 4 The implementation methods are the same, so the different configurations will be mainly described below.

[0208] like Figure 11 As shown, a display device according to another embodiment of the present disclosure includes a first substrate 100a, a plurality of pad electrodes PE, a plurality of link lines LL, a low power supply voltage contact VSC, a shield line ESL, a first high power supply voltage short circuit bar VDDSa, a second high power supply voltage short circuit bar VDDSb, an additional horizontal line ASL, a plurality of first signal lines SL1, a plurality of second signal lines SL2, and a plurality of pixels P.

[0209] An additional horizontal line ASL can be set in the first non-display area NDAa. For example, the additional horizontal line ASL can be set in the first non-display area NDAa to be relative to the adjacent display area DA, with a short circuit bar VDDSa of the first high power supply voltage.

[0210] Although not shown in detail, the additional horizontal line ASL can receive any of the low power supply voltage applied to the low power supply voltage contact VSC, the ground voltage, and the signal flowing through another line provided in the first non-display area NDAa.

[0211] and Figure 4 The implementation methods are different, in Figure 11 In the implementation of the method, the flexible membrane (see Figure 1 (320) can be electrically connected to the fourth pad electrode PE4 used to apply signals to the shielded line ESL.

[0212] According to another embodiment of this disclosure, the shielding line ESL includes a protrusion ESLp that protrudes (e.g., downwards) on one side and extends.

[0213] The protrusion ESLp can be electrically connected to the additional horizontal line ASL through the fifth contact hole CH5. Therefore, the shielded line ESL can receive any of the following signals: low power supply voltage, ground voltage, and signals flowing to another line located in the first non-display area NDAa. By forming it in this way, the shielded line ESL can be positioned between the low power supply voltage contact VSC and the first-1 link line LL1a in a non-floating state.

[0214] Figure 12 This is a cross-sectional view of a display device according to another embodiment of the present disclosure. In this case, Figure 12 Involving Figure 11 Section III-III′. Meanwhile, Figure 12 Involving Figure 11 The implementation methods are described, and the same reference numerals are assigned to the same configurations, and repeated descriptions are omitted.

[0215] like Figure 12 As shown, a display device according to another embodiment of the present disclosure includes a first substrate 100a, a shield line ESL, a protrusion ESLp, a buffer layer 110, a gate insulating layer 130, a low power supply voltage contact VSC, a first high power supply voltage short circuit bar VDDSa, an additional horizontal line ASL, an interlayer insulating layer 150, and a second electrode 230.

[0216] The shielding wire ESL can be electrically connected to the additional horizontal wire ASL via a protrusion ESLp that protrudes and extends in the second direction Y. In this case, the additional horizontal wire ASL and the shielding wire ESL can be electrically connected via the fifth contact hole CH5.

[0217] According to another embodiment of this disclosure, the shielded wire ESL can be electrically connected to the additional horizontal wire ASL via the protrusion ESLp to receive a predetermined voltage without floating. Therefore, it is possible to prevent contact between the contact VSC and the first-1 link wire (see [link to documentation]) due to low power supply voltage. Figure 4 Interference caused by static electricity between LL1a and LL1a.

[0218] Figure 13 This is a plan view of a display device according to another embodiment of the present disclosure. In addition to the arrangement of the shielding wires, Figure 13 Implementation methods and Figure 4 The implementation methods are the same, and therefore the different configurations will be mainly described below.

[0219] like Figure 13 As shown, a display device according to another embodiment of the present disclosure includes a first substrate 100a, a plurality of pad electrodes PE, a plurality of link lines LL, a low power supply voltage contact VSC, a first shield line ESLa, a second shield line ESLb, a first high power supply voltage short circuit bar VDDSa, a second high power supply voltage short circuit bar VDDSb, a plurality of first signal lines SL1, a plurality of second signal lines SL2, and a plurality of pixels P.

[0220] The first shielding line ESLa and the second shielding line ESLb can be placed between multiple link lines LL and the low power supply voltage contact VSC.

[0221] According to another embodiment of this disclosure, by forming a shield line ESL (including a first shield line ESL1 and a second shield line ESLb) between the multiple link lines LL and the low power supply voltage contact VSC, the influence of the voltage applied to the low power supply voltage contact VSC during the inspection process on the multiple link lines LL can be minimized. For example, the inspection process may be a process of checking whether a signal such as a data voltage is properly applied to the multiple first signal lines SL1, or a process of checking whether the low power supply voltage is properly applied to the low power supply voltage contact VSC, but is not limited thereto.

[0222] Specifically, when a voltage is applied to the low power supply voltage contact VSC, the threshold voltage Vth of the driving thin-film transistor TRd of the pixel closest to the low power supply voltage contact VSC, the first data line DL1, and the first link line LL1 may change. However, according to another embodiment of this disclosure, the effect of the voltage applied to the low power supply voltage contact VSC during the inspection process on the multiple link lines LL can be minimized or eliminated by the first shield line ESLa and the second shield line ESLb.

[0223] at the same time, Figure 13 Only two shielded wires between the multiple link lines LL and the low power supply voltage contact VSC are shown, but this is not the only example. The number of shielded wires can be adjusted in various ways depending on the performance of the display device to be implemented.

[0224] Therefore, according to another embodiment of this disclosure, by providing a first shielding line ESLa and a second shielding line ESLb, the fluctuation of the threshold voltage Vth of the plurality of driving thin-film transistors disposed in the plurality of pixels in the display device according to another embodiment of this disclosure can be minimized. Therefore, the appearance of blemishes or lines can be minimized or prevented when displaying or reproducing an image.

[0225] According to embodiments of this disclosure, the first shielding wire ESLa and the second shielding wire ESLb can surround the outer side of the low power supply voltage contact VSC within the link region LA. Simultaneously, the interior of the low power supply voltage contact VSC can be defined as the interior of the contact CNT formed based on the boundary of the low power supply voltage contact VSC, and the exterior of the low power supply voltage contact VSC can be defined as the exterior of the boundary of the low power supply voltage contact VSC where the contact CNT is not formed.

[0226] Compared to the first shielding wire ESLa, the second shielding wire ESLb can be spaced apart from the low power supply voltage contact VSC in the outward direction. Therefore, the first shielding wire ESLa can surround the low power supply voltage contact VSC, and the second shielding wire ESLb can surround either the low power supply voltage contact VSC or the first shielding wire ESLa.

[0227] According to another embodiment of this disclosure, different voltages can be applied to the first shield line ESLa and the second shield line ESLb. For example, a first-1 voltage can be applied to the first shield line ESLa through the 5-1 pad electrode PE5a, and a first-2 voltage can be applied to the second shield line ESLb through the 5-2 pad electrode PE5b. In this case, different voltages can be applied to the first-1 voltage and the first-2 voltage.

[0228] However, this disclosure is not limited thereto. As another example, the 5-1 pad electrode PE5a connected to the first shielding line ESLa can be kept in a floating state without being electrically connected to the flexible film (see [link]). Figure 1 (320), and the first and second voltages can be applied only to the second shield line ESLb, so that it is not floated.

[0229] Figure 14 This is a plan view of a display device according to another embodiment of the present disclosure. In addition to the configuration of the second shielding line, Figure 14 Implementation methods and Figure 13 The implementation methods are the same, and therefore the different configurations will be mainly described below.

[0230] like Figure 14 As shown, a display device according to another embodiment of the present disclosure includes a first substrate 100a, a plurality of pad electrodes PE, a plurality of link lines LL, a low power supply voltage contact VSC, a first shield line ESLa, a second shield line ESLb, a first high power supply voltage short circuit bar VDDSa, a second high power supply voltage short circuit bar VDDSb, a plurality of first signal lines SL1, a plurality of second signal lines SL2, and a plurality of pixels P.

[0231] and Figure 13 The implementation methods differ, flexible membranes (see...) Figure 1 (320) can be electrically connected to the 5-2 pad electrode PE5b used to apply signals to the second shield line ESLb.

[0232] According to another embodiment of this disclosure, the second shielding line ESLb includes a protrusion ESLp that protrudes (e.g., downwardly) on one side and extends.

[0233] The protrusion ESLp can be electrically connected to the first high power supply voltage shorting bar VDDSa through the fourth contact hole CH4. Therefore, the second shielding wire ESLb can be supplied with a high power supply voltage through the first high power supply voltage shorting bar VDDSa. By forming it in this way, the second shielding wire ESLb can be provided between the low power supply voltage contact VSC and the first 1-1 link wire LL1a in a non-floating state.

[0234] Figure 15 This is a plan view of a display device according to another embodiment of the present disclosure. Furthermore, due to the arrangement of the second shielding line and the additional horizontal line, Figure 15 Implementation methods and Figure 13 The implementation methods are the same, so the different configurations will be mainly described below.

[0235] like Figure 15 As shown, a display device according to another embodiment of the present disclosure includes a first substrate 100a, a plurality of pad electrodes PE, a plurality of link lines LL, a low power supply voltage contact VSC, a shield line ESL, a first high power supply voltage short circuit bar VDDSa, a second high power supply voltage short circuit bar VDDSb, an additional horizontal line ASL, a plurality of first signal lines SL1, a plurality of second signal lines SL2, and a plurality of pixels P.

[0236] An additional horizontal line ASL can be set in the first non-display area NDAa. For example, the additional horizontal line ASL can be set in the first non-display area NDAa to be relative to the adjacent display area DA, with a short circuit bar VDDSa of the first high power supply voltage.

[0237] Although not shown in detail, the additional horizontal line ASL can receive any of the low power supply voltage applied to the low power supply voltage contact VSC, the ground voltage, and the signal flowing through another line provided in the first non-display area NDAa.

[0238] and Figure 13 The implementation methods are different, in Figure 15 In the implementation of the method, the flexible membrane (see Figure 1 (320) can be electrically connected to the 5-2 pad electrode PE5b used to apply signals to the second shield line ESLb.

[0239] According to another embodiment of this disclosure, the second shielding line ESLb includes a protrusion ESLp that protrudes (e.g., downwardly) on one side and extends.

[0240] The protrusion ESLp can be electrically connected to the additional horizontal line ASL through the fifth contact hole CH5. Therefore, the second shield line ESLb can receive any one of the low power supply voltage, ground voltage, and signals flowing through another line located in the first non-display area NDAa. Formed as described above, the second shield line ESLb can be positioned between the low power supply voltage contact VSC and the first link line LL1a in a non-floating state.

[0241] It will be apparent to those skilled in the art that the present disclosure is not limited to the above-described embodiments and drawings, and that various substitutions, modifications, and variations can be made to the present disclosure without departing from its spirit or scope. Therefore, the scope of the present disclosure is defined by the appended claims, and all variations or modifications derived from the meaning, scope, and equivalent concepts of the claims are intended to fall within the scope of the present disclosure.

Claims

1. A display device, comprising: A substrate, the substrate including a display area and a non-display area; Multiple first signal lines in the display area; Multiple second signal lines are disposed in the display area and extend in a direction perpendicular to the multiple first signal lines; Multiple pad electrodes in the non-display area; Multiple link lines are disposed in the non-display area and electrically connected to the plurality of pad electrodes and the plurality of first signal lines; Low power supply voltage contact in the non-display area; as well as The shielding wire between the multiple connecting lines and the low power supply voltage contact.

2. The display device according to claim 1, wherein, The shielding wire surrounds the outside of the low power supply voltage contact portion.

3. The display device according to claim 1 further includes a high power supply voltage short-circuit bar that overlaps with the plurality of link lines and is electrically connected to the high power supply voltage line, and in, The protrusion extending from the shielding wire is electrically connected to the high power supply voltage shorting bar.

4. The display device according to claim 1, further comprising a horizontal signal line that overlaps with the plurality of link lines and extends in a direction parallel to the plurality of second signal lines, and in, The protrusion extending from the shielding wire is electrically connected to the horizontal signal line.

5. The display device according to claim 4, wherein, The horizontal signal line receives signals from ground voltage or low power supply voltage.

6. The display device according to claim 1, wherein, The shielding wire includes a first shielding wire disposed adjacent to the low power supply voltage contact portion, and a second shielding wire disposed adjacent to the plurality of connecting wires, and The first shielding wire surrounds the outside of the low power supply voltage contact portion, and the second shielding wire surrounds the outside of the first shielding wire.

7. The display device according to claim 6, wherein, The first shielding line and the second shielding line are electrically connected to different pad electrodes among the plurality of pad electrodes.

8. The display device according to claim 6, wherein, The first shielding line is floating, and the second shielding line receives signals from the pad electrodes.

9. The display device according to claim 6, further comprising a high power supply voltage short-circuit bar that overlaps with the plurality of link lines and is electrically connected to the high power supply voltage line, and in, The protrusion extending from the second shielding wire is electrically connected to the high power supply voltage short-circuit bar.

10. The display device of claim 6, further comprising a horizontal signal line that overlaps with the plurality of link lines and extends in a direction parallel to the plurality of second signal lines, and in, The protrusion extending from the second shielding wire is electrically connected to the horizontal signal line.

11. The display device according to claim 10, wherein, The horizontal signal line receives signals from ground voltage or low power supply voltage.

12. The display device according to claim 1, further comprising an electrostatic discharge pattern disposed at a first end of the plurality of first signal lines, and in, The first end of the plurality of first signal lines is disposed in the area facing the plurality of link lines.

13. The display device according to claim 1, further comprising a bridging wire extending from the low power supply voltage contact in a first direction.

14. The display device according to claim 13, wherein, The first end of the bridging wire is connected to the low power supply voltage contact, and the second end of the bridging wire coincides with the end of the substrate.

15. The display device according to claim 13, wherein, The bridging wire is located on a different layer than the multiple link wires.

16. A display device, comprising: A substrate, the substrate including a display area and a non-display area; Low power supply voltage contact portion provided in the non-display area; The low power supply voltage line is disposed in the non-display area and connected to the low power supply voltage contact; as well as The bridging wire is located in the non-display area and connected to the low power supply voltage contact. The pad electrodes are connected to the low power supply voltage line but not to the bridging wire.

17. The display device according to claim 16, wherein, The first end of each of the low power supply voltage line and the bridging wire is connected to the low power supply voltage contact, and the second end of each of the low power supply voltage line and the bridging wire coincides with the end of the substrate.

18. The display device according to claim 16, wherein, Each of the low power supply voltage line and the bridging wire is connected to the low power supply voltage contact via a contact hole.

19. The display device according to claim 18, wherein, The low power supply voltage line and the bridging wire are formed of the same material in the same layer.

20. The display device according to claim 16, wherein, The low power supply voltage line is connected to the low power supply voltage contact through a contact hole, and the bridging wire is integrally formed with the low power supply voltage contact.

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