Flash memory checking method and device, microcontroller chip and storage medium

Abstract

This application proposes a flash memory verification method and device, a microcontroller chip, and a storage medium. The method includes: responding to detecting a first write command issued to a flash memory controller, parsing the first write command to obtain first data to be written and a first address where the first data needs to be written to the flash memory; responding to detecting a first write completion signal from the flash memory controller, sending a read operation request to the flash memory controller, the read operation request including the first address; receiving first current data written to the first address from the flash memory controller; controlling the flash memory controller to instruct the central processing unit (CPU) to send a second write command, simultaneously verifying the first current data with the first data, and feeding back the verification result to the flash memory controller to instruct the CPU to execute the corresponding operation. Based on this, this application does not require the CPU to participate in the acquisition and verification of flash memory data, saving valuable CPU resources, and the verification and the next write operation are executed synchronously, improving overall system efficiency.

Description

Technical Field

[0001] This application relates to the field of storage technology, specifically to the field of storage data verification technology, and particularly to a flash memory verification method and device, a microcontroller chip, and a storage medium. Background Technology

[0002] With the rapid development of embedded systems, microcontroller units (MCUs) have been widely used in industrial control, consumer electronics, automotive electronics, and other fields. Flash memory (also known as FLASH storage) is the primary medium for storing program code and critical data in microcontroller chips, and the reliability of the stored data directly affects the stable operation of the entire system. During the program download process of the microcontroller chip, the data written to the flash memory is verified—a process commonly referred to as flash memory verification—to ensure the correctness of the data written to the flash memory, which is a fundamental guarantee of system reliability.

[0003] Currently, there are two main methods for flash memory verification: 1. The Central Processing Unit (CPU) reads the data from the flash memory byte by byte and compares it with the original data; 2. The CPU reads the data from the flash memory, calculates the corresponding CRC (Cyclic Redundancy Check) value, and then compares it with the expected CRC value corresponding to the original data. However, both methods require the CPU to participate in the entire data reading and verification process, consuming valuable CPU resources and reducing the overall system efficiency. This negative impact is particularly pronounced when updating programs in batches and frequently. Summary of the Invention

[0004] In view of this, this application provides a flash memory verification method and device, a microcontroller chip, and a storage medium, which can at least improve the problem that flash memory verification requires the full participation of the central processing unit, thus occupying valuable CPU resources and affecting the overall efficiency of the microcontroller chip.

[0005] This application provides a flash memory verification method for a microcontroller chip, wherein the microcontroller chip integrates a central processing unit and flash memory, and the flash memory is equipped with a flash memory controller; the method includes: In response to detecting the first write command sent to the flash memory controller, the first data to be written and the first address where the first data needs to be written to the flash memory are parsed from the first write command; In response to detecting a first write completion signal from the flash memory controller, a read operation request is sent to the flash memory controller, the read operation request including the first address; Receive the first current data written to the first address from the flash memory controller; Determine whether the first current data has been received completely; If so, a read completion signal is fed back to the flash memory controller to control the flash memory controller to release the bus ready signal, thereby instructing the central processing unit to send a second write command; if the first current data has not been received and a preset time has been exceeded, the flash memory controller is controlled to send a preset format signal to the central processing unit to instruct the central processing unit to send a second write command; while instructing the central processing unit to send the second write command, the first current data is verified against the first data, and the verification result is fed back to the flash memory controller to instruct the central processing unit to perform the corresponding operation.

[0006] Optionally, the method further includes: Determine whether an enable signal has been received from the central processing unit; If so, monitor the first write command sent to the flash memory controller; If not, the central processing unit obtains the first current data written to the first address in the flash memory, and the central processing unit verifies the first current data with the first data.

[0007] Optionally, the method for monitoring the first write command sent to the flash controller includes any of the following: The first write command is monitored from the central processing unit; The first write command is monitored from the flash memory controller; The central processing unit is connected to the flash memory controller via a bus, and monitors the first write command from the bus.

[0008] Optionally, the central processing unit (CPU) and the flash memory controller are connected via an AHB (Automatic Bus Buffer). The flash memory controller generates a high-level bus ready signal and feeds it back to the CPU via the AHB to instruct the CPU to send the second write command.

[0009] Optionally, the preset format signal is an all-zero data signal.

[0010] Optionally, the method further includes: The parsed first data and the first address are cached in a micro memory; Determine whether the verification between the first current data and the first data is complete; If completed, the first data and the first address are deleted from the micro memory, and the second data and the second address obtained by parsing the second write command are updated in the micro memory; If not completed, determine whether the remaining storage space of the micro-memory is less than a preset threshold and whether the second write command sent to the flash memory controller is detected; and when the remaining storage space of the micro-memory is less than the preset threshold and the second write command is detected, control the central processing unit to calculate the CRC value of the second data and store it in the micro-memory. In response to detecting a second write completion signal from the flash memory controller, a read operation request is sent to the flash memory controller, the read operation request including the second address; The central processing unit is controlled to acquire the second current data written to the second address in the flash memory, and to calculate the CRC value corresponding to the second current data; In response to obtaining the CRC value corresponding to the second current data, the flash memory controller instructs the central processing unit to send a third write command, while comparing the CRC value of the second data with the CRC value of the second current data, and feeding back the comparison result to the flash memory controller to instruct the central processing unit to perform the corresponding operation.

[0011] This application provides a microcontroller chip that integrates a central processing unit, flash memory, and an automatic verification device. The flash memory is equipped with a flash memory controller, and the automatic verification device is connected to the central processing unit. According to the enable signal issued by the central processing unit, the automatic verification device communicates with the flash memory controller to execute the steps of the flash memory verification method as described above.

[0012] This application provides a flash memory verification device, including a processor and a memory, wherein the memory stores a flash memory verification program, and when the flash memory verification program is executed by the processor, it implements the steps of the flash memory verification method as described in any of the preceding claims.

[0013] This application provides a storage medium storing a computer program, which, when executed by a processor, implements the steps of the flash memory verification method as described in any of the preceding claims.

[0014] As described above, this application automatically acquires the data to be written and its address when a write command is detected, and automatically triggers the reading and verification of the written data after the writing is completed. The acquisition and verification of flash data (i.e., the data to be written) and original data (i.e., the data to be written) do not require the participation of the central processing unit, which can save valuable CPU resources. Furthermore, the verification and the next write operation are executed synchronously, thereby shortening the program update time of the microcontroller chip and improving the overall system efficiency of the microcontroller chip. Attached Figure Description

[0015] Figure 1 This is a schematic flowchart of a flash memory verification method according to an embodiment of this application; Figure 2This is a flowchart illustrating another embodiment of the flash memory verification method of this application; Figure 3 This is a schematic diagram of the structure of a microcontroller chip according to an embodiment of this application; Figure 4 This is a schematic diagram of the structure of a flash memory verification device according to an embodiment of this application. Detailed Implementation

[0016] To address the aforementioned technical problems, this application provides a flash memory verification method and apparatus, a microcontroller chip, and a storage medium. These protected subjects are based on the same concept, and their principles for solving the problems are essentially the same or similar. The implementation methods of each protected subject can be referred to mutually, and repeated details will not be elaborated upon.

[0017] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly described below in conjunction with specific embodiments and corresponding drawings. Obviously, the embodiments described below are only a part of the embodiments of this application, and not all of them. Unless otherwise specified, the following embodiments and their technical features can be combined with each other, and also belong to the technical solutions of this application.

[0018] Figure 1 This is a schematic flowchart of a flash memory verification method according to an embodiment of this application. The flash memory verification method may also be referred to as a "method", and the execution subject of each step may be a suitable flash memory verification device (e.g., a microcontroller chip), or a storage medium, processor, controller, etc. with flash memory verification function.

[0019] Combined Figure 1 and Figure 2 As shown, the method includes at least the following steps S11 to S14.

[0020] S11: In response to detecting the first write command sent to the flash memory controller, the first data to be written and the first address of the flash memory to be written are parsed from the first write command.

[0021] S12: In response to detecting a first write completion signal from the flash memory controller, a read operation request is sent to the flash memory controller, the read operation request including the first address.

[0022] S13: Receive the first current data written to the first address in the flash memory from the flash memory controller.

[0023] S14: Control the flash memory controller to instruct the central processing unit to send a second write command, and at the same time verify the first current data with the first data, and feed back the verification result to the flash memory controller to instruct the central processing unit to perform the corresponding operation.

[0024] The first address is the address of the storage unit in the flash memory that needs to be written in this write operation. The first data is the "original data" that needs to be written to the first address in this write operation. The first current data is the data that is actually written to the first address in this write operation, which can be called "written data". The verification in step S14 refers to comparing the written data with the original data to determine whether the written data is the same as the original data. When the same or similar ratio reaches a preset threshold, the verification is considered to be successful.

[0025] To clearly illustrate the process and principle of the method, the following text will use the following terms. Figure 3 The microcontroller chip with the structure shown is used as an example for illustrative description. Combined with... Figure 3 As shown, the microcontroller chip 30 integrates a central processing unit 31, flash memory 32, and an automatic verification device 33. The flash memory 32 includes a flash memory controller 321 and storage units (also referred to as "flash memory units") 322. Storage units 322 are the actual storage medium of the flash memory 32, used at least to store data related to program updates and downloads performed by the microcontroller chip 30. The flash memory controller 321 controls the read and write operations of the flash memory 32 and generates corresponding write completion signals. The central processing unit 31 has an interface (also referred to as a "CPU interface") and is connected to the flash memory controller 321 through this interface. In scenarios where the central processing unit 31 and the flash memory controller 321 are connected via a bus 34, this interface can be a bus interface, including but not limited to AHB (Advanced High-performance Bus) or AXI (Advanced eXtensible Interface) bus. In one example, the automatic verification device 33 may include a trigger module 331, a verification module 332, and an error logging module 333. The functions of each module are described below. The automatic verification device 33 can be connected to the central processing unit 31 via the bus 34. The central processing unit 31 can send an enable signal to the automatic verification device 33 to enable the flash memory automatic verification function. The automatic verification device 33 communicates with the flash memory controller 321 to execute the above steps S11 to S14.

[0026] In other words, the method described in this application can also determine whether an enable signal is received from the central processing unit 31, i.e. whether the flash memory automatic verification function is enabled; if so, the automatic verification device 33 monitors the first write command issued to the flash memory controller 321 and subsequent steps; if not, the central processing unit 31 obtains the first current data written to the first address in the flash memory 32, and the central processing unit 31 verifies the first current data with the first data, i.e., when the flash memory automatic verification function is not enabled, the central processing unit 31 obtains and verifies the written data.

[0027] Regardless of whether the flash memory automatic verification function is enabled, the first write command can only be generated by the central processing unit 31, that is, the central processing unit 31 initiates the write request. In one example of step S11, the automatic verification device 33 monitors the first write command in any of the following ways: 1. The automatic verification device 33 directly monitors the first write command from the central processing unit 31; 2. The central processing unit 31 sends the generated first write command to the flash memory controller 321, and the automatic verification device 33 monitors the first write command from the flash memory controller 321; 3. In a scenario where the central processing unit 31 and the flash memory controller 321 are connected via a bus 34, the automatic verification device 33 monitors the first write command from the bus 34.

[0028] In step S11, the automatic verification device 33 parses the first data to be written and the first address from the first write command, which can be temporarily stored or cached. Figure 3 The micromemory 334 shown is used in an example where the micromemory 334 can be a storage module of the automatic verification device 33 or a storage module of the microcontroller chip 30 that is independent of the automatic verification device 33.

[0029] When the write operation of flash memory 32 is completed, the flash memory controller 321 generates a write completion signal, referred to here as the first write completion signal. In a practical scenario, the write completion signal can be a Ready signal, which is a high-level signal. When the write operation is not completed, the flash memory controller 321 generates a Busy signal, which is a low-level signal. The automatic verification device 33 monitors flash memory 32 to determine whether the write operation of flash memory 32 is complete by monitoring the write completion signal. When the first write completion signal is detected in step S12, a read operation request for the first address is sent to the flash memory controller 321. In other words, the automatic verification mechanism is triggered by the write completion signal without the intervention of the central processing unit 31.

[0030] In step S13, the flash memory controller 321 generates a Ready signal, and the automatic verification device 33 obtains the first current data actually written to the first address based on the Ready signal. This indicates that the current read operation or access to the flash memory 32 has been completed, and step S14 can be executed. In other words, the write completion signal automatically triggers the capture of the write address and data without the intervention of the central processing unit 31.

[0031] In step S14, the trigger module 331 of the automatic verification device 33 sends a read completion signal to the flash memory controller 321 to control the flash memory controller 321 to release the bus ready signal, i.e., the HREADY signal, to instruct the central processing unit 31 to send a second write command. This second write command is the instruction to trigger the next write operation. Thus, this application can start the next write operation upon receiving the read completion signal. Simultaneously, the verification module 332 of the automatic verification device 33 verifies the first current data against the first data, and after obtaining the verification result, sends it back to the flash memory controller 321 to instruct the central processing unit 31 to perform the corresponding operation.

[0032] The verification process and principle can be adapted to actual needs. For example, the verification module 332 of the automatic verification device 33 compares the first current data with the first data byte by byte. If they are completely identical or the similarity ratio reaches a preset threshold, the verification is considered to have passed; otherwise, the verification is considered to have failed. Another example is that the verification module 332 of the automatic verification device 33 calculates the CRC value corresponding to the first current data and compares it with the expected CRC value corresponding to the first data. The expected CRC value can be pre-calculated and cached in the micro memory 334. If they are completely identical, the verification is considered to have passed; otherwise, the verification is considered to have failed.

[0033] In one example, the central processing unit 31 is instructed to perform the corresponding operation, including: if the verification passes, clearing the corresponding error flag bit of the flash memory controller 321 and preparing for the next data verification; if the verification fails, the error recording module 333 of the automatic verification device 33 records the write error address and corresponding data of the storage unit 322 in the flash memory 32 for query and processing by the central processing unit 31.

[0034] Based on the above steps S11 to S14, this application automatically obtains the data to be written and the address when a write command is detected, and automatically triggers the reading and verification of the written data after the writing is completed. The acquisition and verification of flash data (i.e., the first current data) and original data (i.e., the first data) do not require the participation of the CPU, which can save valuable CPU resources. Furthermore, the verification and the next write operation are executed synchronously, thereby shortening the program update time of the microcontroller chip 30 and improving the overall system efficiency of the microcontroller chip 30.

[0035] In one example, after step S13 or while performing step S13, the method of this application further includes: determining whether the first current data has been received.

[0036] If the first current data has been received, in step S14, the flash memory controller 321 is controlled to instruct the central processing unit 31 to send a second write command, including: feeding back a read completion signal to the flash memory controller 321 to control the flash memory controller 321 to release a bus ready signal to instruct the central processing unit 31 to send a second write command.

[0037] If the first current data is not received completely and a preset time period is exceeded (i.e., the reception of the first current data is not completed for an extended period), the flash memory controller 321 is controlled to instruct the central processing unit 31 to send a second write command. This includes controlling the flash memory controller 321 to send a preset format signal to the central processing unit 31 to instruct the central processing unit 31 to send the second write command. In one example, the preset format signal is an all-zero data signal. When the central processing unit 31 receives this all-zero data signal, it can determine that the signal read this time is only for triggering the second write command, and then automatically discard it. In other examples, the flash memory controller 321 can report a data signal of a predetermined format to the central processing unit 31 through the bus 34. When the central processing unit 31 receives it, once it confirms that it conforms to the predetermined format, it can directly trigger the second write command and then automatically discard it.

[0038] Based on this, regardless of whether the reception of the first current data is completed, this example will send a second write command to start the next write operation, thereby ensuring that the current flash memory verification and the next write operation are executed synchronously, shortening the program update time of the microcontroller chip 30 and improving the overall system efficiency.

[0039] Please continue reading. Figure 3 In one example, the method of this application further includes: caching the parsed first data and the first address in a micro memory 334, and determining whether the verification of the first current data and the first data is completed during the execution of step S14.

[0040] If the verification is complete, the first data and the first address are deleted from the micro memory 334, and the second data and the second address obtained by parsing the second write command are updated in the micro memory 334.

[0041] If the verification is incomplete, it is determined whether the remaining storage space of the micro-memory 334 is less than a preset threshold and whether the second write command sent to the flash memory controller has been detected. When the remaining storage space of the micro-memory 334 is less than the preset threshold and the second write command has been detected, the central processing unit is controlled to calculate the CRC value of the second data and store it in the micro-memory 334. Once the second write completion signal of the flash memory controller 321 is detected, in response to the detection of the second write completion signal, a read operation request is sent to the flash memory controller 321, the read operation request including the second address. Then, the central processing unit 31 is controlled to obtain the second current data written to the second address in the flash memory 32. The system calculates the CRC value corresponding to the second current data. Then, in response to obtaining the CRC value corresponding to the second current data, the system controls the flash memory controller 321 to instruct the central processing unit 31 to send a third write command. The third write command is a write operation instruction following the second write command. If the second write command is regarded as an instruction to trigger the next write operation, then the third write command is an instruction to trigger the next write operation. At the same time as sending the third write command, the verification module 332 of the automatic verification device 33 compares the CRC value of the second data with the CRC value of the second current data and feeds back the comparison result to the flash memory controller 321 to instruct the central processing unit 31 to perform the corresponding operation.

[0042] This application embodiment also provides a storage medium storing a flash memory verification program, which is essentially a computer program, and when executed by a processor, the flash memory verification program implements the steps of the flash memory verification method of any of the foregoing examples.

[0043] The storage medium includes, but is not limited to, any one of read-only memory (ROM), random access memory (RAM), magnetic disk, and optical disk.

[0044] Since the flash memory verification program stored in the storage medium can execute the steps in the flash memory verification method of any embodiment provided in this application, it can achieve the beneficial effects that the flash memory verification method of any of the foregoing embodiments can achieve, as detailed in the foregoing embodiments, which will not be repeated here.

[0045] This application also provides a flash memory verification device or chip, including a memory and a processor. The memory stores a flash memory verification program, which, when executed by the processor, implements the steps of the flash memory verification method of any of the foregoing embodiments; and / or, the flash memory verification device or chip is provided with a storage medium as shown in the above example, and the processor loads the storage medium to execute the steps of the flash memory verification method, thereby achieving the beneficial effects that the flash memory verification method of the corresponding embodiment can achieve.

[0046] Figure 4 This is a schematic diagram of a flash memory verification device provided in an embodiment of this application. The flash memory verification device 40 can be simply referred to as device 40, such as... Figure 4 As shown, it includes: The first monitoring module 41 is used to monitor the write commands sent to the flash memory controller; Parsing module 42 is used to parse the write command to obtain the data to be written and the target address to be written to the flash memory; The second monitoring module 43 is used to monitor the write completion signal of the flash memory controller; Sending module 44 is configured to send a read operation request to the flash memory controller in response to a write completion monitoring signal, the read operation request including the target address; The receiving module 45 is used to receive the current data written to the target address in the flash memory from the flash memory controller; The sending module 44 is also used to control the flash memory controller to instruct the central processing unit to send the next write command; The data comparison module 46 is used to verify the current data with the data to be written while the sending module 44 sends the next write command, and to feed back the verification result to the flash memory controller to instruct the central processing unit to perform the corresponding operation.

[0047] Through the cooperation of the above modules, the flash memory verification is completed.

[0048] It should be understood that the various modules of the flash memory verification device 40 can be represented as physical devices or virtual modules (i.e., commonly referred to as logical modules) in actual scenarios. A single module can be implemented by a single physical device or by two or more physical devices working together. Similarly, the function performed by a single module can be implemented by a single physical device or by two or more physical devices working together. Furthermore, the functions corresponding to each module can be implemented by the corresponding steps of the flash memory verification method in any of the foregoing embodiments.

[0049] This application also provides a microcontroller chip that integrates a central processing unit (CPU), flash memory, and an automatic verification device. The flash memory includes a flash memory controller, and the automatic verification device is connected to the CPU. Based on an enable signal issued by the CPU, the automatic verification device communicates with the flash memory controller to execute the steps of the flash memory verification method in any of the aforementioned examples, thereby achieving the beneficial effects achievable by the flash memory verification method of the corresponding embodiment. This microcontroller chip can be used with the aforementioned... Figure 3 The microcontroller chip 30 shown has the same structural design, which will not be described in detail here.

[0050] The above are only some embodiments of this application and do not limit the patent scope of this application. For those skilled in the art, any equivalent structural transformations made using the content of this specification and drawings are similarly included within the patent protection scope of this application.

[0051] The use of step designations such as S11 and S12 in this document is intended to more clearly and concisely describe the corresponding content and does not constitute a substantial restriction on the order. In specific implementation, those skilled in the art may execute S12 first and then S11, etc., but these should all be within the protection scope of this application.

[0052] Although this document uses terms such as "first," "second," etc., to describe various types of information, this information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. Furthermore, the singular forms "a," "an," and "the" are intended to also include the plural forms. The terms "or" and "and / or" are interpreted as inclusive, or meaning either one or any combination thereof. Exceptions to this definition only arise when combinations of elements, functions, steps, or operations are inherently mutually exclusive in some way.

Claims

1. A flash memory verification method, characterized in that, For use in a microcontroller chip, the microcontroller chip integrating a central processing unit and flash memory, the flash memory having a flash memory controller, the method includes: In response to detecting the first write command sent to the flash memory controller, the first data to be written and the first address where the first data needs to be written to the flash memory are parsed from the first write command; In response to detecting a first write completion signal from the flash memory controller, a read operation request is sent to the flash memory controller, the read operation request including the first address; Receive the first current data written to the first address from the flash memory controller; Determine whether the first current data has been received completely; If so, a read completion signal is fed back to the flash memory controller to control the flash memory controller to release the bus ready signal, thereby instructing the central processing unit to send a second write command; if the first current data has not been received and a preset time has been exceeded, the flash memory controller is controlled to send a preset format signal to the central processing unit to instruct the central processing unit to send a second write command; while instructing the central processing unit to send the second write command, the first current data is verified against the first data, and the verification result is fed back to the flash memory controller to instruct the central processing unit to perform the corresponding operation; The method further includes: The parsed first data and the first address are cached in a micro memory; Determine whether the verification between the first current data and the first data is complete; If completed, the first data and the first address are deleted from the micro memory, and the second data and the second address obtained by parsing the second write command are updated in the micro memory; If not completed, determine whether the remaining storage space of the micro-memory is less than a preset threshold and whether the second write command sent to the flash memory controller has been detected; and, When the remaining storage space of the micro-memory is less than a preset threshold and the second write command is detected, the central processing unit is controlled to calculate the CRC value of the second data and store it in the micro-memory. In response to detecting a second write completion signal from the flash memory controller, a read operation request is sent to the flash memory controller, the read operation request including the second address; The central processing unit is controlled to acquire the second current data written to the second address in the flash memory, and to calculate the CRC value corresponding to the second current data; In response to obtaining the CRC value corresponding to the second current data, the flash memory controller instructs the central processing unit to send a third write command, while comparing the CRC value of the second data with the CRC value of the second current data, and feeding back the comparison result to the flash memory controller to instruct the central processing unit to perform the corresponding operation.

2. The method according to claim 1, characterized in that, The method further includes: Determine whether an enable signal has been received from the central processing unit; If so, monitor the first write command sent to the flash memory controller; If not, the central processing unit obtains the first current data written to the first address in the flash memory, and the central processing unit verifies the first current data with the first data.

3. The method according to claim 1, characterized in that, The method of monitoring the first write command issued to the flash memory controller includes any of the following: The first write command is monitored from the central processing unit; The first write command is monitored from the flash memory controller; The central processing unit is connected to the flash memory controller via a bus, and monitors the first write command from the bus.

4. The method according to any one of claims 1 to 3, characterized in that, The central processing unit (CPU) and the flash memory controller are connected via an AHB (Automatic Bus Buffer). The flash memory controller generates a high-level bus ready signal and feeds it back to the CPU via the AHB to instruct the CPU to send the second write command.

5. The method according to claim 1, characterized in that, The preset format signal is an all-zero data signal.

6. A microcontroller chip, characterized in that, The microcontroller chip integrates a central processing unit, flash memory, and an automatic verification device. The flash memory is equipped with a flash memory controller. The automatic verification device is connected to the central processing unit and communicates with the flash memory controller according to the enable signal issued by the central processing unit to execute the steps of the flash memory verification method according to any one of claims 1 to 5.

7. A flash memory verification device, characterized in that, The device includes a processor and a memory, wherein the memory stores a flash memory verification program, and when the flash memory verification program is executed by the processor, it implements the steps of the flash memory verification method as described in any one of claims 1 to 5.

8. A storage medium, characterized in that, The device contains a computer program that, when executed by a processor, implements the steps of the flash memory verification method as described in any one of claims 1 to 5.

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