A method of controlling the gate drive of a MOSFET

Abstract

The application relates to the technical field of power electronics and semiconductor control, and discloses a MOSFET gate drive control method, which comprises the following steps: reading parameters and turning on a push-pull branch to inject a pulse current, and outputting a pre-trigger reference voltage which is pre-compensated and reduced; when a gate-source voltage reaches an opening threshold, a timer is triggered to time, and a blanking window is activated to shield the input of a comparator; when the pre-trigger reference is touched, the timing is stopped to latch a time difference parameter, the push-pull branch is synchronously turned off, and a constant current circuit is turned on; the time difference parameter is compared to determine the driving current gradient level of the next cycle, a compensation amount is corrected to overwrite a lookup table, and iteration is completed. Through the accurate offset of the reference voltage, inherent hardware propagation delay is precisely offset, the overdrive of gate charge is prevented, the blanking window is combined with an anti-interference mechanism and a cross-cycle parameter iteration evaluation mechanism, the driving system has the ability to cope with load fluctuation, and the switching efficiency is considered.

Description

Technical Field

[0001] This invention relates to the field of power electronics and semiconductor control technology, specifically to a MOSFET gate drive control method. Background Technology

[0002] Power devices such as MOSFETs are widely used in switching power supplies and motor drive systems. To reduce system switching losses, it is typically necessary to increase the switching speed of these power devices. Current gate drive circuits mainly accelerate the device across the Miller plateau by injecting transient large pulse currents into the gate of the power device.

[0003] Existing drive control circuits suffer from inherent physical propagation delays in their internal analog comparators and logic gates when performing large-pulse current cutoff operations. When the drive circuit detects that the gate-source voltage has deviated from the Miller plateau and issues a cutoff command, the actual physical turn-off action is delayed. This lag causes excess charge to continue being injected into the gate during the delay period, resulting in overdrive. This excess charge not only increases the power consumption of the drive circuit but also increases the charge discharge burden on the parasitic capacitances within the power device during the next half-cycle, slowing down the device's turn-off speed.

[0004] Meanwhile, during the initial turn-on of high-current driven power devices, voltage oscillations occur between the gate and source due to the parasitic inductance of the device package and the circuit board traces. Traditional threshold detection circuits are prone to false triggering when faced with such voltage signals accompanied by high-frequency fluctuations, leading to incorrect drive commands output by the control logic.

[0005] Furthermore, most current drive controls use fixed current output parameters, making them unable to sense changes in external operating conditions. When the system load increases or the junction temperature of power devices rises, the amount of Miller charge required inside the devices increases significantly. A fixed drive current will cause the time for the devices to cross the Miller plateau to lengthen, leading to increased switching losses. On the other hand, maintaining a large drive current under light load conditions can cause unnecessary high-frequency electromagnetic interference. This static drive mode lacks a dynamic feedback adjustment mechanism, making it difficult to balance switching efficiency and electromagnetic compatibility under different load conditions. Summary of the Invention

[0006] To address the shortcomings of existing technologies, this invention provides a MOSFET gate drive control method that solves the problems of gate overdrive caused by hardware link propagation delay, voltage oscillation and false triggering caused by parasitic parameters in the early stage of turn-on, and the inability of fixed drive parameters to adapt to load and junction temperature changes, resulting in difficulty in balancing switching losses and electromagnetic interference.

[0007] To achieve the above objectives, the present invention provides the following technical solution: a MOSFET gate drive control method, comprising: At the start of the PWM cycle, the base drive current gradient level, fine-tuning current compensation, and leading-edge blanking time window parameters are read from the two-dimensional lookup table. The push-pull output branch is turned on to inject an initial large pulse current into the gate of the driven power device, while simultaneously outputting a pre-compensated and down-adjusted pre-trigger reference voltage to the second analog comparator. When the gate-source voltage reaches the turn-on threshold voltage reference, the high-resolution timer unit is triggered to accumulate timing, and the leading-edge blanking time window is activated to shield the input of the second analog comparator.

[0008] When the gate-source voltage touches the pre-triggered reference voltage after pre-compensation and reduction, the second analog comparator outputs a valid toggle signal, the high-resolution timer unit stops timing and latches the time difference parameter. The captured valid toggle signal generates a hardware truncation instruction to disconnect the push-pull output branch and simultaneously turn on the milliampere-level constant current output circuit. The time difference parameter is compared with the operating time threshold to determine the basic drive current gradient level to be allocated in the next PWM cycle. Based on the difference between the time difference parameter and the preset ideal reference time, the fine-tuning current compensation amount for the next cycle is corrected and written into a two-dimensional lookup table to complete cross-cycle closed-loop iterative control.

[0009] The process of outputting the pre-triggered reference voltage after pre-compensation and reduction includes slope-based delay pre-compensation calculation logic: the basic drive current gradient level is added to the fine-tuning current compensation amount to obtain the total drive current level value. Combined with the nominal input capacitance parameters of the driven power device, the ramp-up slope of the gate-source voltage under the current operating condition is calculated. Based on the obtained ramp-up slope multiplied by the known inherent physical propagation delay time, the additional voltage rise within the inherent physical propagation delay time interval is calculated.

[0010] The pre-triggered reference voltage is obtained by offsetting the calculated additional voltage rise value downwards from the reference voltage setting value when the driven power device ideally disconnects from the Miller plateau under the target operating condition. The reference voltage setting value when the driven power device ideally disconnects from the Miller plateau under the target operating condition is set to a value higher than the actual Miller plateau voltage of the driven power device.

[0011] During the process of activating the leading-edge blanking time window to block the input of the second analog comparator, the leading-edge blanking time window is activated at the same physical moment when the output of the first analog comparator flips. During the duration of the leading-edge blanking time window, any level transition signal of the second analog comparator output is forcibly ignored, blocking the interrupt input channel of the second analog comparator.

[0012] For triggering the high-resolution timer unit to accumulate time: the toggling level signal output by the first analog comparator is directly transmitted to the digital control and arithmetic module as the start trigger source for the high-resolution timer unit. After receiving the trigger signal, the high-frequency clock counter register inside the high-resolution timer unit begins to perform the accumulation operation.

[0013] When the milliampere-level constant current output circuit is synchronously turned on, the bypass milliampere-level constant current output circuit is turned on at the same time as the push-pull output branch is turned off, so as to maintain the continuous injection of a small DC current into the gate of the driven power device.

[0014] The operation of determining the basic drive current gradient level to be allocated in the next PWM cycle includes: comparing the acquired time difference parameter with the preset heavy load time threshold and light load time threshold. If the time difference parameter is greater than the heavy load time threshold, it is determined that the current operating condition is heavy load or high junction temperature, and the basic drive current gradient level to be allocated in the next PWM cycle is set to level 3A.

[0015] If the time difference parameter is less than or equal to the light load time threshold, it is determined to be under normal light load operating conditions, and the basic drive current gradient level for the next cycle is downgraded to 1.5A. The heavy load time threshold is numerically greater than the light load time threshold, forming a hysteresis interval between the two. When the value of the time difference parameter is within the hysteresis interval, the basic drive current gradient level of the previous cycle remains unchanged.

[0016] In the operation of correcting the fine-tuning current compensation amount for the next cycle, the time difference parameter of the discrete iterative fine-tuning calculation is calculated and the difference between it and the preset ideal reference time is determined. This difference is multiplied by the set discrete proportional compensation coefficient and added to the actual output fine-tuning current compensation amount of the current cycle to obtain the fine-tuning current compensation amount that needs to be added to the output in the next PWM switching cycle, thus completing the discrete iterative fine-tuning calculation.

[0017] Finally, via the internal digital bus, the updated base drive current gradient level, the associated matching leading-edge blanking time window parameters, and the calculated fine-tuning current compensation for the next cycle are all written into the corresponding address space of the two-dimensional lookup table. The newly written data directly overwrites the historical records of the previous cycle, so that they can be directly accessed in the next cycle.

[0018] This invention provides a MOSFET gate drive control method. It has the following advantages: 1. This invention calculates the gate-source voltage ramp-up slope by combining the drive current level and the nominal input capacitance, and shifts the pre-trigger reference voltage downward in advance, thus offsetting the inherent physical propagation delay time of the system hardware link. This ensures that the actual cut-off time of the push-pull output branch falls on the target voltage point, avoiding the injection of excess gate charge due to the lag in the cut-off command, reducing the power consumption of the drive circuit, and preventing subsequent turn-off from being slowed down.

[0019] 2. This invention activates the leading-edge blanking time window simultaneously with triggering the high-resolution timer, forcibly blocking the interrupt input of the second analog comparator, thus eliminating false triggering caused by voltage oscillations due to parasitic inductance in the package and wiring during the initial conduction of the driven power device. After the large pulse current injection ends, the bypassed milliampere-level constant current output circuit is simultaneously turned on to continuously replenish the small leakage current caused by parasitic effects, stabilizing the gate-source voltage of the driven power device at a high level and low on-resistance state.

[0020] 3. This invention evaluates the overall system operating condition by latching the time difference parameter in the Miller plateau region and uses discrete iterative fine-tuning to calculate the cross-cycle correction of the basic drive current gradient level and the fine-tuning current compensation amount. The system automatically increases the drive current to accelerate the switching process under heavy load or high junction temperature, and degrades the drive current under light load to reduce drive losses and high-frequency electromagnetic interference, enabling the drive system to have closed-loop adaptive capability to cope with load fluctuations and parameter drift. Attached Figure Description

[0021] Figure 1 This is a diagram showing the overall hardware architecture of the gate drive control system according to an embodiment of the present invention. Figure 2 This is a flowchart illustrating the gate drive control method according to an embodiment of the present invention. Figure 3 This is a comparison diagram of the gate-source voltage turn-on transient response of an embodiment of the present invention. Detailed Implementation

[0022] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0023] See attached document Figure 1 The present invention provides a MOSFET gate drive control system, which includes multiple mutually coupled hardware functional topology modules.

[0024] The system hardware layer includes a parallel drive output module. Located inside the isolated driver chip, this module features multiple independent parallel push-pull output branches. Through register gating operations on the internal digital bus, the parallel drive output module activates the corresponding push-pull output branch to provide initial large pulse currents of varying gradients. For the KP886761QL and KP886763QL series driven power devices, the large pulse current level is configured to be 1.5A or 3A, and it also includes an auxiliary fine-tuning current source configurable via the internal digital bus. The parallel drive output module has an internal bypass connection to a milliampere-level constant current output circuit, which takes over the drive task and maintains a steady state after the driven power device is fully turned on.

[0025] The system front end is equipped with a signal detection and acquisition module. This module includes a first analog comparator and a second analog comparator connected to the drive node. The inverting input of the first analog comparator is connected to a fixed threshold voltage reference for the driven power device. The inverting input of the second analog comparator is connected to the output channel of the internal digital-to-analog converter. The non-inverting inputs of both the first and second analog comparators are connected to the gate node of the driven power device to acquire the dynamic rise signal of the gate-source voltage in real time.

[0026] The system core includes a digital control arithmetic module. This module consists of a high-resolution timer unit, a logic gate array (GNA) core, and a register set configured with a two-dimensional lookup table. The start / stop control pins of the high-resolution timer unit are connected to the interrupt output pins of the first and second analog comparators, respectively. The GNA core reads the state toggling edges of the first and second analog comparators and directly controls the on / off states of each push-pull output branch in the parallel drive output module. The register set stores the timing parameters and compensation coefficients required by the digital control logic.

[0027] The aforementioned hardware architecture module executes a series operation mechanism based on a specific timing state machine within a complete PWM switching cycle.

[0028] See attached document Figure 2 This invention provides a MOSFET gate drive control method, comprising the following steps: S10, Initial parameter loading and configuration are performed. At the start of the PWM cycle, the digital control operation module accesses the two-dimensional lookup table to read the preset basic drive current gradient level, fine-tuning current compensation amount, and corresponding matching leading-edge blanking time window parameters for the current cycle. Based on the internally set slope coupling operation relationship, the digital control operation module drives the digital-to-analog converter to output the pre-compensated and down-adjusted pre-trigger reference voltage to the second analog comparator. After the parameters are loaded, the parallel drive output module selects the push-pull output branch corresponding to the basic drive current gradient level and injects an initial large pulse current into the gate of the driven power device. S20, execute shielding control and feature extraction. As charge is injected, the gate-source voltage of the driven power device rises; when the gate-source voltage of the driven power device reaches the threshold voltage reference of the first analog comparator, the first analog comparator outputs a toggle signal; this signal triggers the high-resolution timer unit to start accumulating time and simultaneously activates the leading-edge blanking time window; during the leading-edge blanking time window, the logic gate array operation core shields the status signal input of the second analog comparator; after the blanking window ends, the system unshields; when the gate-source voltage crosses the Miller plateau and touches the pre-trigger reference voltage, the second analog comparator outputs a valid toggle signal; the high-resolution timer unit stops timing, and the digital control operation module extracts and latches the time difference parameter at this time; S30 performs hardware delay alignment and stepped current switching. After the logic gate array operation core captures the valid toggle signal of the second analog comparator, it triggers a hardware truncation instruction, disconnects the push-pull output branch inside the parallel drive output module, and simultaneously turns on the milliampere-level constant current output circuit. Since the pre-trigger reference voltage of the second analog comparator has been pre-adjusted and compensated, the time margin for early toggle is canceled out by the inherent physical propagation delay time. The compensation mechanism ensures that the actual truncation time falls at the target voltage point. S40, perform cross-cycle parameter evaluation and iterative update. After the large current injection of the current PWM cycle ends and enters the steady-state maintenance phase, the digital control calculation module calls the latched time difference parameter to evaluate the comprehensive operating conditions of the current system load and the junction temperature of the driven power device; the digital control calculation module compares the time difference parameter with the set operating time threshold to determine the basic drive current gradient level to be allocated in the next PWM cycle; the digital control calculation module applies discrete iterative fine-tuning calculation, and corrects the fine-tuning current compensation amount of the drive current in the next cycle based on the difference between the time difference parameter and the preset ideal reference time; the digital control calculation module writes the updated basic drive current gradient level and fine-tuning current compensation amount into a two-dimensional lookup table to complete the cross-cycle closed-loop iterative control.

[0029] During step S10, the system is at the beginning of a PWM switching cycle, performing initial parameter loading and configuration. This process maps low-level hardware instructions to specific registers and completes the pre-configuration of the reference voltage to compensate for physical delays. The specific implementation process includes the following sub-steps: S101 reads the underlying drive parameters and performs physical mapping. At the synchronization moment of generating the PWM turn-on edge pulse, the digital control arithmetic module accesses the two-dimensional lookup table in its internal memory. The specific underlying implementation of the digital control arithmetic module includes digital integrated circuits with digital computation and addressing capabilities, such as microcontroller units, digital signal processors, or field-programmable gate arrays. The two-dimensional lookup table is deployed in the on-chip static random access memory or non-volatile flash memory of the digital control arithmetic module. During the first PWM switching cycle of the system's initial power-on initialization, the digital control arithmetic module sets the fine-tuning current compensation amount in the two-dimensional lookup table to zero by default.

[0030] The digital control arithmetic module reads the preset base drive current gradient level and fine-tuning current compensation amount from a two-dimensional lookup table using addressing instructions, and simultaneously reads the leading-edge blanking time window parameters associated with and matched the base drive current gradient level. The digital control arithmetic module converts the read base drive current gradient level and fine-tuning current compensation amount into low-level hardware control instructions, and sends the corresponding multiplexing configuration words to the gating register of the parallel drive output module through the internal digital bus.

[0031] S102 performs hardware delay pre-compensation calculations for slope coupling and outputs the reference voltage. The toggling action of the second analog comparator in the gate drive control system and the signal transmission of the logic gate array operation core have inherent physical propagation delays. If the actual target voltage at which the driven power device is disconnected from the Miller platform is directly used as the trigger threshold of the second analog comparator, a time lag will occur when the system issues a cutoff command and performs a physical disconnection, resulting in the injection of excess charge into the driven power device.

[0032] During the inherent physical propagation delay period of the system's cutoff action, the large pulse current continues to be injected into the gate of the driven power device, and the gate-source voltage of the driven power device continues to rise at a certain slope. Therefore, this step calculates the additional voltage rise during the delay time and shifts the reference voltage setting value for when the driven power device ideally breaks away from the Miller plateau under the target operating condition downwards by this value, causing the second analog comparator to trigger earlier. This mechanism utilizes the inherent physical propagation delay time as a buffer for physical cutoff, ultimately ensuring that the actual cutoff time falls precisely at the target voltage point.

[0033] The digital control calculation module calls the base drive current gradient level and fine-tuning current compensation amount loaded in the aforementioned sub-steps, adds them together to obtain the total drive current level value, and uses the ratio of the total drive current level value to the nominal input capacitance of the driven power device to characterize the ramp-up slope of the gate-source voltage under the current operating condition. Based on the calculated ramp-up slope and the known inherent physical propagation delay time of the system, the digital control calculation module calculates a pre-trigger reference voltage for early triggering. The calculation relationship of the pre-trigger reference voltage based on slope coupling is shown in the following formula: ; In the formula, Indicates the first The pre-trigger reference voltage after pre-compensation and reduction within each PWM switching cycle; This represents the reference voltage setting value when the driven power device ideally breaks away from the Miller plateau under the target operating condition. This setting value is obtained by referring to the gate charge characteristic curve in the datasheet of the selected driven power device, or by calibration through offline static testing of the system. Indicates the first The total drive current level value allocated for each PWM switching cycle is equal to the sum of the base drive current gradient level and the fine-tuning current compensation amount for the current cycle. The nominal input capacitance of the driven power device is provided by the selection specification of the driven power device and is pre-written into the digital control calculation module during system initialization. It represents the inherent physical propagation delay time, which is an inherent constant of the hardware link from the detection of the voltage threshold by the gate drive control system to the actual execution of the disconnection action by the parallel drive output module. It is obtained by measuring the end-to-end delay of the signal link inside the drive chip and its value is usually between a few nanoseconds and tens of nanoseconds.

[0034] To ensure the safety and reliability of the early triggering mechanism, the reference voltage setting value when the driven power device ideally disconnects from the Miller plateau under the target operating condition is... This value must be set higher than the actual Miller plateau voltage of the driven power device, with sufficient voltage margin. This margin must ensure that the voltage calculated after subtracting the aforementioned delay compensation term within any normal operating parameter range... It is always higher than the actual Miller plateau voltage of the driven power device to prevent premature truncation caused by false triggering of the second analog comparator after the blanking window ends.

[0035] Calculation Item Used to characterize the gate-source voltage ramp-up slope under the current injection current condition. Calculation terms This represents an absolute physical quantity estimate of the voltage's continued rise within the inherent physical propagation delay time interval. Based on this calculation logic, the digital control module quantizes the digital result and drives the internal digital-to-analog converter to convert it into an actual analog voltage signal, which is then continuously output to the inverting input of the second analog comparator.

[0036] S103 executes a large pulse current injection. After completing the digital instruction mapping and pre-trigger reference voltage physical configuration, the parallel drive output module, based on the configuration word written in the gating register, turns on the corresponding push-pull output branch internally. For the characteristics of the KP886761QL and KP886763QL series driven power devices adapted to the system, the parallel drive output module turns on the set number of parallel branches, continuously injecting a large pulse current of 1.5A or 3A into the gate of the driven power device, driving the gate-source voltage of the driven power device to rise rapidly. Regarding the specific multi-stage transistor push-pull topology used internally in the parallel drive output module, those skilled in the art can select and connect devices according to the integrated circuit design specifications of conventional isolated gate driver chips. The specific arrangement of its internal push-pull circuit and complementary metal-oxide-semiconductor is well-known in the art and will not be described further here.

[0037] During step S20, the system performs shielding control and feature extraction based on the initial large pulse current injected into the parallel drive output module. This process mainly completes the anti-interference processing at the moment the driven power device is turned on and the accurate acquisition of the time difference parameter across the Miller plateau. The specific implementation process includes the following sub-steps: S201, execute the turn-on threshold capture and timing trigger. As the initial large pulse current continuously injects charge into the gate of the driven power device, the gate-source voltage of the driven power device is in a rapid ramp-up state. The first analog comparator in the signal detection and capture module monitors the gate-source voltage in real time through the non-inverting input. When the amplitude of the gate-source voltage rises to and exceeds the turn-on threshold voltage reference set at the inverting input of the first analog comparator, the output state of the first analog comparator flips. The turn-on threshold voltage reference characterizes the physical critical point at which the internal conductive channel of the driven power device begins to form. The value of this reference voltage is determined according to the typical gate turn-on threshold voltage given in the datasheet of the driven power device, or it can be measured by a static characteristic tester. Its value range is usually set between 2V and 5V.

[0038] The toggle signal output by the first analog comparator is directly transmitted to the digital control and arithmetic module as the trigger source for the high-resolution timer unit. After receiving the trigger signal, the high-resolution timer unit begins to accumulate its internal high-frequency clock counter register to record the current physical time point as the starting point for the time difference parameter.

[0039] S202 activates the leading-edge blanking logic and performs dynamic masking. At the same physical moment the first analog comparator outputs a toggle signal, the logic gate array (GNA) core synchronously activates the leading-edge blanking time window. In the actual physical operation of isolated gate driving, when injecting charge into the gate with a large pulse current of 1.5A or 3A, the gate-source voltage will oscillate at a high frequency in the initial stage of the driven power device's conduction due to the parasitic inductance of the driven power device package and the parasitic inductance of the printed circuit board traces. This oscillation manifests as fluctuations in the voltage waveform, which can easily cause the second analog comparator to produce erroneous toggle actions. To eliminate false triggering caused by parasitic parameters, the GNA core, through internal instruction configuration at the hardware level, blocks the interrupt input channel of the second analog comparator. During the duration of the leading-edge blanking time window, the GNA core forcibly ignores any level transition signals output by the second analog comparator.

[0040] The length of the leading-edge blanking time window is set based on the size of the system's parasitic inductance and the estimated oscillation decay period of the drive current gradient, typically ranging from tens of nanoseconds to 150 nanoseconds, to ensure coverage of the entire high-frequency oscillation decay period without obscuring the subsequent real voltage signal. The lower-level physical implementation of this shielding mechanism relies on a combination of mask registers controlled by a high-resolution timer unit. For conventional methods of eliminating signal jitter caused by high-frequency electromagnetic interference, those skilled in the art can use AND gate masking circuits to achieve timed signal shielding; the masking trigger logic is well-known in the field and will not be elaborated upon here.

[0041] S203, capture the feature reference point and latch time difference parameter. When the timing period set by the leading-edge blanking time window is reached, the logic gate array operation core automatically unmasks the second analog comparator and resumes signal listening of the interrupt channel. At this time, the driven power device is in the Miller plateau stage, and the gate-source voltage remains relatively flat. With the continuous injection of large pulse current, the charge accumulation of the Miller capacitor inside the driven power device is gradually completed, and the gate-source voltage leaves the Miller plateau region and begins to rise again. When the gate-source voltage crosses this flat region and touches the pre-trigger reference voltage configured in step S10, the second analog comparator outputs a valid toggle signal.

[0042] The valid toggle signal is directly input to the stop control pin of the high-resolution timer unit. The high-resolution timer unit terminates its accumulation counting operation. The digital control arithmetic module reads the final count value from the internal register of the high-resolution timer unit, multiplies this count value by the inherent high-frequency clock cycle value of the high-resolution timer unit, obtains the precise physical time span, and latches it into the data register as a time difference parameter. This time difference parameter represents the physical time span from the start of timing by the toggle signal output by the first analog comparator to the stop of timing by the output of the valid toggle signal by the second analog comparator. Through the above steps, the system completes the conversion of the analog transient process inside the driven power device into discrete time characteristic data.

[0043] During step S30, the system performs a hardware-level state switch based on the captured valid toggle signal of the second analog comparator. This process mainly completes the conversion of the drive current between transient large current pulses and steady-state small currents, and utilizes prior configuration to offset hardware execution delays. The specific implementation process includes the following sub-steps: S301 triggers a hardware cutoff instruction and blocks the high-current branch. After the input port of the logic gate array (GGA) core captures a valid toggle signal from the second analog comparator, the internal combinational logic circuit responds immediately. The GGA core generates a hardware cutoff instruction to turn off the parallel drive output module by changing the state of its internal reset flip-flop. This cutoff instruction is transmitted to the gating control terminal of the parallel drive output module via the internal digital bus, changing the control level of the corresponding push-pull output branch to the off state, thereby forcibly turning off the transistor that is outputting a large pulse current. This action terminates the process of injecting the initial large pulse current into the gate of the driven power device.

[0044] S302, perform propagation delay cancellation and time node alignment. From the time the second analog comparator detects the voltage threshold to the time the push-pull output branch actually completes physical shutdown, the signal experiences an inherent physical propagation delay in the transmission path. In step S10, the system has pre-compensated the pre-trigger reference voltage of the second analog comparator based on this inherent physical propagation delay. Compared to directly using the reference voltage setting value when the driven power device ideally leaves the Miller plateau under the target operating condition as the trigger threshold of the second analog comparator, the reduction of the reference voltage causes the second analog comparator to flip earlier, and the time margin formed by this early triggering is used to compensate for the inherent physical propagation delay.

[0045] This time-based cancellation ensures that the actual cutoff time falls on the target voltage point. Failure to achieve this alignment results in turn-off hysteresis, leading to excess dynamic charge injection into the gate and causing gate-source voltage overshoot. This extra charge not only increases the power consumption of the drive circuit but also prolongs the discharge time of the parasitic capacitance within the driven power device when it needs to be turned off in the next half-cycle, thus slowing down the turn-off speed. This delayed alignment mechanism prevents the aforementioned overdrive phenomenon.

[0046] S303 is used for conducting steady-state maintenance circuitry and replenishing leakage charge. While the push-pull output branch is turned off, the digital control module controls the bypass milliampere-level constant current output circuit to turn on, achieving transient switching of the stepped current. After the driven power device leaves the Miller plateau and enters a fully conducting state, a small parasitic leakage current exists between the gate and source due to parasitic effects of the driven power device's package and internal structure. If power supply to the gate is completely stopped during steady-state operation, this leakage current causes the accumulated charge on the gate to slowly dissipate, resulting in a drop in the gate-source voltage, which in turn increases the on-resistance of the driven power device and increases conduction losses.

[0047] After the system switches to the milliampere-level constant current output circuit, a small DC current is continuously injected into the gate of the driven power device. The specific value of this steady-state sustaining current is determined based on the maximum gate-source leakage current parameter specified in the datasheet of the driven power device, combined with the derating curve at the highest operating ambient temperature of the system. The magnitude of this steady-state sustaining current is typically set between 2mA and 10mA to compensate for the aforementioned parasitic leakage charge, stabilizing the gate-source voltage of the driven power device at a high level and ensuring that the driven power device remains in a low on-impedance condition. For the specific implementation of the milliampere-level constant current output circuit, those skilled in the art can use a topology combining a reference current source and a current mirror to provide a stable output. The current mirror ratio setting and bias network design are well-known techniques in the field and will not be elaborated here.

[0048] During step S40, the system enters the adaptive closed-loop iterative update phase for cross-cycle driving parameters and gradients. This process is performed in the background after the large current injection of the current PWM cycle ends and the system enters the steady-state maintenance phase. It mainly completes system condition evaluation and corrects the output parameters for the next cycle. The specific implementation process includes the following sub-steps: S401 evaluates the overall system operating conditions and performs drive current gradient determination. The digital control arithmetic module reads the time difference parameter latched in the data register. The time difference parameter reflects the actual broadening of the Miller plateau of the driven power device. When the load current increases or the junction temperature of the driven power device rises, the Miller charge inside the driven power device increases significantly, resulting in a longer physical time required to cross the Miller plateau. Therefore, the time difference parameter can be used as a characterizing parameter for evaluating the overall operating conditions of the current system load and the junction temperature of the driven power device. The digital control arithmetic module compares the time difference parameter with preset heavy load time thresholds and light load time thresholds.

[0049] If the time difference parameter is greater than the heavy load time threshold, the system is determined to be under heavy load or high junction temperature conditions. The digital control module sets the basic drive current gradient level to be allocated in the next PWM cycle to 3A to accelerate the switching process of subsequent cycles and reduce switching losses. If the time difference parameter is less than or equal to the light load time threshold, the system is determined to be under light load normal conditions. The digital control module downgrades the basic drive current gradient level to 1.5A in the next cycle to reduce drive losses and high-frequency electromagnetic interference.

[0050] To prevent frequent mode switching under critical operating conditions, the heavy-load time threshold is numerically greater than the light-load time threshold, forming a hysteresis interval between them. When the time difference parameter value is within this hysteresis interval, the digital control module maintains the basic drive current gradient level of the previous cycle unchanged. The specific values ​​of the heavy-load and light-load time thresholds are obtained offline based on the total gate charge characteristic curves of the driven power device under different operating conditions and are pre-stored in the non-volatile memory of the digital control module.

[0051] S402, perform cross-cycle iterative correction of the fine-tuning current compensation amount. After determining the basic drive current gradient level, the digital control calculation module fine-tunes the overall injection capability of the large pulse current in the next cycle. If the current judgment result triggers a cross-level switch of the basic drive current gradient level (such as switching from 1.5A level to 3A level, or vice versa), the digital control calculation module resets the historical integral value of the current fine-tuning current compensation amount to zero to prevent current overshoot caused by the instantaneous state switch; if the basic drive current gradient level remains unchanged, the logic unit inside the digital control calculation module runs discrete iterative fine-tuning calculation to calculate the difference between the time difference parameter and the preset ideal reference time.

[0052] If the time difference parameter of the current cycle is greater than the preset ideal reference time, it indicates that the current charge injection rate lags behind the ideal state. In the next cycle, the system needs to increase the fine-tuning current compensation at the basic drive current gradient level to inject more initial charge into the gate of the driven power device during the Miller plateau, prompting the Miller to approach the ideal value again over time. The discrete iterative fine-tuning calculation relationship is shown in the following equation: ; In the formula, This indicates that the fine-tuning current compensation amount will be superimposed on the output in the next PWM switching cycle after the update; Indicates the current number The actual superimposed fine-tuning current compensation amount for each cycle; Indicates the time difference parameter; Indicates the preset ideal reference time; This represents the discrete proportional compensation coefficient.

[0053] Regarding the parameter determination method: discrete proportional compensation coefficient The specific value is determined by the closed-loop control bandwidth set by the system to ensure the convergence of the iterative process and prevent system oscillations. Through this calculation logic, if the current time difference parameter is greater than the preset ideal reference time, the system will increase the fine-tuning current compensation in the next cycle, and vice versa.

[0054] S403, the two-dimensional lookup table is overwritten to complete the closed-loop update. The digital control arithmetic module stores and overwrites the new parameters generated in the above steps. The digital control arithmetic module writes the updated base drive current gradient level, the associated matching leading-edge blanking time window parameters, and the calculated fine-tuning current compensation for the next cycle into the corresponding address space of the two-dimensional lookup table via the internal digital bus. The newly written data directly overwrites the historical records of the previous cycle. When the next PWM switching cycle arrives, the system re-executes step S10, directly calling the updated parameters from the two-dimensional lookup table for configuration and drive.

[0055] The parameter overwrite operation establishes a closed-loop link between physical feedback and digital computation, enabling the gate drive control system to adaptively adjust to load fluctuations and parameter drift of the driven power devices. For the specific implementation of the lower-level features of the internal microcontroller's operation registers and updating the memory address pointer, those skilled in the art can use conventional digital integrated circuit data bus read / write timing. The data overwrite logic of its internal static random access memory is well-known in the field and will not be elaborated upon here.

[0056] Specific application examples: This system is designed for use in a 400V / 800W AC / DC switching power supply, with the driven power device being the KP886761QL model.

[0057] The initial known parameters of the system are set as follows: The switching frequency is 100kHz (i.e., one PWM cycle is 10μs).

[0058] The nominal input capacitance of the driven power device =5nF.

[0059] Inherent physical propagation delay time =20ns.

[0060] Preset ideal reference time =80ns.

[0061] Discrete proportional compensation coefficient =0.02A / ns.

[0062] The dynamic operation process of the example is as follows: Cycle 1 (System Cold Start and Parameter Initialization): S10: The digital control module accesses a two-dimensional lookup table, reads the current cycle's preset base drive current gradient level as 1.5A, and the fine-tuning current compensation as 0A. The sum of these two values ​​yields a total drive current level of 1.5A. Based on the aforementioned slope coupling operation relationship, the digital control module calculates the pre-triggered reference voltage after pre-compensation and adjustment, ensuring that this voltage remains consistently higher than the actual Miller plateau voltage of the driven power device within its normal operating parameter range. The system injects charge into the gate of the driven power device with a total drive current level of 1.5A.

[0063] S20: When the gate-source voltage of the driven power device reaches the turn-on threshold voltage reference, the high-resolution timer unit starts timing and activates a 50ns leading-edge blanking time window. When the gate-source voltage crosses the Miller plateau and touches the pre-triggered reference voltage after pre-compensation and downsampling, the second analog comparator outputs a valid toggle signal. The high-resolution timer unit stops timing and latches the time difference parameter at this moment. =130ns.

[0064] S30: The logic gate array operation core issues a hardware truncation command. Due to the inherent physical propagation delay of 20ns, after the aforementioned pre-compensation, the actual truncation time falls at the target voltage point, and a 5mA milliampere-level constant current output circuit is simultaneously turned on to maintain steady state.

[0065] S40: The digital control calculation module found that the extracted time difference parameter of 130ns was greater than the preset ideal reference time of 80ns, indicating that the current injection speed was too slow. The digital control calculation module calculated the fine-tuning current compensation amount for the next cycle. =0+0.02×(130 80) = 1.0A. The updated total drive current level value is to be set to 2.5A (i.e., 1.5A + 1.0A), and written into a two-dimensional lookup table to complete the closed-loop update.

[0066] Cycle Two (Cross-cycle closed-loop iteration takes effect): Upon entering a new cycle, the digital control module directly calls the updated 2.5A total drive current level value for driving, and simultaneously calculates a new pre-trigger reference voltage to match the gate-source voltage ramp-up slope under the current operating conditions. After continuous cross-cycle iterative corrections, the measured time difference parameter converges to 80ns. Even with changes in the load and the junction temperature of the driven power devices, the system maintains stable turn-on characteristics through the aforementioned closed-loop mechanism.

[0067] Combined with appendix Figure 3 Experimental verification and effect analysis: To verify the effectiveness of the technical solution of the present invention, the gate drive control method of the present invention (adaptive step drive method, in a steady state after parameter convergence) was tested and compared with the traditional fixed drive method on the same hardware platform.

[0068] See attached document Figure 3 , Figure 3 This reflects the internal transient physical processes of the driven power device at the beginning of the PWM cycle: The horizontal axis represents time (ns), which represents the physical time elapsed from the moment the PWM turn-on pulse is generated; The vertical axis represents the gate-source voltage. (V) reflects the charge accumulation state of the internal Miller capacitance and the degree of opening of the conductive channel of the driven power device.

[0069] Combined with appendix Figure 3 The waveform characteristics are analyzed in detail below: Traditional fixed drive method waveform (corresponding) Figure 3 (dotted lines in the middle) Rise process: In the 0 to 120 ns stage, due to the use of fixed gate resistor drive, the current injection capability is limited, which results in a long time required for the gate source voltage to reach and cross the Miller plateau (it takes about 120 ns to leave the Miller plateau).

[0070] Voltage overshoot and oscillation: After the gate-source voltage crosses the Miller plateau (after 120 ns), due to the lack of delay pre-compensation and cutoff mechanisms in conventional methods, the hardware delay causes excess charge to be continuously injected into the gate. This phenomenon causes a voltage spike of up to 15V (i.e., an overshoot of 5.0V compared to the steady state of 10V), accompanied by continuous high-frequency damped oscillations, increasing the risk of electromagnetic interference to the system.

[0071] Waveforms of the drive control system of this invention (corresponding) Figure 3 (solid line in the middle) Initial ramp-up phase (0-30ns): Corresponds to step S10 of this invention. The system selects the corresponding push-pull output branch and injects an initial large pulse current. The solid waveform rapidly rises to the Miller plateau of approximately 5V with a high slope, shortening the initial conduction delay.

[0072] Miller platform end reference node (corresponding to) Figure 3 (Vertical dashed line at 110 ns): This vertical dashed line is used to mark the reference time when the waveform of this invention breaks away from the Miller plateau. Subsequently, the gate-source voltage continues to rise, and the system generates a trigger based on the pre-triggered reference voltage after pre-compensation and adjustment, and the actual cutoff time falls on the target voltage point through propagation delay compensation.

[0073] Steady-state transition phase (after 110ns): Corresponds to step S30 of this invention. After crossing the cutoff determination point, the push-pull output branch is disconnected, and the system switches to the milliampere-level constant current output circuit to take over the driving task. The solid waveform smoothly transitions at approximately 130ns and maintains a steady-state high level of 10V, without voltage overshoot (overshoot amplitude of 0V) or high-frequency oscillation.

[0074] Key test data comparison statistics: Example Conclusion: Based on the above parameters, the deduction and appendix are as follows: Figure 3 As can be seen from the features and measured data, the gate drive control system of this invention, through slope coupling calculation of the pre-triggered reference voltage and cross-cycle iteration, ensures that the actual cutoff time of the large pulse current falls at the target voltage point. This mechanism reduces turn-on losses while avoiding gate voltage overshoot and high-frequency oscillations caused by physical delays, thus improving the steady-state maintenance of the driven power device.

Claims

1. A MOSFET gate drive control method, characterized in that, include: At the start of the PWM cycle, read the basic drive current gradient level, fine-tuning current compensation amount, and leading-edge blanking time window parameters from the two-dimensional lookup table. The push-pull output branch is turned on to inject an initial large pulse current into the gate of the driven power device, and outputs a pre-triggered reference voltage after pre-compensation and reduction to the second analog comparator. The total drive current level is obtained by adding the basic drive current gradient level to the fine-tuning current compensation amount. The ratio of the total drive current level to the nominal input capacitance of the driven power device is used to characterize the ramp-up slope of the gate-source voltage under the current operating condition. Based on the ramp-up slope and the known inherent physical propagation delay time of the system, the additional voltage rise during the inherent physical propagation delay time is calculated. The reference voltage setting value when the driven power device ideally leaves the Miller plateau under the target operating condition is shifted downward by the additional voltage rise value in advance to obtain the pre-triggered reference voltage after pre-compensation and reduction. When the gate-source voltage reaches the turn-on threshold voltage reference of the first analog comparator, the first analog comparator outputs a toggle signal. The toggle signal triggers the high-resolution timer unit to accumulate the count and activates the leading-edge blanking time window to shield the input of the second analog comparator. When the set timing period of the leading edge blanking time window is reached, the shielding of the second analog comparator is removed and the signal listening of the second analog comparator is restored; When the gate-source voltage breaks away from the Miller plateau and touches the pre-triggered reference voltage after pre-compensation and reduction, the second analog comparator outputs a valid toggle signal, the high-resolution timer unit stops timing and latches the time difference parameter. The time difference parameter is the physical time span obtained by the high-resolution timer unit from the start of accumulating time from the output flip signal of the first analog comparator to the stop of timekeeping from the output of the valid flip signal of the second analog comparator. Capture a valid flip signal to generate a hardware truncation instruction to disconnect the push-pull output branch and simultaneously turn on the milliampere-level constant current output circuit. The time difference parameter is compared with the operating time threshold to determine the basic drive current gradient level to be allocated in the next PWM cycle. The fine-tuning current compensation amount for the next cycle is corrected based on the difference between the time difference parameter and the preset ideal reference time. The result is written into a two-dimensional lookup table to complete the cross-cycle closed-loop iterative control for use in the next PWM cycle.

2. The MOSFET gate drive control method according to claim 1, characterized in that, The pre-triggered reference voltage, after pre-compensation and reduction, is always higher than the actual Miller plateau voltage of the driven power device within the normal operating parameter range.

3. The MOSFET gate drive control method according to claim 2, characterized in that, The reference voltage setting value for the ideal disconnection of the driven power device from the Miller plateau under the target operating condition is set to a value higher than the actual Miller plateau voltage of the driven power device.

4. The MOSFET gate drive control method according to claim 1, characterized in that, The steps for activating the leading edge blanking time window and masking the input of the second analog comparator include: At the same physical moment when the first analog comparator outputs a toggle signal, the leading edge blanking time window is activated. During the duration of the leading edge blanking time window, any level transition signal output by the second analog comparator is forcibly ignored, thus blocking the interrupt input channel of the second analog comparator. The length of the leading edge blanking time window is set according to the size of the system parasitic inductance and the oscillation decay period estimated by the driving current gradient, so as to cover the high-frequency oscillation decay period without blocking the subsequent real voltage signal. When the set timing period of the leading edge blanking time window is reached, the shielding of the second analog comparator is released and signal monitoring of the interrupt channel is resumed.

5. The MOSFET gate drive control method according to claim 1, characterized in that, The steps to trigger the high-resolution timer unit to accumulate timing include: The flip-level signal output by the first analog comparator is directly transmitted to the digital control and arithmetic module as the start trigger source for the high-resolution timer unit. After receiving the trigger signal, the high-frequency clock counter register inside the high-resolution timer unit begins to perform accumulation operation.

6. The MOSFET gate drive control method according to claim 1, characterized in that, The steps for synchronously turning on the milliampere-level constant current output circuit include: While the push-pull output branch is turned off, the milliampere-level constant current output circuit of the control bypass is turned on, continuously injecting a small DC current into the gate of the driven power device.

7. The MOSFET gate drive control method according to claim 1, characterized in that, The steps for determining the basic drive current gradient level to be allocated in the next PWM cycle include: The time difference parameter is compared with the preset heavy load time threshold and light load time threshold. If the time difference parameter is greater than the overload time threshold, it is determined that the system is currently under overload or high junction temperature conditions, and the basic drive current gradient level to be allocated in the next PWM cycle is set to 3A. If the time difference parameter is less than or equal to the light load time threshold, the system is determined to be in a light load normal operating condition, and the basic drive current gradient level for the next cycle is set to 1.5A.

8. A MOSFET gate drive control method according to claim 7, characterized in that, The heavy load time threshold is numerically greater than the light load time threshold, and a hysteresis interval is formed between the two. When the value of the time difference parameter is within the hysteresis interval, the basic drive current gradient level of the previous cycle remains unchanged.

9. A MOSFET gate drive control method according to claim 1, characterized in that, The steps for adjusting the fine-tuning current compensation amount for the next cycle include: Perform discrete iterative fine-tuning calculations to calculate the difference between the time difference parameter and the preset ideal reference time. Multiply the difference by the set discrete proportional compensation coefficient and add it to the fine-tuning current compensation amount actually output in the current PWM cycle to obtain the fine-tuning current compensation amount to be added in the next PWM cycle. The specific value of the discrete proportional compensation coefficient is determined by the closed-loop control bandwidth set by the system, so as to ensure the convergence of the iterative process and prevent system oscillation. When the basic drive current gradient level switches across levels, the current fine-tuning current compensation is reset to zero.

10. A MOSFET gate drive control method according to claim 1, characterized in that, The steps for completing cross-cycle closed-loop iterative control by writing data into a two-dimensional lookup table include: The updated base drive current gradient level, the associated matching leading-edge blanking time window parameters, and the calculated fine-tuning current compensation for the next cycle are written into the corresponding address space of the two-dimensional lookup table via the internal digital bus. The newly written data directly overwrites the historical records of the previous cycle. When the next PWM switching cycle arrives, the updated parameters in the two-dimensional lookup table are called for configuration and driving.

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