Packet ordering method and network card

Abstract

The application relates to the technical field of data communication, and discloses a message sequence preserving method and a network card, the network card is preconfigured with a bitmap, the bits in the bitmap correspond to message sequence numbers one by one and are used for identifying whether the payloads of the corresponding messages have been successfully written into a target device. The method applied to the network card comprises the following steps: receiving a message, setting a bit Bn corresponding to the message sequence number Pn in the bitmap; if the message is an acknowledgement message, the acknowledgement message is cached and a write completion confirmation operation is not executed temporarily; if the acknowledgement message has been cached after the bit is set, it is judged whether the bit corresponding to the sequence number of the cached acknowledgement message and all the bits before the bit are all set; if yes, the write completion confirmation operation is executed and the cache is cleared. The application preserves the sequence through a hardware bitmap, ensures that the acknowledgement message is executed only after all the previous data is written into the target device, and avoids data integrity errors caused by out-of-order transmission.

Description

Technical Field

[0001] This application relates to the field of data communication technology, and in particular to a message ordering method and a network interface card (NIC). Background Technology

[0002] In high-speed network transmission scenarios, especially in scenarios such as Packet Spray where data fragments are transmitted concurrently through multiple paths, the receiving network card may receive data packets and acknowledgment packets out of order.

[0003] Acknowledgment messages are used to indicate to the target device that all preceding payloads have been transmitted. However, due to out-of-order arrival of packets, acknowledgment messages may arrive at the receiving end before some data packets. If the network interface card (NIC) executes the acknowledgment message immediately upon receiving it, the receiving application may mistakenly believe that all data has been transmitted and read incomplete data, resulting in data integrity errors.

[0004] In existing technologies, message reordering is typically performed using software protocol stacks or by employing order-preserving delivery mechanisms. However, software involvement increases processing overhead and latency, failing to meet the demands of high-bandwidth, low-latency scenarios.

[0005] Therefore, how to avoid the above-mentioned misjudgments in out-of-order transmission scenarios, while reducing processing overhead and latency, is a technical problem that urgently needs to be solved. Summary of the Invention

[0006] This application provides a message ordering method and a network interface card (NIC). By using hardware bitmap ordering, it ensures that confirmation messages are only executed after all preceding data has been written to the target device, thus avoiding data integrity errors caused by out-of-order transmission.

[0007] Firstly, one embodiment of this application provides a message order preservation method applied to a network interface card (NIC) at a receiving end. The NIC has a pre-configured bitmap, where bits in the bitmap are pre-established to have a one-to-one correspondence with message sequence numbers, used to identify whether the payload of the message corresponding to the sequence number has been successfully written to the target device. The method includes: Upon receiving a message, set bit Bn in the bitmap corresponding to the sequence number Pn of the message; If the message is an acknowledgment message, the acknowledgment message is cached and the write completion acknowledgment operation is not performed temporarily; wherein, the acknowledgment message is used to trigger the network card to perform the write completion acknowledgment operation that the payload has been stored in the target device; After setting bit Bn, if an acknowledgment message has been cached, it is determined whether the bit corresponding to the sequence number of the cached acknowledgment message and all previous bits have been set. If the determination result is yes, then the write completion confirmation operation is performed, and the cached confirmation message is cleared.

[0008] Optionally, the confirmation message carries a write completion identifier to be written to the target device; The execution of the write completion confirmation operation specifically includes: The write completion identifier carried in the confirmation message is written to the flag memory of the target device to notify the target device that all payloads with serial numbers less than the serial number of the confirmation message have been written to the target device.

[0009] Optionally, the method further includes: After performing the write completion confirmation operation, the bit corresponding to the sequence number of the cached confirmation message in the bitmap and all previous bits are reset.

[0010] Optionally, the network interface card also maintains a start valid bit, which is used to indicate the starting position to be checked in the bitmap; The method further includes: When one or more consecutive bits are set in the bitmap starting from the bit corresponding to the start valid bit, these consecutive set bits are treated as a continuous set segment, and the start valid bit is updated to the next bit after the continuous set segment. The step of determining whether all bits preceding the sequence number of the cached acknowledgment message are set specifically includes: Determine whether all bits from the bit corresponding to the current start valid bit to the bit corresponding to the sequence number of the cached acknowledgment message are set.

[0011] Optionally, the method is executed by hardware logic circuitry within the network card.

[0012] Secondly, one embodiment of this application provides a network interface card (NIC), comprising: Bitmap storage unit is used to store bitmaps. The bits in the bitmaps are pre-established to have a one-to-one correspondence with the message sequence number, which is used to identify whether the payload of the message corresponding to the sequence number has been successfully written to the target device. The message receiving unit is used to receive messages; Bitmap setting unit, used to set bit Bn in the bitmap corresponding to the sequence number Pn of the message; A confirmation message caching unit is used to cache the confirmation message when the message is a confirmation message, and temporarily not perform the write completion confirmation operation; wherein, the confirmation message is used to trigger the network card to perform the write completion confirmation operation that the payload has been stored in the target device; The sequence-preserving judgment unit is used to determine whether the bit corresponding to the sequence number of the cached acknowledgment message and all previous bits have been set after setting the bit Bn, if a cached acknowledgment message has been cached. The confirmation execution unit is used to execute the write completion confirmation operation and clear the cached confirmation message when the judgment result is yes.

[0013] The message ordering method and network interface card (NIC) provided in this application record message status through a hardware bitmap. Early-arriving acknowledgment messages are buffered and delayed. The write completion acknowledgment operation corresponding to the acknowledgment message is only executed when the bitmap meets the ordering conditions. This ensures that all preceding data of the acknowledgment message has been written to the target device before it is executed, avoiding data errors caused by out-of-order delivery. This solution is naturally adapted to multi-path concurrent transmission, does not require the receiving end to receive messages in order, reduces the ordering requirements of the sending end and the transmission path, and improves transmission bandwidth utilization. The message ordering method is automatically completed by the hardware logic within the NIC, without software intervention, avoiding the scheduling overhead and context switching latency of the software protocol stack. Attached Figure Description

[0014] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1 This is a flowchart illustrating a message order preservation method provided in an embodiment of this application. Detailed Implementation

[0016] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, a detailed description is provided below in conjunction with the accompanying drawings and specific implementation methods. Although the embodiments of this application provide method operation steps as shown in the following embodiments or drawings, the method may include more or fewer operation steps based on conventional or non-inventive effort. For steps that do not logically have a necessary causal relationship, the execution order of these steps is not limited to the execution order provided in the embodiments of this application. Unless otherwise specified, the embodiments and features in the embodiments of this application can be arbitrarily combined with each other.

[0017] For ease of understanding, the terms used in the embodiments of this application are explained below: Bitmap: A data structure consisting of multiple bits, each bit corresponding to a message sequence number, used to identify whether the payload corresponding to that sequence number has been successfully written to the target device. For example, a bit of 1 indicates that it has been written, and a bit of 0 indicates that it has not been written; the reverse is also true.

[0018] Set: This refers to setting a specified bit in the bitmap to a valid state (e.g., logic "1"), indicating that the payload for the corresponding sequence number has been successfully written to the target device. Conversely, reset: This refers to restoring the bit to its initial state (e.g., logic "0").

[0019] Payload: refers to the data content in a message that needs to be written to the target device, excluding control information such as the message header.

[0020] Packet Sequence Number (PSN): A unique identifier for a packet, used to determine its order within the transport stream. In this application, "packet sequence number" is simply referred to as "sequence number," which typically starts from a starting sequence number (e.g., 1) and increments sequentially.

[0021] Starting sequence number: This refers to the sequence number of the first packet in the current transmission session. In most embodiments, the starting sequence number is 1. In scenarios that support bitmap reset or segmented transmission, the starting sequence number can be the starting sequence number of the current session.

[0022] Acknowledgment message: Used to trigger the network interface card (NIC) to perform a write completion acknowledgment operation confirming that the payload has been stored in the target device. The acknowledgment message itself does not carry "data written" status information, but rather serves as a trigger signal, which the NIC executes the corresponding acknowledgment operation when the conditions are met.

[0023] Write completion confirmation operation: This refers to the operation performed by the network interface card (NIC) after confirming that the payloads of all preceding data packets have been written to the target device. It is used to notify the target device (or the application running on the target device) that the data is ready. Specific implementations of this operation may include, but are not limited to: writing the confirmation value to the flag memory, sending an interrupt, or updating the doorbell register.

[0024] Target device: refers to the final destination to which the payload is written, such as GPU memory, CPU memory, or other storage devices.

[0025] Flag memory: This refers to a specific memory address on the target device used to store acknowledgment values ​​or write completion flags. Applications running on the target device determine whether data transmission has been completed by polling the value in this flag memory.

[0026] Start valid bit: refers to the bit corresponding to the starting position to be checked in the bitmap. The initial value of the start valid bit is the start sequence number, which moves forward as consecutive set segments are confirmed, thus narrowing down the range of subsequent judgments.

[0027] Continuous set segment: refers to an interval in which multiple consecutive bits are set, starting from the start valid bit. This interval indicates that the payload corresponding to the sequence number has been continuously written to the target device.

[0028] The proposed solution is implemented in a computer system containing the following components: (1) Network card: It is an intelligent network card with hardware logic control capabilities, used to receive and process network packets, and can maintain hardware bitmaps, perform order-keeping judgment, cache acknowledgment packets, and perform write completion acknowledgment operation when the conditions are met.

[0029] (2) Target device: Storage or computing device coupled to the network card via a high-speed bus, including but not limited to GPU (graphics processing unit), FPGA (field programmable gate array), NPU (neural network processor) or SSD (solid-state drive).

[0030] The network interface card (NIC) is coupled to the target device via a high-speed bus. The NIC and the target device can be connected via switching equipment (such as PCIe switches, CXL switches, etc.) to support point-to-point (P2P) transmission, or directly connected via a bus root node, or coupled via other high-speed bus interfaces. The high-speed bus includes, but is not limited to, PCIe, CXL, or NVLink.

[0031] The proposed solution can be applied to scenarios such as distributed AI training, high-performance computing, data center storage, and edge computing, and is especially suitable for out-of-order transmission environments that require highly reliable data transmission and time-series deterministic guarantees.

[0032] refer to Figure 1 This application provides a message order preservation method applied to a network interface card (NIC) at a receiving end, specifically including the following steps: S101. Receive the message and set the bit Bn corresponding to the sequence number Pn of the message in the bitmap.

[0033] In practice, the network interface card (NIC) receives packets from the sender, each packet carrying a sequence number Pn. The sequence number increments sequentially according to the order in which the packets are sent. For example, the first packet sent by the sender has a sequence number of 1, the second 2, and so on, with the Nth packet having a sequence number of N. The sequence number identifies the order of packets in the transmission stream, and the receiving NIC uses the sequence number to determine the order of the packets. However, because packets may be transmitted concurrently through multiple paths (i.e., packet spread), the transmission delays of each path differ, and the NIC may not receive packets in order. For example, the sender may send packets in the order of sequence numbers 1, 2, 3, 4, 5, but the NIC may receive sequence number 1 first, then sequence number 4, then sequence number 2, and so on; out-of-order packet arrival is a common phenomenon.

[0034] In this application, a transmission session contains a series of messages with consecutive sequence numbers, typically starting from a first sequence number (e.g., 1) and incrementing. After a session ends, the bitmap can be reset to begin a new session.

[0035] The network interface card (NIC) receives both data packets and acknowledgment packets. Whether the NIC receives a data packet or an acknowledgment packet, the bitmap setting operation in step S101 will be triggered.

[0036] In addition to carrying a sequence number, the data packet also carries a payload that needs to be written to the target device. For a data packet, the network interface card (NIC) initiates a DMA write operation to write the payload to the target device, and after confirming the completion of the DMA write operation, executes the setting operation in step S101; alternatively, the NIC performs the setting operation simultaneously with the completion of the DMA write operation. This ensures that when the bit in the bitmap is set, the corresponding payload has been reliably written to the target device. If the setting operation is performed before the completion of the DMA write operation, the bitmap state may be inconsistent with the actual write state, affecting the accuracy of the order-keeping judgment. After the setting is completed, the corresponding bit in the bitmap is 1, indicating that the data packet has been received and its payload has been successfully written to the target device.

[0037] The acknowledgment message does not carry the payload to be written to the target device; instead, it triggers the network interface card (NIC) to perform a write completion acknowledgment operation. The purpose of the acknowledgment message is to act as a trigger signal, notifying the NIC to perform the corresponding acknowledgment operation when conditions are met. The acknowledgment message itself does not carry "previous data has been written" status information; this status is determined by the NIC itself using a bitmap.

[0038] The network interface card (NIC) is pre-configured with a bitmap, which can be stored in the NIC's internal on-chip memory (such as SRAM or a register array). Each bit in this bitmap has a pre-established one-to-one correspondence with a packet sequence number, used to identify whether the payload of the packet corresponding to the sequence number has been successfully written to the target device. Initially, all bits in the bitmap are 0, indicating that no packets have been received and there are no buffered acknowledgment packets in the NIC.

[0039] Each time the network interface card (NIC) receives a packet, it parses the packet, identifies the packet type, extracts the sequence number Pn, and then calculates the corresponding bit index in the bitmap based on Pn, setting the bit Bn corresponding to that index to 1. This bit-setting operation is automatically completed by the NIC hardware logic without software intervention. This bit-setting operation can be completed within a single clock cycle and does not affect the data path throughput.

[0040] If the message type is identified as an acknowledgment message, then step S102 is executed; if it is a data message, then step S102 is skipped and the judgment logic of step S103 is continued.

[0041] It should be noted that the above-mentioned setting operation is independent of the operation of writing the payload to the target device. For data packets, the network interface card (NIC) performs the setting operation in step S101 simultaneously or after initiating a DMA write operation to write the payload to the target device, indicating that the data packet has been received and its payload has been written to the target device. For acknowledgment packets, the acknowledgment packet itself does not carry the payload that needs to be written to the target device; the NIC only performs the setting operation in step S101 to indicate that the acknowledgment packet has been received.

[0042] S102. If the message is an acknowledgment message, then the acknowledgment message is cached and the write completion acknowledgment operation is not performed for the time being.

[0043] In practice, the network card is equipped with an acknowledgment message buffer unit (such as a register or FIFO) to temporarily store acknowledgment messages.

[0044] Unlike existing technologies where confirmation messages are executed immediately upon receipt, in this application, the network interface card (NIC) does not immediately execute the write completion confirmation operation after receiving the confirmation message. Specifically, the NIC only buffers the confirmation message and does not trigger the write completion confirmation operation. The execution of the confirmation message is delayed, waiting for subsequent order-preserving conditions to be met (see step S103 for details).

[0045] It should be noted that there is no dependency between the setting operation in step S101 and the caching operation in step S102. Therefore, the two can be executed in parallel, or the setting operation can be executed before the caching operation.

[0046] S103. After setting bit Bn, if an acknowledgment message has been cached, determine whether the bit corresponding to the sequence number of the cached acknowledgment message and all previous bits have been set.

[0047] The network interface card (NIC) obtains the sequence number of the cached acknowledgment packet, denoted as Pc. Then, the NIC checks whether all bits from the bit corresponding to the starting sequence number to the bit corresponding to Pc are set. For example, if the sequence number Pc of the cached acknowledgment packet is 5, it checks whether bits 1, 2, 3, 4, and 5 are all 1; if all are 1, it means that the acknowledgment packet and all preceding data packets have been received, the order preservation condition is met, and step S104 is triggered; if not all are 1, it means that there are still preceding packets that have not arrived or have not been written, the order preservation condition is not met, the NIC does not perform any operation, and waits for subsequent packets to arrive before triggering the order preservation judgment in step S103 again.

[0048] Of course, when performing the order preservation judgment operation, it is also possible not to check the bits corresponding to the sequence number Pc, for example, only to check whether bits 1 to 4 are all 1. Since the acknowledgment message itself will also trigger the setting operation of S101, the Pc bit has already been set to 1 when the order preservation judgment is triggered. Therefore, this implementation is equivalent to the judgment including the Pc bit in terms of result, and also falls within the protection scope of this application. Regardless of which judgment method is used, as long as the bits corresponding to the preceding message (sequence number less than Pc) are all 1, the order preservation condition can be considered to be satisfied.

[0049] In some optional implementations, the order preservation judgment in step S103 can be implemented by a hardware comparator (or AND gate array), which can output the judgment result within a single clock cycle, meeting the line-speed processing requirements.

[0050] S104. If the judgment result is yes, then perform the write completion confirmation operation and clear the cached confirmation message.

[0051] The network card performs a write completion confirmation operation, which is used to confirm to the target device that the payloads of all packets with sequence numbers less than the confirmation message sequence number have been successfully written to the target device.

[0052] After completing the write completion confirmation operation, the network card clears the cached confirmation message. Specifically, this includes deleting the relevant information of the confirmation message (such as sequence number, confirmation value, operand, or write completion identifier) ​​from the confirmation message cache unit to prevent the same confirmation message from being executed repeatedly. At the same time, it releases the storage resources occupied by the confirmation message cache unit so that subsequent confirmation messages can be cached.

[0053] If there are other cached acknowledgment messages in the acknowledgment message buffer unit, the network card will perform a pre-order check on the next acknowledgment message when it arrives.

[0054] In some alternative implementations, the write completion confirmation operation in step S104 is performed by the hardware DMA write engine without the need for host software intervention, further reducing latency.

[0055] Assume the sender sends message sequence numbers 1, 2, 3, 4, and 5 sequentially, with message 5 being an acknowledgment message. Due to multipath transmission methods such as PacketSpray, the receiving network card may receive the messages out of order, for example, in the following sequence: message 1 → message 2 → message 5 → message 3 → message 4.

[0056] Step 1: Upon receiving message 1 (sequence number Pn=1), set bit 1 in the bitmap, changing the bitmap state to 10000. Message 1 is not an acknowledgment message, so no buffering operation is performed. Since there are no buffered acknowledgment messages, no ordering check or write completion acknowledgment operation is performed.

[0057] Step 2: Upon receiving message 2 (sequence number Pn=2), set bit 2 in the bitmap, changing the bitmap state to 11000. Message 2 is not an acknowledgment message, so no buffering operation is performed. Since there are no buffered acknowledgment messages, no ordering check is performed, and no write completion acknowledgment operation is executed.

[0058] Step 3: Upon receiving message 5 (sequence number Pn=5, acknowledgment message), set bit 5 in the bitmap, changing the bitmap state to 11001. Message 5 is an acknowledgment message; buffer it and do not execute the write completion acknowledgment operation yet. The currently buffered acknowledgment message (sequence number = 5) is checked to see if the bit corresponding to its sequence number (bit 5) and all previous bits (bits 1, 2, 3, 4) are set. Bits 3 and 4 are not yet set (both are 0), the result is negative (i.e., the order preservation condition is not met), and the write completion acknowledgment operation is not executed.

[0059] Step 4: Upon receiving message 3 (sequence number Pn=3), set bit 3 in the bitmap, changing the bitmap state to 11101. Message 3 is not an acknowledgment message, so no buffering operation is performed. An acknowledgment message (sequence number=5) has already been buffered. Check if the bit corresponding to its sequence number (bit 5) and all previous bits (bits 1, 2, 3, 4) are set. Bit 4 is not yet set (it is 0). The result is negative (i.e., the order preservation condition is not met), and no write completion acknowledgment operation is performed.

[0060] Step 5: Upon receiving message 4 (sequence number Pn=4), set bit 4 in the bitmap, changing the bitmap state to 11111. Message 4 is not an acknowledgment message, so no buffering operation is performed. The currently buffered acknowledgment message (sequence number 5) is checked. It is determined whether bit 5 and all preceding bits (bits 1, 2, 3, and 4) are set. If the result is yes (i.e., the order-keeping condition is met), a write completion acknowledgment operation is performed to notify the target device (e.g., the computing kernel running on the GPU) that the payloads in all data packets with sequence numbers less than this acknowledgment message's sequence number have been successfully written to the target device. Simultaneously, the buffered acknowledgment message (message 5) is cleared.

[0061] As shown in the example above, although acknowledgment message 5 arrives at the network interface card (NIC) before messages 3 and 4, the write completion acknowledgment operation is not executed immediately. The NIC buffers acknowledgment message 5 and executes the write completion acknowledgment operation only after messages 3 and 4 arrive and are written to the target device. This ensures that when the write completion acknowledgment operation is executed, all previous payloads have been successfully written to the target device, avoiding data integrity errors.

[0062] The message ordering method provided in this application uses a hardware bitmap to record the writing status of data packets and the receiving status of acknowledgment packets. Specifically, for data packets, the bitmap is set after the payload is successfully written to the target device; for acknowledgment packets, the bitmap is set after the packet is received, indicating that the acknowledgment packet has been received. The network card buffers the acknowledgment packets and delays execution, only performing the write completion acknowledgment operation when the bitmap meets the ordering condition (i.e., the bit corresponding to the acknowledgment packet sequence number and all bits before it are set). This ensures that when the write completion acknowledgment operation is executed, the payloads of all data packets preceding the acknowledgment packet have been successfully written to the target device, avoiding application misjudgments and data integrity errors caused by out-of-order packet arrival.

[0063] The message ordering method provided in this application is naturally adapted to multi-path concurrent transmission scenarios such as Packet Spray. Regardless of the order in which messages arrive, the network card can accurately record the status of each message through a bitmap and trigger the execution of a write completion acknowledgment operation when the ordering condition is met. This method does not require the receiving end to receive messages in order, reducing the ordering requirements of the sending end and the transmission path, and improving the utilization of transmission bandwidth.

[0064] Furthermore, the message ordering method provided in this application embodiment is automatically completed by the hardware logic within the network card, without the need for software intervention, thus avoiding the scheduling overhead and context switching delay of the software protocol stack.

[0065] In one embodiment, the acknowledgment message can be an atomic operation message. An atomic operation message carries the operation type (e.g., addition, bitwise OR, comparison swap, etc.) and operands, used to perform an atomic update on the flag memory in the target device.

[0066] The specific processing flow is as follows: After receiving the atomic operation message, the network interface card (NIC) extracts the sequence number Pn, operation type, and operands, and caches this data in the NIC's acknowledgment message buffer unit. The atomic operation is not executed immediately, and the bit corresponding to the sequence number Pn in the bitmap is set. When the bitmap meets the order-preserving condition, the execution of the atomic operation is triggered: The NIC reads the current acknowledgment value from the target device's flag memory via a DMA read operation; based on the operation type and operands cached in the acknowledgment message buffer unit, the NIC performs an atomic operation on the read acknowledgment value (e.g., adding the acknowledgment value to the operands, or performing a bitwise OR operation between the acknowledgment value and the operands), calculating a new acknowledgment value; the NIC writes the new acknowledgment value back to the target device's flag memory via a DMA write operation, notifying the target device that all payloads with sequence numbers less than the acknowledgment message sequence number have been written to the target device.

[0067] For example, the sending end needs to increment the flag memory value of the target device by 5. The sending end sends an atomic operation message, carrying the operation type "ADD" and the operand 5. After the order-keeping condition is met, the network card reads the current value (e.g., 0) from the flag memory, calculates 0+5=5, and then writes 5 back to the flag memory. The application running on the target device polls the flag memory and eventually reads 5, indicating that the previous data has been written.

[0068] The above atomic operation schemes are all automatically completed by the network card hardware logic.

[0069] The above atomic operation scheme requires at least two DMA transfers (one read and one write) and involves computational logic. While it can guarantee data integrity, it consumes network card hardware resources and increases processing latency in high-bandwidth scenarios.

[0070] To further reduce processing overhead and hardware resource consumption, this application also provides another confirmation message implementation method—Strict Order Write (SOW) message. Unlike the atomic operation messages mentioned above, the SOW message does not carry the operation type and operands, but directly carries the write completion identifier (final value) of the target device's flag memory to be written. It does not require DMA read operations and calculations, and confirmation can be completed with only a single DMA write operation.

[0071] The SOW message is a custom acknowledgment message defined in this application, carrying a write completion flag to be written to the target device's flag memory. Unlike atomic operation messages, which require a "read-compute-write" process at the receiving end, the write completion flag in the SOW message is pre-calculated by the sending end and directly carried in the message. The sending end can use computational logic similar to atomic operations (e.g., accumulation, bitwise OR, etc.) to generate the write completion flag (i.e., the acknowledgment value in the aforementioned embodiments), or it can directly use a predefined conventional value (e.g., 1, 0, or a specific constant). After receiving the SOW message, the receiving end network card, when the order-keeping condition is met, only needs to write the write completion flag to the target device's flag memory through a single DMA write operation to notify the application running on the target device that "the payloads in all data packets preceding this acknowledgment message have been successfully written to the target device."

[0072] After the write completion flag is written to the target device's flag memory, the application running on the target device can poll the value of this flag memory to determine whether the data transmission is complete. When the application reads the write completion flag (e.g., a value of 1), it can confirm that the payloads of all data packets with sequence numbers less than the SOW message sequence number have been successfully written to the target device, thus allowing for subsequent processing.

[0073] The identification, caching, order preservation judgment, and DMA write operation of the aforementioned SOW messages are all automatically completed by the network card hardware logic without the need for software intervention. Only one DMA transfer is required to complete the confirmation, which significantly reduces processing latency.

[0074] This embodiment simplifies the acknowledgment operation into a single DMA write by introducing the SOW message, avoiding the "read-compute-write" process required by atomic operation messages, significantly reducing network card hardware overhead and processing latency, and is particularly suitable for high-bandwidth, low-latency transmission scenarios (such as distributed AI training, GPU Direct communication, etc.).

[0075] Based on any of the above embodiments, this embodiment further includes a bitmap reset operation to release bitmap resources, which facilitates the order-keeping determination of subsequent messages.

[0076] After performing the write completion confirmation operation and clearing the cached confirmation packets in step S104, the network interface card (NIC) resets the processed bits in the bitmap. The reset range is from the bit corresponding to the starting sequence number to the bit corresponding to the sequence number of the cached confirmation packet.

[0077] Assuming the sequence number of the cached acknowledgment message is Pc, then reset bits 1, 2, ..., (Pc-1), and Pc. For example, if Pc=5, then reset bits 1, 2, 3, 4, and 5.

[0078] In practice, the network interface card (NIC) internally sets up bitmap reset logic. When the reset condition is triggered, the following operations are performed: the range of bits to be reset is calculated based on the serial number Pc; a write operation is performed on each bit in the bitmap that falls within the aforementioned range, setting it to 0 (i.e., returning to the initial state). The reset operation can be performed bit by bit or in batches (e.g., clearing by word or byte). The reset operation is automatically completed by the hardware logic without software intervention.

[0079] After the reset, the processed bits in the bitmap (including the bits corresponding to the acknowledgment message) are cleared to zero. For subsequent messages in the same transmission session (e.g., sequence numbers 6, 7, 8, etc.), their corresponding bits have not yet been set and can be used normally. For a new transmission session, a full bitmap reset is usually required during session initialization to ensure that all bits are in their initial state.

[0080] By resetting all processed bits, including the acknowledgment message itself, after the write completion confirmation operation, bitmap resources can be completely released, preventing any historical state from interfering with subsequent judgments and supporting the cyclic use of bitmaps and multiple rounds of continuous transmission. Furthermore, the reset operation is performed automatically by hardware, without increasing software overhead.

[0081] Based on the above embodiments, this embodiment further optimizes the starting position of the order-preserving judgment by maintaining a dynamic "starting valid bit" to reduce the bitmap range that needs to be checked in each judgment, thereby reducing hardware comparison overhead.

[0082] The network interface card (NIC) maintains a start valid bit (denoted as StartValidBit) to indicate the starting position of the current check in the bitmap. The initial value of the start valid bit is the start sequence number (usually 1), meaning that the check starts from bit 1 in the bitmap initially.

[0083] The start valid bit is a dynamic pointer that moves forward as messages are received continuously, used to "logically" clear consecutive set segments that have been processed.

[0084] After setting a bit in the bitmap each time (i.e., after executing step S101), the network interface card (NIC) first determines whether a write completion acknowledgment operation is needed: if an acknowledgment packet has already been cached, then the order-preserving judgment in step S103 is executed (using the current start valid bit). Then, the NIC checks if there are consecutive set bits in the bitmap starting from the bit corresponding to the current start valid bit. When it detects that one or more consecutive bits are set starting from the bit corresponding to the start valid bit, the NIC performs the following operations: treats these consecutive set bits as a whole, called a consecutive set segment; and updates the start valid bit to the next bit after this consecutive set segment.

[0085] For example, assuming the current starting valid bit is 1, and bits 1, 2, and 3 in the bitmap are all 1, and bit 4 is 0, then the consecutive bit segments are bit 1, bit 2, and bit 3, and the starting valid bit becomes 4 after the update.

[0086] In practice, the network interface card (NIC) internally includes a start valid bit register and consecutive set bit detection logic. After each set bit, the detection logic checks the consecutively set bits starting from the current start valid bit and updates the start valid bit register accordingly. This detection and update operation is completed by combinational logic within a single clock cycle, without affecting the critical path latency of the data path.

[0087] In this embodiment, the judgment logic of step S103 is replaced by: judging whether all bits between the bit corresponding to the current start valid bit and the bit corresponding to the sequence number of the cached acknowledgment message are set.

[0088] Since the starting valid bit has been moved to the end of the continuous set segment, the judgment range is greatly reduced compared to starting from a fixed starting sequence number, which reduces the number of bits that need to be checked and lowers hardware overhead.

[0089] For example, the sender sends message sequence numbers 1, 2, 3, 4, and 5 in sequence, where message 5 is an acknowledgment message. The out-of-order arrival order of the messages is: message 1 → message 2 → message 5 → message 4 → message 3.

[0090] The initial state is: start valid bit = 1, bitmap is 00000.

[0091] Step 1: Upon receiving message 1, first set bit 1, and update the bitmap to 10000. At this time, there are no buffered acknowledgment messages, so no order-keeping check is performed. Then, check the continuous set segment: starting from the first valid bit (bit 1), bit 1=1, the continuous set segment is bit 1, and update the first valid bit to 2.

[0092] Step 2: Upon receiving message 2, set bit 2 and update the bitmap to 11000. At this point, there are no buffered acknowledgment messages, so no order-keeping check is performed. Then, check the consecutive set segments: starting from the first valid bit (bit 2), bit 2 = 1, the consecutive set segments are bit 2, and update the first valid bit to 3.

[0093] Step 3: Upon receiving message 5 (acknowledgment message), set bit 5, update the bitmap to 11001, and buffer acknowledgment message 5. First, perform a sequence-preserving check: starting from the first valid bit (bit 3) to bit 5, where bit 3=0, bit 4=0, and bit 5=1, not all bits are 1, the sequence-preserving condition is not met, and the write completion acknowledgment operation is not performed. Then, check for consecutive set segments: starting from the first valid bit (bit 3), bit 3=0, there is no consecutive set segment, and the first valid bit remains at 3.

[0094] Step 4: Upon receiving message 4, set bit 4, and update the bitmap to 11011. First, perform a sequence preservation check: starting from the first valid bit (bit 3) to bit 5, where bit 3=0, bit 4=1, and bit 5=1, not all bits are 1, thus the sequence preservation condition is not met. Then, check for consecutive set segments: starting from the first valid bit (bit 3), bit 3=0, there is no consecutive set segment, and the first valid bit remains at 3.

[0095] Step 5: Upon receiving message 3, set bit 3, updating the bitmap to 11111. First, perform a sequence preservation check: starting from the first valid bit (bit 3) up to bit 5, all bits are 1, satisfying the sequence preservation condition. After confirming that the sequence preservation condition is met, perform the write completion acknowledgment operation, clearing the buffered acknowledgment message 5. After performing the sequence preservation check, update the first valid bit: check that starting from the first valid bit (bit 3), bits 3, 4, and 5 are all 1, and set the consecutive bit segments to bits 3, 4, and 5, updating the first valid bit to 6.

[0096] It should be noted that the start valid bit is the starting point of a sliding window, and its movement depends only on the detection of consecutive set segments in the bitmap, and is unrelated to the execution of acknowledgment messages. For example, after receiving messages 1 and 2, the start valid bit can move from 1 to bit 3, and subsequent order-preserving checks start from bit 3. Bits 1 and 2 are no longer involved in the check, naturally narrowing the scope of the judgment. For subsequent messages sent within the same session (e.g., sequence numbers 6, 7, and 8), the start valid bit remains at 6, and the judgment scope starts from bit 6.

[0097] If a new session begins (i.e., the message sequence number starts again from 1), since the historical bits in the bitmap may still be 1, the bitmap needs to be cleared and the starting valid bits reset to 1 first; otherwise, the historical state will interfere with the judgment of the new session.

[0098] This embodiment introduces a dynamic start valid bit, narrowing the inspection range for order preservation judgment from a fixed starting point to a dynamic one. As consecutive packets are received, the number of bits that need to be checked gradually decreases, significantly reducing hardware overhead. Furthermore, this scheme only requires moving the start valid bit pointer to clear the logic, without modifying the bitmap itself, further reducing hardware resource consumption. This scheme is particularly suitable for long-session, high-throughput transmission scenarios.

[0099] In practice, the size of the acknowledgment message buffer unit can be configured as needed, for example, to support caching one or more acknowledgment messages.

[0100] In one optional embodiment, the acknowledgment packet caching unit only supports caching one acknowledgment packet at a time. When a new acknowledgment packet arrives and the cache is already occupied, the network interface card (NIC) can directly discard the new packet, which will then be retransmitted by the sender through a timeout retransmission mechanism. Alternatively, the application layer or upper-layer protocol can ensure that only one acknowledgment packet is sent at any given time, thereby avoiding packet loss.

[0101] In another alternative embodiment, the acknowledgment message caching unit supports caching multiple acknowledgment messages.

[0102] In this embodiment, the acknowledgment message buffer unit in the network interface card (NIC) can be implemented using a FIFO (First-In-First-Out) or multi-entry register group. Each entry stores the sequence number of an acknowledgment message and related information (e.g., the write completion identifier of a SOW message, the operation type and operands of an atomic operation message). The depth of the acknowledgment message buffer unit can be configured according to application requirements, for example, supporting the buffering of 2, 4 or more acknowledgment messages.

[0103] Each acknowledgment message can independently notify the data segment corresponding to its own sequence number. For example, acknowledgment message A (sequence number 5) notifies the data segment with sequence numbers 1 to 5, and acknowledgment message B (sequence number 10) notifies the data segment with sequence numbers 6 to 10. Multiple acknowledgment messages do not interfere with each other. The specific notification range can be determined by the sender based on application requirements.

[0104] In embodiments that support caching multiple acknowledgment messages, a logical zeroing scheme (i.e., maintaining the start valid bit) is adopted, and the order of judgment is first maintained, followed by updating the start valid bit. Because logical zeroing only moves the start valid bit and does not modify the bit values ​​in the bitmap, it will not interfere with the judgment of other cached acknowledgment messages.

[0105] For example, the buffer contains acknowledgment message A (sequence number 5) and acknowledgment message B (sequence number 10). When messages 1 through 5 arrive consecutively, the network card first checks the order of acknowledgment message A (at this point, the start valid bit has not yet moved, for example, it is still 1). If the order condition is met, acknowledgment message A is executed and cleared; then, based on the consecutive set segments (bits 1 through 5), the start valid bit is moved to bit 6. Acknowledgment message B continues to wait for subsequent messages to arrive, and the two do not interfere with each other.

[0106] If a physical reset of the bitmap is required, it is recommended not to perform it immediately after each acknowledgment message is executed, but rather to perform it at the following times: when the current transmission session ends, reset the entire bitmap at once; or when the start valid bits exceed the bitmap range, reset the bitmap and remap the sequence number; or when the upper-layer software actively triggers the reset based on the session state.

[0107] In embodiments that support caching multiple acknowledgment messages, a sequential checking method can be used, strictly adhering to the order of first preserving the sequence number and then updating the start valid bit. After each bitmap setting, the network interface card (NIC) first checks the acknowledgment message with the smallest sequence number in the cache, determining if all bits from the current start valid bit to the bit corresponding to the sequence number of that acknowledgment message are 1. If so, the acknowledgment message is executed and the cache is cleared, then this step is repeated (continuing to check for the new smallest message). If not, the NIC updates the start valid bit (detecting consecutive set segments and shifting the start valid bit), and then checks the current smallest acknowledgment message again; if the condition is still not met, it waits for the next bitmap setting.

[0108] In this embodiment, the sender can continuously send multiple acknowledgment messages without waiting for the completion response of the previous acknowledgment message. The sender should ensure that the sequence number of the acknowledgment message maintains a globally increasing order with the sequence number of the data message so that the receiver can correctly determine the order preservation condition. When multiple acknowledgment messages correspond to the same flag memory address, the sender needs to pay attention to the semantics of the final value: the value written by the later executed acknowledgment message will overwrite the value written by the earlier executed acknowledgment message. If it is necessary to retain multiple acknowledgment results, the sender should allocate a different flag memory address for each acknowledgment message, or coordinate through an upper-layer protocol.

[0109] Supporting multiple acknowledgment message caching improves the sender's flexibility, allowing batch sending of acknowledgment messages and reducing the number of round-trip interactions. This is suitable for transmission scenarios requiring multiple synchronization points or segmented acknowledgments (such as segmented file transfers and multi-level pipeline synchronization). Combined with a logical zeroing scheme, it avoids conflicts caused by physical resets, ensuring the correct execution of multiple acknowledgment messages.

[0110] Based on the same inventive concept, this application also provides a network card. Since the principle of this network card in solving the problem is similar to that of a message order preservation method, the implementation of this network card can refer to the implementation of the method, and the repeated parts will not be described again.

[0111] In some implementations, the network interface card provided in this application includes: Bitmap storage unit is used to store bitmaps. The bits in the bitmaps are pre-established to have a one-to-one correspondence with the message sequence number, which is used to identify whether the payload of the message corresponding to the sequence number has been successfully written to the target device. The message receiving unit is used to receive messages; Bitmap setting unit, used to set bit Bn in the bitmap corresponding to the sequence number Pn of the message; A confirmation message caching unit is used to cache the confirmation message when the message is a confirmation message, and temporarily not perform the write completion confirmation operation; wherein, the confirmation message is used to trigger the network card to perform the write completion confirmation operation that the payload has been stored in the target device; The sequence-preserving judgment unit is used to determine whether the bit corresponding to the sequence number of the cached acknowledgment message and all previous bits have been set after setting the bit Bn, if a cached acknowledgment message has been cached. The confirmation execution unit is used to execute the write completion confirmation operation and clear the cached confirmation message when the judgment result is yes.

[0112] In some optional embodiments, the confirmation message carries a write completion identifier to be written to the target device; the confirmation execution unit is specifically used to: write the write completion identifier carried in the confirmation message into the flag memory of the target device, so as to notify the target device that all payloads with serial numbers less than the serial number of the confirmation message have been written to the target device.

[0113] In some alternative embodiments, the network interface card (NIC) further includes: The bitmap reset unit is used to reset the bit corresponding to the sequence number of the cached confirmation message in the bitmap and all previous bits after the write completion confirmation operation is performed.

[0114] In some alternative embodiments, the network interface card (NIC) further includes: A start valid bit maintenance unit is used to maintain a start valid bit, which is used to indicate the starting position to be checked in the bitmap. A continuous set segment detection unit is used to, when one or more consecutive bits are set in the bitmap starting from the bit corresponding to the start valid bit, take these consecutive set bits as a continuous set segment and update the start valid bit to the next bit after the continuous set segment; The sequence preservation judgment unit is specifically used to: determine whether all bits from the bit corresponding to the current start valid bit to the bit corresponding to the sequence number of the cached acknowledgment message are set.

[0115] In some optional embodiments, the bitmap storage unit, message receiving unit, acknowledgment message buffering unit, order preservation judgment unit, and acknowledgment execution unit are all implemented by hardware logic circuits.

[0116] The network card provided in this application embodiment adopts the same inventive concept as the above-mentioned message order preservation method and can achieve the same beneficial effects, which will not be repeated here.

[0117] The above embodiments are only used to provide a detailed description of the technical solutions of this application. However, the description of the above embodiments is only for the purpose of helping to understand the methods of the embodiments of this application and should not be construed as a limitation on the embodiments of this application. Any changes or substitutions that can be easily conceived by those skilled in the art should be covered within the protection scope of the embodiments of this application.

Claims

1. A message order preservation method, characterized in that, A network interface card (NIC) used at the receiving end, wherein the NIC is pre-configured with a bitmap, and a one-to-one correspondence is pre-established between the bits in the bitmap and the packet sequence number, used to identify whether the payload of the packet corresponding to the sequence number has been successfully written to the target device; the method includes: Upon receiving a message, set bit Bn in the bitmap corresponding to the sequence number Pn of the message; If the message is an acknowledgment message, the acknowledgment message is cached and the write completion acknowledgment operation is not performed temporarily; wherein, the acknowledgment message is used to trigger the network card to perform the write completion acknowledgment operation that the payload has been stored in the target device; After setting bit Bn, if an acknowledgment message has been cached, it is determined whether the bit corresponding to the sequence number of the cached acknowledgment message and all previous bits have been set. If the determination result is yes, then the write completion confirmation operation is performed, and the cached confirmation message is cleared.

2. The method according to claim 1, characterized in that, The confirmation message carries a write completion identifier to be written to the target device; The execution of the write completion confirmation operation specifically includes: The write completion identifier carried in the confirmation message is written to the flag memory of the target device to notify the target device that all payloads with serial numbers less than the serial number of the confirmation message have been written to the target device.

3. The method according to claim 1, characterized in that, The method further includes: After performing the write completion confirmation operation, the bit corresponding to the sequence number of the cached confirmation message in the bitmap and all previous bits are reset.

4. The method according to any one of claims 1 to 3, characterized in that, The network interface card also maintains a start valid bit, which is used to indicate the starting position to be checked in the bitmap; The method further includes: When one or more consecutive bits are set in the bitmap starting from the bit corresponding to the start valid bit, these consecutive set bits are treated as a continuous set segment, and the start valid bit is updated to the next bit after the continuous set segment. The step of determining whether all bits preceding the sequence number of the cached acknowledgment message are set specifically includes: Determine whether all bits from the bit corresponding to the current start valid bit to the bit corresponding to the sequence number of the cached acknowledgment message are set.

5. The method according to claim 1, characterized in that, The method is executed by the hardware logic circuitry within the network card.

6. A network interface card (NIC), characterized in that, include: Bitmap storage unit is used to store bitmaps. The bits in the bitmaps are pre-established to have a one-to-one correspondence with the message sequence number, which is used to identify whether the payload of the message corresponding to the sequence number has been successfully written to the target device. The message receiving unit is used to receive messages; Bitmap setting unit, used to set bit Bn in the bitmap corresponding to the sequence number Pn of the message; A confirmation message caching unit is used to cache the confirmation message when the message is a confirmation message, and temporarily not perform the write completion confirmation operation; wherein, the confirmation message is used to trigger the network card to perform the write completion confirmation operation that the payload has been stored in the target device; The sequence-preserving judgment unit is used to determine whether the bit corresponding to the sequence number of the cached acknowledgment message and all previous bits have been set after setting the bit Bn, if a cached acknowledgment message has been cached. The confirmation execution unit is used to perform the write completion confirmation operation and clear the cached confirmation message when the judgment result is yes.

7. The network interface card according to claim 6, characterized in that, The confirmation message carries a write completion identifier to be written to the target device; the confirmation execution unit is specifically used to: write the write completion identifier carried in the confirmation message into the flag memory of the target device, so as to notify the target device that all payloads with serial numbers less than the serial number of the confirmation message have been written to the target device.

8. The network interface card according to claim 6, characterized in that, The network interface card also includes: The bitmap reset unit is used to reset the bit corresponding to the sequence number of the cached confirmation message in the bitmap and all previous bits after the write completion confirmation operation is performed.

9. The network interface card according to any one of claims 6 to 8, characterized in that, The network interface card also includes: A start valid bit maintenance unit is used to maintain a start valid bit, which is used to indicate the starting position to be checked in the bitmap. A continuous set segment detection unit is used to, when one or more consecutive bits are set in the bitmap starting from the bit corresponding to the start valid bit, take these consecutive set bits as a continuous set segment and update the start valid bit to the next bit after the continuous set segment; The sequence preservation judgment unit is specifically used to: determine whether all bits from the bit corresponding to the current start valid bit to the bit corresponding to the sequence number of the cached acknowledgment message are set.

10. The network interface card according to claim 6, characterized in that, The bitmap storage unit, message receiving unit, acknowledgment message buffering unit, order preservation judgment unit, and acknowledgment execution unit are all implemented by hardware logic circuits.

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