Link training method and system, electronic equipment and storage medium

Abstract

The invention discloses a link training method and system, electronic equipment and a storage medium, and relates to the field of data processing. The method comprises the following steps: acquiring a plurality of stable intervals of a differential link based on a fixed delay step length and a training code; calculating the ratio of each stable interval to the unit interval of the differential link; selecting a stable interval of which the ratio is an odd number after rounding up as an effective interval; and delaying the clock signal or the differential signal based on the delay amount corresponding to the central point of any effective interval so as to realize data alignment. On the basis of the processing, the effective interval with the ratio being an odd number after rounding up is selected, the stable interval with the center point not being the jump area is screened out, and therefore in the subsequent data alignment process according to the center point of the effective interval, the error that the collection edge of the clock signal is located in the jump area can be avoided.

Description

Technical Field

[0001] This invention belongs to the field of data processing, and particularly relates to a link training method, system, electronic device, and storage medium. Background Technology

[0002] A differential link that uses differential signals for data transmission has the following actual waveform: Figure 1 As shown, there are stable and transition regions within a clock cycle. For differential links that use external clock signals for triggering sampling (such as LVDS, Low Voltage Differential Signaling), due to factors such as trace delay and process deviation, there may be a phase deviation (also known as clock offset) between the data channel and the clock channel at the receiving end of the differential link.

[0003] When phase deviation causes the sampling edge of the clock signal to fall within the transition region of the differential signal, errors in the acquired data are highly likely. During data transmission in a differential link, the sampling point of the clock signal must fall within the stable region of the transmitted data.

[0004] To correct phase deviation in the differential link, a stable time window is obtained during power-on by delay scanning. Simultaneously, to improve the anti-interference capability of the aligned differential link, the sampling edge of the clock signal is often aligned to the center point of the stable time window to achieve data alignment between the clock signal and the differential link. The stable time window, also known as the stable interval, represents the delay time range within which the receiver of the differential link can receive a constant latch value. The latch value is obtained by the receiver sampling the input data (including the training code) using the sampling edge of the clock signal. However, during the training process of the existing link, when the delay step used to adjust the delay time exceeds the transition region, there is a situation where the transition region cannot be detected during the delay scan (i.e., there is a transition region in the stable time window). This causes the sampling edge of the clock signal to be aligned to the center of the stable time window, but instead aligned to the transition region of the differential link, resulting in errors in the data alignment result.

[0005] Therefore, a link training method is urgently needed to solve the above problems. Summary of the Invention

[0006] This application proposes a link training method, system, electronic device, and storage medium to avoid errors in data alignment results when the delay step exceeds the transition region of the differential link and the data is aligned to the center of the stable time window.

[0007] To achieve the above objectives, this application proposes the following technical solutions: In a first aspect of this application, a link training method is provided, applied to the data alignment process of a differential link under a single data channel, comprising: Based on a fixed delay step and training code, several stable intervals of the differential link are obtained; wherein, the stable interval represents the delay time range in which the receiver of the differential link can receive a constant latch value; the latch value is obtained by the receiver sampling the training code using a clock signal; Calculate the ratio between each stable interval and the unit interval of the differential link; Select the stable intervals where the ratio becomes an odd number after being rounded up as the effective intervals; Based on the delay amount corresponding to the center point of any valid interval, the clock signal or differential signal is delayed to achieve data alignment.

[0008] Optionally, if a stable interval of the differential link is obtained based on a fixed delay step size and training code, the link training method further includes: Calculate the ratio between the stable interval and the unit interval of the differential link; Determine whether the ratio, after being rounded up, is an odd number; if so, delay the clock signal or differential signal based on the delay amount corresponding to the center point of the stable interval; if not, re-acquire the stable interval of the differential link.

[0009] Optionally, after calculating the ratio between the stable interval and the unit interval of the differential link, the link training method further includes: Determine whether the integer part of the ratio is even; if so, delay the clock signal or differential signal based on the delay amount corresponding to the center point of the stable interval; if not, re-acquire the stable interval of the differential link; wherein, the even number includes 0.

[0010] Optionally, after calculating the ratio between each stable interval and the unit interval of the differential link, the link training method further includes: The stable interval in which the ratio is rounded up to 1 is selected as the optimal interval. Based on the delay amount corresponding to the center point of any optimal interval, the clock signal or differential signal is delayed to achieve data alignment.

[0011] Optionally, if the differential link includes multiple data channels, then after obtaining the optimal interval for each data channel in the differential link, the link training method further includes: Obtain the intersection interval of the optimal intervals corresponding to all data channels; Based on the delay amount corresponding to the center point of the intersection interval, the clock signal is delayed to achieve data alignment of any data channel in the differential link.

[0012] Optionally, based on a fixed delay step size and training code, several stable intervals of the differential link are obtained, including: Based on a fixed delay step, the clock signals in the differential link are delayed sequentially, and the preset training code is input to the differential link at different delay step sizes; sequential delay means that the delay amount is increased in units of delay step size according to the signal input order. After each delay, the training code is sampled multiple times at the receiving end of the differential link using the sampling edge of the clock signal to obtain multiple latch values; wherein the sampling edge is the upper edge or the lower edge of the clock signal. Determine whether the multiple latch values ​​are consistent; if yes, set the current delay step size to the first delay time; if no, indicate that the current delay step size is the second delay time. Several delay time ranges formed by consecutive first delay times are obtained as several stable intervals of the differential link.

[0013] Optionally, based on a fixed delay step size and training code, several stable intervals of the differential link are obtained, including: Based on a fixed delay step size, the training code input to the differential link is sequentially delayed using a delay chain; wherein, the delay time corresponding to each delay unit in the delay chain is the same; the delay time corresponding to one delay unit is one delay step size; After each delay, the training code is sampled multiple times at the receiving end of the differential link using the sampling edge of the clock signal to obtain multiple latch values. Determine whether the multiple latch values ​​are consistent; if yes, set the current delay step size to the first delay time; if no, indicate that the current delay step size is the second delay time. Several delay time ranges formed by consecutive first delay times are obtained as several stable intervals of the differential link.

[0014] In a second aspect of this application, a link training system is provided for data alignment in a differential link under a single data channel, comprising: The interval acquisition module is used to acquire several stable intervals of the differential link based on a fixed delay step size and training code; wherein, the stable interval represents the delay time range in which the receiver of the differential link can receive a constant latch value; the latch value is obtained by the receiver sampling the training code using a clock signal; The ratio calculation module is used to calculate the ratio between each stable interval and the unit interval of the differential link; The interval selection module is used to select a stable interval where the ratio, after being rounded up, is an odd number, as the effective interval; The data alignment module is used to achieve data alignment based on the delay amount corresponding to the center point of any valid interval, delaying the clock signal or the differential signal.

[0015] In a third aspect of this application, an electronic device is provided, including a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other through the communication bus. Memory, used to store computer programs; When a processor executes a program stored in memory, it implements the link training method described in any of the first aspects.

[0016] In a fourth aspect of this application, a computer-readable storage medium is provided, wherein a computer program is stored therein, and when executed by a processor, the computer program implements the link training method described in any of the first aspects.

[0017] The beneficial effects of this application are as follows: This application provides a link training method applied to the data alignment process of differential links under a single data channel, including: Based on a fixed delay step size and training code, several stable intervals of the differential link are obtained; wherein, a stable interval represents the delay time range within which the receiver of the differential link can receive a constant latch value; the latch value is obtained by the receiver sampling the training code using a clock signal; the ratio between each stable interval and the unit interval of the differential link is calculated; a stable interval whose ratio is rounded up to an odd number is selected as an effective interval; based on the delay amount corresponding to the center point of any effective interval, the clock signal or differential signal is delayed to achieve data alignment.

[0018] Based on the above processing, in the link training method provided in this application, for the case where the delay step exceeds the transition region, considering the characteristic that when the stable interval contains an even number of transition regions, the center point of the stable interval does not belong to the transition region, the ratio between the stable interval and the unit interval is calculated based on the obtained stable interval. By selecting the effective intervals whose ratio is odd after rounding up, the stable intervals whose center point is not a transition region are filtered out. Thus, in the subsequent data alignment process based on the center point of the effective interval, the error of the clock signal acquisition edge being in the transition region can be avoided. Attached Figure Description

[0019] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this application, illustrate exemplary embodiments of the invention and, together with their description, serve to explain the invention and do not constitute an undue limitation thereof. In the drawings: Figure 1 This is a schematic diagram of a differential link provided in this application; Figure 2 This is a schematic diagram of data sampling for a differential link provided in this application; Figure 3 This is a schematic diagram of data sampling of a differential link under different delay times provided in this application; Figure 4 This is another data sampling diagram of a differential link provided in this application under different delay times; Figure 5 This is a flowchart illustrating a link training method provided in this application; Figure 6 This is a flowchart illustrating another link training method provided in this application; Figure 7 This is a flowchart illustrating a link training method with multiple data channels provided in this application; Figure 8 This is a structural diagram of a link training system provided in this application; Figure 9 This is a structural diagram of an electronic device provided in this application. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some embodiments of this application, but not all embodiments.

[0021] The voltage change process on the two lines transmitting a differential signal requires a certain amount of time, resulting in voltage change regions at both ends and a constant voltage region in the middle within one cycle of the differential signal. These are respectively considered the transition region and the stable region. Figure 1 As shown. Accordingly, by utilizing the rising or falling edge of the clock signal, the signal receiver can stably acquire logic "1" and logic "0" states from the constant voltage region.

[0022] In the field of machine vision, most image sensors employ differential links for high-speed data transmission, with data and clock signals transmitted through separate channels. Due to factors such as trace delays and manufacturing process variations, phase skew may exist between different data and clock channels at the receiving end of the differential link (i.e., a phase deviation exists between them). This causes the sampling edge of the clock signal to fall within the transition region of the differential signal in the differential link, leading to a risk of bit errors in data latching. The differential link provided in this application refers to a communication link based on differential signals for data transmission, such as LVDS.

[0023] Before performing effective data latching, the receiver of a differential link typically needs to align the differential link skew of the data channel to avoid the sampling edge of the clock signal being in the transition region of the differential signal in the differential link. This is known as link training.

[0024] A common link training method involves inputting a fixed training pattern into the differential link. The receiving end (e.g., FPGA) adjusts the idelay of the link channel or clock channel and determines whether the data is stable. The delay time window after the delay scan to obtain a stable latch value is used as the stable interval. Finally, considering that changes in factors such as temperature and voltage can cause the stable time window to shift, the delay time of the differential link or clock signal needs to be fixed at the center of the aforementioned stable interval. This improves the anti-interference capability of the trained differential link while obtaining a constant latch value.

[0025] With the continuous development of signal transmission technology, the transition region width of differential links in existing signal transmission systems is relatively narrow (i.e., the data transition time is shorter). The delay time setting at the differential link receiver has certain precision limitations; that is, there is a minimum delay step size for adjusting the delay time. For example... Figure 2 As shown, during the link training process, there are cases where the delay step exceeds the transition region.

[0026] When the delay step used to adjust the delay time exceeds the transition region, there may be a problem where the transition region cannot be scanned during the steady-state time window scanning process. This results in the transition region being included in the steady-state interval scanned using the delay time. Figure 3 , Figure 4 As shown.

[0027] Specifically, Figure 3 This belongs to the link training method through the delay differential link. delay=1 indicates that the current delay is 1 delay step. The data corresponds to the differential link. bit0, bit1 and bit2 correspond to the numbers of the corresponding bits in the training code. The latch result represents the judgment result under the current delay. In the latch result, 1 corresponds to the flag when a constant sample value can be obtained based on the clock signal under the current delay time (i.e., the sampling edge falls in the stable region of the differential link). 0 corresponds to the flag when the data cannot be stably sampled based on the clock signal under the current delay time (i.e., the sampling edge falls in the transition region of the differential link).

[0028] Figure 4 This belongs to the link training method using delayed clock signals. The arrows correspond to the sampling edges of the clock signals at different delay times, and the stable time window is a time window composed of multiple delay times under which stable data can be sampled.

[0029] Therefore, under the aforementioned circumstances, when aligned to the center of the data stability window, the sampling edge of the clock signal is very likely to be in the transition region, causing the differential link training to fail and the data alignment result to be incorrect.

[0030] To avoid the aforementioned errors, this application provides a link training method for use in the data alignment process of differential links, such as... Figure 5 As shown, the method includes the following steps: S1. Based on a fixed delay step size and training code, obtain several stable intervals of the differential link. A stable interval represents the delay time range within which the receiver of the differential link can receive a constant latch value; the latch value is obtained by the receiver sampling the training code using a clock signal.

[0031] S2. Calculate the ratio between each stable interval and the unit interval of the differential link.

[0032] S3. Select the stable interval where the ratio is odd after being rounded up as the effective interval.

[0033] S4. Based on the delay amount corresponding to the center point of any valid interval, delay the clock signal or differential signal to achieve data alignment.

[0034] Based on the above processing, in the link training method provided in this application, for the case where the delay step exceeds the transition region, considering the characteristic that when the stable interval contains an even number of transition regions, the center point of the stable interval does not belong to the transition region, the ratio between the stable interval and the unit interval is calculated based on the obtained stable interval. By selecting the effective intervals whose ratio is odd after rounding up, the stable intervals whose center point is not a transition region are filtered out. Thus, in the subsequent data alignment process based on the center point of the effective interval, the error of the clock signal acquisition edge being in the transition region can be avoided.

[0035] For step S1, the stable interval can be obtained by delaying the clock signal, including the following: S101. Based on a fixed delay step size, the clock signals in the differential link are sequentially delayed, and the preset training code is input from the input terminal of the differential link to the differential link at different delay step sizes. Here, sequential delay means that the delay amount is increased in units of delay step size according to the signal input order.

[0036] S102. After each delay, the training code is sampled multiple times at the receiving end of the differential link using the sampling edge of the clock signal to obtain multiple latch values; wherein, the sampling edge is the upper edge or the lower edge of the clock signal. S103. Determine whether the multiple latch values ​​are consistent; if yes, set the current delay step size to the first delay time; if no, indicate that the current delay step size is the second delay time. S104. Obtain several delay time ranges formed by consecutive first delay times, as several stable intervals of the differential link.

[0037] In this application, different delay times are obtained by successively increasing a fixed delay step size; that is, the delay time in this application can be understood as the delay step size. Regarding step S101, after the clock signal is successively delayed, the position of the sampling edge of the clock signal relative to the differential link changes, such as... Figure 2 As shown, the sampling edges of the clock signal are sequentially delayed by a fixed delay step.

[0038] In this application, the training code is a multi-bit binary value. For example, with 12 bits, the training code could be 101110101101; with 4 bits, the training code could be 1010. In step S101, after each delay of the clock signal, the preset training code is input into the differential link. The training codes input for different delay step sizes can be the same or different. For step S1, this application uses the training code to detect whether the sampling edge of the clock signal is within the stable region of the differential link under different delay step sizes, thereby obtaining the stable range. Therefore, there is no need to limit the specific value of the training code.

[0039] For step S102, the sampling edges of the clock signal in this application include either a rising edge or a falling edge. For example... Figure 2 As shown, the sampling edge is the rising edge of the clock signal.

[0040] Taking the training code 101110101101 as an example, with different delay times composed of a fixed delay step, when the delay step is 0, the training code is input from the differential link input terminal. Then, at the differential link receiving terminal, the training code is sampled multiple times based on the clock signal to obtain multiple latch values ​​corresponding to the training code. The number of latch values ​​only needs to be higher than a preset threshold, which can be 1000 or 2000; the specific number is not limited in this application. It should be noted that, according to the basic concepts of differential link transmission, the clock signal is sampled only once within a unit interval, obtaining only one bit of the digit. Correspondingly, in the process of obtaining 2000 12-bit latch values ​​at the receiving terminal, the sampling edge of the clock signal is triggered 24000 times.

[0041] Next, in step S103, it is determined whether the aforementioned multiple latch values ​​are consistent. If they are, it means that the clock signal can be stably sampled under the current delay time, the sampling edge is in the stable region, and the current delay step size is the first delay time. If not, it means that the clock signal cannot be stably sampled, the sampling edge is in the transition region, and the current delay step size is the second delay time.

[0042] Finally, in step S104, an interval consisting of consecutive first delay times (i.e., the delay time range) is obtained as the stable interval. In practice, 0 and 1 are usually used to distinguish whether the latch value is stable under different delay times. For example, when the latch result is 0, it indicates that the latch value is unstable under the current delay time, and the sampling edge of the clock signal is in the transition region, corresponding to the second delay time; when the latch result is 1, it indicates that the latch value is constant under the current delay time, and the sampling edge is in the stable region, corresponding to the first delay time. Figure 3 As shown. In Figure 4 In the scenario shown, the latch result corresponds to "011111111110", and the delay time range consisting of consecutive 1s corresponds to the stable interval of this application.

[0043] In some embodiments, a stable range can be obtained by delaying differential links. For the aforementioned steps S101-S104, step S101 can be replaced by the following step S105, while the remaining steps remain unchanged.

[0044] S105. Based on a fixed delay step size, the training code input to the differential link is sequentially delayed using a delay chain. Each delay unit within the delay chain corresponds to the same delay time; the delay time corresponding to one delay unit is considered as one delay step size.

[0045] For step S105, the training code input from the differential link input is delayed using a tapped delay chain method. The delay time of the differential link is controlled by controlling the number of delay units the training code passes through. The tapped delay chain method can be found in the paper "Research on TDC Algorithm Based on FPGA". The process of delaying the differential link in step S105 is as follows: Figure 3 As shown. Furthermore, the training code or clock signal can also be delayed using a PLL (phase-locked loop) method in this application.

[0046] In step S2, the unit interval represents the time required to transmit one bit of data, corresponding to the clock cycle of one bit time during differential link transmission, or equivalent to the horizontal width of a single eye diagram. The unit interval of a differential link is usually calculated by the reciprocal of the differential link transmission rate. For example, for a differential link with a transmission rate of 8Gbps, the corresponding unit interval is 125ps. In step S2, the ratio of the duration of each stable interval to the unit interval is calculated.

[0047] For step S3, stable intervals whose ratios, after being rounded up, result in an odd number are selected as valid intervals. For example, if the duration of a stable interval is less than one unit interval, then the ratio is a positive number less than 1, which, after being rounded up, results in an integer of 1, and thus belongs to the valid interval. Figure 4 As shown, if the duration of a stable interval exceeds one unit interval but is less than two unit intervals, then the ratio, after being rounded up, is an even number and therefore does not belong to the effective interval.

[0048] like Figure 4 In the differential link shown, when the duration of a stable interval contains an odd number of unit intervals (such as 1, 3, 5, etc.), the center point of the stable interval belongs to the transition region; when the duration of a stable interval contains an even number of unit intervals (such as 0, 2, 4, etc.), the center point of the stable interval belongs to the stable region. This corresponds to the method in step S3 of determining whether the value is odd by rounding up the ratio.

[0049] If multiple stable intervals of a single data channel in the differential link are obtained in step S1, and the number of valid intervals in subsequent step S3 is multiple, then the delay amount corresponding to the center point of any valid interval can be selected to delay the sampling edge of the clock signal or the transmission data of the differential link, so as to achieve data alignment between the differential signal and the clock signal in the differential link, and make the sampling edge of the clock signal in the stable region of the differential link.

[0050] For step S4, considering that the effective interval consists of continuous delay step sizes, the delay amount corresponding to the center point of the effective interval is the delay step size at the center of the continuous delay step sizes. Taking the continuous delay step size corresponding to the stable interval as "3-11", the delay amount corresponding to the center point is 7 delay steps. If the center point corresponds to two delay amounts, either one can be selected. Taking the continuous delay step size corresponding to the stable interval as "3-10" as an example, the delay amount corresponding to the center point can be 6 or 7 delay steps.

[0051] In the technical solution provided in this application, the longer the duration of the effective interval, the more transition regions it contains. In practice, to minimize the accidental risk of the clock signal sampling edge falling into the transition region in step S4, if there are multiple effective intervals, the center point of the effective interval with the shortest duration is usually selected to delay the clock signal or differential signal.

[0052] In some embodiments, if the number of stable intervals in step S1 is 1, then after step S1, such as Figure 6 As shown, the link training method provided in this application also includes the following: S5. Calculate the ratio between the stable interval and the unit interval of the differential link.

[0053] S6. Determine whether the ratio, after being rounded up, is an odd number. If yes, proceed to step S7. If no, proceed to step S1 to re-obtain the stable interval of the differential link.

[0054] S7. Based on the delay amount corresponding to the center point of the stable interval, delay the clock signal or differential signal to achieve data alignment.

[0055] For step S6, if the ratio of the duration of the stable interval to the unit interval is not odd after rounding up, it means that the center point of the stable interval is likely to be a transition region and cannot be used for data alignment. Step one needs to be executed again to obtain a new stable interval.

[0056] In some embodiments, step S6 can be replaced by step S8, specifically: S8. Determine whether the integer part of the ratio is even. If yes, proceed to step S7; otherwise, proceed to step S1 to re-obtain the stable interval of the differential link. Even numbers include 0.

[0057] like Figure 4 As shown, if the duration of the stable interval is less than the unit interval, it indicates that the stable interval does not contain a transition region. Therefore, after step S2, the technical solution provided by this application also includes the following: S9. Select the stable interval where the ratio is rounded up to 1 as the optimal interval. The optimal interval does not contain any transition regions within its corresponding delay time range.

[0058] S10. Based on the delay amount corresponding to the center point of any optimal interval, delay the clock signal or differential signal to achieve data alignment of the differential link.

[0059] Furthermore, the link training method provided in this application is applicable to data alignment of differential links under a single data channel. If there are multiple data channels in a differential link, after obtaining the delay amount corresponding to the center point of the effective interval of each data channel based on the link training scheme provided in this application, the delay amount of the clock signal can be kept unchanged, and the differential signal of each data channel can be delayed according to the delay amount corresponding to the center point in each data channel, thereby achieving data alignment under multiple data channels.

[0060] In some embodiments, if the differential link includes multiple data channels, such as Figure 7 As shown, the link training method provided in this application also includes the following: Step 1: Based on a fixed delay step size and training code, obtain several stable intervals within each data channel of the differential link.

[0061] Step 2: Calculate the ratio between each stable interval and the unit interval of the differential link.

[0062] Step 3: Select a stable interval within each data channel whose ratio, after being rounded up, equals 1. This stable interval is then considered the optimal interval. If an optimal interval does not exist for some data channels, proceed to Step 1 to re-obtain a stable interval for that data channel.

[0063] Step 4: Obtain the intersection interval of the optimal intervals corresponding to all data channels.

[0064] Step 5: Based on the delay amount corresponding to the center point of the intersection interval, delay the clock signal to achieve data alignment of any data channel in the differential link.

[0065] Based on the above processing, a common stable region for multiple data channels is found by intersecting the optimal intervals. By delaying the clock signal to the center point of this common stable region, data alignment under multiple data channels can be achieved.

[0066] In some embodiments, such as Figure 8 As shown, this application also provides a link training system applied to the data alignment process of differential links under a single data channel, including: The interval acquisition module 801 is used to acquire several stable intervals of any data channel in the differential link based on a fixed delay step size and training code; wherein, the stable interval represents the delay time range in which the receiver of the differential link can receive a constant latch value; the latch value is obtained by the receiver sampling the training code using a clock signal; The ratio calculation module 802 is used to calculate the ratio between each stable interval and the unit interval of the differential link; The interval selection module 803 is used to select a stable interval where the ratio is odd after being rounded up, as the effective interval; The data alignment module 804 is used to delay the clock signal or differential signal based on the delay amount corresponding to the center point of any valid interval, so as to achieve data alignment of the differential link.

[0067] This application also provides an electronic device, such as... Figure 9 As shown, it includes a processor 901, a communication interface 902, a memory 903, and a communication bus 904, wherein the processor 901, the communication interface 902, and the memory 903 communicate with each other through the communication bus 904. Memory 903 is used to store computer programs; The processor 901, when executing the program stored in the memory 903, implements any of the above-mentioned link training methods.

[0068] The communication bus mentioned in the above electronic devices can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. This communication bus can be divided into address bus, data bus, control bus, etc. For ease of illustration, only one thick line is used to represent it in the diagram, but this does not indicate that there is only one bus or one type of bus.

[0069] The communication interface is used for communication between the aforementioned electronic devices and other devices.

[0070] The memory may include random access memory (RAM) or non-volatile memory (NVM), such as at least one disk storage device. Optionally, the memory may also be at least one storage device located remotely from the aforementioned processor.

[0071] The processors mentioned above can be general-purpose processors, including central processing units (CPUs), network processors (NPs), etc.; they can also be digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0072] In another embodiment provided in this application, a computer-readable storage medium is also provided, which stores a computer program that, when executed by a processor, implements any of the above-described link training method steps.

[0073] In another embodiment provided in this application, a computer program product containing instructions is also provided, which, when run on a computer, causes the computer to execute any of the link training method steps in the above embodiments.

[0074] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A link training method, applied to the data alignment process of a differential link under a single data channel, characterized in that, include: Based on a fixed delay step and training code, several stable intervals of the differential link are obtained; wherein, the stable interval represents the delay time range in which the receiver of the differential link can receive a constant latch value; the latch value is obtained by the receiver sampling the training code using a clock signal; Calculate the ratio between each stable interval and the unit interval of the differential link; Select the stable intervals where the ratio becomes an odd number after being rounded up as the effective intervals; Based on the delay amount corresponding to the center point of any valid interval, the clock signal or differential signal is delayed to achieve data alignment.

2. The link training method according to claim 1, characterized in that, If a stable interval of the differential link is obtained based on a fixed delay step size and training code, then the link training method further includes: Calculate the ratio between the stable interval and the unit interval of the differential link; Determine whether the ratio, after being rounded up, is an odd number; if so, delay the clock signal or differential signal based on the delay amount corresponding to the center point of the stable interval; if not, re-acquire the stable interval of the differential link.

3. The link training method according to claim 2, characterized in that, After calculating the ratio between the stable interval and the unit interval of the differential link, the link training method further includes: Determine whether the integer part of the ratio is even; if so, delay the clock signal or differential signal based on the delay amount corresponding to the center point of the stable interval; if not, re-acquire the stable interval of the differential link; wherein, the even number includes 0.

4. The link training method according to claim 1, characterized in that, After calculating the ratio between each stable interval and the unit interval of the differential link, the link training method further includes: The stable interval in which the ratio is rounded up to 1 is selected as the optimal interval. Based on the delay amount corresponding to the center point of any optimal interval, the clock signal or differential signal is delayed to achieve data alignment.

5. The link training method according to claim 4, characterized in that, If the differential link includes multiple data channels, then after obtaining the optimal interval for each data channel in the differential link, the link training method further includes: Obtain the intersection interval of the optimal intervals corresponding to all data channels; Based on the delay amount corresponding to the center point of the intersection interval, the clock signal is delayed to achieve data alignment of any data channel in the differential link.

6. The link training method according to claim 1, characterized in that, Based on a fixed delay step size and training code, several stable intervals of the differential link are obtained, including: Based on a fixed delay step, the clock signals in the differential link are delayed sequentially, and the preset training code is input to the differential link at different delay step sizes; sequential delay means that the delay amount is increased in units of delay step size according to the signal input order. After each delay, the training code is sampled multiple times at the receiving end of the differential link using the sampling edge of the clock signal to obtain multiple latch values; wherein the sampling edge is the upper edge or the lower edge of the clock signal. Determine whether the multiple latch values ​​are consistent; if yes, set the current delay step size to the first delay time; if no, indicate that the current delay step size is the second delay time. Several delay time ranges formed by consecutive first delay times are obtained as several stable intervals of the differential link.

7. The link training method according to claim 1, characterized in that, Based on a fixed delay step size and training code, several stable intervals of the differential link are obtained, including: Based on a fixed delay step size, the training code input to the differential link is sequentially delayed using a delay chain; wherein, the delay time corresponding to each delay unit in the delay chain is the same; the delay time corresponding to one delay unit is one delay step size; After each delay, the training code is sampled multiple times at the receiving end of the differential link using the sampling edge of the clock signal to obtain multiple latch values. Determine whether the multiple latch values ​​are consistent; if yes, set the current delay step size to the first delay time; if no, indicate that the current delay step size is the second delay time. Several delay time ranges formed by consecutive first delay times are obtained as several stable intervals of the differential link.

8. A link training system, applied to the data alignment process of a differential link under a single data channel, characterized in that, include: The interval acquisition module is used to acquire several stable intervals of the differential link based on a fixed delay step size and training code; wherein, the stable interval represents the delay time range in which the receiver of the differential link can receive a constant latch value; the latch value is obtained by the receiver sampling the training code using a clock signal; The ratio calculation module is used to calculate the ratio between each stable interval and the unit interval of the differential link; The interval selection module is used to select a stable interval where the ratio, after being rounded up, is an odd number, as the effective interval; The data alignment module is used to achieve data alignment based on the delay amount corresponding to the center point of any valid interval, delaying the clock signal or the differential signal.

9. An electronic device, characterized in that, It includes a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other through the communication bus; Memory, used to store computer programs; A processor, when executing a program stored in memory, implements the link training method according to any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, A computer-readable storage medium stores a computer program that, when executed by a processor, implements the link training method according to any one of claims 1-7.

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