An igbt power gate drive circuit

Abstract

The application relates to an IGBT power gate drive circuit, and relates to the technical field of power integrated circuits.The IGBT power gate drive circuit comprises a gate control circuit, a detection circuit, a voltage feedback circuit and a band gap reference circuit;an input end of the detection circuit is connected with a collector of an IGBT;an output end of the detection circuit is connected with a first input end of the voltage feedback circuit;the gate of the IGBT is connected with a second input end of the voltage feedback circuit and an output end of the gate control circuit respectively;an output end of the band gap reference circuit is connected with the gate control circuit, the detection circuit and the voltage feedback circuit respectively; and an output end of the voltage feedback circuit is connected with a control end of the gate control circuit.The application realizes multi-gear dynamic output of a drive current and effectively adapts to the nonlinear change of a Miller capacitor.

Description

Technical Field

[0001] This invention relates to the field of power integrated circuit technology, and in particular to an IGBT power gate drive circuit. Background Technology

[0002] The power gate drive circuit is the core interface circuit connecting the low-voltage logic control unit and the high-voltage power switching device. Its driving performance directly determines the switching efficiency, electrical stress resistance, electromagnetic compatibility characteristics and system reliability of the power device.

[0003] Traditional power gate drivers often employ fixed gate resistor schemes, which cannot achieve independent decoupled control of the switching slope and struggle to balance switching losses and voltage / current overshoot. Furthermore, the nonlinear variation of the Miller capacitance of power devices can easily lead to drive current distortion and degraded switching stability, and drive performance is prone to drift under wide temperature, wide voltage, and variable load conditions. Existing open-loop active drivers lack adaptive capabilities, while closed-loop active drivers suffer from complex detection circuits, large loop delays, and high integration difficulty, making it difficult to meet the requirements of high integration, low loss, and wide-condition adaptive capabilities of monolithic integrated intelligent power driver chips. Summary of the Invention

[0004] This invention provides an IGBT power gate drive circuit to solve the problem of Miller capacitance nonlinearity affecting drive stability in existing power gate drive circuits.

[0005] This invention provides an IGBT power gate drive circuit, which includes a gate control circuit, a detection circuit, a voltage feedback circuit, and a bandgap reference circuit. The input terminal of the detection circuit is connected to the collector of the IGBT, and the output terminal of the detection circuit is connected to the first input terminal of the voltage feedback circuit. The gate of the IGBT is connected to the second input terminal of the voltage feedback circuit and the output terminal of the gate control circuit, respectively. The output terminal of the bandgap reference circuit is connected to the gate control circuit, the detection circuit, and the voltage feedback circuit, respectively. The output terminal of the voltage feedback circuit is connected to the control terminal of the gate control circuit.

[0006] A further technical solution is that the gate control circuit includes a current control unit, a current mirror bias unit, and a push-pull output drive unit. The input terminal of the current mirror bias unit is used to connect to the bias voltage, and the output terminal of the current mirror bias unit is connected to the input terminal of the current control unit. The control input terminal of the current control unit is used to receive control signals, and the output terminal of the current control unit is connected to the input terminal of the push-pull output drive unit. The output terminal of the push-pull output drive unit constitutes the output terminal of the gate control circuit.

[0007] A further technical solution is that the current mirror bias unit is used to provide two mirror bias currents; The current control unit is used to selectively turn on at least one of the two mirror bias currents according to the two control signals.

[0008] A further technical solution is that the voltage feedback circuit includes a multi-reference voltage comparison unit and a logic operation unit; The output of the multi-reference voltage comparison unit is connected to the input of the logic operation unit; The input terminals of the multi-reference voltage comparison unit constitute the first input terminal, the second input terminal, and the reference voltage input terminal of the voltage feedback circuit; The output terminal of the logic operation unit constitutes the output terminal of the voltage feedback circuit.

[0009] A further technical solution is that the multi-reference voltage comparison unit includes at least three comparators; The three comparators are respectively used to receive the detection signal, the gate voltage, and at least three reference voltages.

[0010] A further technical solution is that the detection circuit includes an RC differentiating unit and a signal amplification unit; The output of the RC differentiating unit is connected to the input of the signal amplifying unit; The input terminal of the RC differentiating unit constitutes the input terminal of the detection circuit; The bias terminal of the signal amplification unit constitutes the bias terminal of the detection circuit, and the output terminal of the signal amplification unit constitutes the output terminal of the detection circuit.

[0011] A further technical solution is that the RC differentiating unit is used to convert the voltage change of the IGBT collector into a transient voltage signal; The signal amplification unit is used to amplify the transient voltage signal and output a detection signal.

[0012] A further technical solution is that the bandgap reference circuit includes a bandgap reference unit and a voltage divider output unit; The output terminal of the bandgap reference unit is connected to the input terminal of the voltage divider output unit; The bias terminal of the bandgap reference unit constitutes the bias voltage output terminal of the bandgap reference circuit. The output terminal of the voltage divider output unit constitutes the reference voltage output terminal of the bandgap reference circuit.

[0013] A further technical solution is that the bandgap reference unit is used to output a reference current; The voltage divider output unit is used to convert the reference current into multiple reference voltages.

[0014] A further technical solution is that the gate control circuit is used to output multi-level drive current according to the first output signal and the second output signal of the logic operation unit.

[0015] The technical solutions provided in the embodiments of the present invention have the following advantages compared with the prior art: Through module collaboration and multi-stage adaptive adjustment, multi-level dynamic output of drive current can be achieved, effectively adapting to the nonlinear changes of Miller capacitance. It maintains stable drive performance under wide temperature, wide voltage, and variable load conditions. At the same time, it eliminates the need for complex high-voltage detection and feedback loops, resulting in a simplified circuit structure that is easy to integrate on a single chip. It can reduce switching losses while suppressing voltage and current overshoot, thereby improving the overall reliability and electromagnetic compatibility of the power device drive system. Attached Figure Description

[0016] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 A structural block diagram of an IGBT power gate drive circuit provided in an embodiment of the present invention; Figure 2 A schematic diagram of a gate control circuit provided in an embodiment of the present invention; Figure 3 A schematic diagram of a voltage feedback circuit provided in an embodiment of the present invention; Figure 4 The gate voltage V during the entire turn-on process provided in the embodiments of the present invention GE The first output signal Vina, the second output signal Vinb, and the gate current I G Waveform variation diagram; Figure 5 A schematic diagram of a detection circuit provided in an embodiment of the present invention; Figure 6A schematic diagram of a bandgap reference circuit provided in an embodiment of the present invention; Figure 7 This is a schematic flowchart of an IGBT power gate drive circuit provided in an embodiment of the present invention. Detailed Implementation

[0019] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Similar component reference numerals in the drawings represent similar components. Obviously, the embodiments described below are only some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0020] It should be understood that, when used in this specification and the appended claims, the terms "comprising" and "including" indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0021] It should also be understood that the terminology used in this specification of embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to limit the embodiments of the invention. As used in this specification of embodiments of the invention and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0022] Example See Figure 1 , Figure 1 This is a structural block diagram of an IGBT power gate driving circuit provided in an embodiment of the present invention. The IGBT power gate driving circuit includes a gate control circuit, a detection circuit, a voltage feedback circuit, and a bandgap reference circuit. The input terminal of the detection circuit is connected to the collector of the IGBT, and the output terminal of the detection circuit is connected to the first input terminal of the voltage feedback circuit. The gate of the IGBT is connected to both the second input terminal of the voltage feedback circuit and the output terminal of the gate control circuit. The output terminal of the bandgap reference circuit is connected to the gate control circuit, the detection circuit, and the voltage feedback circuit. The output terminal of the voltage feedback circuit is connected to the control terminal of the gate control circuit.

[0023] In this embodiment, the gate control circuit is a circuit unit that regulates and outputs the gate charging and discharging current of the power device; the detection circuit is a circuit used to acquire the collector voltage change rate of the power device and convert it into a usable level signal; the voltage feedback circuit is a circuit that compares and performs logical operations based on the detection signal, the gate voltage, and the reference voltage, and outputs a control signal. The bandgap reference circuit is a circuit that provides a stable bias voltage and multiple reference voltages, unaffected by significant changes in temperature and power supply voltage.

[0024] In one embodiment, the gate control circuit includes a current control unit, a current mirror bias unit, and a push-pull output drive unit; the input terminal of the current mirror bias unit is used to receive a bias voltage, and the output terminal of the current mirror bias unit is connected to the input terminal of the current control unit; the control input terminal of the current control unit is used to receive a control signal, and the output terminal of the current control unit is connected to the input terminal of the push-pull output drive unit; the output terminal of the push-pull output drive unit constitutes the output terminal of the gate control circuit.

[0025] Furthermore, the current mirror bias unit is used to provide two mirror bias currents; the current control unit is used to selectively conduct at least one of the two mirror bias currents according to the two control signals.

[0026] In this embodiment, the current mirror bias unit is a unit that generates a stable and proportional bias current through a current mirror structure; the current control unit is a unit that selects and switches the mirror current according to a control signal; and the push-pull output drive unit is a unit that outputs drive current to the gate of the power device using a push-pull structure.

[0027] In a specific embodiment, see Figure 2 , Figure 2 The schematic diagram of a gate control circuit provided in an embodiment of the present invention is shown below. The circuit is analyzed as follows: The current mirror bias unit includes PMOS transistor PM1 and PMOS transistor PM2. The current control unit includes PMOS transistor PM3, PMOS transistor PM4, NMOS transistor NM1, NMOS transistor NM2, NMOS transistor NM3, NMOS transistor NM4 and NMOS transistor NM5; The push-pull output drive unit includes PMOS transistors PM5, PM6, PM7, PM8, PM9, NMOS transistors NM6 and NMOS transistors NM7. PMOS transistor PM1 is connected to power supply VCC; the gate of PMOS transistor PM1 is connected to the gate of PMOS transistor PM2 and simultaneously to a bias voltage VBP; the drain of PMOS transistor PM1 is connected to the source of PMOS transistor PM3; the source of PMOS transistor PM2 is connected to power supply VCC; the drain of PMOS transistor PM2 is connected to the source of PMOS transistor PM4; the gate of PMOS transistor PM3 is connected to a control voltage Vina; the drain of PMOS transistor PM3 is connected to the drain of PMOS transistor PM4; the gate of PMOS transistor PM4 is connected to a control voltage Vinb; the source of PMOS transistor PM5 is connected to power supply VC. C; The gate of PMOS transistor PM5 is connected to the gate of PMOS transistor PM6; the drain of PMOS transistor PM5 is connected to the source of PMOS transistor PM7; the source of PMOS transistor PM6 is connected to power supply VCC; the drain of PMOS transistor PM6 is connected to the source of PMOS transistor PM9; the gate of PMOS transistor PM7 is connected to the gate of PMOS transistor PM8; the drain of PMOS transistor PM7 is connected to the source of PMOS transistor PM8 and simultaneously to the gate of PMOS transistor PM5; the gate of PMOS transistor PM8 is connected to the drain of NMOS transistor NM3; the drain of PMOS transistor PM8 is connected to NMOS transistor NM3. Drain; The gate of PMOS transistor PM9 is connected to the input voltage Vin; The drain of PMOS transistor PM9 is connected to the gate of the power device IGBT; The drain of NMOS transistor NM1 is connected to the drain of PMOS transistor PM3; The gate of NMOS transistor NM1 is connected to the drain of PMOS transistor PM3; The source of NMOS transistor NM1 is connected to the drain of NMOS transistor NM2; The gate of NMOS transistor NM2 is connected to the gate of NMOS transistor NM1; The source of NMOS transistor NM2 is connected to the drain of NMOS transistor NM4; The gate of NMOS transistor NM3 is connected to the gate of NMOS transistor NM2; NMOS transistor NM3... The source of NMOS transistor NM4 is connected to the drain of NMOS transistor NM2; the source of NMOS transistor NM4 is grounded; the gate of NMOS transistor NM5 is connected to the gate of NMOS transistor NM4; the source of NMOS transistor NM5 is grounded; the gate of NMOS transistor NM6 is connected to the input voltage Vin; the drain of NMOS transistor NM6 is connected to the gate of the power device IGBT; the source of NMOS transistor NM6 is connected to the drain of NMOS transistor NM7; the gate of NMOS transistor NM7 is connected to the gate of NMOS transistor NM4; the source of NMOS transistor NM7 is grounded.

[0028] See also Figure 2PMOS transistors PM1 and PM2 form a current mirror bias unit, with the gate voltage provided by the bias voltage VBP, generating current and output current. PMOS transistors PM3 and PM4 act as switches, controlled by control signals Vina and Vinb. When the control signal is high, the PMOS transistor is off; when the control signal is low, the PMOS transistor is on. When the first output signal Vina is low and the second output signal Vinb is high, PMOS transistor PM3 is on and PMOS transistor PM4 is off. At this time, the current flowing into the branch of NMOS transistor NM1 is relatively small. This current passes through the current mirror formed by NMOS transistors NM2, NM3, NM4, and NM5, causing a small current to also be generated in the branch containing PMOS transistor PM8. Then, through the current mirror formed by PMOS transistors PM5 and PM6, the gate input capacitor of the IGBT is charged. This reduces and suppresses the current spikes generated by the reverse recovery current. See also Figure 7 , Figure 7 This is a flowchart illustrating an IGBT power gate drive circuit according to an embodiment of the present invention. When the first output signal Vina is high and the second output signal Vinb is low, PMOS transistor PM3 is off and PMOS transistor PM4 is on. At this time, the current flowing into the NMOS transistor NM1 branch is relatively large. Through the two current mirrors, a larger current is provided to charge the IGBT's gate input capacitor, thereby increasing and decreasing the Miller plateau time, and thus reducing the turn-on loss in the third stage. When the first output signal Vina is low and the second output signal Vinb is low, both PMOS transistors PM3 and PM4 are on. At this time, the current flowing into the NMOS transistor NM1 branch is the sum of the currents in both branches, which is a large current. Therefore, through the current mirror, the IGBT's gate input capacitor can be charged with a large current, reducing the turn-on delay time. The NMOS transistor NM1 and PMOS transistor PM8 are connected in a diode configuration to ensure that the corresponding NMOS transistors and PMOS transistors remain in a saturated operating state throughout the entire circuit operation.

[0029] In one embodiment, the voltage feedback circuit includes a multi-reference voltage comparison unit and a logic operation unit; the output terminal of the multi-reference voltage comparison unit is connected to the input terminal of the logic operation unit; the input terminal of the multi-reference voltage comparison unit constitutes the first input terminal, the second input terminal, and the reference voltage input terminal of the voltage feedback circuit; the output terminal of the logic operation unit constitutes the output terminal of the voltage feedback circuit.

[0030] Furthermore, the multi-reference voltage comparison unit includes at least three comparators; the three comparators are respectively used to receive a detection signal, a gate voltage, and at least three reference voltages.

[0031] Furthermore, the gate control circuit is used to output multi-level drive current according to the first output signal and the second output signal of the logic operation unit.

[0032] In this embodiment, the multi-reference voltage comparison unit is a unit that uses a multi-channel comparator to compare the detection signal, gate voltage and reference voltage; the logic operation unit is a unit that performs CMOS logic operations on the comparator output signal to generate two control signals.

[0033] In a specific embodiment, see Figure 3 , Figure 3 The schematic diagram of a voltage feedback circuit provided in an embodiment of the present invention is as follows: The multi-reference voltage comparison unit includes a first comparator CMP1, a second comparator CMP2, and a third comparator CMP3; The logic operation unit includes multi-level CMOS logic circuits; wherein, PMOS transistors PM1, PM2, PM3, PM4, and PM5 and NMOS transistors NM1, NM2, NM3, NM4, and NM5 constitute a two-inverting-input AND gate; PMOS transistors PM6, PM7, PM8, and PM9 and NMOS transistors NM6, NM7, NM8, and NM9 constitute a three-input AND gate; and PMOS transistors PM10, PM11, PM12, NM10, NM11, and NM1... The OS transistor NM12 forms a two-input AND gate. PMOS transistors PM13, PM14, PM15, PM16, PM17, PM18, and PM19, along with NMOS transistors NM13, NM14, NM15, NM16, NM17, NM18, and NM19, form a three-inverting AND gate. PMOS transistors PM20, PM21, NM20, NM21, PM22, PM23, NM22, and NM23 each form a two-input NOR gate.

[0034] The non-inverting input of the first comparator CMP1 is used to connect the detection signal Vop, and the inverting input of the first comparator CMP1 is used to connect the first reference voltage VREF1; the first reference voltage VREF1 is determined by the gate voltage V of the IGBT. GEThe voltage at the Miller plateau voltage and the resistance in the detection circuit together determine the voltage. The non-inverting input of the second comparator CMP2 is used to connect to the gate voltage VG of the power device, and the inverting input of the second comparator CMP2 is used to connect to the second reference voltage VREF2; VREF2 corresponds to the threshold voltage V of the IGBT. th ; The non-inverting input of the third comparator CMP3 is used to connect the gate voltage V of the power device. GE The inverting input of the third comparator CMP3 is used to connect to the third reference voltage VREF3; VREF3 is between the Miller plateau voltage V PT The voltage between the power supply VCC and the voltage between the power supply VCC; The outputs of the first comparator CMP1, the second comparator CMP2, and the third comparator CMP3 are respectively connected to the inputs of the multi-level CMOS logic circuit. The output terminals of the multi-level CMOS logic circuit are used to output the first output signal Vina and the second output signal Vinb.

[0035] See Figures 3-4 , Figure 4 The gate voltage V during the entire turn-on process provided in the embodiments of the present invention GE The first output signal Vina, the second output signal Vinb, and the gate current I G Waveform change diagram, Figure 4 The first to fourth stages are divided by dotted lines, and the operational logic of each stage is as follows: In the first stage, the outputs of the three comparators are all low. After the logic operation of these logic gates, the control signals Vina and Vinb output by the two NOR gates are both low, which can control the subsequent PMOS transistor to turn on, so that the current passing through the branch is a large current. When entering the second stage, the gate voltage V GE When the output of comparator CMP2 is greater than VREF2, the output of comparator CMP2 is high, and the outputs of the other two comparators are low. After the logic operation of these logic gates, the control signals Vina output by the two NOR gates are low and Vinb is high, thereby controlling the PMOS transistors corresponding to the control signals to turn on or off, so that the current flowing through the branch is a smaller current. When entering the third stage, the output voltage Vop of the detection circuit is greater than the first reference voltage VREF1. The output of comparator CMP1 is high, the output of comparator CMP2 is still high, and the output of comparator CMP3 is still low. After the logic operation of the logic gate, the first output signal Vina is high and the second output signal Vinb is low. Therefore, the conduction state of the corresponding PMOS transistor can be controlled to be opposite to that in the second stage, so that the branch current is larger. Upon entering the fourth stage, the Miller plateau ends, and the gate voltage V of the IGBT... GE When the voltage is greater than the third reference voltage VREF3, both the first output signal Vina and the second output signal Vinb are at a low level, so the branch current can be changed from a larger current to a larger current.

[0036] By comparing the IGBT gate voltage VG and collector voltage slope detection signal Vop with multiple reference voltages in real time, two digital logic control signals Vina and Vinb are output to drive the subsequent gate output current adaptive control circuit, thereby realizing multi-stage adaptive drive control of the IGBT switching process.

[0037] In one embodiment, the detection circuit includes an RC differentiating unit and a signal amplifying unit; the output terminal of the RC differentiating unit is connected to the input terminal of the signal amplifying unit; the input terminal of the RC differentiating unit constitutes the input terminal of the detection circuit; the bias terminal of the signal amplifying unit constitutes the bias terminal of the detection circuit; and the output terminal of the signal amplifying unit constitutes the output terminal of the detection circuit.

[0038] Furthermore, the RC differentiating unit is used to convert the voltage change of the IGBT collector into a transient voltage signal; the signal amplification unit is used to amplify the transient voltage signal and output a detection signal.

[0039] In this embodiment, the RC differentiating unit is composed of resistors and capacitors and is a unit that converts the voltage slope into a transient voltage signal; the signal amplification unit is a unit that amplifies the differential output signal to improve detection accuracy and sensitivity.

[0040] In a specific embodiment, see Figure 5 , Figure 5 The schematic diagram of a detection circuit provided in an embodiment of the present invention is as follows: The RC differentiating unit includes a first capacitor C1 and a first resistor R1; The signal amplification unit includes PMOS transistors PM1, PM2, PM3, and PM4, NMOS transistors NM1, NMOS transistors NM2, and NMOS transistors NM3, a second resistor R2, and a third resistor R3. One end of the first capacitor C1 is used to connect to the collector voltage of the power device, and the other end of the first capacitor C1 is connected to the gate of the PMOS transistor PM1. One end of the first resistor R1 is connected to the gate of the PMOS transistor PM1, and the other end of the first resistor R1 is grounded. The source of PMOS transistor PM1 is connected to the source of PMOS transistor PM2, and is connected to the drain of PMOS transistor PM3. The drain of PMOS transistor PM1 is connected to the drain of NMOS transistor NM1, and the drain of PMOS transistor PM2 is connected to the drain of NMOS transistor NM2. The source of PMOS transistor PM3 is connected to the source of PMOS transistor PM4 and connected to the power supply. The gate of PMOS transistor PM3 is connected to the gate of PMOS transistor PM4 and is used to apply the bias voltage. One end of the second resistor R2 is connected to the drain of the PMOS transistor PM4, and the other end of the second resistor R2 is connected to the gate of the PMOS transistor PM2. One end of the third resistor R3 is connected to the gate of the PMOS transistor PM2, and the other end of the third resistor R3 is grounded. The gate of NMOS transistor NM1 is connected to the gate of NMOS transistor NM2, and is also connected to the drain of NMOS transistor NM2; The sources of NMOS transistors NM1, NM2, and NM3 are all grounded; The gate of NMOS transistor NM3 is connected to the drain of NMOS transistor NM1, and the drain of NMOS transistor NM3 is connected to the drain of PMOS transistor PM4 and used to output the detection signal.

[0041] The detection circuit consists of an RC differentiating unit and a signal amplification unit. The RC differentiating unit collects changes in the collector voltage and outputs the data to the signal amplification unit. The amplification unit is connected to a bias voltage and outputs the processed detection signal. This combination of differentiating and amplifying structures allows for precise detection of voltage change rates, providing crucial signals for Miller platform recognition.

[0042] In one embodiment, the bandgap reference circuit includes a bandgap reference unit and a voltage divider output unit; the output terminal of the bandgap reference unit is connected to the input terminal of the voltage divider output unit; the bias terminal of the bandgap reference unit constitutes the bias voltage output terminal of the bandgap reference circuit; and the output terminal of the voltage divider output unit constitutes the reference voltage output terminal of the bandgap reference circuit.

[0043] Furthermore, the bandgap reference unit is used to output a reference current; the voltage divider output unit is used to convert the reference current into multiple reference voltages.

[0044] In this embodiment, the bandgap reference unit is a unit that generates a reference current that is independent of temperature and power supply voltage; the voltage divider output unit is a unit that converts the reference current into multiple reference voltages of different amplitudes.

[0045] In a specific embodiment, see Figure 6 , Figure 6 The schematic diagram of a bandgap reference circuit provided in an embodiment of the present invention is as follows: The bandgap reference unit includes PMOS transistors PM1, PM2, PM3, PM4, and PM5, NMOS transistors NM1, NM2, NM3, and NM4, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a first transistor Q1, and a second transistor Q2. The voltage divider output unit includes a PMOS transistor PM6, a sixth resistor R6, a seventh resistor R7, and an eighth resistor R8. The gates of PMOS transistors PM1, PM2, and PM5 are interconnected and used to output bias voltage, while their sources are all connected to the power supply. The drain of PMOS transistor PM1 is connected to the source of PMOS transistor PM3, and the drain of PMOS transistor PM2 is connected to the source of PMOS transistor PM4. The gates of PMOS transistors PM3, PM4, and PM6 are interconnected. The drain of PMOS transistor PM3 is connected to one end of the first resistor R1, and the drain of PMOS transistor PM4 is connected to one end of the second resistor R2. The gates of NMOS transistors NM1 and NMOS transistors NM2 are connected to each other and connected to the other end of the first resistor R1; The drain of NMOS transistor NM1 is connected to the other end of the first resistor R1, and the source is connected to the drain of NMOS transistor NM3. The drain of NMOS transistor NM2 is connected to the other end of the second resistor R2, and the source is connected to the drain of NMOS transistor NM4. The gates of NMOS transistors NM3 and NMOS transistors NM4 are connected to each other and connected to the other end of the first resistor R1; The source of NMOS transistor NM3 is connected to the emitter of the first transistor Q1, and the source of NMOS transistor NM4 is connected to one end of the fourth resistor R4. The base and collector of the first transistor Q1 and the second transistor Q2 are both grounded; The emitter of the second transistor Q2 is connected to the other end of the fourth resistor R4; The third resistor R3 is connected between the emitter of the first transistor Q1 and ground, and the fifth resistor R5 is connected between one end of the fourth resistor R4 and ground. The sixth resistor R6, the seventh resistor R7, and the eighth resistor R8 are connected in series between the drain of the PMOS transistor PM6 and ground. The common terminal of the sixth resistor R6 and the seventh resistor R7 is used to output the second reference voltage VREF2, the common terminal of the seventh resistor R7 and the eighth resistor R8 is used to output the first reference voltage VREF1, and the drain of the PMOS transistor PM6 is used to output the third reference voltage VREF3.

[0046] VBP provides bias voltage to the current mirror and differential amplifier, while VREF1, VREF2, and VREF3 provide reference voltages to the three comparators. The PMOS and NMOS transistors, along with resistors R1 and R2, form a self-biased Cascode current mirror structure. The first resistor R1 ensures that the difference between the gate voltages of the upper and lower NMOS transistors is equal to or greater than an overdrive voltage, and the second resistor R2 ensures that the difference between the gate voltages of the upper and lower PMOS transistors is equal to or greater than an overdrive voltage, thereby keeping all MOS transistors in a saturated operating state. The fourth resistor R4 generates a PTAT current through the voltage difference between the emitters of the first transistor Q1 and the second transistor Q2. The fifth resistor R5 generates a CTAT current using the collector-emitter voltage of the first transistor Q1. The PTAT current and the CTAT current are added together by a current mirror and then copied to the branch where the output voltage is located. The superposition of the PTAT current and the CTAT current cancels out the offset caused by temperature, thus forming a current that is independent of temperature. The sixth resistor R6, the seventh resistor R7, and the eighth resistor R8 then divide the voltage to obtain stable different reference voltage outputs.

[0047] See also Figure 7 , Figure 7 This is a flowchart illustrating an IGBT power gate drive circuit according to an embodiment of the present invention. By detecting the gate voltage signal and the collector voltage slope, the operating state of the power device is determined. The logic control circuit then outputs control signals (Vina and Vinb). Based on the different states of the control signals, the output current is adjusted to optimize the IGBT drive. During the switching process of the power device, gate current is injected or extracted, and this current is mainly limited by the gate resistance and gate voltage. Simultaneously, since the gate current charges and discharges the parasitic capacitance inside the IGBT during switching, it determines the switching speed of the IGBT. Taking turn-on as an example, when the gate-emitter voltage V... GE At threshold voltage V th and Miller plateau voltage VM When the gate current is between the gate and emitter voltages, the relationship between the gate current and the gate-emitter voltage is expressed as follows:

[0048] Among them, I G It is the gate drive current; C GC It is the gate-collector Miller capacitance, which varies with V. CE It exhibits nonlinear variation; C GE It is the gate-emitter parasitic capacitance; V GE It is the gate-emitter voltage (or simply gate voltage) of a power device; V CE It is the collector-emitter voltage of a power device; I mos This is the branch current of the MOSFET, which is approximately zero. Therefore, based on the collector current and the gate-emitter voltage V... GE The relationship between collector current and gate current can be obtained as follows:

[0049] Among them, (dI) CE / dt) on It is the rate of change of the current during the opening process; the input capacitance C ies For (C) GC +C GE ); g fs It is the forward transconductance of the power device; I G It is the gate drive current; after the Miller plateau phase begins, the collector-emitter voltage V CE It begins to decrease, and at the same time, the collector-emitter voltage V... CE The voltage decreases, affecting the gate-collector capacitance C. GC It will increase dramatically. At this point, all the gate current will be supplied to C. GC The relationship between the collector-emitter voltage change rate and the required gate current during charging is as follows:

[0050] Among them, (dV CE / dt) on It is the rate of change of voltage during the opening process; I G Gate drive current; C GC It is the gate-collector Miller capacitance, which varies with V. CE It exhibits a non-linear change; during the turn-off process, when the gate-emitter voltage V... GE Reaching Miller plateau voltage V PT At that time, the collector-emitter voltage V CE As it begins to rise, this process will affect the gate-collector capacitance C. GC The discharge process is expressed as follows:

[0051] Among them, (dV CE / dt) off It is the rate of change of voltage during the turn-off process; I G Gate drive current; C GC This is the gate-collector Miller capacitance, which changes non-linearly with VCE; during this discharge process, the collector current remains essentially constant. However, when the gate-emitter voltage V... GE Drop to threshold voltage V th and Miller plateau voltage V M During this period, the collector current begins to decrease. The relationship between the collector current and the gate current during this process is as follows:

[0052] Among them, (dI) CE / dt) off It is the rate of change of current during the turn-off process; g fs It is the forward transconductance of the power device; I G Gate drive current; C GC It is the gate-collector Miller capacitance, which varies with V. CE It exhibits a nonlinear variation; V GE Gate-emitter voltage of power devices (gate voltage for short); turn-on loss E of circuit on and the current overshoot I generated during the turn-on process rrm They are respectively:

[0053]

[0054] Among them, E on It is the turn-on loss; V DC It is the DC bus voltage of the main power circuit; g m It is the transconductance of a power device, characterizing the ability of the gate voltage to control the collector current; I rrm It is the reverse recovery peak current (i.e., current overshoot); I CE It is the collector current of the power device; R on It is the gate resistance; R off It is the gate-off resistor; L E It is the emitter stray inductance; τ is the reverse recovery time constant of the freewheeling diode; C ies It is the input capacitor; V CC It is the power supply voltage of the drive circuit; V GE It is the gate-emitter voltage (or simply gate voltage) of a power device; V GC It refers to the gate-collector voltage of the power device; the turn-on loss of the circuit; and the current overshoot I generated during the turn-on process. rrmBoth can be expressed as functions of the gate current, but in most switching power drive circuits, the collector current change rate dI cannot be independently controlled. CE / dt and collector voltage change rate dV CE / dt, therefore, a trade-off between switching losses and current overshoot cannot be achieved.

[0055] The activation process can be controlled in four stages: First stage: Power device is not turned on, collector current is zero, V CE Maintain high pressure; V ina Low level, V inb When the level is low, the gate control circuit simultaneously conducts two mirror currents, outputting a large drive current I. G1 +I G2 It can quickly charge the gate capacitor, thereby shortening the gate voltage rise time, reducing turn-on delay, and improving the switching response speed.

[0056] The second stage: The power device begins to conduct, the collector current rises, VCE remains at a high voltage, and the Miller plateau has not yet been reached; V ina Low level, V inb The voltage level is high; the gate control circuit only conducts the first mirror current, outputting a moderate drive current I. G1 Slow charging of the gate capacitor; thus reducing the rate of change of current dI. CE / dt, which suppresses the current spikes caused by the reverse recovery of the freewheeling diode, and reduces electromagnetic interference and electrical stress on the device.

[0057] Phase Three: Entering the Miller Platform, V CE The voltage drops rapidly, the Miller capacitance increases sharply, and the collector current remains basically stable; V op Exceeding the reference threshold, V ina High level, V inb When the level is low, the gate control circuit only conducts the second mirror current, outputting the second largest drive current I. G2 The focus is on charging the Miller capacitor to improve the collector voltage change rate dV. CE / dt shortens the Miller platform duration and reduces activation losses.

[0058] Phase 4: Miller platform ends, V CE When the voltage drops to a low level, the Miller capacitance reaches its maximum value, V G Continue to rise to the power supply voltage; V ina Low level, V inb When the level is low, the gate control circuit resumes operation and simultaneously conducts both mirror currents, outputting a large drive current I. G1 +I G2This completes the final charging of the enlarged Miller capacitance and gate capacitance; it adapts to the nonlinear increase characteristics of the Miller capacitance, accelerates the gate voltage to reach a steady state, avoids voltage oscillation, and improves the stability and reliability of the switch.

[0059]

[0060]

[0061] Among them, I G1 It is the first mirror current (low current setting); I G2 It is the second mirror current (medium current setting); I G1 +I G2 It is the superimposed current (high current setting); g fs It is a positive transconductance; C GE It is the gate-emitter parasitic capacitance; C GC It is the gate-collector Miller capacitance; C GC1 It is a Miller capacitance (small value) under high voltage conditions; C GC2 This refers to Miller capacitance (large capacitance value) under low voltage conditions; (dI) CE / dt) on It is the rate of change of the current during the opening process; (dV) CE / dt) on It is the rate of change of the voltage during the opening process; through the required reverse recovery peak current I rrm Indicators and E on The collector current change rate dI can be calculated from the index. CE / dt and collector voltage change rate dV CE / dt, and then substitute it into the specific expression of the gate current at each stage to obtain the drive current.

[0062] The embodiments of the present invention can achieve the following advantages: Through module collaboration and multi-stage adaptive adjustment, multi-level dynamic output of drive current can be achieved, effectively adapting to the nonlinear changes of Miller capacitance. It maintains stable drive performance under wide temperature, wide voltage, and variable load conditions. At the same time, it eliminates the need for complex high-voltage detection and feedback loops, resulting in a simplified circuit structure that is easy to integrate on a single chip. It can reduce switching losses while suppressing voltage and current overshoot, thereby improving the overall reliability and electromagnetic compatibility of the power device drive system.

[0063] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0064] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0065] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0066] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0067] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0068] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. The illustrative expressions of the above terms in this specification should not be construed as necessarily referring to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0069] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Since these modifications and variations fall within the scope of the claims and their equivalents, this invention also intends to include these modifications and variations.

[0070] The above description describes specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and these modifications or substitutions should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. An IGBT power gate drive circuit, characterized in that, This includes a gate control circuit, a detection circuit, a voltage feedback circuit, and a bandgap reference circuit; The input terminal of the detection circuit is connected to the collector of the IGBT, and the output terminal of the detection circuit is connected to the first input terminal of the voltage feedback circuit. The gate of the IGBT is connected to the second input terminal of the voltage feedback circuit and the output terminal of the gate control circuit, respectively. The output terminal of the bandgap reference circuit is connected to the gate control circuit, the detection circuit, and the voltage feedback circuit, respectively. The output terminal of the voltage feedback circuit is connected to the control terminal of the gate control circuit. The gate control circuit includes a current control unit, a current mirror bias unit, and a push-pull output drive unit. The input terminal of the current mirror bias unit is used to connect to the bias voltage, and the output terminal of the current mirror bias unit is connected to the input terminal of the current control unit. The control input terminal of the current control unit is used to receive control signals, and the output terminal of the current control unit is connected to the input terminal of the push-pull output drive unit; the control signals include a first output signal Vina and a second output signal Vinb. The output terminal of the push-pull output drive unit constitutes the output terminal of the gate control circuit. The voltage feedback circuit includes a multi-reference voltage comparison unit and a logic operation unit; The output of the multi-reference voltage comparison unit is connected to the input of the logic operation unit; The input terminals of the multi-reference voltage comparison unit constitute the first input terminal, the second input terminal, and the reference voltage input terminal of the voltage feedback circuit; The output terminal of the logic operation unit constitutes the output terminal of the voltage feedback circuit. The gate control circuit is used to output multi-level drive current according to the first output signal Vina and the second output signal Vinb of the logic operation unit; wherein, the turn-on process is divided into four stages: In the first stage, the first output signal Vina=0 and the second output signal Vinb=0, and the two mirror currents are superimposed to output a large drive current. In the second stage, the first output signal Vina=0 and the second output signal Vinb=1, only a medium drive current is output. In the third stage, the first output signal Vina=1 and the second output signal Vinb=0, and only the second largest drive current is output. In the fourth stage, the first output signal Vina=0 and the second output signal Vinb=0, and the two mirror currents are superimposed to output a large drive current.

2. The IGBT power gate drive circuit according to claim 1, characterized in that, The current mirror bias unit is used to provide two mirror bias currents; The current control unit is used to selectively turn on at least one of the two mirror bias currents according to the two control signals.

3. The IGBT power gate drive circuit according to claim 1, characterized in that, The multi-reference voltage comparison unit includes: A first comparator is used to receive a detection signal and a first reference voltage; The second comparator is used to receive the gate voltage and the second reference voltage; The third comparator is used to receive the gate voltage and the third reference voltage.

4. The IGBT power gate drive circuit according to claim 1, characterized in that, The detection circuit includes an RC differentiating unit and a signal amplification unit; The output of the RC differentiating unit is connected to the input of the signal amplifying unit; The input terminal of the RC differentiating unit constitutes the input terminal of the detection circuit; The bias terminal of the signal amplification unit constitutes the bias terminal of the detection circuit, and the output terminal of the signal amplification unit constitutes the output terminal of the detection circuit.

5. The IGBT power gate drive circuit according to claim 4, characterized in that, The RC differentiating unit is used to convert the voltage change at the IGBT collector into a transient voltage signal; The signal amplification unit is used to amplify the transient voltage signal and output a detection signal.

6. The IGBT power gate drive circuit according to claim 1, characterized in that, The bandgap reference circuit includes a bandgap reference unit and a voltage divider output unit; The output terminal of the bandgap reference unit is connected to the input terminal of the voltage divider output unit; The bias terminal of the bandgap reference unit constitutes the bias voltage output terminal of the bandgap reference circuit. The output terminal of the voltage divider output unit constitutes the reference voltage output terminal of the bandgap reference circuit.

7. The IGBT power gate drive circuit according to claim 6, characterized in that, The bandgap reference unit is used to output a reference current; The voltage divider output unit is used to convert the reference current into multiple reference voltages.

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