LDMOS device and method for improving breakdown voltage thereof

Abstract

The application provides an LDMOS device and a method for improving the breakdown voltage of the LDMOS device. In the LDMOS device, a substrate comprises a core active region; a P-type body region and an N-type drift region are located in the core active region; an N-type doped field limiting ring is located at an edge region of the core active region, the N-type doped field limiting ring is a closed ring and is connected with the N-type drift region, part of the N-type drift region and the P-type body region are located on the inner side of the N-type doped field limiting ring, and the doping concentration of the N-type doped field limiting ring gradually increases in the direction from the inner side to the outer side. By increasing the N-type doped field limiting ring, the lateral electric field distribution can be optimized to improve the breakdown voltage, and the device maintains a low on-resistance. The method for improving the breakdown voltage of the LDMOS device is applied to the manufacturing process of the LDMOS device.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to an LDMOS device and a method for increasing its breakdown voltage. Background Technology

[0002] Traditional laterally diffused metal-oxide-semiconductor (LDMOS) devices face the bottleneck of insufficient breakdown voltage in high-voltage applications, especially prone to avalanche breakdown under high temperature and high current conditions.

[0003] Currently, most buck converter chips rely on external MOSFETs, and their efficiency and system stability are directly affected by the MOSFET's breakdown voltage (BV). Conventional methods to increase the breakdown voltage of LDMOS devices, such as increasing the drift region length, lead to a significant increase in the device's on-resistance (RDS(on)), reducing energy efficiency and increasing heat loss. This fails to meet the requirements of electric vehicle BMS, DC-DC converters, and other applications where MOSFETs possess high BV, low RDS(on), and excellent heat dissipation performance. While existing field plate or reduced surface field (RESURF) technologies can optimize the electric field distribution, they suffer from high process complexity and limited control over the surface electric field. Summary of the Invention

[0004] One of the objectives of this application is to provide an LDMOS device and a method for improving its breakdown voltage, which can optimize the lateral electric field distribution of the device to improve the breakdown voltage while maintaining a low on-resistance.

[0005] To achieve the above objectives, one aspect of this application provides an LDMOS device. The LDMOS device includes: a substrate comprising a core active region; a P-type body region and an N-type drift region, both located within the core active region; and an N-type doped field-limiting ring located at the edge of the core active region. The N-type doped field-limiting ring is a closed loop and is connected to the N-type drift region. A portion of the N-type drift region and the P-type body region are located inside the N-type doped field-limiting ring, and the doping concentration of the N-type doped field-limiting ring gradually increases in the direction from its inner side to its outer side.

[0006] Optionally, the depth of the N-type doped field confinement ring is less than the depth of the N-type drift region, and the outer edge of the top surface of the core active region overlaps with the outer edge of the N-type doped field confinement ring.

[0007] Optionally, the LDMOS device further includes: a gate structure located above the core active region, the gate structure spanning the P-type body region and the N-type drift region and covering a portion of the P-type body region and a portion of the N-type drift region; an N-type source region located on top of the P-type body region and on the side of the gate structure away from the N-type drift region; and an N-type drain region located on top of the N-type drift region and on the side of the gate structure away from the P-type body region.

[0008] Optionally, the N-type doped field confinement ring surrounds the N-type drain region; the doping concentration of each region of the N-type doped field confinement ring is less than the doping concentration of the N-type drain region.

[0009] Optionally, the N-type drift region is annular, and the gate structure is annular; the top of the P-type body region has two N-type source regions, and the two N-type source regions are respectively disposed close to the gate structures on both sides of the P-type body region.

[0010] Optionally, the ring width of the N-type doped field confinement ring is greater than or equal to 1µm and less than or equal to 3µm, and the depth of the N-type doped field confinement ring in the substrate is greater than or equal to 0.5µm and less than or equal to 1.2µm.

[0011] Optionally, the doping concentration of the N-type doped field confinement ring is greater than or equal to 2e17 / cm. 3 And less than or equal to 1.5e18 / cm 3 .

[0012] Optionally, the substrate further includes a peripheral active region surrounding the core active region, the peripheral active region and the core active region being isolated by an isolation structure, and an annular P-type well region being formed in the peripheral active region.

[0013] Another aspect of this application provides a method for improving the breakdown voltage of an LDMOS device. The method includes: providing a substrate, the substrate including a core active region; forming an N-type doped field-limiting ring in the core active region, the N-type doped field-limiting ring being located at the edge region of the core active region, the N-type doped field-limiting ring being a closed loop and connected to the N-type drift region, a portion of the N-type drift region and a P-type body region being located inside the N-type doped field-limiting ring, and the doping concentration of the N-type doped field-limiting ring gradually increasing in the direction from its inner side to its outer side.

[0014] Optionally, the LDMOS device including the N-type doped field confinement ring is a high-voltage LDMOS device; a low-voltage LDMOS is also formed on the substrate, and the N-type doped field confinement ring is formed synchronously with the N-type drift region of the low-voltage LDMOS.

[0015] The LDMOS device provided in this application includes a substrate, the substrate including a core active region, the core active region having a P-type body region, an N-type drift region and an N-type doped field confinement ring, the N-type doped field confinement ring being located at the edge region of the core active region, the N-type doped field confinement ring being a closed loop and connected to the N-type drift region, a portion of the N-type drift region and the P-type body region being located inside the N-type doped field confinement ring, and the doping concentration of the N-type doped field confinement ring gradually increasing in the direction from its inner side to its outer side. In this way, the N-type doped field confinement ring can serve as a progressive electric field buffer layer. When the device is subjected to high reverse voltage, the N-type doped field confinement ring forms a reverse bias junction with the substrate, which expands the depletion region and suppresses the electric field spikes at the edge of the core active region. Through the charge balance effect, the N-type doped field confinement ring transfers the electric field peak from the surface of the core active region to the interior of the N-type doped field confinement ring, making the electric field distribution more uniform and improving the breakdown voltage. At the same time, the device can maintain low on-resistance, which can meet the requirements of electric vehicle BMS, DC-DC converters and other scenarios where MOSFETs have both high breakdown voltage, low on-resistance and excellent heat dissipation performance. In addition, the N-type doped field confinement ring can be formed by ion implantation and annealing steps that are compatible with standard CMOS processes without increasing the complexity of the process. Attached Figure Description

[0016] Figure 1 This is a cross-sectional structural diagram of an LDMOS device provided in an embodiment of this application.

[0017] Figure 2 This is a schematic diagram of the layout of the core active region, the peripheral active region, and the N-type doped field confinement ring in one embodiment of this application.

[0018] Figure 3 This is an Id_Vd curve of an existing LDMOS device.

[0019] Figure 4 The Id_Vd curve of an LDMOS device provided in an embodiment of this application.

[0020] Figure 5 This is a simulated electric field distribution diagram of an LDMOS device provided in an embodiment of the present invention.

[0021] Explanation of reference numerals in the attached figures: 10-substrate; 10a-core active region; 10b-peripheral active region; 101-N-type drift region; 102-P-type body region; 103-N-type doped field confinement ring; 104-N-type source region; 105-N-type drain region; 107-first P-type lead-out region; 108-P-type well region; 109-second P-type lead-out region; 110-isolation structure; 20-gate structure. Detailed Implementation

[0022] The present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present application will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present application.

[0023] As used herein, the singular forms “a,” “an,” and “the” include plural objects unless otherwise expressly indicated. As used herein, the term “or” is generally used to include “and / or” unless otherwise expressly indicated. As used herein, the term “a number” is generally used to include “at least one” unless otherwise expressly indicated. As used herein, the term “at least two” is generally used to include “two or more” unless otherwise expressly indicated. Furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as “first,” “second,” or “third” may explicitly or implicitly include one or at least two of that feature, unless otherwise expressly indicated.

[0024] Figure 1 This is a cross-sectional structural diagram of an LDMOS device provided in an embodiment of this application. Figure 2 This is a schematic diagram of the layout of the core active region, the peripheral active region, and the N-type doped field confinement ring in one embodiment of this application. The Z-direction is the thickness direction of the substrate, and both the X and Y directions are perpendicular to the thickness direction of the substrate.

[0025] Combination Figure 1 and Figure 2 As shown, the LDMOS device provided in this embodiment includes a substrate 10, a P-type body region 102, an N-type drift region 101, and an N-type doped field confinement ring 103. The substrate 10 includes a core active region 10a, and the P-type body region 102 and the N-type drift region 101 are both located within the core active region 10a. The N-type doped field confinement ring 103 is located at the edge region of the core active region 10a. The N-type doped field confinement ring 103 is a closed ring and is connected to the N-type drift region 101. A portion of the N-type drift region 101 and the P-type body region 102 are located inside the N-type doped field confinement ring 103, and the doping concentration of the N-type doped field confinement ring 103 gradually increases in the direction from its inner side to its outer side.

[0026] Thus, the N-type doped field confinement ring 103 can serve as a progressive electric field buffer layer. When the device is subjected to a high reverse voltage, the N-type doped field confinement ring 103 forms a reverse bias junction with the substrate 10, which expands the depletion region and suppresses the electric field spike at the edge of the core active region 10a. Through the charge balance effect, the N-type doped field confinement ring 103 transfers the electric field peak from the surface of the core active region 10a to the interior of the N-type doped field confinement ring 103, making the electric field distribution more uniform and achieving an increase in breakdown voltage. At the same time, the device can maintain a low on-resistance.

[0027] Specifically, in this embodiment, the substrate 10 can be a P-type substrate. The material of the substrate 10 can include silicon, germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide. The substrate 10 can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, etc. In this embodiment, the substrate 10 is a silicon substrate.

[0028] In one embodiment of this application, reference is made to... Figure 1 As shown, the N-type drift region 101 can be annular, and the P-type body region 102 is located inside the N-type drift region 101. The N-type doped field confinement ring 103 can be located at the top of the N-type drift region 101.

[0029] refer to Figure 1 As shown, in this embodiment, the N-type drift region 101 and the P-type body region 102 are spaced apart, that is, there is a P-type substrate between the N-type drift region 101 and the P-type body region 102.

[0030] refer to Figure 1 As shown, the LDMOS device may further include a gate structure 20, an N-type source region 104, and an N-type drain region 105.

[0031] For example, the gate structure 20 is located above the core active region 10a, and the gate structure 20 spans the P-type body region 102 and the N-type drift region 101 and covers a portion of the P-type body region 102 and a portion of the N-type drift region 101.

[0032] For example, the gate structure 20 is annular. The gate structure 20 may include, but is not limited to, a gate oxide layer attached to the surface of the substrate 10, a polysilicon gate located on the gate oxide layer, and sidewalls covering the gate oxide layer and the polysilicon gate sidewalls.

[0033] refer to Figure 1As shown, the N-type source region 104 is located on top of the P-type body region 102 and on the side of the gate structure 20 away from the N-type drift region 101. The N-type drain region 105 is located on top of the N-type drift region 101 and on the side of the gate structure 20 away from the P-type body region 102. More specifically, two N-type drain regions 105 may be formed on the top of the N-type drift region 101, and the N-type drain regions 105 are disposed on both sides of the annular gate structure 20.

[0034] In this embodiment, as Figure 1 As shown, the top of the P-type body region 102 may have two N-type source regions 104, and the two N-type source regions 104 are respectively disposed close to the gate structures 20 on both sides of the P-type body region 102; the LDMOS device may be mirror-symmetrical about the centerline (extending along the Z direction) of the P-type body region 102.

[0035] In this embodiment, both the N-type drain region 105 and the N-type source region 104 are N+ doped regions.

[0036] refer to Figure 1 As shown, the N-type doped field confinement ring 103 can extend from the top surface of the core active region 10a to the bottom surface of the substrate 10. The outer edge of the top surface of the core active region 10a overlaps with the outer edge of the N-type doped field confinement ring 103. That is, the N-type doped field confinement ring 103 is located at the outermost edge of the core active region and surrounds the core active region 10a.

[0037] In the core active region 10a, the depth of the N-type doped field confinement ring 103 is less than the depth of the N-type drift region 101. The concentration of the N-type doped field confinement ring 103 is similar to the concentration of the drift region 101, for example, the concentration of the N-type doped field confinement ring 103 is slightly greater than the concentration of the drift region 101.

[0038] The N-type doped field confinement ring 103 surrounds the N-type drain region 105.

[0039] More specifically, the core active region 10a is defined by the isolation structure 110, and the N-type drift region 101 can partially extend below the isolation structure 110. One sidewall of the N-type doped field confinement ring 103 can be attached to the sidewall of the isolation structure 110, and the other sidewall can be connected to the N-type drain region 105. The bottom and part of the sidewall of the N-type doped field confinement ring 103 are connected to the N-type drift region 101, and part of the N-type doped field confinement ring 103 can also be located below the isolation structure 110.

[0040] In this embodiment, the doping concentration of the N-type doped field confinement ring 103 gradually increases in the direction from its inner side to its outer side. For example, the doping concentration in each region of the N-type doped field confinement ring 103 is less than the doping concentration in the N-type drain region 105, or in other words, the maximum doping concentration of the N-type doped field confinement ring 103 is less than the doping concentration in the N-type drain region 105. This results in a better effect of the N-type doped field confinement ring 103 on improving the breakdown voltage of the LDMOS device.

[0041] In one embodiment of this application, the doping concentration in each region of the N-type doped field confinement ring 103 is greater than or equal to 2e17 / cm². 3 And less than or equal to 1.5e18 / cm 3 Thus, the N-type doped field confinement ring 103 effectively improves the breakdown voltage of the LDMOS device. In other embodiments, with the doping concentration gradually increasing in the direction from the inner side to the outer side of the N-type doped field confinement ring 103, the specific concentration in each region of the N-type doped field confinement ring 103 can be set as needed.

[0042] In this embodiment, the width of the N-type doped field confinement ring 103 can be greater than or equal to 1µm and less than or equal to 3µm, and the depth of the N-type doped field confinement ring 103 in the substrate 10 can be greater than or equal to 0.5µm and less than or equal to 1.2µm. This results in a better effect of the N-type doped field confinement ring 103 on improving the breakdown voltage of the LDMOS device. In other embodiments, the width and depth of the N-type doped field confinement ring 103 can be adjusted as needed.

[0043] Continue to refer to Figure 1 As shown, the top of the P-type body region 102 also has a first P-type lead-out region 107. The doping concentration of the first P-type lead-out region 107 is greater than the doping concentration of the P-type body region 102, which is used to reduce the lead-out resistance of the P-type body region 102. For example, the first P-type lead-out region 107 may be located between the two N-type source regions 104 of the P-type body region 102, but is not limited thereto.

[0044] refer to Figure 1 and Figure 2 As shown, the substrate 10 may further include a peripheral active region 10b surrounding the core active region 10a. The peripheral active region 10b and the core active region 10a are isolated by an isolation structure 110. A ring-shaped P-type well region 108 may be formed in the peripheral active region 10b. A second P-type lead-out region 109 may be formed on the top of the P-type well region 108. The doping concentration of the second P-type lead-out region 109 is greater than that of the P-type well region 108, which is used to reduce the lead-out resistance of the P-type well region 108. The P-type well region 108 may partially extend below the isolation structure 110, but the isolation requirements between the P-type well region 108 and the N-type drift region 101 must be met.

[0045] Figure 3 This is an Id_Vd curve for an existing LDMOS device. (Reference) Figure 3 As shown, existing LDMOS devices without N-type doped field limiting rings have already been damaged by breakdown under voltages below 60V. Figure 4 A graph showing the Id_Vd curve of an LDMOS device provided in an embodiment of this application. (Reference) Figure 4 As shown, after setting an N-type doped field-limiting ring 103 at the edge region of the core active region 10a in this application, the LDMOS device can still operate normally without breakdown under a voltage greater than 60V. (Comparison) Figure 3 and Figure 4 It is understood that the N-type doped field confinement ring 103 at the edge of the core active region 10a in this application helps to improve the breakdown voltage of the LDMOS device. Tests have shown that adding the N-type doped field confinement ring 103 can increase the breakdown voltage of the LDMOS device by approximately 15% to 25%.

[0046] In one embodiment of this application, the breakdown voltage of the LDMOS device can be greater than or equal to 80V, and the on-resistance can be less than or equal to 35mΩ. The operating voltage of the LDMOS device can be greater than or equal to 60V, for example, greater than or equal to 60V and less than or equal to 120V, but is not limited thereto.

[0047] For example, the LDMOS device provided in this application can be used in battery charging and discharging control circuits or DC-DC buck converter circuits, etc.

[0048] This application also provides a method for increasing the breakdown voltage of an LDMOS device. This method for increasing the breakdown voltage of an LDMOS device can be applied to the manufacturing process of the LDMOS device described above.

[0049] refer to Figure 1 The LDMOS device shown includes a method for increasing the breakdown voltage of the LDMOS device, comprising: providing a substrate 10, the substrate 10 including a core active region 10a; forming an N-type doped field-limiting ring 103 in the core active region 10a, the N-type doped field-limiting ring 103 being located at the edge region of the core active region 10a, the N-type doped field-limiting ring 103 being a closed ring and connected to the N-type drift region 101, a portion of the N-type drift region 101 and the P-type body region 102 being located inside the N-type doped field-limiting ring 103, and the doping concentration of the N-type doped field-limiting ring 103 gradually increasing in the direction from its inner side to its outer side.

[0050] For example, the N-type doped field confinement ring 103 can be formed using ion implantation and annealing processes compatible with standard CMOS processes, thus not increasing the complexity of the process. More specifically, the substrate 10 can include a high-voltage region and a low-voltage region. The LDMOS device of this application can be formed in the high-voltage region, that is, the LDMOS device including the N-type doped field confinement ring 103 provided in this application is a high-voltage LDMOS device, and the low-voltage region can be used to form a low-voltage LDMOS device; the N-type doped field confinement ring 103 can be formed synchronously with the N-type drift region of the low-voltage LDMOS, thus eliminating the need for additional masks or complex epitaxial layers, simplifying the process.

[0051] During ion implantation to form the N-type doped field confinement ring 103, reference Figure 2 As shown, the layout of the N-type doped field confinement ring 103 (or the corresponding window of the N-type doped field confinement ring 103) can cover the edge region of the core active region 10a and part of the isolation structure 110 covering the side of the core active region 10a. This ensures that the N-type doped field confinement ring 103 can cover the edge of the core active region 10a, resulting in a better effect of the N-type doped field confinement ring 103 in optimizing the lateral electric field distribution of the device, which helps to improve the breakdown voltage of the device. For example, the extension width of the layout of the N-type doped field confinement ring 103 beyond the core active region 10a (i.e., the width of the layout of the N-type doped field confinement ring 103 extending onto the isolation structure 110) can be 0.2µm to 0.8µm. This ensures that the formed N-type doped field confinement ring 103 covers the edge of the core active region 10a, and the extension width on the isolation structure 110 is not too large, so as not to affect the isolation effect of the isolation structure 110.

[0052] Figure 5 This is a simulated electric field distribution diagram of an LDMOS device according to an embodiment of the present invention. (Reference) Figure 5 As shown, after setting an N-type doped field confinement ring 103 in the edge region of the core active region 10a, the electric field distribution of the LDMOS device is uniform.

[0053] The LDMOS device provided in this application includes a substrate 10, which includes a core active region 10a. The core active region 10a has a P-type body region 102, an N-type drift region 101, and an N-type doped field confinement ring 103. The N-type doped field confinement ring 103 is located at the edge region of the core active region 10a. The N-type doped field confinement ring 103 is a closed ring and is connected to the N-type drift region 101. A portion of the N-type drift region 101 and the P-type body region 102 are located inside the N-type doped field confinement ring 103. The doping concentration of the N-type doped field confinement ring 103 gradually increases in the direction from its inner side to its outer side. In this way, the N-type doped field confinement ring 103 can serve as a progressive electric field buffer layer. When the device is subjected to a high reverse voltage, the N-type doped field confinement ring 103 forms a reverse bias junction with the substrate, which expands the depletion region and suppresses the electric field spike at the edge of the core active region 10a. Through the charge balance effect, the N-type doped field confinement ring 103 transfers the electric field peak from the surface of the core active region 10a to the interior of the N-type doped field confinement ring 103, making the electric field distribution more uniform and achieving an increase in breakdown voltage. At the same time, the device can maintain low on-resistance, which can meet the requirements of electric vehicle BMS, DC-DC converters and other scenarios where MOSFETs have both high breakdown voltage, low on-resistance and excellent heat dissipation performance. In addition, the N-type doped field confinement ring can be formed by ion implantation and annealing steps that are compatible with standard CMOS processes without increasing the complexity of the process.

[0054] The above description is merely a description of preferred embodiments of this application and is not intended to limit the scope of the claims of this application. Any person skilled in the art can make possible changes and modifications to the technical solutions of this application by utilizing the methods and techniques disclosed above without departing from the spirit and scope of this application. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of this application without departing from the content of the technical solutions of this application shall fall within the protection scope of the technical solutions of this application.

Claims

1. An LDMOS device, characterized in that, include: Substrate, including the core active region; The P-type body region and the N-type drift region are both located within the core active region; An N-type doped field confinement ring is located at the edge of the core active region. The N-type doped field confinement ring is a closed loop and is connected to the N-type drift region. A portion of the N-type drift region and the P-type body region are located inside the N-type doped field confinement ring. The doping concentration of the N-type doped field confinement ring gradually increases in the direction from its inner side to its outer side.

2. The LDMOS device as described in claim 1, characterized in that, The depth of the N-type doped field confinement ring is less than the depth of the N-type drift region, and the outer edge of the top surface of the core active region overlaps with the outer edge of the N-type doped field confinement ring.

3. The LDMOS device as described in claim 1, characterized in that, Also includes: A gate structure is located above the core active region, the gate structure spans the P-type body region and the N-type drift region and covers part of the P-type body region and part of the N-type drift region; The N-type source region is located at the top of the P-type body region and on the side of the gate structure away from the N-type drift region; as well as The N-type drain region is located at the top of the N-type drift region and on the side of the gate structure away from the P-type body region. The depth of the N-type drain region is less than the depth of the N-type doped field confinement ring.

4. The LDMOS device as described in claim 3, characterized in that, The N-type doped field confinement ring surrounds the N-type drain region; the doping concentration of each region of the N-type doped field confinement ring is less than the doping concentration of the N-type drain region.

5. The LDMOS device as described in claim 3, characterized in that, The N-type drift region is annular, and the gate structure is annular; the top of the P-type body region has two N-type source regions, and the two N-type source regions are respectively located close to the gate structures on both sides of the P-type body region.

6. The LDMOS device as described in claim 1, characterized in that, The width of the N-type doped field confinement ring is greater than or equal to 1µm and less than or equal to 3µm, and the depth of the N-type doped field confinement ring in the substrate is greater than or equal to 0.5µm and less than or equal to 1.2µm.

7. The LDMOS device as described in claim 1, characterized in that, The doping concentration of the N-type doped field confinement ring is greater than or equal to 2e17 / cm. 3 And less than or equal to 1.5e18 / cm 3 .

8. The LDMOS device as described in claim 1, characterized in that, The substrate also includes a peripheral active region surrounding the core active region, which is isolated from the core active region by an isolation structure, and an annular P-type well region is formed in the peripheral active region.

9. A method for increasing the breakdown voltage of an LDMOS device, characterized in that, include: A substrate is provided, the substrate including a core active region; An N-type doped field confinement ring is formed in the core active region. The N-type doped field confinement ring is located in the edge region of the core active region. The N-type doped field confinement ring is a closed ring and is connected to the N-type drift region. A portion of the N-type drift region and the P-type body region are located inside the N-type doped field confinement ring. The doping concentration of the N-type doped field confinement ring gradually increases in the direction from its inner side to its outer side.

10. The method for increasing the breakdown voltage of an LDMOS device as described in claim 9, characterized in that, The LDMOS device including the N-type doped field confinement ring is a high-voltage LDMOS device; a low-voltage LDMOS is also formed on the substrate, and the N-type doped field confinement ring is formed synchronously with the N-type drift region of the low-voltage LDMOS.

Images