Semiconductor device and method of manufacturing the same

Abstract

The application provides a semiconductor device and a preparation method thereof, and belongs to the technical field of semiconductors. The semiconductor device comprises a substrate, wherein the substrate has a drift region and a drain region arranged in the drift region; a field oxide layer covering at least a surface of the drift region close to the drain region; a first conductive layer arranged on the field oxide layer and close to the drain region; a first side wall covering at least a sidewall of the first conductive layer; an isolation layer covering at least a top wall of the first conductive layer, the first side wall and part of a surface of the field oxide layer in a direction away from the drain region, wherein the isolation layer has a plurality of steps on the top wall of the first conductive layer and a side away from the drain region, and an arc-shaped transition is formed between steps close to the drain region; and a field plate arranged on the isolation layer and covering at least surfaces of the plurality of steps. The application can optimize the performance of the semiconductor device and the preparation process.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to a semiconductor device and its fabrication method. Background Technology

[0002] In the field of semiconductor device manufacturing, especially in power semiconductor devices such as laterally diffused metal-oxide-semiconductor (LDMOS), field plate technology is widely used to improve the electric field distribution. The common goal of this technology is to homogenize the electric field at the drain terminal of the device by adjusting the surface potential distribution, thereby improving the breakdown voltage and overall reliability to meet the requirements of high-voltage applications.

[0003] In related technologies, a multi-level field plate structure is often used as a typical solution to further reduce the peak electric field at the drain edge. This solution typically increases the number of field plates sequentially to distribute the electric field in a stepped manner, thereby mitigating the electric field spikes at the edges of individual field plates. However, the implementation of this multi-level field plate structure relies on the independent patterning process of each field plate. Each additional field plate generally requires an additional mask and corresponding photolithography and etching processes, which leads to a longer manufacturing process and a significant increase in manufacturing costs. As the breakdown voltage requirements of devices continue to increase, more levels of field plates are needed to optimize the electric field distribution, but the increase in the number of masks makes cost control a bottleneck.

[0004] Therefore, in semiconductor device manufacturing, optimizing the field plates in the aforementioned semiconductor devices and improving their performance while minimizing the increase in the number of photomasks has become a technical challenge. Summary of the Invention

[0005] In view of this, this application aims to provide a semiconductor device and a method for fabricating the same, which can optimize the performance and fabrication process of the semiconductor device.

[0006] Based on one aspect of this application, a semiconductor device is provided, comprising: A substrate having a drift region and a drain region disposed in the drift region; An oxygen layer, at least covering the surface of the drift region near the leak region; A first conductive layer is located on the field oxygen layer and is disposed close to the drain region; The first sidewall at least covers the sidewall of the first conductive layer; An isolation layer conformally covers at least a portion of the top wall of the first conductive layer, the first sidewall, and the surface of the field oxygen layer in a direction away from the drain area. The isolation layer has multiple steps on the top wall of the first conductive layer and on the side away from the drain area, with an arc-shaped transition formed between the steps near the drain area. A field plate is located on the isolation layer and at least conformally covers the surface of the multi-level steps.

[0007] Optionally, the isolation layer has a first opening on the side away from the first conductive layer; along the direction away from the drain area, the surface of the isolation layer on the first conductive layer, the surface of the isolation layer near the first sidewall, and the bottom surface of the first opening form a three-step structure, and the field plate conformally covers the surface of the three-step structure.

[0008] Optionally, the field oxide layer has a second opening on the side away from the first conductive layer, and the isolation layer conformally covers the first conductive layer, the first sidewall, the surface of the field oxide layer, and the inner wall of the second opening; along the direction away from the drain area, the isolation layer surface on the first conductive layer, the isolation layer surface near the first sidewall, and the isolation layer surface at the bottom of the second opening form a three-step structure, and the field plate conformally covers the surface of the three-step structure.

[0009] Optionally, the semiconductor device further includes a gate structure and a second sidewall, the second sidewall covering the sidewall of the gate structure, the gate structure including a gate conductive layer. The gate conductive layer has the same material and thickness as the first conductive layer, and / or the second sidewall has the same material as the first sidewall.

[0010] Optionally, the gate conductive layer further includes an extension that covers a portion of the surface of the field oxide layer near the gate structure. The extension has a second sidewall on the side near the drain region. The isolation layer covers the surface of the extension and the surface near the second sidewall of the extension. The field plate conformally covers the isolation layer on the second sidewall.

[0011] Optionally, the isolation layer and / or the first sidewall comprises a stacked structure consisting of silicon oxide / silicon nitride / silicon oxide groups.

[0012] Optionally, the semiconductor device further includes a plug located on the drain region, and the field plate is made of the same material as the plug.

[0013] Based on another aspect of this application, a method for fabricating a semiconductor device is also provided, comprising: A substrate is provided, the substrate having a drift region and a drain region disposed in the drift region; A field oxygen layer is formed, at least covering the surface of the drift region near the leak region; A gate structure and a first conductive layer are formed. The gate structure is located on the substrate and includes a gate conductive layer. The first conductive layer is located on the field oxide layer and is disposed near the drain region. The gate conductive layer and the first conductive layer are obtained by patterning the same conductive material. A first sidewall is formed, at least covering the sidewall of the first conductive layer; An isolation layer is formed, which conformally covers at least a portion of the top wall of the first conductive layer, the first sidewall, and the surface of the field oxygen layer in a direction away from the drain area. The isolation layer has multiple steps on the top wall of the first conductive layer and on the side away from the drain area, and an arc-shaped transition is formed between the steps near the drain area. A field plate is formed on the isolation layer, the field plate at least conformally covering the surface of the multi-level steps.

[0014] Optionally, after forming the isolation layer, a first opening is also formed in the isolation layer. The first opening is located on the side of the isolation layer away from the first conductive layer, so that the surface of the isolation layer on the first conductive layer, the surface of the isolation layer near the first sidewall, and the bottom surface of the first opening form a three-level step.

[0015] Optionally, after forming the field oxygen layer, a second opening is also formed in the field oxygen layer; After the field oxygen layer is formed, a second opening is also formed in the field oxygen layer; When the first sidewall is formed, the first sidewall also covers the inner sidewall of the second opening; When the isolation layer is formed, the isolation layer conformally covers the surface of the first conductive layer, the first sidewall, the field oxygen layer, and the inner wall of the second opening, so that the isolation layer surface on the first conductive layer, the isolation layer surface near the first sidewall, and the isolation layer surface at the bottom of the second opening form a three-level step.

[0016] In summary, the unexpected effect of this application is that a first conductive layer is formed on the end of the field oxide layer near the drain region. This first conductive layer is covered by a first sidewall and an isolation layer and is suspended relative to the field plate. The combination of the suspended first conductive layer and the field plate (e.g., with a fixed potential) makes the electric field adjustment of the drift region more flexible, increases the degree of freedom of electric field adjustment, and achieves a more optimized adjustment effect, thereby improving the performance of the semiconductor device. For example, this application can adjust the electric field near the drain region separately by means of the floating first conductive layer while ensuring that the electric field is kept relatively suppressed at most locations of the entire drift region, avoiding excessive suppression at the end of the drift region near the drain region, thereby optimizing the electric field adjustment of the entire drift region at the same time. Moreover, the first conductive layer can be used to form multiple steps above the drift region to form multiple levels of field plates, and the first sidewall can be used to form arc transitions between the multiple steps, so that the adjacent levels of the multiple levels of field plates form smooth transitions, which is conducive to the smooth transition of the electric field below. In addition, from the perspective of fabricating the semiconductor device, the first conductive layer and the gate conductive layer of the gate structure can be obtained by patterning the same conductive material, and the first sidewall and the second sidewall of the gate structure are formed simultaneously, so that the formation of the first conductive layer and the first sidewall of this application does not require additional process steps and masks, thereby simplifying the process and reducing costs. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of an LDMOS device with a single-stage field plate.

[0018] Figure 2 This is a schematic diagram of an LDMOS device with a secondary field plate.

[0019] Figure 3 To and Figure 1 and Figure 2 A schematic diagram of the electric field distribution under the field plate.

[0020] Figure 4 This is a schematic diagram of a semiconductor device provided in an embodiment of this application.

[0021] Figure 5 for Figure 4 A schematic diagram of the electric field distribution of a semiconductor device.

[0022] Figure 6 for Figure 4 A schematic diagram of the impact ionization rate distribution of a semiconductor device.

[0023] Figure 7 This is a schematic diagram of another semiconductor device provided in an embodiment of this application.

[0024] Figure 8 This is a schematic diagram of another semiconductor device provided in an embodiment of this application.

[0025] Figure 9 A flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of this application.

[0026] Figure 10 This is a schematic diagram of a substrate provided in one embodiment of this application.

[0027] Figure 11 This is a schematic diagram of the formation of a field oxygen layer provided in an embodiment of this application.

[0028] Figure 12 This is a schematic diagram of the formation of a gate conductive layer and a first conductive layer according to an embodiment of this application.

[0029] Figure 13 This is a schematic diagram of the formation of a first sidewall and a second sidewall according to an embodiment of this application.

[0030] Figure 14 This is a schematic diagram of the formation of an isolation layer provided in an embodiment of this application.

[0031] Figure 15 This is a schematic diagram of the forming plate and plug provided in an embodiment of this application.

[0032] exist Figures 4-15 In the middle: 100-substrate; 110-body region; 120-drift region; 130-source region; 140-drain region; 101-overlapping region; 201-field oxide layer; 203-thin oxide layer; 205-gate conductive layer; 210-first conductive layer; 207-extension; 211-first sidewall; 209-second sidewall; 230-isolation layer; 231-secondary step; 232-first opening; 233-tertiary step; 234-second opening; 310-field plate; 320-plug. Detailed Implementation

[0033] Figure 1 This is a schematic diagram of an LDMOS device with a single-stage field plate. Figure 2 This is a schematic diagram of an LDMOS device with a secondary field plate. (Example) Figure 1 and Figure 2 As shown, Pwell is the body region, N-drift (blue region) is the drift region, N+ is the drain region, Poly-gate (green region) is the field plate made of polysilicon, and field oxide (gray region) is located between the drift region and the field plate. Figure 1 The surface of the field oxygen is flat, and the field plate on it is a single-level field plate. Figure 2 The surface of the field oxygen has a second-order step, and the field plate on it is a second-order field plate. The drift region and the curves in the field oxygen are electric field lines. Figure 1 and Figure 2 The distribution trend of electric field lines can be seen from this. Figure 2 The distribution of electric field lines in the relative Figure 1 The electric field lines are more evenly distributed, which alleviates the peak electric field.

[0034] Figure 3 To and Figure 1 and Figure 2 A schematic diagram of the electric field distribution under the field plate. (See diagram below.) Figure 3 As shown, the horizontal axis represents the position from the source region to the drain region (from left to right), and the vertical axis represents the electric field intensity in the substrate. The solid line represents... Figure 1 The electric field intensity distribution in the substrate (drift region) corresponding to the single-stage field plate, represented by the dashed line. Figure 2 The electric field intensity distribution in the substrate (drift region) corresponding to the secondary field plate. Figure 3 The displayed potential distribution and Figure 1 and Figure 2 The electric field lines in the two-stage field plate are basically corresponding, and the peak value of the electric field intensity corresponding to the second-stage field plate is lower than that corresponding to the single-stage field plate.

[0035] Therefore, as the voltage withstand requirements of devices increase, creating more steps on the field oxide surface to form more levels of field plates is a feasible solution for further optimizing the electric field. However, each additional level of field plate requires an additional deposition and patterning process, including at least one mask layer and corresponding photolithography and etching processes. Meanwhile, as the number of field plate levels increases, the problem of a large peak electric field near the drain becomes more prominent. In other words, simply adding more levels of field plates does not significantly improve the electric field, and it is difficult to simultaneously consider the electric field distribution in all regions of the drift region, especially the electric field distribution near the drain.

[0036] In view of this, embodiments of this application provide a semiconductor device and a method for fabricating the same. The semiconductor device includes: a substrate having a drift region and a drain region disposed in the drift region; a field oxide layer covering at least the surface of the drift region near the drain region; a first conductive layer located on the field oxide layer and disposed near the drain region; a first sidewall covering at least the sidewall of the first conductive layer; an isolation layer conformally covering at least the top wall of the first conductive layer, the first sidewall, and a portion of the surface of the field oxide layer in a direction away from the drain region, wherein the isolation layer has multiple steps on the top wall of the first conductive layer and on the side away from the drain region, and an arc-shaped transition is formed between the steps near the drain region; and a field plate located on the isolation layer and conformally covering at least the surface of the multiple steps. An unexpected effect of this application is that a first conductive layer is formed on the end of the field oxide layer near the drain region. This first conductive layer is covered by a first sidewall and an isolation layer and is suspended relative to the field plate. The combination of the suspended first conductive layer and the field plate (e.g., with a fixed potential) makes the electric field adjustment of the drift region more flexible, increases the degree of freedom of electric field adjustment, and achieves a more optimized adjustment effect, thereby improving the performance of the semiconductor device. Specifically, this application can adjust the electric field near the drain region separately through the floating first conductive layer while ensuring that the electric field is kept relatively suppressed at most locations of the entire drift region. This avoids excessive suppression of the drift region near the drain region, thereby optimizing the electric field adjustment of the entire drift region. Moreover, the first conductive layer can be used to form multiple steps above the drift region to form multiple levels of field plates, and the first sidewall can be used to form arc transitions between the multiple steps, so that the adjacent levels of the multiple levels of field plates form smooth transitions, which is conducive to a smooth transition of the electric field below. In addition, from the perspective of fabricating the semiconductor device, the first conductive layer and the gate conductive layer of the gate structure can be obtained by patterning the same conductive material, and the first sidewall and the second sidewall of the gate structure are formed simultaneously, so that the formation of the first conductive layer and the first sidewall of this application does not require additional process steps and masks, thereby simplifying the process and reducing costs.

[0037] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0038] Figure 4 This is a schematic diagram of a semiconductor device provided in an embodiment of this application. Figure 4As shown, the semiconductor device provided in this application embodiment can be a power device, such as an LDMOS (Laterally Diffused Metal-Oxide Field-Effect Transistor) device. The semiconductor device may include a substrate 100, in which a body region 110, a drift region 120, a source region 130, and a drain region 140 are provided. The body region 110 and the drift region 120 are connected. The source region 130 is disposed in the body region 110 and located on the side of the body region 110 away from the drift region 120. The drain region 140 is located in the drift region 120 and located on the side of the drift region 120 away from the body region 110. The body region 110 and the substrate 100 have the same conductivity type. The drift region 120, the source region 130, and the drain region 140 have the same conductivity type. The body region 110 and the drift region 120 have opposite conductivity types.

[0039] In some examples, the semiconductor device may be an NLDMOS (N-type laterally diffused metal-oxide field-effect transistor) device, the substrate 100 and body region 110 may be P-type, and the drift region 120, source region 130 and drain region 140 may be N-type.

[0040] In some examples, the doping depth of the drift region 120 is greater than that of the body region 110, and there is also an overlap between the body region 110 and the drift region 120 (i.e., the overlap region 101), for example, part of the body region 110 extends into the drift region 120.

[0041] Please continue to refer to Figure 4 The field oxide layer 201 covers the entire surface of the drift region 120, including the surface of the overlapping region 101. That is, one end of the drift region 120 is in contact with the edge of the drain region 140, and the other end is in contact with the edge of the body region 110 outside the overlapping region 101. The first conductive layer 210 is located on the end of the field oxide layer 201 near the drain region 140. The first sidewall 211 covers the sidewall of the first conductive layer 210, and the side of the first sidewall 211 away from the first conductive layer 210 has a smooth arc.

[0042] In some examples, the end of the first conductive layer 210 near the drain region 140 may be aligned or substantially aligned with the end of the field oxide layer 201 near the drain region 140, such that the first sidewall 211 away from the drain region 140 is located on the field oxide layer 201, while the first sidewall 211 near the drain region 140 is located on the edge of the drain region 140 and simultaneously covers the field oxide layer 201 and the sidewall of the first conductive layer 210 on that side.

[0043] In some examples, for practical process considerations, the end of the first conductive layer 210 near the drain region 140 can be recessed by a preset distance relative to the end of the field oxide layer 201 near the drain region 140. This preset distance can be approximately the thickness of a first sidewall 211, so that the first sidewalls 211 covering both sides of the first conductive layer 210 are located on the field oxide layer 201, avoiding the first sidewall 211 near the drain region 140 from being too thin or having a steep curve on the sidewall of the first conductive layer 210.

[0044] Please continue to refer to Figure 4 A gate structure and a second sidewall 209 covering the sidewalls of the gate structure are provided on the body region 110. The gate structure is located on the body region 110 between the source region 130 and the overlapping region 101, and includes a stacked gate oxide layer (i.e., a thinner oxide layer 203) and a gate conductive layer 205. The gate oxide layer covers the surface of the body region 110 and is connected to the field oxide layer 201. The thickness of the gate oxide layer is less than the thickness of the field oxide layer 201. The gate conductive layer 205 covers the surface of the gate oxide layer. In this application, the gate conductive layer 205 and the first conductive layer 210 have the same material and thickness. In other words, the gate conductive layer 205 and the first conductive layer 210 are obtained by patterning the same conductive material (e.g., polysilicon).

[0045] In some examples, the gate conductive layer 205 also includes an extension 207 that is connected to the gate conductive layer 205 on the gate oxide layer (integrated), that is, the gate conductive layer 205 extends from the surface of the gate oxide layer toward the drain region 140 and extends to cover part of the surface of the field oxide layer 201 to enhance the modulation capability of the gate structure to the electric field of the drift region 120, for example, covering the surface of the field oxide layer 201 above the overlapping region 101.

[0046] In some examples, the second sidewall 209 near the source region 130 is located on the body region 110, and the second sidewall 209 on the other side is located on the field oxide layer 201, covering the sidewall of the extension 207. The first sidewall 211 and the second sidewall 209 have the same material and thickness. In other words, the second sidewall 209 and the first sidewall 211 are patterned from the same sidewall material, which can be, for example, a stacked structure made of silicon oxide / silicon nitride / silicon oxide.

[0047] Please continue to refer to Figure 4The isolation layer 230 conformally covers the top wall of the first conductive layer 210, the first sidewall 211 on the field oxide layer 201, and at least a portion of the surface of the field oxide layer 201 in a direction away from the drain region 140. A secondary step 231 is formed on the top wall of the first conductive layer 210 and on the side away from the drain region 140. In the secondary step 231, the first step is the surface of the isolation layer 230 on the field oxide layer 201, which is located on the side of the first conductive layer 210 away from the drain region 140. The second step is the surface of the isolation layer 230 on the first conductive layer 210, which is located above the first conductive layer 210. The isolation layer 230 between the first and second steps has an arcuate transition formed by the first sidewall 211.

[0048] In some examples, the isolation layer 230 also extends along the surface of the field oxygen layer 201 toward the source region 130 and extends to cover the surface of the second sidewall 209 and part of the extension 207.

[0049] In some examples, the isolation layer 230 may be a stacked structure of silicon oxide / silicon nitride / silicon oxide.

[0050] Please continue to refer to Figure 4 The field plate 310 is located on the isolation layer 230 and conformally covers the surface of the secondary step 231. The field plate 310 may be made of a conductive material, such as a metal. The field plate 310 is conformal to the surface of the underlying isolation layer 230, thereby creating different vertical distances between it and different regions of the drift region 120 to modulate the surface electric field distribution of the drift region 120. Specifically, in the region of the field plate 310 near the drain region 140 and corresponding to the area above the first conductive layer 210 (i.e., the second-level step), the effective dielectric thickness between the field plate 310 and the surface of the drift region 120 is the largest; in the region of the field plate 310 corresponding to the slope of the first sidewall 211 (the arc transition between the second and first-level steps), the effective dielectric thickness is intermediate and decreases gradually away from the drain region 140; in the region of the field plate 310 away from the first conductive layer 210 (the first-level step), the effective dielectric thickness is the smallest. This gradual coupling relationship allows the electric field to be sequentially distributed to regions with different coupling strengths as it extends from the edge of the drain region 140 toward the gate, which is equivalent to the hierarchical modulation effect of the multi-level field plate 310 (i.e., the multi-level field plate 310). This effectively reduces the peak electric field near the drain end, improves the breakdown voltage of the device, and prevents surface electric field concentration and hot carrier deterioration.

[0051] In some examples, plugs 320 are also provided on the source region 130 and the drain region 140 for electrical lead-out. The plugs 320 can be made of metallic materials, such as tungsten or copper. The field plate 310 is made of the same material as the plugs 320, that is, the field plate 310 and the plugs 320 are obtained by the same metalworking process. It is understandable that during the metalworking process of forming the field plate 310, the isolation layer 230 serves as an etching stop layer, and it is unavoidable that the portion of the isolation layer 230 in contact with the field plate 310 is removed. That is, the isolation layer 230 in contact with the field plate 310 only retains a portion of the stacked structure (silicon oxide / silicon nitride / silicon oxide).

[0052] In some examples, the field plate 310 extends along the surface of the isolation layer 230 toward the gate structure and covers the surface of the isolation layer 230 on the second sidewall 209 (near the side of the extension 207). In the region of the field plate 310 corresponding to the slope of the second sidewall 209, the effective dielectric layer thickness between the field plate 310 and the surface of the drift region 120 gradually increases in the direction close to the gate structure, thereby adjusting the electric field through a smooth transition.

[0053] In some examples, the potential of the field plate 310 can be set as needed, for example, the field plate 310 can be grounded (at the same potential as the source region), electrically connected to the gate (at the same potential as the gate), or connected to another preset potential (fixed potential).

[0054] It should be noted that the first conductive layer 210 is not electrically connected and is in a floating state, without a fixed potential. It can be matched with the potential setting of the field plate 310, thereby making the electric field adjustment more flexible (increasing the degree of freedom of electric field adjustment) and achieving a more optimized adjustment effect. For example, in order to simultaneously control the electric field of different areas of the entire drift region 120, the fixed potential electrically connected to the field plate 310 is difficult to take into account the electric field distribution of the area near the drain region 140, which may excessively suppress the electric field of the area near the drain region 140. However, in this application, the end of the field plate 310 near the drain region 140 is relatively far away from the surface of the drift region 120, and a floating first conductive layer 210 is provided below it. Under the condition of ensuring that the electric field of the entire drift region 120 is kept relatively large, the floating first conductive layer 210 can form a suitable (relatively small) suppression of the electric field of the end of the drift region 120 near the drain region 140, avoiding excessive suppression of the end of the drift region 120 near the drain region 140.

[0055] Figure 5 for Figure 4 A schematic diagram of the electric field distribution of a semiconductor device. (See diagram below.) Figure 5 As shown, the horizontal axis represents the channel direction of the longitudinal section, and the vertical axis represents the depth direction of the longitudinal section. Different colors in the substrate represent different electric field intensities. The electric field intensities are higher in warm-colored areas (yellow and orange) and lower in cool-colored areas (green). The red curve in the figure represents the equipotential lines of the electric potential. Figure 5 As shown, through the multi-level field plate and the floating first conductive layer of this application, the electric field transitions smoothly from the body region to the drain region (the equipotential lines extend smoothly), and in particular, there are no spikes in the electric field below the multi-level field plate and the first conductive layer.

[0056] Figure 6 for Figure 4 A schematic diagram of the impact ionization rate distribution of a semiconductor device. (See diagram below.) Figure 6 As shown, the horizontal axis represents the channel direction of the longitudinal section, and the vertical axis represents the depth direction of the longitudinal section. Different colors in the substrate represent different collisional ionization rates. Warm-colored regions (yellow, orange, green) have higher collisional ionization rates, while cool-colored regions (blue) have lower collisional ionization rates. The red curve in the figure represents the equipotential lines of the electric potential. Figure 6 As shown, the collisional ionization rate of the multi-level field plate and the floating first conductive layer of this application transitions smoothly from the body region to the drain region (the equipotential lines extend smoothly), especially the collisional ionization rate below the multi-level field plate and the first conductive layer is reduced to invisible.

[0057] In a specific example, compared to using Figure 2 For semiconductor devices with secondary field plates, the electric field distribution diagram and the collisional ionization rate distribution diagram of this application can be referred to respectively. Figure 5 and Figure 6 Due to further optimization of the collisional ionization rate and electric field distribution near the drain region (below the first conductive layer), the breakdown voltage and hot carrier degradation of the semiconductor device are significantly improved. For example, the breakdown voltage can be increased from 38.413V to 44.45V after optimization. At the same time, after a standardized 1000-second accelerated stress test, the decay rate of the drain current in the linear region is significantly reduced from 4.3% before optimization to 0.6% after optimization.

[0058] Figure 7 This is a schematic diagram of another semiconductor device provided in an embodiment of this application. For example... Figure 7 As shown, the semiconductor device provided in this embodiment includes a substrate 100, a field oxide layer 201, a first conductive layer 210, a first sidewall 211, an isolation layer 230, and a field plate 310. The basic configuration and principle of each of the above structures are similar to those in the above embodiment. Among them, relative to... Figure 4The main difference in this embodiment is that, in this embodiment, the isolation layer 230 has a first opening 232 on the side away from the first conductive layer 210. Along the direction away from the drain region 140, the surface of the isolation layer 230 on the first conductive layer 210, the surface of the isolation layer 230 near the first sidewall 211, and the bottom surface of the first opening 232 form a three-tiered step 233, and the field plate 310 conformally covers the surface of the three-tiered step 233. Specifically, in the three-tiered step 233, the first tier is the bottom surface of the first opening 232 in the isolation layer 230, the second tier is the surface of the isolation layer 230 between the first opening 232 and the first sidewall 211, and the third tier is the surface of the isolation layer 230 on the first conductive layer 210. The isolation layer 230 between the second and third tiers has an arc-shaped transition formed by the first sidewall 211, but there is no such arc-shaped transition between the first and second tiers. Furthermore, viewed from the other side of the first opening 232, the bottom surface of the first opening 232 and the surface of the isolation layer 230 near the second side wall 209 can also form corresponding secondary steps.

[0059] Compared to Figure 4 In this embodiment, more steps are formed on the surface of the isolation layer 230 to form more levels of field plates 310, which can help to further refine the control of the electric field and optimize the electric field distribution.

[0060] In some examples, the depth of the first opening 232 can be determined according to the requirements. For example, based on the minimum spacing requirement between the field plate 310 and the drift area 120, the depth of the first opening 232 can be less than, equal to or greater than the depth of the isolation layer 230. In other words, the first opening 232 can cut off or not cut off the isolation layer 230, or even partially extend into the field oxygen layer 201, which is feasible.

[0061] Figure 8 This is a schematic diagram of yet another semiconductor device provided in an embodiment of this application. (See diagram below.) Figure 8 As shown, the semiconductor device provided in this application embodiment includes a substrate 100, a field oxide layer 201, a first conductive layer 210, a first sidewall 211, an isolation layer 230, and a field plate 310. The basic configuration and basic principle of the above structures are similar to those of the semiconductor device provided in this application embodiment. Figure 4 The embodiments are similar. Among them, relative Figure 4The main difference in this embodiment is that, in this embodiment, the field oxide layer 201 has a second opening 234 on the side away from the first conductive layer 210, and the first sidewall 211 also covers the sidewall (inner sidewall) of the second opening 234. The insulating layer 230 conformally covers the surfaces of the first conductive layer 210, the first sidewall 211, the field oxide layer 201, and the inner wall of the second opening 234. Along the direction away from the drain region 140, the surface of the insulating layer 230 on the first conductive layer 210, the surface of the insulating layer 230 near the first sidewall 211, and the surface of the insulating layer 230 at the bottom of the second opening 234 form a three-level step 233, and the field plate 310 conformally covers the surface of the three-level step 233. Specifically, in the three-stage step 233, the first stage step is the surface of the isolation layer 230 on the bottom surface of the second opening 234 in the field oxygen layer 201, the second stage step is the surface of the isolation layer 230 between the second opening 234 and the first conductive layer 210, and the third stage step is the surface of the isolation layer 230 on the first conductive layer 210. The isolation layer 230 between the second and third stages has an arc-shaped transition formed by the first sidewall 211, and there is also an arc-shaped transition between the first and second stages formed by the first sidewall 211.

[0062] In some examples, the depth of the second opening 234 can be determined according to requirements. For example, based on the minimum spacing requirement between the field plate 310 and the drift zone 120, the depth of the second opening 234 can be less than or equal to the depth of the field oxygen layer 201. In other words, the second opening 234 can cut off or not cut off the isolation layer 230.

[0063] Compared to Figure 4 In this embodiment, more steps are formed on the surface of the isolation layer 230 to form more levels of field plates 310, which can facilitate further refinement of the electric field control and optimization of the electric field distribution. Compared to Figure 7 In the embodiment of the three-stage steps 233, the first and second stages also have an arc-shaped transition formed by the first sidewall 211, which can further smooth (uniform) the electric field distribution in the drift region 120.

[0064] It should be noted that, in the above Figure 4 , Figure 7 and Figure 8 In some embodiments, the field plate 310 is a single, continuous segment. However, in other embodiments of this application, the field plate 310 may be at least two separate parts (truncated into at least two segments), meaning that the portion above the drift region 120 is not equipped with the field plate 310, allowing for further fine-tuning of the electric field. Furthermore, in some embodiments, the field oxygen layer 201 and the isolation layer 230 corresponding to the field plate 310 may also be truncated into at least two matching segments.

[0065] This application also provides a method for fabricating a semiconductor device. Figure 9 A flowchart of a method for fabricating a semiconductor device according to an embodiment of this application is provided, used to form such a... Figure 4 The semiconductor device shown. (As shown) Figure 9 As shown, an embodiment of this application provides a method for fabricating a semiconductor device including: S100: A substrate is provided, the substrate having a drift region and a drain region disposed in the drift region; S200: Form a field oxygen layer that at least covers the surface of the drift region near the leak region; S300: Forming a gate structure and a first conductive layer, wherein the gate structure is located on the substrate and includes a gate conductive layer, the first conductive layer is located on the field oxide layer and disposed near the drain region, and the gate structure and the first conductive layer are obtained by patterning the same conductive material; S400: Form a first sidewall that at least covers the sidewall of the first conductive layer; S500: Form an isolation layer that conformally covers at least a portion of the top wall of the first conductive layer, the first sidewall, and the surface of the field oxide layer in a direction away from the drain region. The isolation layer has multiple steps on the top wall of the first conductive layer and on the side away from the drain region, and an arc transition is formed between the steps near the drain region. S600: A field plate is formed on the isolation layer, the field plate at least conformally covering the surface of the multi-level steps.

[0066] Figures 10-15 This is a schematic diagram of the structure corresponding to the respective steps of the method for fabricating a semiconductor device according to an embodiment of this application. Next, we will combine... Figures 10-15 The method for fabricating the semiconductor device provided in this application will be described in detail.

[0067] First, please refer to Figure 10 Step S100 is performed, providing a substrate 100, which has a drift region 120 and a drain region 140 disposed in the drift region 120.

[0068] The substrate 100 can be a substrate suitable for forming power devices, and its material can be, for example, silicon, silicon carbide, gallium nitride, etc. The substrate 100 has a body region 110, a drift region 120, a source region 130, and a drain region 140. The body region 110 and the drift region 120 are connected. The source region 130 is disposed in the body region 110 and is located on the side of the body region 110 away from the drift region 120. The drain region 140 is located in the drift region 120 and is located on the side of the drift region 120 away from the body region 110. The body region 110 and the substrate 100 have the same conductivity type. The drift region 120, the source region 130, and the drain region 140 have the same conductivity type. The body region 110 and the drift region 120 have opposite conductivity types.

[0069] In some examples, the semiconductor device may be an NLDMOS device, the substrate 100 and body region 110 may be P-type, and the drift region 120, source region 130 (to be defined) and drain region 140 (to be defined) may be N-type.

[0070] In some examples, the doping depth of the drift region 120 is greater than that of the body region 110, and there is also an overlap between the body region 110 and the drift region 120 (overlapping region 101), for example, part of the body region 110 extends into the drift region 120.

[0071] Next, please refer to Figure 11 Step S200 is executed to form a field oxygen layer 201, which at least covers the surface of the drift region 120 near the leak region 140.

[0072] A relatively thick oxide layer can be formed through thermal oxidation and deposition processes, and this thick oxide layer is patterned, retaining the portion covering the drift region 120 as the field oxide layer 201. This field oxide layer 201 covers the entire surface of the drift region 120, including the surface of the overlapping region 101, i.e., one end of the drift region 120 is connected to the edge of the drain region 140, and the other end is connected to the edge of the body region 110 outside the overlapping region 101. Furthermore, a relatively thin oxide layer 203 can be formed (retained) on the surfaces of the body region 110 (outside the overlapping region 101), the source region 130, and the drain region 140. The remaining relatively thin oxide layer 203 on the body region 110 can serve as a subsequent gate oxide layer.

[0073] Next, please refer to Figure 12 In step S300, a gate structure and a first conductive layer 210 are formed. The gate structure is located on the substrate 100 and includes a gate conductive layer 205. The first conductive layer 210 is located on the field oxide layer 201 and is disposed near the drain region 140. The gate conductive layer 205 and the first conductive layer 210 are obtained by patterning the same conductive material.

[0074] The steps of forming the gate conductive layer 205 and the first conductive layer 210 may include, for example, forming a conductive material that conformally covers the entire surface of the substrate 100, the conductive material being, for example, polysilicon, and forming it by a CVD process; then, performing a patterning process on the conductive material, using the remaining conductive material on the gate oxide layer of the body region 110 as the gate conductive layer 205, and using the remaining conductive material on the field oxide layer 201 as the first conductive layer 210.

[0075] In some examples, the end of the first conductive layer 210 near the drain region 140 may be recessed by a predetermined distance relative to the end of the field oxide layer 201 near the drain region 140, which may be approximately the thickness (width) of a sidewall (i.e., the first sidewall).

[0076] In some examples, the gate conductive layer 205 further includes an extension 207 connected to the gate conductive layer 205 on the gate oxide layer. That is, the gate conductive layer 205 extends from the surface of the gate oxide layer toward the drain region 140 and extends to cover part of the surface of the field oxide layer 201 to enhance the modulation capability of the gate structure to the electric field of the drift region 120, for example, covering the surface of the field oxide layer 201 above the overlapping region 101.

[0077] Next, please refer to Figure 13 Step S400 is executed to form a first sidewall 211 that at least covers the sidewall of the first conductive layer 210.

[0078] The gate structure also has a second sidewall 209. The second sidewall 209 and the first sidewall 211 can be obtained by dry etching of the same sidewall material. The sidewall material can be, for example, a stacked structure of silicon oxide / silicon nitride / silicon oxide.

[0079] Next, please refer to Figure 14 In step S500, an isolation layer 230 is formed. The isolation layer 230 conformally covers at least a portion of the top wall of the first conductive layer 210, the first sidewall 211, and the surface of the field oxide layer 201 in a direction away from the drain region 140. The isolation layer 230 has multiple steps on the top wall of the first conductive layer 210 and on the side away from the drain region 140. An arc transition is formed between the steps near the drain region 140.

[0080] In some examples, the isolation layer 230 may be a silicon oxide / silicon nitride / silicon oxide stacked structure. The step of forming the isolation layer 230 may include: sequentially forming each layer in the stacked structure so that each layer conformally covers the entire surface of the substrate 100; then, patterning the stacked structure and retaining only the portion of the stacked structure located above the drift region 120 as the isolation layer 230. The isolation layer 230 conformally covers the top wall of the first conductive layer 210, the first sidewall 211 on the field oxide layer 201, and at least a portion of the surface of the field oxide layer 201 in a direction away from the drain region 140. A secondary step 231 is formed on the top wall of the first conductive layer 210 and on the side away from the drain region 140. In the secondary step 231, the first step is the surface of the isolation layer 230 on the field oxide layer 201, which is located on the side of the first conductive layer 210 away from the drain region 140. The second step is the surface of the isolation layer 230 on the first conductive layer 210, which is located above the first conductive layer 210. The isolation layer 230 between the first and second steps has an arcuate transition formed by the first sidewall 211.

[0081] In some examples, the isolation layer 230 also extends along the surface of the field oxygen layer 201 toward the source region 130 and extends to cover the surface of the second sidewall 209 and part of the extension 207.

[0082] Next, please refer to Figure 15 Step S600 is performed to form a field plate 310 on the isolation layer 230, the field plate 310 at least conformally covering the surface of the multi-step.

[0083] In some examples, the field plate 310 can be made of metal, such as tungsten or copper, and can be formed simultaneously with the plugs 320 on the source region 130 and the drain region 140. In this metal process, the isolation layer 230 serves as an etching stop layer, and it is also possible to remove the portion of the isolation layer 230 that is in contact with the field plate 310.

[0084] In some examples, the field plate 310 may extend along the surface of the isolation layer 230 on the secondary step 231 toward the gate structure and extend to cover the surface of the isolation layer 230 on the second sidewall 209 (on the side of the extension 207).

[0085] This application also provides a method for fabricating a semiconductor device, used to form such a semiconductor device. Figure 7 The semiconductor device shown. Compared to the aforementioned fabrication method, such as... Figure 7As shown, in the preparation method of this application embodiment, after forming the isolation layer 230, a first opening 232 is also formed in the isolation layer 230. The first opening 232 is located in the middle position of the isolation layer 230, and the isolation layer 230 can be cut into two parts (two segments) for example, so that the surface of the isolation layer 230 on the first conductive layer 210, the surface of the isolation layer 230 near the first sidewall 211 and the bottom surface of the first opening 232 form a three-level step 233, and the field plate 310 covers the surface of the three-level step 233.

[0086] This application also provides a method for fabricating a semiconductor device, used to form such a semiconductor device. Figure 8 The semiconductor device shown. Compared to the aforementioned fabrication method, such as... Figure 8 As shown, in the preparation method of this application embodiment, after forming the field oxygen layer 201, a second opening 234 is also formed in the field oxygen layer 201. The second opening 234 may be located in the middle of the field oxygen layer 201, and the field oxygen layer 201 may be cut into two parts (two segments), for example. When forming the first sidewall 211, the first sidewall 211 also covers the inner sidewall of the second opening 234. When forming the isolation layer 230, the isolation layer 230 conformally covers the surface of the first conductive layer 210, the first sidewall 211, the field oxygen layer 201, and the inner wall of the second opening 234, so that the surface of the isolation layer 230 on the first conductive layer 210, the surface of the isolation layer 230 near the first sidewall 211, and the surface of the isolation layer 230 at the bottom of the second opening 234 constitute a three-level step 233.

[0087] In summary, embodiments of this application provide a semiconductor device and a method for fabricating the same. The semiconductor device includes: a substrate having a drift region and a drain region disposed in the drift region; a field oxide layer covering at least the surface of the drift region near the drain region; a first conductive layer located on the field oxide layer and disposed near the drain region; a first sidewall covering at least the sidewall of the first conductive layer; an isolation layer conformally covering at least the top wall of the first conductive layer, the first sidewall, and a portion of the surface of the field oxide layer in a direction away from the drain region, wherein the isolation layer has multiple steps on the top wall of the first conductive layer and on the side away from the drain region, and an arc-shaped transition is formed between the steps near the drain region; and a field plate located on the isolation layer and conformally covering at least the surface of the multiple steps. An unexpected effect of this application is that a first conductive layer is formed on the end of the field oxide layer near the drain region. This first conductive layer is covered by a first sidewall and an isolation layer and is suspended relative to the field plate. The combination of the suspended first conductive layer and the field plate (e.g., with a fixed potential) makes the electric field adjustment of the drift region more flexible, increases the degree of freedom of electric field adjustment, and achieves a more optimized adjustment effect, thereby improving the performance of the semiconductor device. Specifically, this application can adjust the electric field near the drain region separately through the floating first conductive layer while ensuring that the electric field is kept relatively suppressed at most locations of the entire drift region. This avoids excessive suppression of the drift region near the drain region, thereby optimizing the electric field adjustment of the entire drift region. Moreover, the first conductive layer can be used to form multiple steps above the drift region to form multiple levels of field plates, and the first sidewall can be used to form arc transitions between the multiple steps, so that the adjacent levels of the multiple levels of field plates form smooth transitions, which is conducive to a smooth transition of the electric field below. In addition, from the perspective of fabricating the semiconductor device, the first conductive layer and the gate conductive layer of the gate structure can be obtained by patterning the same conductive material, and the first sidewall and the second sidewall of the gate structure are formed simultaneously, so that the formation of the first conductive layer and the first sidewall of this application does not require additional process steps and masks, thereby simplifying the process and reducing costs.

[0088] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the systems disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and relevant parts can be referred to the method section.

[0089] It should also be noted that although preferred embodiments have been disclosed above, these embodiments are not intended to limit this application. Any person skilled in the art can make many possible variations and modifications to the technical solutions of this application, or modify them into equivalent embodiments, without departing from the scope of the technical solutions of this application. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of this application, without departing from the content of the technical solutions of this application, shall still fall within the scope of protection of the technical solutions of this application.

[0090] It should also be understood that, unless otherwise specified or indicated, the terms “first,” “second,” “third,” etc., in the specification are used only to distinguish the various components, elements, and steps in the specification, and not to indicate the logical or sequential relationships between the various components, elements, and steps.

[0091] Furthermore, it should be recognized that the terminology described herein is used only to describe particular embodiments and is not intended to limit the scope of this application. It must be noted that the singular forms “a” and “an” as used herein include plural bases unless the context clearly indicates the opposite. For example, a reference to “a step” or “an apparatus” means a reference to one or more steps or apparatuses, and may include secondary steps and secondary apparatuses. All conjunctions used should be understood in the broadest sense. Also, the word “or” should be understood as having the definition of logical “or”, not logical “exclusive OR”, unless the context clearly indicates the opposite. Furthermore, implementations of the methods and / or devices in the embodiments of this application may include performing selected tasks manually, automatically, or in combination.

Claims

1. A semiconductor device, characterized in that, include: A substrate having a drift region and a drain region disposed in the drift region; An oxygen layer, at least covering the surface of the drift region near the leak region; A first conductive layer is located on the field oxygen layer and is disposed close to the drain region; The first sidewall at least covers the sidewall of the first conductive layer; An isolation layer conformally covers at least a portion of the top wall of the first conductive layer, the first sidewall, and the surface of the field oxide layer in a direction away from the drain area. The isolation layer has a first opening on the side away from the first conductive layer, and the isolation layer surface on the first conductive layer, the isolation layer surface near the first sidewall, and the bottom surface of the first opening form three steps in a direction away from the drain area. Alternatively, the field oxide layer has a second opening on the side away from the first conductive layer, and the isolation layer conformally covers the surfaces of the first conductive layer, the first sidewall, the field oxide layer, and the inner wall of the second opening. The isolation layer surface on the first conductive layer, the isolation layer surface near the first sidewall, and the isolation layer surface at the bottom of the second opening form three steps in a direction away from the drain area. A field plate is located on the isolation layer and at least conformally covers the surface of the three-tiered steps, wherein an arc-shaped transition is formed between the steps closest to the leak area.

2. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes a gate structure and a second sidewall, the second sidewall covering the sidewall of the gate structure, the gate structure including a gate conductive layer. The gate conductive layer has the same material and thickness as the first conductive layer, and / or the second sidewall has the same material as the first sidewall.

3. The semiconductor device according to claim 2, characterized in that, The gate conductive layer further includes an extension that covers a portion of the surface of the field oxide layer near the gate structure. The extension has a second sidewall on the side near the drain region. The isolation layer covers the surface of the extension and the surface near the second sidewall of the extension. The field plate conformally covers the isolation layer on the second sidewall.

4. The semiconductor device according to claim 1, characterized in that, The isolation layer and / or the first sidewall comprises a stacked structure consisting of silicon oxide / silicon nitride / silicon oxide groups.

5. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes a plug located on the drain region, and the field plate is made of the same material as the plug.

6. A method for fabricating a semiconductor device, characterized in that, The method for preparing the semiconductor device as described in any one of claims 1 to 5 comprises: A substrate is provided, the substrate having a drift region and a drain region disposed in the drift region; A field oxygen layer is formed, at least covering the surface of the drift region near the leak region; A gate structure and a first conductive layer are formed. The gate structure is located on the substrate and includes a gate conductive layer. The first conductive layer is located on the field oxide layer and is disposed near the drain region. The gate conductive layer and the first conductive layer are obtained by patterning the same conductive material. A first sidewall is formed, at least covering the sidewall of the first conductive layer; An isolation layer is formed, which conformally covers at least a portion of the top wall of the first conductive layer, the first sidewall, and the surface of the field oxygen layer in a direction away from the drain area. The isolation layer has three steps on the top wall of the first conductive layer and on the side away from the drain area, and an arc transition is formed between the steps closer to the drain area. A field plate is formed on the isolation layer, the field plate at least conformally covering the surface of the three steps.

7. The method for fabricating a semiconductor device according to claim 6, characterized in that, After the isolation layer is formed, a first opening is also formed in the isolation layer. The first opening is located on the side of the isolation layer away from the first conductive layer, so that the surface of the isolation layer on the first conductive layer, the surface of the isolation layer near the first sidewall, and the bottom surface of the first opening constitute the three-level steps.

8. The method for fabricating a semiconductor device according to claim 6, characterized in that, After the field oxygen layer is formed, a second opening is also formed in the field oxygen layer; After the field oxygen layer is formed, a second opening is also formed in the field oxygen layer; When the first sidewall is formed, the first sidewall also covers the inner sidewall of the second opening; When the isolation layer is formed, the isolation layer conformally covers the surfaces of the first conductive layer, the first sidewall, the field oxygen layer, and the inner wall of the second opening, such that the isolation layer surface on the first conductive layer, the isolation layer surface near the first sidewall, and the isolation layer surface at the bottom of the second opening constitute the three-level steps.

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