Semiconductor structure and method of fabricating the same

Abstract

The application relates to a semiconductor structure and a manufacturing method thereof. After a seed layer is formed, the seed layer is oxidized to make at least part of the overhanging portion be oxidized into an oxide layer, then the seed layer is infiltrated by a wetting liquid to dissolve and remove the oxide layer, so as to remove or thin the overhanging portion, avoid the conductive metal from being prematurely sealed at the opening of the groove, improve the electroplating cavity, improve the quality of the metal interconnection structure, and improve the product yield and reliability.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] As the feature size of semiconductor devices continues to shrink, copper interconnect technology has become a key process in integrated circuit manufacturing, particularly in advanced chip manufacturing processes at 55nm and below. Currently, copper interconnects are typically formed using the damascus process, which involves first etching trenches in a dielectric layer, then depositing a copper seed layer, and finally filling the copper layer using electrochemical plating (ECP).

[0003] However, in the Damascus process, plating voids are a significant factor affecting chip yield and reliability. Summary of the Invention

[0004] Therefore, it is necessary to provide a semiconductor structure and its fabrication method to address the problems in the existing technology.

[0005] In a first aspect, this application provides a method for fabricating a semiconductor structure, comprising:

[0006] A substrate is provided, on which a dielectric layer is formed, and trenches are formed in the dielectric layer;

[0007] A seed layer is formed, which covers the trench walls and the top surface of the medium layer, and a cantilever is formed at the top of the trench;

[0008] The seed layer is oxidized, at least the overhanging portion is oxidized, to form an oxide layer;

[0009] The oxidized seed layer is wetted with a wetting solution to remove the oxidized layer, thereby removing or thinning the overhang.

[0010] Electroplating a conductive metal into the trench fills the trench.

[0011] In one embodiment, prior to the oxidation treatment of the seed layer, the method further includes:

[0012] A metal salt solution is injected into the trench. After injection, the liquid level of the metal salt solution in the trench is lower than the opening of the trench, exposing the overhang.

[0013] After the seed layer is oxidized, the metal salt solution in the trench is drained to expose the seed layer inside the trench.

[0014] In one embodiment, the seed layer is subjected to ultraviolet light-assisted oxidation or thermal oxidation to form the oxide layer.

[0015] In one embodiment, the seed layer is treated with ultraviolet light-assisted oxidation, including:

[0016] Ultraviolet light is used to excite oxygen-containing gas to generate oxygen free radicals. The exposed surface of the seed layer is then treated with these oxygen free radicals to form the oxide layer.

[0017] In one embodiment, during the process of wetting the oxidized seed layer with the wetting liquid, the unoxidized seed layer in the trench is also wetted by the wetting liquid, and the wetting contact angle of the substrate is reduced after wetting.

[0018] In one embodiment, during the process of wetting the oxidized seed layer with a wetting solution, the first ions in the wetting solution form a hydrophilic adsorption layer on the surface of the seed layer, and the hydrophilic adsorption layer reduces the wetting contact angle of the substrate surface.

[0019] In one embodiment, the seed layer is a copper seed crystal layer, the metal salt solution is a saturated copper sulfate solution, the wetting solution is an acidic aqueous solution of metallic copper, and the wetting solution includes a first ion.

[0020] In one embodiment, the first ion is a chloride ion; the wetting solution comprises an acidic aqueous solution of copper ions, sulfate ions and chloride ions.

[0021] In one embodiment, after electroplating conductive metal into the trench and filling the trench, the process further includes: grinding to remove the conductive metal and the seed layer from the top surface of the dielectric layer, thereby forming a metal interconnect structure in the trench.

[0022] In a second aspect, this application provides a semiconductor structure fabricated using the semiconductor structure fabrication method described in the first aspect; the semiconductor structure includes a substrate, a dielectric layer disposed on the substrate, trenches disposed on the dielectric layer, and metal interconnect structures disposed in the trenches.

[0023] The unexpected technical effect of this application is that, after the formation of the seed layer, the semiconductor structure and its fabrication method are oxidized to form an oxide layer, and then the seed layer is wetted with a wetting solution to dissolve and remove the oxide layer, thereby removing or thinning the overhang, avoiding premature sealing of the conductive metal at the opening of the trench, thereby improving electroplating voids, improving the quality of the metal interconnect structure, and improving product yield and reliability. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This is a process flow diagram of a method for fabricating a semiconductor structure provided in an exemplary embodiment of this application;

[0026] Figure 2 This is a schematic diagram of the structure after a seed layer is formed in a trench and a metal salt solution is injected, as provided in an exemplary embodiment of this application.

[0027] Figure 3 This is a schematic diagram of the structure after the metal salt solution is partially discharged and the hanging portion is exposed, as provided in an exemplary embodiment of this application.

[0028] Figure 4 This is a schematic diagram of the structure after the oxide seed layer is formed into an oxide layer, as provided in an exemplary embodiment of this application;

[0029] Figure 5 This is a schematic diagram of the structure after all the metal salt solution in the draining trench is discharged, as provided in an exemplary embodiment of this application.

[0030] Figure 6 This is a schematic diagram of the structure of the seed layer after treatment with a wetting agent in an exemplary embodiment of this application;

[0031] Figure 7 This is a schematic diagram of the structure after the electroplated conductive metal has filled the trench in an exemplary embodiment of this application;

[0032] Figure 8 This is a schematic diagram of the structure after the metal interconnect structure is formed in an exemplary embodiment of this application.

[0033] Explanation of reference numerals in the attached figures:

[0034] 31. Dielectric layer; 32. Trench; 33. Seed layer; 34. Overhang; 35. Conductive metal layer; 36. Metal interconnect structure; 37. Hydrophilic adsorption layer; 38. Oxide layer. Detailed Implementation

[0035] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0037] Embodiments of the invention are described herein with reference to cross-sectional views illustrating ideal embodiments (and intermediate structures) of this application, thus allowing for variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of this application should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For instance, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of this application.

[0038] In the Damascus process, the formation of plating voids can be attributed to two main factors: First, physical vapor deposition (PVD) is typically used to deposit the seed layer. Due to the inherent directional characteristics of PVD, overhangs easily form at the top of the trench opening. These overhangs reduce the trench opening width, leading to premature sealing of the opening during subsequent plating filling. This traps electrolyte or voids within the trench, resulting in plating voids. Second, in the initial stage of the plating process, when the wafer enters the wetting solution, surface tension exists at the solid-liquid interface between the dry wafer surface and the wetting solution. The high aspect ratio of the trench easily traps gas, forming bubbles. These bubbles prevent copper deposition during the plating process, thus creating plating voids.

[0039] In some solutions, the size of the overhang is reduced by optimizing the physical vapor deposition process. However, due to limitations in equipment cost and process complexity, it is difficult to completely eliminate the overhang. Other solutions employ deionized water pre-wetting of the wafer to remove gas from the microstructure. While deionized water pre-wetting can partially remove gas, the compositional difference between pure water and the subsequent wetting solution may still introduce microbubbles during liquid exchange. Furthermore, deionized water cannot improve the chemical state of the seed layer surface.

[0040] Therefore, how to effectively eliminate overhangs and improve wafer surface wettability before electroplating, thereby fundamentally suppressing the formation of void defects, is a technical problem that urgently needs to be solved in this field.

[0041] According to an exemplary embodiment, this embodiment provides a method for fabricating a semiconductor structure, such as... Figure 1 As shown, in conjunction with reference Figures 2-8 The method for fabricating a semiconductor structure includes the following steps:

[0042] Step S101: Provide a substrate (not shown in the figure), on which a dielectric layer 31 is formed, and trenches 32 are formed.

[0043] Step S102: Form a seed layer 33, which covers the trench wall of the trench 32 and the top surface of the medium layer 31, and form a hanging portion 34 at the top of the trench 32.

[0044] Step S103: Oxidize the seed layer 33, at least oxidize the overhang 34, to form an oxide layer 38.

[0045] Step S104: Wet the oxidized seed layer 33 with a wetting solution to remove the oxide layer 38, thereby removing or thinning the overhang 34.

[0046] Step S105: Electroplating conductive metal into the trench 32 to fill the trench 32.

[0047] In the semiconductor structure fabrication method of this embodiment, after forming the seed layer 33, the seed layer 33 is oxidized so that at least a portion of the overhang 34 is oxidized to form an oxide layer 38. Then, the seed layer 33 is wetted with a wetting solution to dissolve and remove the oxide layer 38, thereby removing or thinning the overhang 34. This prevents the conductive metal from prematurely sealing at the opening of the trench 32, thereby improving electroplating voids, enhancing the quality of the metal interconnect structure 36, and improving product yield and reliability.

[0048] Below, in conjunction with reference Figures 2-8 The process of fabricating the semiconductor structure in this embodiment will be further explained.

[0049] In step S101, the substrate may be composed of semiconductor material, insulating material, conductive material, or any combination thereof. The substrate may be a single-layer structure or a multi-layer structure. For example, the substrate may be a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon-germanium-carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V or II / VI semiconductor substrates. Alternatively, for example, the substrate may be a layered substrate comprising materials such as Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator. Therefore, the type of substrate should not limit the scope of this disclosure.

[0050] Understandably, referring to Figure 2 In this embodiment, the substrate has undergone multiple processing steps before the formation of the dielectric layer 31. One or more stacked semiconductor device layers can be formed on or in the substrate. Each semiconductor device layer can contain various semiconductor devices and various metal interconnects. The semiconductor devices can include at least one of metal-oxide-semiconductor field-effect transistors, bipolar junction transistors, resistors, inductors, diodes, and optical devices.

[0051] In this embodiment, a dielectric layer 31 is formed on the substrate. The material of the dielectric layer 31 includes, but is not limited to, silicon oxide, silicon nitride, silicon carbide, or silicon oxynitride, and its dielectric constant (k value) is less than 3.0 to reduce interconnect delay.

[0052] In this embodiment, refer to Figure 2 A trench 32 is formed in the dielectric layer 31. The trench 32 may penetrate the dielectric layer 31 or may not penetrate it; this embodiment does not impose any limitations on this. The trench 32 for copper interconnection can be formed in the dielectric layer 31 using photolithography and etching processes. The trench 32 has a high aspect ratio. For example, the aspect ratio of the trench 32 is 3:1 to 10:1, and further, the aspect ratio of the trench 32 is 5:1 or higher. The formation process of the trench 32 includes: coating photoresist on the dielectric layer 31, forming a pattern through exposure and development, then performing dry etching using fluorocarbon-based plasma to transfer the pattern to the dielectric layer 31, and finally removing the photoresist and performing wet cleaning.

[0053] In step S102, refer to Figure 2 A barrier layer (not shown) and a copper seed layer are sequentially deposited on the surface of the dielectric layer 31 and within the trench 32 using physical vapor deposition. The seed layer 33 covers the bottom wall, sidewalls of the trench 32, and the top surface of the dielectric layer 31. Due to the directional deposition of the physical vapor deposition process, the thickness at the top of the opening is greater than the thickness at the bottom and sidewalls, forming a cantilever 34 at the top of the opening of the trench 32. The barrier layer can be a single-layer or multi-layer structure, and the material of the barrier layer includes at least one of tantalum or tantalum nitride, titanium or titanium nitride; the seed layer 33 can be a copper seed layer.

[0054] In step S103, refer to Figure 4 The seed layer 33 is subjected to targeted oxidation treatment to oxidize the overhang 34, forming an oxide layer 38 at least on the surface of the overhang 34, so that the material of the overhang 34 is different from the material of the unoxidized seed layer 33, so as to facilitate the subsequent removal or reduction of the overhang 34.

[0055] In some embodiments, the seed layer 33 is subjected to ultraviolet light-assisted oxidation treatment or thermal oxidation treatment to form an oxide layer 38.

[0056] In some embodiments, prior to oxidizing the seed layer 33, the method further includes: referring to Figure 2 A metal salt solution is injected into the trench 32. In this embodiment, the metal salt solution can be a copper sulfate solution, or other inert salt solutions that do not react with the seed layer 33. During the injection process, the injection volume can be controlled so that the liquid level of the metal salt solution in the trench 32 is lower than the opening of the trench 32, thereby exposing the overhang 34 located at the top of the opening above the liquid surface, while the seed layer 33 on the bottom and side walls of the trench 32 is submerged below the liquid surface and protected. Maintaining the above liquid level state, refer to... Figure 4 The exposed seed layer 33 is oxidized. Since the overhang 34 is exposed to the gas phase environment, it can directly contact the oxidizing atmosphere. The seed layer 33 inside the trench 32 is covered by a metal salt solution and isolated from the oxidizing atmosphere. Under these conditions, only the exposed overhang 34 is oxidized and converted into copper oxide, while the seed layer 33 below the liquid surface remains in the state of metallic copper.

[0057] This ensures that the overhang 34 is exposed to the liquid surface and fully oxidized, while the seed layer 33 inside the trench 32 is protected by the solution, resulting in extremely low oxidation and maximizing its preservation. This allows the oxide layer 38 to be basically formed in the overhang 34 area, enabling more precise removal of the oxide layer 38 formed in the overhang 34 in subsequent steps. Removing or reducing the overhang 34 improves the problem of reduced opening linewidth caused by the overhang 34 and prevents the conductive metal from sealing the opening of the trench 32 prematurely, thereby improving electroplating voids.

[0058] In some embodiments, refer to Figure 2 After filling the trench 32 with the metal salt solution, ensure that the inside of the trench 32 is completely filled with the solution and that there is no gas residue; then, refer to Figure 3 Then, a portion of the metal salt solution is drained to control the liquid level. Seed layer 33 is a copper seed crystal layer, and the metal salt solution can be a saturated copper sulfate solution. The copper sulfate solution contains a high concentration of copper ions, which can inhibit the dissolution of copper in seed layer 33 in the solution.

[0059] In this embodiment, a copper sulfate solution, which is homologous to copper ions, is selected to avoid introducing contamination from foreign ions. It is understood that in other embodiments, other inert electrolytes, such as potassium sulfate, sodium sulfate, or sodium chloride solutions, may be used as the metal salt solution.

[0060] For example, some of the metal salt solution in the trench 32 can be removed by heating until the overhang 34 is exposed. Heating can precisely control the liquid level of the metal salt solution, so that the metal salt solution is just exposed below the overhang 34, thereby maximizing the protection of the seed layer 33 in the trench 32.

[0061] After the oxidation treatment is completed, refer to Figure 5 The metal salt solution in the trench 32 is drained to expose the unoxidized seed layer 33 within the trench 32. The draining method can be rotary spin drying, nitrogen purging, or natural flow to ensure that the solution is completely removed and no residue remains.

[0062] In step S104, refer to Figure 6 The oxidized seed layer 33 is wetted with a wetting solution to remove the oxide layer 38, thereby removing or thinning the overhang 34. The wetting solution is an acidic aqueous solution of metallic copper, containing a first ion. Further, the first ion is chloride ion; the wetting solution is an acidic aqueous solution containing copper ions, sulfate ions, and chloride ions. In this embodiment, the wetting solution is an acidic copper sulfate aqueous solution without organic additives and contains chloride ions. The oxidized seed layer 33 is wetted with the wetting solution. The oxide layer 38 is made of copper oxide. The copper oxide reacts chemically with the sulfuric acid in the wetting solution, selectively dissolving the copper oxide at the overhang 34, thereby eliminating or significantly reducing the overhang 34, while the bottom metallic copper seed layer remains largely unaffected. Afterwards, the wetting solution in the trench 32 is drained.

[0063] The wetting solution used in this embodiment has extremely strong hydrophilicity, which increases the wetting angle better than using deionized water for wetting. This further reduces the surface tension between the electroplating solution and the seed layer 33 during the subsequent electroplating process, which is beneficial to improving the electroplating filling effect.

[0064] In some embodiments, refer to Figure 6 During the process of wetting the oxidized seed layer 33 with a wetting solution, the first ions in the wetting solution form a hydrophilic adsorption layer 37 on the surface of the seed layer 33, which reduces the wetting contact angle of the substrate surface. In this embodiment, during the process of wetting the oxidized seed layer 33 with a wetting solution, the unoxidized seed layer 33 in the trench 32 is also wetted by the wetting solution, resulting in a decrease in the wetting contact angle of the substrate after wetting.

[0065] It is understandable that chloride ions in the wetting solution form a chloride ion hydrophilic adsorption layer 37 on the clean seed layer 33 surface. The hydrophilic adsorption layer 37 has extremely strong hydrophilicity, which reduces the wetting contact angle of the substrate surface for subsequent electroplating processes. The reduction in the wetting contact angle means a smaller solid-liquid interface, allowing the electroplating solution to spread better. At the same time, the hydrophilic adsorption layer 37 can also release the residual stress of the overhang 34 and remove the tiny particulate contaminants introduced during the physical vapor deposition process to form the seed layer 33.

[0066] In step S105, the substrate is transferred to an electroplating bath for electroplating to fill it with conductive metal. (Refer to...) Figure 7In the initial stage of electroplating, since the overhang 34 has been eliminated or reduced, the opening of the trench 32 is unobstructed; at the same time, since the hydrophilic adsorption layer 37 has been formed on the surface of the seed layer 33 in the trench 32, the wetting angle is smaller, which reduces the surface tension between the electroplating solution and the seed layer 33. The electroplated conductive metal is filled from bottom to top in the trench 32 until the trench 32 is completely filled, forming a conductive metal layer 35.

[0067] In some embodiments, after electroplating conductive metal into the trench 32 and filling the trench 32, the method further includes step S106: grinding to remove the conductive metal and seed layer 33 on the top surface of the dielectric layer 31, and forming a metal interconnect structure 36 in the trench 32.

[0068] In this embodiment, refer to Figure 8 After electroplating, the structure is annealed and then chemical mechanical polishing (CMP) is performed to remove excess material on the top surface of the dielectric layer 31, forming a conductive metal layer 35, a seed layer 33, and a barrier layer, and forming a metal interconnect structure 36 in the trench 32.

[0069] Scanning electron microscopy (SEM) was used to observe the cross-section of the structure after chemical mechanical polishing. The results showed that the copper filling in the trench 32 was dense, with no visible voids or pits, and the overhang 34 was completely eliminated. The semiconductor structure fabrication method of this embodiment reduces the defect density of the metal interconnect structure 36 and improves the product yield.

[0070] In some embodiments, ultraviolet light-assisted oxidation treatment of the seed layer 33 includes: using ultraviolet light to excite oxygen-containing gas to generate oxygen free radicals, and treating the exposed surface of the seed layer 33 with oxygen free radicals to form an oxide layer 38.

[0071] In this embodiment, after injecting a metal salt solution into the trench 32 and adjusting the liquid level of the metal salt solution to expose the overhang 34, the substrate is transferred to the oxidation treatment chamber for ultraviolet light-assisted oxidation treatment to selectively oxidize the overhang 34.

[0072] An oxygen-containing gas (e.g., oxygen, air, or a mixture of oxygen and an inert gas) is introduced into the oxidation chamber, while the surface of the seed layer 33 is irradiated with ultraviolet light. The ultraviolet light can be vacuum ultraviolet (VUV), with a wavelength range of 172nm-254nm, such as 172nm, 185nm, 190nm, 195nm, 200nm, 212nm, 220nm, 230nm, 240nm, 250nm, or 254nm. Under ultraviolet light (especially vacuum ultraviolet light), oxygen molecules absorb photon energy and undergo photodecomposition, producing oxygen free radicals (O·). These oxygen free radicals have extremely strong oxidizing properties and can directly react with copper to form copper oxide or cuprous oxide. Simultaneously, some oxygen free radicals (O·) may combine with oxygen to form ozone (O3), which can also participate in the oxidation reaction. The oxygen free radicals and / or ozone act on the exposed surface of the seed layer 33, reacting with copper to form an oxide layer 38. Since the overhang 34 is exposed to the gaseous environment of oxygen free radicals or ozone, it is directly in contact with oxygen free radicals or ozone and is therefore oxidized; while the seed layer 33 inside the trench 32 is covered by a metal salt solution, is isolated from oxygen free radicals, and is thus preserved intact.

[0073] Unlike oxygen plasma treatment, the ultraviolet light-assisted oxidation treatment used in this embodiment is a photochemical process that does not generate high-energy ion bombardment, thus avoiding damage to the seed layer 33. It is suitable for the selective oxidation of the ultrathin seed layer 33.

[0074] In one embodiment, this embodiment provides a method for fabricating a semiconductor structure, including the following steps:

[0075] Step S201: Provide a substrate, referring to Figure 2 A dielectric layer 31 is formed on the substrate, and trenches 32 are formed in the dielectric layer 31.

[0076] Step S202: Refer to Figure 2 A seed layer 33 is formed, covering the trench walls 32 and the top surface of the dielectric layer 31, with a hanging portion 34 formed at the top of the trench 32. In this embodiment, the seed layer 33 is formed using a physical vapor deposition process. The seed layer 33 covers the bottom wall and sidewalls of the trench 32 and the top surface of the dielectric layer 31, and a hanging portion 34 is formed at the top of the opening of the trench 32. In this embodiment, the seed layer 33 is a copper seed layer.

[0077] Step S203: Refer to Figure 2 The trench 32 is filled with a metal salt solution, and then a portion of the metal salt solution is drained to control the liquid level of the metal salt solution to be lower than the suspended portion 34. The seed layer 33 is a copper seed crystal layer, and the metal salt solution can be a saturated copper sulfate solution. The saturated copper sulfate solution contains a high concentration of copper ions, which can inhibit the dissolution of copper in the seed layer 33 in the solution. For example, refer to... Figure 3A portion of the metal salt solution in the evaporation trench 32 can be heated and evaporated so that the liquid level of the remaining metal salt solution in the trench 32 is lower than that of the suspended part 34.

[0078] In this embodiment, a copper sulfate solution, which is homologous to copper ions, is selected to avoid introducing contamination from foreign ions. It is understood that in other embodiments, other inert electrolytes, such as potassium sulfate, sodium sulfate, or sodium chloride solutions, may be used as the metal salt solution.

[0079] Step S204: Refer to Figure 4 Ultraviolet light is used to excite oxygen-containing gas, generating oxygen free radicals. These free radicals then treat the exposed surface of the seed layer 33, forming an oxide layer 38. The oxide layer 38 is primarily made of copper oxide or cuprous oxide. Because the seed layer 33 inside the trench 32 is covered by a metal salt solution and does not come into contact with the oxygen free radicals, it remains unoxidized.

[0080] Step S205: Refer to Figure 5 The metal salt solution in the trench 32 is drained to expose the unoxidized seed layer 33 within the trench 32. The draining method can be rotary spin drying, nitrogen purging, or natural flow to ensure that the solution is completely removed and no residue remains.

[0081] Step S206: Refer to Figure 6 The oxidized seed layer 33 is wetted with a wetting solution, which is an acidic aqueous solution containing copper ions, sulfate ions and chloride ions. The copper oxide reacts chemically with the sulfuric acid in the wetting solution, and the copper oxide at the overhang 34 is selectively dissolved, thereby eliminating or significantly reducing the overhang 34, while the bottom copper seed layer is basically unaffected. The chloride ions in the wetting solution form a chloride ion hydrophilic adsorption layer 37 on the surface of the seed layer 33. The hydrophilic adsorption layer 37 reduces the wetting contact angle of the substrate surface.

[0082] Step S207: Refer to Figure 7 The substrate is transferred to an electroplating tank for electroplating. Conductive metal is electroplated into the trench 32, filling the trench 32. In the initial stage of electroplating, since the overhang 34 has been eliminated or reduced, the opening of the trench 32 is unobstructed. At the same time, since a hydrophilic adsorption layer 37 has been formed on the surface of the seed layer 33 in the trench 32, the wetting angle is smaller, reducing the surface tension between the electroplating solution and the seed layer 33. The electroplated conductive metal achieves bottom-up filling in the trench 32 until the trench 32 is completely filled.

[0083] Step S208: Refer to Figure 8 The conductive metal and seed layer 33 on the top surface of the dielectric layer 31 are removed by grinding, and a metal interconnect structure 36 is formed in the trench 32. The metal interconnect structure 36 is dense and free of voids and defects, meeting the requirements of technology nodes of 55nm and below.

[0084] The semiconductor structure fabrication method of this embodiment involves, on one hand, injecting a saturated copper sulfate solution into a trench 32, controlling the liquid level of the copper sulfate solution to expose the overhang portion 34, and maximizing the protection of the uniformly thick seed layer 33 below. Then, ultraviolet-assisted oxidation is used to expose only the overhang portion 34 to the oxidation environment. Ultraviolet light is used to excite oxygen free radicals, selectively oxidizing the copper in the overhang portion 34 region to form an oxide layer 38. Subsequently, the seed layer 33 is treated with a wetting solution to selectively dissolve and remove the overhang portion 34, ensuring its complete removal. The seed layer 33 surface at the bottom and sidewalls of the trench 32 has no oxide layer 38 attached and is almost unaffected by any loss. This achieves selective removal of the overhang portion 34, increases the opening of the trench 32, and facilitates subsequent electroplating. The filling creates deposition conditions, thereby improving the void defects in the metal interconnect structure 36. On the other hand, while removing the overhang 34, the chloride ions in the wetting solution form a dense hydrophilic adsorption layer 37 on the surface of the copper seed layer. The hydrophilic adsorption layer 37 has extremely strong hydrophilicity, which can reduce the water contact angle on the surface of the seed layer 33, which is far superior to the effect of traditional deionized water pre-wetting. The extremely low contact angle means that the electroplating solution can spread instantly and penetrate into the bottom of the high aspect ratio trench 32, completely eliminating the bubble trapping phenomenon caused by surface tension. At the same time, the chloride ion adsorption layer serves as an adsorption site for subsequent electroplating additives (especially inhibitors), which can quickly establish an inhibition layer in the initial stage of electroplating, promote bottom-up super filling, and further ensure void-free filling.

[0085] The semiconductor structure fabrication method of this embodiment can flexibly adapt to trenches 32 with different aspect ratios by adjusting the ultraviolet oxidation time, power and wetting agent immersion time. For structures with an aspect ratio ≤ 5:1, the overhang portion 34 can be completely removed and voids can be eliminated.

[0086] According to an exemplary embodiment, this embodiment provides a semiconductor structure fabricated using the semiconductor structure fabrication method of the above embodiment. The semiconductor structure includes a substrate, on which a dielectric layer 31 is disposed. The material of the dielectric layer 31 includes, but is not limited to, silicon oxide, silicon nitride, silicon oxycarbide, or silicon oxynitride, and its dielectric constant (k value) is less than 3.0 to reduce interconnect delay. The dielectric layer 31 is provided with trenches 32, and metal interconnect structures 36 are disposed in the trenches 32.

[0087] In this embodiment, a metal interconnect structure 36 is disposed in a trench 32. The metal interconnect structure 36 includes a barrier layer, a seed layer 33, and a conductive metal layer 35. The barrier layer covers the bottom and sidewalls of the trench 32. The barrier layer can be a single layer or a multi-layer structure, and the material of the barrier layer includes at least one of tantalum or tantalum nitride, titanium or titanium nitride. The seed layer 33 covers the inner surface of the barrier layer and can be a copper seed layer. The conductive metal layer 35 covers the seed layer 33 and fills the unfilled areas of the trench 32.

[0088] Scanning electron microscopy (SEM) was used to observe the cross-section of the structure after chemical mechanical polishing. The results showed that the copper filling in the trench 32 was dense, with no visible voids or pits, and the seed layer 33 had no overhangs 34 at the top opening of the trench 32. This embodiment reduces the defect density of the metal interconnect structure 36 and improves the product yield.

[0089] The semiconductor structure in this embodiment can be Dynamic Random Access Memory (DRAM), Static Random-Access Memory (SRAM), Flash EPROM, Ferroelectric Random Access Memory (FeRAM), Magnetic Random-Access Memory (MRAM), or other types of memory.

[0090] The unexpected technical effect of this application is that, after the formation of the seed layer, the semiconductor structure and its fabrication method are oxidized to form an oxide layer, and then the seed layer is wetted with a wetting solution to dissolve and remove the oxide layer, thereby removing or thinning the overhang, avoiding premature sealing of the conductive metal at the opening of the trench, thereby improving electroplating voids, improving the quality of the metal interconnect structure, and improving product yield and reliability.

[0091] The semiconductor structure and its fabrication method disclosed in this application fundamentally solve the problem of electroplating voids in advanced node copper interconnect processes. It has advantages in process technology, cost, and reliability, and can be widely used in logic chips, memory chips, and advanced packaging fields at technology nodes of 55nm and below.

[0092] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0093] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, on which a dielectric layer is formed, and trenches are formed in the dielectric layer; A seed layer is formed, which covers the trench walls and the top surface of the medium layer, and a cantilever is formed at the top of the trench; A metal salt solution is injected into the trench, such that after injection, the liquid level of the metal salt solution in the trench is lower than the opening of the trench, exposing the overhang; wherein, the seed layer is a copper seed crystal layer, and the metal salt solution is a saturated copper sulfate solution; The seed layer is oxidized, at least the overhanging portion is oxidized, to form an oxide layer; The metal salt solution in the trench is drained to expose the seed layer inside the trench; The seed layer after oxidation is wetted with a wetting solution to remove the oxide layer, thereby removing or thinning the overhang; the wetting solution is an acidic aqueous solution including copper ions, sulfate ions and chloride ions, and the wetting solution includes a first ion, which is chloride ions; Electroplating a conductive metal into the trench fills the trench.

2. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The seed layer is subjected to ultraviolet light-assisted oxidation or thermal oxidation to form the oxide layer.

3. The method for fabricating a semiconductor structure according to claim 2, characterized in that, The seed layer is treated with ultraviolet light-assisted oxidation, including: Ultraviolet light is used to excite oxygen-containing gas to generate oxygen free radicals. The exposed surface of the seed layer is then treated with these oxygen free radicals to form the oxide layer.

4. The method for fabricating a semiconductor structure according to claim 1, characterized in that, During the process of wetting the oxidized seed layer with the wetting solution, the unoxidized seed layer in the trench is also wetted by the wetting solution, and the wetting contact angle of the substrate decreases after wetting.

5. The method for fabricating a semiconductor structure according to claim 4, characterized in that, During the process of wetting the oxidized seed layer with a wetting solution, the first ions in the wetting solution form a hydrophilic adsorption layer on the surface of the seed layer, and the hydrophilic adsorption layer reduces the wetting contact angle of the substrate surface.

6. The method for fabricating a semiconductor structure according to claim 1, characterized in that, Electroplating conductive metal into the trench and filling the trench further includes: grinding to remove the conductive metal and the seed layer from the top surface of the dielectric layer, thereby forming a metal interconnect structure in the trench.

7. A semiconductor structure, characterized in that, The semiconductor structure is fabricated using the method described in any one of claims 1-6; the semiconductor structure includes a substrate, a dielectric layer is disposed on the substrate, trenches are disposed on the dielectric layer, and metal interconnect structures are disposed in the trenches.

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