Semiconductor device and method for manufacturing semiconductor device
By introducing a second metal layer containing platinum group elements and impurity atoms into the semiconductor device, the problem of high contact resistance between the metal layer and the semiconductor layer is solved, thereby improving yield and resistance stability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-01-22
- Publication Date
- 2026-08-04
AI Technical Summary
In existing semiconductor devices, the contact resistance between the metal layer and the semiconductor layer is high, which leads to a decrease in yield.
In a semiconductor device, a second metal layer containing platinum group elements, such as a palladium layer, is introduced as an etch stop layer for the through-hole, and impurity atoms are introduced into a second nitride semiconductor layer to improve the stability of the ohmic contact. A third metal layer is then combined to cover the inner wall of the through-hole to form an ohmic contact.
By improving the stability of ohmic contacts and reducing resistance, the yield and resistance stability of semiconductor devices are enhanced.
Smart Images
Figure CN122514243A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to a semiconductor device and a method of manufacturing a semiconductor device. Background Technology
[0002] A semiconductor device is known to have the following: a metal layer that makes ohmic contact with the semiconductor layer is formed on the semiconductor layer containing a high concentration of charge carriers as an etch stop layer, a through-hole is formed in the semiconductor layer that reaches the etch stop layer, and an electrode that contacts the etch stop layer is formed in the through-hole.
[0003] Existing technical documents Patent documents Patent Document 1: Japanese Patent Application Publication No. 2024-092747 In conventional semiconductor devices, the contact resistance between the metal layer and the semiconductor layer can sometimes increase, which can lead to a decrease in yield. Summary of the Invention
[0004] The purpose of this disclosure is to provide a semiconductor device and a method for manufacturing a semiconductor device that can improve yield.
[0005] The semiconductor device disclosed herein includes: a substrate having a first surface and a second surface opposite to the first surface; a first nitride semiconductor layer having a third surface contacting the second surface and a fourth surface opposite to the third surface, wherein a recess is formed on the fourth surface; a second nitride semiconductor layer disposed in the recess; and a first metal layer disposed on the second nitride semiconductor layer, the first metal layer having a second metal layer comprising a platinum group element; a through-hole formed in the substrate, the first nitride semiconductor layer, and the second nitride semiconductor layer, wherein the through-hole penetrates the substrate, the first nitride semiconductor layer, and the second nitride semiconductor layer and reaches the second metal layer; the semiconductor device has a third metal layer, wherein the third metal layer contacts the second metal layer and covers the first surface and the inner wall surface of the through-hole; the second nitride semiconductor layer has a diameter of 1.0 × 10⁻⁶. 18 cm -3 The above concentrations contain impurity atoms.
[0006] Invention Effects According to this disclosure, the yield rate can be improved. Attached Figure Description
[0007] Figure 1 This is a diagram showing the layout of the gate electrode, source wiring, and drain wiring in the semiconductor device of the first embodiment.
[0008] Figure 2 This is a cross-sectional view showing the semiconductor device according to the first embodiment.
[0009] Figure 3 This is a diagram showing the band structure of the semiconductor layer (regenerated layer).
[0010] Figure 4 This is a cross-sectional view (one of the first embodiments) showing a method for manufacturing a semiconductor device according to the first embodiment.
[0011] Figure 5 This is a cross-sectional view (second one) showing the manufacturing method of the semiconductor device according to the first embodiment.
[0012] Figure 6 This is a cross-sectional view (third one) showing the manufacturing method of the semiconductor device according to the first embodiment.
[0013] Figure 7 This is a cross-sectional view (fourth one) showing the manufacturing method of the semiconductor device according to the first embodiment.
[0014] Figure 8 This is a cross-sectional view (fifth) showing the manufacturing method of the semiconductor device according to the first embodiment.
[0015] Figure 9 This is a cross-sectional view (sixth) showing the manufacturing method of the semiconductor device according to the first embodiment.
[0016] Figure 10 This is a cross-sectional view (seventh) showing the manufacturing method of the semiconductor device according to the first embodiment.
[0017] Figure 11 This is a cross-sectional view (eighth) showing the manufacturing method of the semiconductor device according to the first embodiment.
[0018] Figure 12 This is a cross-sectional view (nine) showing the manufacturing method of the semiconductor device according to the first embodiment.
[0019] Figure 13 This is a cross-sectional view showing the semiconductor device according to the second embodiment.
[0020] Figure 14 This is a cross-sectional view (one of the two embodiments) showing a method for manufacturing a semiconductor device according to the second embodiment.
[0021] Figure 15 This is a cross-sectional view (second embodiment) showing the manufacturing method of the semiconductor device according to the second embodiment.
[0022] Figure 16 This is a cross-sectional view (third one) showing the manufacturing method of the semiconductor device according to the second embodiment.
[0023] Explanation of reference numerals in the attached figures 11: Substrate; 11A: First surface; 11B: Second surface; 12: Semiconductor layer; 12C: Third surface; 12D: Fourth surface; 13D, 13S: Recesses; 15: Gate common connection; 21D, 21S: Semiconductor layer; 26: Conductor band; 27: Valence band; 30G: Gate electrode; 31G, 32D, 32G, 32S, 33G, 34D, 34S, 35D, 35S: Metal layers; 50: Through-hole; 52D: Drain wiring; 52S: Source wiring; 53: Back electrode; 55: Drain pad; 61, 62, 63: Insulating film; 61D, 61G, 61S, 62D, 62S: Openings; 100, 200: Semiconductor devices; 131D, 231D: Drain electrodes; 131S, 231S: Source electrodes. Detailed Implementation
[0024] [Description of embodiments of this disclosure] First, the implementation plan disclosed herein will be listed for illustration.
[0025] [1] A semiconductor device according to one aspect of this disclosure includes: a substrate having a first surface and a second surface opposite to the first surface; a first nitride semiconductor layer having a third surface in contact with the second surface and a fourth surface opposite to the third surface, wherein a recess is formed on the fourth surface; a second nitride semiconductor layer disposed in the recess; and a first metal layer disposed on the second nitride semiconductor layer, the first metal layer having a second metal layer comprising a platinum group element, wherein through-holes are formed in the substrate, the first nitride semiconductor layer and the second nitride semiconductor layer, wherein the through-holes penetrate the substrate, the first nitride semiconductor layer and the second nitride semiconductor layer and reach the second metal layer, the semiconductor device having a third metal layer, wherein the third metal layer is in contact with the second metal layer and covers the first surface and the inner wall surface of the through-holes, the second nitride semiconductor layer having a diameter of 1.0 × 10⁻⁶. 18 cm -3 The above concentrations contain impurity atoms.
[0026] A second nitride semiconductor layer is formed in the recess on the fourth side of the first nitride semiconductor layer. The second nitride semiconductor layer has a size of 1.0 × 10⁻⁶. 18 cm -3 The above concentrations contain impurity atoms. Therefore, an ohmic contact is achieved between the second nitride semiconductor layer and the first metal layer. Furthermore, the palladium-containing second metal layer exhibits high resistance to substances that may come into contact with it during the formation of the through-hole and the third metal layer. Therefore, the resistance between the third metal layer and the first nitride semiconductor layer is well-stabilized, thereby improving the yield.
[0027] [2] In [1], the second metal layer may also comprise palladium or platinum. In this case, the second metal layer readily functions as an etch stop layer during the formation of the via and exhibits particularly high resistance to substances that may come into contact with the second metal layer during the formation of the via and the third metal layer.
[0028] [3] In [1] or [2], the first metal layer may have a fourth metal layer comprising titanium between the second metal layer and the second nitride semiconductor layer, and the through-hole penetrates the fourth metal layer. In this case, excellent adhesion is achieved between the second metal layer and the second nitride semiconductor layer.
[0029] [4] In any of [1] to [3], the first metal layer may also have a fifth metal layer covering the second metal layer, the resistance of which is lower than that of the second metal layer. In this case, it is easy to suppress the resistance of the first metal layer, which includes the second metal layer and the fifth metal layer, to be low.
[0030] [5] In [4], the fifth metal layer may also comprise at least one material selected from the group consisting of gold, copper, and aluminum. In this case, it is easier to reduce the resistance of the fifth metal layer.
[0031] [6] In any of [1] to [5], the second nitride semiconductor layer may also be a gallium nitride layer. In this case, it is easy to obtain a low resistance in the second nitride semiconductor layer.
[0032] [7] In any of [1] to [6], the Fermi level in the second nitride semiconductor layer may be higher than the energy at the lower end of the conduction band. In this case, an ohmic contact is readily obtained between the second nitride semiconductor layer and the first metal layer.
[0033] [8] In any of [1] to [7], the carrier density in the second nitride semiconductor layer may also be higher than the carrier density in the first nitride semiconductor layer. In this case, it is easier to reduce the resistance of the second nitride semiconductor layer.
[0034] [9] Another aspect of the present disclosure describes a method for manufacturing a semiconductor device comprising the following steps: forming a first nitride semiconductor layer on a substrate, wherein the substrate has a first surface and a second surface opposite to the first surface, the first nitride semiconductor layer has a third surface in contact with the second surface and a fourth surface opposite to the third surface; forming a recess on the fourth surface; forming a second nitride semiconductor layer on the recess; forming a first metal layer on the second nitride semiconductor layer, wherein the first metal layer has a second metal layer comprising a platinum group element; forming a through-hole on the substrate, the first nitride semiconductor layer, and the second nitride semiconductor layer, wherein the through-hole penetrates the substrate, the first nitride semiconductor layer, and the second nitride semiconductor layer and reaches the second metal layer; and forming a third metal layer, wherein the third metal layer contacts the second metal layer and covers the first surface and the inner wall surface of the through-hole, the second nitride semiconductor layer being 1.0 × 10⁻⁶. 18 cm -3 The above concentrations contain impurity atoms.
[0035] A recess is formed on the fourth surface of the first nitride semiconductor layer, and a second nitride semiconductor layer is formed in the recess. The second nitride semiconductor layer has a size of 1.0 × 10⁻⁶. 18 cm -3 The concentrations mentioned above contain impurity atoms. Furthermore, the second metal layer containing palladium exhibits high resistance to substances that may come into contact with the second metal layer during the formation of the through-hole and the third metal layer. Therefore, the resistance between the third metal layer and the first nitride semiconductor layer is well-stabilized, thereby improving the yield.
[0036] [Details of the embodiments disclosed herein] The embodiments of this disclosure will now be described in detail, but this disclosure is not limited thereto. It should be noted that in this specification and accompanying drawings, elements having substantially the same functional configuration may sometimes be omitted by using the same reference numerals to avoid repetitive descriptions. Furthermore, the XYZ orthogonal coordinate system will be used in the following description, but this coordinate system is specified for illustrative purposes and does not limit the orientation of the semiconductor device. Additionally, when viewed from any point, the +Z side may sometimes be referred to as above, upper, or upper, and the -Z side may sometimes be referred to as below, lower, or lower.
[0037] (First Implementation) The first embodiment will be described. The first embodiment relates to a semiconductor device including a GaN-based high electron mobility transistor (HEMT).
[0038] [Structure of a semiconductor device] The structure of the semiconductor device according to the first embodiment will be described. Figure 1 This is a diagram showing the layout of the gate electrode, source wiring, and drain wiring in the semiconductor device of the first embodiment. Figure 2 This is a cross-sectional view showing the semiconductor device according to the first embodiment. Figure 2 Equivalent to along Figure 1 A sectional view along line II-II.
[0039] like Figure 1 and Figure 2 As shown, the semiconductor device 100 of the embodiment includes a substrate 11, a semiconductor layer 12, a semiconductor layer 21S, a semiconductor layer 21D, a gate electrode 30G, a source electrode 131S, a drain electrode 131D, a source wiring 52S, a drain wiring 52D, and a back electrode 53.
[0040] The substrate 11 is, for example, a silicon carbide (SiC) substrate. The substrate 11 has a first surface 11A and a second surface 11B opposite to the first surface 11A. The second surface 11B is located above the first surface 11A (on the +Z side).
[0041] A semiconductor layer 12 is disposed on the substrate 11. The semiconductor layer 12 has a third surface 12C in contact with the second surface 11B and a fourth surface 12D opposite to the third surface 12C. The fourth surface 12D is located above the third surface 12C (on the +Z side). The semiconductor layer 12 is, for example, a gallium (Ga) nitride semiconductor layer. The nitride semiconductor layer constitutes part of a high electron mobility transistor, including a two-dimensional electron gas (2DEG), such as an electron transit layer (channel layer) and an electron supply layer (blocking layer). The semiconductor layer 12 is an example of a first nitride semiconductor layer.
[0042] Multiple recesses 13S and multiple recesses 13D are formed on the fourth surface 12D. The recesses 13S and 13D extend parallel to the Y-axis and are alternately arranged along the X-axis. For example, the recesses 13S and 13D reach the electron transit layer (channel layer). Alternatively, the bottom surfaces of the recesses 13S and 13D may be located in the electron transit layer.
[0043] Semiconductor device 100 includes an insulating film 61. The insulating film 61 covers the fourth surface 12D of semiconductor layer 12. For example, the insulating film 61 is a silicon nitride (SiN) film or other nitride film. A plurality of openings 61S, a plurality of openings 61D, and a plurality of openings 61G are formed on the insulating film 61. The openings 61S, 61D, and 61G penetrate the insulating film 61. The openings 61S, 61D, and 61G extend parallel to the Y-axis. The opening 61S is connected to the recess 13S, and the opening 61D is connected to the recess 13D. The opening 61G is disposed between adjacent openings 61S and 61D along the X-axis.
[0044] Semiconductor layer 21S is disposed in recess 13S, and semiconductor layer 21D is disposed in recess 13D. Alternatively, a portion of semiconductor layer 21S may be located inside opening 61S, or a portion of semiconductor layer 21D may be located inside opening 61D. For example, semiconductor layers 21S and 21D are n-type gallium nitride (GaN) layers. Semiconductor layers 21S and 21D are regrown layers. The carrier density in semiconductor layers 21S and 21D is higher than the carrier density in semiconductor layer 12. Semiconductor layers 21S and 21D have a carrier density of 1.0 × 10⁻⁶. 18 cm -3 The above concentrations contain n-type impurity atoms. Semiconductor layers 21S and 21D are, for example, degenerate semiconductor layers. The n-type impurities are, for example, silicon (Si) or germanium (Ge). Semiconductor layer 21S is an example of a second nitride semiconductor layer.
[0045] The gate electrode 30G extends parallel to the Y-axis. The gate electrode 30G makes a Schottky contact with the semiconductor layer 12 through an opening 61G. The gate electrode 30G has metal layers 31G, 32G, and 33G. Metal layer 31G is in direct contact with the semiconductor layer 12. Metal layer 32G covers metal layer 31G. Metal layer 33G covers metal layer 32G. Metal layer 31G is located above the semiconductor layer 12 and the insulating film 61, while metal layer 32G and metal layer 33G are located above metal layer 32G. Metal layer 31G contains nickel (Ni). Metal layer 31G is, for example, a nickel (Ni) layer. Metal layer 32G contains palladium (Pd). Metal layer 32G is, for example, a palladium (Pd) layer. Metal layer 33G contains gold (Au). Metal layer 33G is, for example, a gold (Au) layer. Figure 1 As shown, multiple gate electrodes 30G are connected to the gate common connection portion 15.
[0046] The source electrode 131S extends parallel to the Y-axis. The source electrode 131S has a metal layer 32S and a metal layer 35S. Metal layer 32S is in direct contact with the semiconductor layer 21S. Metal layer 35S covers metal layer 32S. Metal layer 32S is located above semiconductor layer 21S, and metal layer 35S is located above metal layer 32S. Metal layer 32S contains palladium (Pd). Metal layer 32S is, for example, a palladium (Pd) layer. The thickness of metal layer 32S is, for example, greater than or equal to 10 nm and less than or equal to 100 nm. The resistance of metal layer 35S is lower than that of metal layer 32S. Metal layer 35S is, for example, a gold (Au) layer. The thickness of metal layer 35S is, for example, greater than or equal to 200 nm and less than or equal to 1000 nm. The source electrode 131S is an example of a first metal layer. Metal layer 32S is an example of a second metal layer. Metal layer 35S is an example of a fifth metal layer.
[0047] The drain electrode 131D extends parallel to the Y-axis. The drain electrode 131D has a metal layer 32D and a metal layer 35D. Metal layer 32D is in direct contact with semiconductor layer 21D. Metal layer 35D covers metal layer 32D. Metal layer 32D is located above semiconductor layer 21D, and metal layer 35D is located above metal layer 32D. Metal layer 32D contains palladium (Pd). Metal layer 32D is, for example, a palladium (Pd) layer. The thickness of metal layer 32D is, for example, greater than or equal to 10 nm and less than or equal to 100 nm. The resistance of metal layer 35D is lower than that of metal layer 32D. Metal layer 35D is, for example, a gold (Au) layer. The thickness of metal layer 35D is, for example, greater than or equal to 200 nm and less than or equal to 1000 nm.
[0048] Semiconductor device 100 includes an insulating film 62. The insulating film 62 covers semiconductor layer 21S, semiconductor layer 21D, source electrode 131S, drain electrode 131D, gate electrode 30G, and the insulating film 61. For example, the insulating film 62 is a silicon nitride (SiN) film or other nitride film. A plurality of openings 62S and a plurality of openings 62D are formed on the insulating film 62. The openings 62S and 62D extend parallel to the Y-axis. The openings 62S reach the source electrode 131S, and the openings 62D reach the drain electrode 131D.
[0049] Source wiring 52S is located above source electrode 131S. Source wiring 52S is disposed on insulating film 62. Source wiring 52S contacts source electrode 131S through opening 62S. Drain wiring 52D is located above drain electrode 131D. Drain wiring 52D is disposed on insulating film 62. Drain wiring 52D contacts drain electrode 131D through opening 62D. Source wiring 52S and drain wiring 52D may, for example, have a seed layer and a plating layer on top of the seed layer. For example, the seed layer may include a titanium (Ti) layer, and the plating layer may include a gold (Au) layer. Alternatively, as... Figure 1As shown, multiple drain wirings 52D are connected to drain pads 55, and multiple source wirings 52S are interconnected.
[0050] The semiconductor device 100 has an insulating film 63. The insulating film 63 covers the source wiring 52S, the drain wiring 52D, and the insulating film 62. For example, the insulating film 63 is a silicon nitride (SiN) film or other nitride film.
[0051] Although not shown in the figure, an opening is formed in the insulating film 62 to reach the gate common connection portion 15, and a gate pad is formed on the insulating film 62 to contact the gate common connection portion 15 through the opening. In addition, an opening to the gate pad and an opening to the drain pad 55 are formed in the insulating film 63.
[0052] Through-holes 50 are formed in the substrate 11, semiconductor layer 12, and semiconductor layer 21S, penetrating the substrate 11, semiconductor layer 12, and semiconductor layer 21S. The through-holes 50 reach the source electrode 131S. The through-holes 50 reach the metal layer 32S. At least one through-hole 50 is formed for each of the source electrodes 131S. Alternatively, multiple through-holes 50 may be formed for each of the source electrodes 131S. Alternatively, source electrodes 131S with through-holes 50 and source electrodes 131S without through-holes 50 may coexist.
[0053] A back electrode 53 is formed on the lower surface of the metal layer 32S of the source electrode 131S, the inner wall surface of the through hole 50, and the lower surface (first surface 11A) of the substrate 11. The back electrode 53 is in contact with the metal layer 32S of the source electrode 131S and covers the first surface 11A and the inner wall surface of the through hole 50. The back electrode 53 may have a seed layer and a plating layer, for example. For example, the seed layer may include a titanium (Ti) layer, a nickel (Ni) layer, a nickel-chromium (NiCr) alloy layer, or a tantalum (Ta) layer, and the plating layer may include a gold (Au) layer. The back electrode 53 is an example of a third metal layer.
[0054] In the semiconductor device 100, a semiconductor layer 21S is formed in the recess 13S of the semiconductor layer 12, and the semiconductor layer 21S has a size of 1.0 × 10⁻⁶. 18 cm -3 The above concentrations contain impurity atoms. In such a semiconductor layer 21S, the distances between impurity atoms are short, such as... Figure 3 As shown, an impurity energy level (E) is formed. D The bound energy bands interact with each other and are connected to the conduction band 26. At this time, the Fermi level (E) F ) exists in the conduction band, that is, the Fermi level (E) F The energy at the lower end of the conduction band (E) CThe semiconductor layer 21S exhibits properties similar to those of a metal due to its high density. In other words, the semiconductor layer 21S functions as a degenerate semiconductor layer. Therefore, an ohmic contact is achieved between the semiconductor layer 21S and the source electrode 131S. Figure 3 This is a diagram showing the band structure of semiconductor layer 21S. Figure 3 E in V This indicates the energy at the upper end of valence band 27.
[0055] [Method for manufacturing semiconductor devices] Next, the manufacturing method of the semiconductor device 100 according to the first embodiment will be described. Figures 4 to 12 This is a cross-sectional view showing a method for manufacturing the semiconductor device 100 according to the first embodiment.
[0056] like Figure 4 As shown, a semiconductor layer 12 is formed on a substrate 11, for example, by metal-organic chemical vapor deposition (MOCVD). The substrate 11 has a first surface 11A and a second surface 11B opposite to the first surface 11A. The semiconductor layer 12 has a third surface 12C in contact with the second surface 11B and a fourth surface 12D opposite to the third surface 12C. Next, an insulating film 61 is formed on the semiconductor layer 12. The insulating film 61 can be formed, for example, by plasma CVD (chemical vapor deposition). The insulating film 61 covers the fourth surface 12D of the semiconductor layer 12.
[0057] Next, as Figure 5 As shown, openings 61S and 61D are formed on the insulating film 61, and recesses 13S and 13D are formed on the semiconductor layer 12. In the formation of openings 61S and 61D, reactive ion etching (RIE) is performed on the insulating film 61 using a resist pattern as a mask, for example. During the RIE of the insulating film 61, a reactive gas containing fluorine (F) is used, for example. In the formation of recesses 13S and 13D, RIE is performed on the semiconductor layer 12 using the resist pattern used in the formation of openings 61S and 61D as a mask. During the RIE of the semiconductor layer 12, a reactive gas containing chlorine (Cl) is used, for example.
[0058] Next, as Figure 6As shown, a semiconductor layer 21S is formed in the recess 13S, and a semiconductor layer 21D is formed in the recess 13D. In the formation of semiconductor layers 21S and 21D, crystal growth of the semiconductor layers is performed, for example, by using MOCVD, molecular beam epitaxy (MBE), or sputtering with a growth mask, followed by removal of the growth mask. Semiconductor layers 21S and 21D are so-called regrown layers.
[0059] Next, as Figure 7 As shown, a source electrode 131S is formed on semiconductor layer 21S, and a drain electrode 131D is formed on semiconductor layer 21D. The source electrode 131S has metal layers 32S and 35S, and the drain electrode 131D has metal layers 32D and 35D. The source electrode 131S and drain electrode 131D can be formed, for example, by vapor deposition and stripping using a growth mask.
[0060] Next, as Figure 8 As shown, an opening 61G is formed in the insulating film 61. In forming the opening 61G, for example, a re-etching process using a resist pattern as a mask is performed. In etching the insulating film 61, for example, a reactive gas containing fluorine (F) is used. Next, a gate electrode 30G is formed on the semiconductor layer 12 and the insulating film 61. The gate electrode 30G has metal layers 31G, 32G, and 33G. The gate electrode 30G can be formed, for example, by vapor deposition and stripping using a growth mask. The gate electrode 30G makes a Schottky contact with the semiconductor layer 12 through the opening 61G.
[0061] Next, as Figure 9 As shown, an insulating film 62 is formed on semiconductor layer 21S, semiconductor layer 21D, source electrode 131S, drain electrode 131D, gate electrode 30G, and insulating film 61. The insulating film 62 can be formed, for example, by plasma CVD. The insulating film 62 covers semiconductor layer 21S, semiconductor layer 21D, source electrode 131S, drain electrode 131D, gate electrode 30G, and insulating film 61.
[0062] Next, as Figure 10 As shown, openings 62S and 62D are formed on the insulating film 62. In forming the openings 62S and 62D, for example, a resist patterning (RIE) is performed on the insulating film 62 using a resist pattern as a mask. During the RIE of the insulating film 62, for example, a reactive gas containing fluorine (F) is used. Next, a source wiring 52S, which contacts the source electrode 131S through the opening 62S, and a drain wiring 52D, which contacts the drain electrode 131D through the opening 62D, are formed on the insulating film 62.
[0063] Next, as Figure 11As shown, an insulating film 63 is formed on the insulating film 62. The insulating film 63 can be formed, for example, by plasma CVD. The insulating film 63 covers the source wiring 52S, the drain wiring 52D, and the insulating film 62.
[0064] Next, as Figure 12 As shown, a through-hole 50 is formed through the substrate 11, semiconductor layer 12, and semiconductor layer 21S. The through-hole 50 is formed to reach the source electrode 131S. In the formation of the through-hole 50, the semiconductor layer 12 and semiconductor layer 21S are etched after the substrate 11 is etched. During the etching of the semiconductor layer 12 and semiconductor layer 21S, a reactive gas containing chlorine (Cl) is used, for example. The metal layer 32S containing palladium (Pd) has high resistance to etching using a reactive gas containing chlorine (Cl). Therefore, the metal layer 32S functions as an etch stop layer, and the lower surface of the metal layer 32S is exposed through the through-hole 50. During the etching of the substrate 11 used to form the through-hole 50, a mask is formed on the first surface 11A, and the mask is removed after the substrate 11 is etched. Furthermore, after the formation of the through-hole 50, cleaning is performed inside the through-hole 50.
[0065] Next, the back electrode 53 is formed (see reference). Figure 2 The back electrode 53 contacts the metal layer 32S of the source electrode 131S and covers the first surface 11A and the inner wall surface of the through hole 50.
[0066] In this way, the semiconductor device 100 of the first embodiment can be manufactured.
[0067] In the semiconductor device 100, the back electrode 53 is in contact with the source electrode 131S, and the source electrode 131S is in ohmic contact with the semiconductor layer 21S. Therefore, the resistance between the semiconductor layer 12, including the 2DEG, and the back electrode 53 is low. Thus, according to the semiconductor device 100, the resistance between the back electrode 53 and the semiconductor layer 12 is well-stable, thereby improving the yield.
[0068] Alternatively, a nickel (Ni) layer could be used as an etch stop layer during the etching of semiconductor layers 12 and 21S. However, nickel may react with the material used for mask removal after etching of substrate 11 and for cleaning within the via 50. Therefore, when using a nickel (Ni) layer as an etch stop layer, a portion of the etch stop layer may be missing, increasing the contact resistance between the source electrode 131S and semiconductor layer 21S, thus reducing yield. On the other hand, in semiconductor device 100, metal layer 32S contains palladium (Pd), which has high resistance to the material used for mask removal after etching of substrate 11 and for cleaning within the via 50. Therefore, the increase in contact resistance that occurs when using a nickel (Ni) layer does not occur, thereby improving yield.
[0069] Metal layer 32S contains platinum group elements, but is not limited to palladium (Pd). For example, metal layer 32S may also contain platinum (Pt), and metal layer 32S may also be a platinum (Pt) layer. Metal layer 32S containing palladium (Pd) or platinum (Pt) allows it to function readily as an etch stop layer during the formation of the through-hole 50, and exhibits particularly high resistance to materials used for mask removal and cleaning within the through-hole 50. Metal layer 32D may also contain platinum group elements other than palladium (Pd). For example, metal layer 32D may also contain platinum (Pt), and metal layer 32D may also be a platinum (Pt) layer.
[0070] Since semiconductor layer 21S is a GaN layer, it is easy to obtain low resistance in semiconductor layer 21S.
[0071] Since the carrier density in semiconductor layers 21S and 21D is higher than that in semiconductor layer 12, it is easier to reduce the resistance of the semiconductor device 100. Specifically, it is easier to reduce the resistance between the back electrode 53 and the drain wiring 52D.
[0072] Semiconductor layer 21S can also be 1.0 × 10 19 cm -3 The above concentrations contain n-type impurity atoms, and can also be increased to 1.0 × 10⁻⁶. 20 cm -3 The above concentrations contain n-type impurity atoms. The higher the concentration of n-type impurity atoms in semiconductor layer 21S, the easier it is to obtain an ohmic contact between semiconductor layer 21S and source electrode 131S. Similarly, semiconductor layer 21D can also be 1.0 × 10⁻⁶. 19 cm -3 The above concentrations contain n-type impurity atoms, and can also be increased to 1.0 × 10⁻⁶. 20 cm -3The above concentrations contain n-type impurity atoms. A higher concentration of n-type impurity atoms in semiconductor layer 21D facilitates the formation of an ohmic contact between semiconductor layer 21D and drain electrode 131D. The concentration of impurity atoms can be determined using secondary ion mass spectrometry (SIMS).
[0073] By including a metal layer 35S in the source electrode 131S, and having a lower resistance than the metal layer 32S, the resistance of the source electrode 131S can be reduced. Similarly, by including a metal layer 35D in the drain electrode 131D, and having a lower resistance than the metal layer 32D, the resistance of the drain electrode 131D can be reduced. The metal layers 35S and 35D are not limited to gold (Au) layers. The metal layers 35S and 35D may also contain at least one element selected from the group consisting of gold (Au), copper (Cu), and aluminum (Al).
[0074] (Second Implementation) The second embodiment will be described. The main difference between the second embodiment and the first embodiment lies in the configuration of the source electrode and the drain electrode.
[0075] [Structure of a semiconductor device] The structure of the semiconductor device according to the second embodiment will be described. Figure 13 This is a cross-sectional view showing the semiconductor device according to the second embodiment.
[0076] like Figure 13 As shown, the semiconductor device 200 of the second embodiment has a source electrode 231S instead of a source electrode 131S, and a drain electrode 231D instead of a drain electrode 131D.
[0077] The source electrode 231S extends parallel to the Y-axis. The source electrode 231S has metal layers 34S, 32S, and 35S. Metal layer 34S is in direct contact with semiconductor layer 21S. Metal layer 32S covers metal layer 34S. Metal layer 35S covers metal layer 32S. Metal layer 34S is located above semiconductor layer 21S, metal layer 32S is located above metal layer 34S, and metal layer 35S is located above metal layer 32S. Metal layer 34S is located between metal layer 32S and semiconductor layer 21S. Metal layer 34S contains titanium (Ti). Metal layer 34S is, for example, a titanium (Ti) layer. The thickness of metal layer 34S is, for example, greater than or equal to 3 nm and less than or equal to 50 nm. Metal layer 34S is an example of a fourth metal layer.
[0078] Drain electrode 231D extends parallel to the Y-axis. Drain electrode 231D has metal layers 34D, 32D, and 35D. Metal layer 34D is in direct contact with semiconductor layer 21D. Metal layer 32D covers metal layer 34D. Metal layer 35D covers metal layer 32D. Metal layer 34D is located above semiconductor layer 21D, metal layer 32D is located above metal layer 34D, and metal layer 35D is located above metal layer 32D. Metal layer 34D is located between metal layer 32D and semiconductor layer 21D. Metal layer 34D contains titanium (Ti). Metal layer 34D is, for example, a titanium (Ti) layer. The thickness of metal layer 34D is, for example, greater than or equal to 3 nm and less than or equal to 50 nm.
[0079] The through-hole 50 penetrates the substrate 11, semiconductor layer 12, semiconductor layer 21S, and metal layer 34S, and reaches metal layer 32S. A back electrode 53 is formed on the lower surface of metal layer 32S, the inner wall of through-hole 50, and the lower surface (first surface 11A) of substrate 11. The back electrode 53 is in contact with the metal layer 32S of source electrode 231S.
[0080] The other components of semiconductor device 200 are the same as those of semiconductor device 100.
[0081] [Method for manufacturing semiconductor devices] Next, the manufacturing method of the semiconductor device 200 according to the second embodiment will be described. Figures 14 to 16 This is a cross-sectional view showing the manufacturing method of the semiconductor device 200 according to the second embodiment.
[0082] The process up to the formation of semiconductor layer 21S and semiconductor layer 21D is performed in the same manner as in the first embodiment (see reference). Figure 6 Next, as... Figure 14 As shown, a source electrode 231S is formed on semiconductor layer 21S, and a drain electrode 231D is formed on semiconductor layer 21D. The source electrode 231S has metal layers 34S, 32S, and 35S, and the drain electrode 231D has metal layers 34D, 32D, and 35D. The source electrode 231S and drain electrode 231D can be formed, for example, by vapor deposition and stripping using a growth mask.
[0083] Next, as Figure 15 As shown, the process from the formation of the opening 61G to the formation of the insulating film 63 is performed in the same manner as in the first embodiment.
[0084] Next, as Figure 16As shown, a via 50 is formed through the substrate 11, semiconductor layer 12, and semiconductor layer 21S. The via 50 is formed to reach the source electrode 231S. In the formation of the via 50, the semiconductor layer 12 and semiconductor layer 21S are etched after the substrate 11 is etched. During the etching of the semiconductor layer 12 and semiconductor layer 21S, a reactive gas containing chlorine (Cl) is used, for example. The titanium (Ti) metal layer 34S has low resistance to etching using a reactive gas containing chlorine (Cl), and the via 50 penetrates the metal layer 34S. Furthermore, the palladium (Pd) metal layer 32S has high resistance to etching using a reactive gas containing chlorine (Cl). Therefore, the metal layer 32S functions as an etch stop layer, and the lower surface of the metal layer 32S is exposed through the via 50. During the etching of the substrate 11 used to form the through-hole 50, a mask is formed on the first surface 11A, and the mask is removed after the etching of the substrate 11. In addition, the through-hole 50 is cleaned after its formation.
[0085] Next, the back electrode 53 is formed (see reference). Figure 13 The back electrode 53 contacts the metal layer 32S of the source electrode 231S and covers the first surface 11A and the inner wall surface of the through hole 50.
[0086] In this way, the semiconductor device 200 of the second embodiment can be manufactured.
[0087] The second embodiment also improves the yield in the same way as the first embodiment. Specifically, in the semiconductor device 200, the back electrode 53 is in contact with the source electrode 231S, and the source electrode 231S is in ohmic contact with the semiconductor layer 21S. Therefore, the resistance between the semiconductor layer 12, which includes 2DEG, and the back electrode 53 is low. Furthermore, the titanium (Ti)-containing metal layer 34S, like the metal layer 32S, exhibits high resistance to materials used for mask removal after etching of the substrate 11 and for cleaning within the through-hole 50. Therefore, according to the semiconductor device 200, the resistance between the back electrode 53 and the semiconductor layer 12 is well-stabilized, thereby improving the yield.
[0088] Furthermore, in the semiconductor device 200, the source electrode 231S has a titanium (Ti)-containing metal layer 34S between the metal layer 32S and the semiconductor layer 21S. The metal layer 34S has high adhesion between itself and both the metal layer 32S and the semiconductor layer 21S. Therefore, excellent adhesion is achieved between the metal layer 32S and the semiconductor layer 21S.
[0089] The embodiments have been described in detail above, but this disclosure is not limited to specific embodiments, and various modifications and alterations can be made within the scope of the claims.
Claims
1. A semiconductor device comprising: A substrate having a first surface and a second surface opposite to the first surface; A first nitride semiconductor layer has a third surface in contact with the second surface and a fourth surface opposite to the third surface, and a recess is formed on the fourth surface; A second nitride semiconductor layer is disposed in the recess; and A first metal layer is disposed on top of the second nitride semiconductor layer. The first metal layer has a second metal layer comprising platinum group elements. A through hole is formed in the substrate, the first nitride semiconductor layer, and the second nitride semiconductor layer, wherein The through-hole penetrates the substrate, the first nitride semiconductor layer, and the second nitride semiconductor layer, and reaches the second metal layer. The semiconductor device has a third metal layer, wherein the third metal layer is in contact with the second metal layer and covers the first surface and the inner wall surface of the through hole. The second nitride semiconductor layer has a thickness of 1.0 x 10 18 cm -3 The above concentrations contain impurity atoms.
2. The semiconductor device according to claim 1, wherein, The second metal layer contains palladium or platinum.
3. The semiconductor device according to claim 1 or 2, wherein, The first metal layer has a fourth metal layer comprising titanium between the second metal layer and the second nitride semiconductor layer. The through hole penetrates the fourth metal layer.
4. The semiconductor device according to claim 1 or 2, wherein, The first metal layer has a fifth metal layer covering the second metal layer. The resistance of the fifth metal layer is lower than that of the second metal layer.
5. The semiconductor device according to claim 4, wherein, The fifth metal layer comprises at least one selected from the group consisting of gold, copper, and aluminum.
6. The semiconductor device according to claim 1 or 2, wherein, The second nitride semiconductor layer is a gallium nitride layer.
7. The semiconductor device according to claim 1 or 2, wherein, In the second nitride semiconductor layer, the Fermi level has a higher energy than the lower end of the conduction band.
8. The semiconductor device according to claim 1 or 2, wherein, The carrier density in the second nitride semiconductor layer is higher than that in the first nitride semiconductor layer.
9. A method for manufacturing a semiconductor device, comprising the following steps: forming a first nitride semiconductor layer over a substrate, wherein The substrate has a first surface and a second surface opposite to the first surface, and the first nitride semiconductor layer has a third surface in contact with the second surface and a fourth surface opposite to the third surface; A recess is formed on the fourth surface; A second nitride semiconductor layer is formed in the recess; A first metal layer is formed on the second nitride semiconductor layer, wherein the first metal layer has a second metal layer comprising platinum group elements; A through-hole is formed in the substrate, the first nitride semiconductor layer, and the second nitride semiconductor layer, wherein the through-hole penetrates the substrate, the first nitride semiconductor layer, and the second nitride semiconductor layer, and reaches the second metal layer; and A third metal layer is formed, wherein the third metal layer is in contact with the second metal layer and covers the first surface and the inner wall surface of the through hole. The second nitride semiconductor layer has a thickness of 1.0 x 10 18 cm -3 The above concentrations contain impurity atoms.