An analysis device and analysis method for electrical parameters of a transistor PN junction

Abstract

This invention discloses an analysis device and method for electrical parameters of a transistor PN junction. The device includes a vacuum chamber with a sample stage inside; a nanoscale four-probe array comprising four electrically isolated, equally spaced probes for step-scanning along the PN junction depth profile; a positioning and driving module for driving the nanoscale four-probe array to perform nanoscale step-like movement; a signal acquisition and bias module for applying a bias voltage and acquiring current and voltage signals; and a data processing unit for calculating the sheet resistance of each depth node based on the four-probe principle, plotting the sheet resistance and carrier concentration curves as a function of depth, and determining the electrical junction depth by combining the PN junction's built-in electric field model. This invention employs a nanoscale four-probe architecture to eliminate contact resistance interference, improving spatial resolution to the nanoscale. It can simultaneously extract multi-dimensional electrical parameters such as carrier concentration, mobility, depletion layer width, and reverse saturation current, making it suitable for precise electrical characterization and process optimization of PN junctions in transistors.

Description

Technical Field

[0001] This invention relates to the field of semiconductor detection technology, and in particular to an analysis device and method for analyzing the electrical parameters of a transistor PN junction. Background Technology

[0002] With the rapid development of semiconductor devices towards three-dimensional integration and miniaturization (such as 3D NAND and advanced logic processes), extremely high requirements are placed on the characterization of the depth distribution of electrical properties inside PN junctions. Accurately measuring the carrier concentration distribution at different depths and precisely locking the electrical junction depth are the core of device process optimization.

[0003] Currently, existing technologies for PN junction depth profiling suffer from the following serious limitations: Secondary ion mass spectrometry (SIMS): While providing extremely high precision in elemental concentration depth distribution, SIMS measures "chemical doping concentration" rather than "electrically active carrier concentration." In advanced processes, doped atoms are often not fully ionized and activated, making SIMS unable to accurately reflect the electrical operating state of the PN junction. Traditional Spreading Resistance Profiling (SRP): SRP is currently the standard method in industry for evaluating carrier depth distribution. This method measures the spread resistance between two osmium or tungsten carbide probes spaced approximately 20 micrometers apart on a semiconductor bevel surface. However, SRP technology has insurmountable physical defects:

[0004] The two-probe principle has its drawbacks: the resistance measured by SRP includes not only the material's inherent extended resistance but also a significant amount of probe contact resistance and surface barrier resistance. Therefore, it is highly dependent on pre-test calibration and extremely sensitive to probe pressure and the sample's natural oxide layer.

[0005] Resolution bottleneck: The probe spacing of up to 20 μm results in a severe lack of lateral resolution when dealing with nanoscale feature sizes. Single parameter: SRP can only measure a single resistance parameter and cannot simultaneously characterize carrier mobility, depletion layer width, and leakage current. Furthermore, it requires assuming bulk material mobility to calculate concentration, leading to significant errors in defect-dense regions (such as regions where ion implantation is not fully annealed).

[0006] In summary, there is an urgent need to develop an analytical device that combines ultra-high spatial resolution, eliminates the need for contact resistance calibration, and enables simultaneous extraction of deep multidimensional electrical parameters (concentration, mobility, junction depth, leakage current, etc.). This is a critical technical challenge that needs to be addressed to overcome the bottlenecks in advanced process detection. Summary of the Invention

[0007] This invention provides an analysis device and method for the electrical parameters of a transistor PN junction, which can be used for the three-dimensional electrical characteristic characterization of transistor PN junctions in integrated circuits, accurate measurement of carrier concentration depth distribution, junction depth positioning, and process optimization, thereby solving the problems encountered in the extraction of transistor PN junction parameters in the prior art, such as large contact resistance interference, low spatial resolution, and single parameter extraction.

[0008] In a first aspect, this application provides an apparatus for analyzing the electrical parameters of a transistor PN junction, comprising:

[0009] A vacuum chamber containing a sample stage for fixing and positioning the transistor under test;

[0010] The nanoscale four-probe system comprises four electrically isolated probes arranged at equal intervals, used for step scanning along the PN junction depth profile of the transistor under test M.

[0011] The positioning and driving module is used to locate the scanning start point of the nanoscale four probes on the PN junction depth profile surface of the transistor under test, and drive the nanoscale four probes to move in nanoscale steps along the PN junction depth profile of the transistor under test.

[0012] The signal acquisition and bias module is connected to the nanoscale four probes and is used to apply a bias voltage to the probes and acquire the current and voltage signals fed back by the probes.

[0013] The data processing unit, connected to the signal acquisition and bias module, is used to receive data from the signal acquisition module and the bias module, and calculate the sheet resistance corresponding to each depth node based on the four-probe principle, and plot the resistivity change curve with depth and the carrier concentration change curve with depth in real time; combined with the PN junction built-in electric field model, it identifies the inflection point of carrier type flipping and / or concentration decrease, and determines the electrical junction depth.

[0014] Optionally, it also includes a temperature control module, which is disposed within the vacuum chamber, for adjusting the sample stage temperature within a preset temperature range.

[0015] Optionally, the data processing and depth profiling unit is also used to simultaneously extract the depletion layer width, carrier mobility and reverse saturation current at each depth node;

[0016] Based on the depletion layer width, carrier mobility, and reverse saturation current, a multidimensional electrical characteristic distribution map of the PN junction in the depth direction is constructed.

[0017] Optionally, the probe tip radius is less than 5 nm, and the probe spacing ranges from 30 nm to 500 nm.

[0018] Optionally, the signal acquisition and bias module supports a block rate testing range of 10. -3 ~10 3 Ω·cm, carrier concentration detection range is 10 13 ~10 20 atoms / cm 3 The applied bias voltage range is -20V to +20V, and the current acquisition accuracy is in the picoampere range.

[0019] Based on the same inventive concept, embodiments of the present invention also provide a method for analyzing the electrical parameters of a transistor PN junction, employing the transistor PN junction electrical parameter analysis apparatus provided in the first aspect, comprising:

[0020] The transistor under test is subjected to angle grinding or focused ion beam section cutting to expose the depth profile of the PN junction, and then fixed on the sample stage of the vacuum chamber.

[0021] The control positioning drive module locates the scanning start point of the depth profile and drives the nanoscale four probes to adhere to the depth profile, performing nanoscale step scanning along the depth direction of the PN junction.

[0022] At each scan step, the control signal acquisition and bias module applies forward and reverse bias voltages to the PN junction and acquires the current and voltage signals fed back by the four sets of probes.

[0023] The control data processing unit collects feedback data from the signal acquisition and bias module, calculates the sheet resistance of each depth node based on the four-probe principle, and plots the resistivity variation curve and the carrier concentration variation curve with depth in real time based on the three-dimensional electrical tomography algorithm.

[0024] The data processing unit identifies the inflection point of carrier type reversal or concentration decrease based on the resistivity-depth curve and the built-in electric field model of the PN junction, and determines the electrical junction depth.

[0025] Optionally, it also includes:

[0026] At each depth node, the data processing unit simultaneously extracts carrier concentration, depletion layer width, carrier mobility, and reverse saturation current.

[0027] Optionally, the method for identifying the inflection point of carrier type reversal or concentration decrease is as follows: based on the resistivity change curve with depth measured by the four sets of probes, calculate its first derivative or second derivative, and determine the extreme point of the derivative as the electrical junction depth.

[0028] Optionally, the method for extracting carrier mobility is to combine the sheet resistance measured by four probes with the Hall effect measurement results, or to extract mobility based on IV curve fitting under different bias conditions.

[0029] Optionally, it also includes step S5: repeating steps S2 to S4 within a preset temperature range to establish a temperature-dependent model of carrier activation rate and reverse leakage current.

[0030] In summary, the transistor PN junction electrical parameter analysis device provided in this application includes a vacuum chamber with a sample stage inside; a nanoscale four-probe array comprising four electrically isolated probes arranged at equal intervals for step scanning along the PN junction depth profile; a positioning and driving module for driving the nanoscale four-probe array to perform nanoscale step-like movement; a signal acquisition and bias module for applying a bias voltage and acquiring current and voltage signals; and a data processing unit for calculating the sheet resistance of each depth node based on the four-probe principle, plotting the sheet resistance and carrier concentration variation curves with depth, and determining the electrical junction depth by combining the PN junction's built-in electric field model. This invention employs a nanoscale four-probe architecture to eliminate contact resistance interference, improving spatial resolution to the nanoscale, and can simultaneously extract multi-dimensional electrical parameters such as carrier concentration, mobility, depletion layer width, and reverse saturation current, making it suitable for precise electrical characterization and process optimization of PN junctions in transistors.

[0031] The apparatus and method for analyzing the electrical parameters of a transistor PN junction provided in this invention have the following advantages compared with the prior art:

[0032] First, it completely eliminates contact resistance interference: Traditional SRP technology uses a two-point probe system, which measures the extended resistance, including a large amount of probe contact resistance. It requires extremely complex calibration curves to calculate the resistivity. In contrast, this invention uses a four-point probe architecture, which physically isolates current injection from voltage measurement, directly measuring the true resistivity without the need for complex surface condition calibration, thus significantly improving accuracy.

[0033] Second, spatial resolution achieves an order-of-magnitude leap: Traditional SRP probe spacing is approximately 20 μm, which is insufficient for high-resolution lateral and longitudinal characterization of modern nanoscale advanced processes (such as FinFET and GAA structures). The probe spacing of this invention is reduced to 30-500 nm, improving spatial resolution by nearly a hundred times.

[0034] Third, it overcomes the industry pain point of "assuming mobility": Traditional SRP technology can only measure resistivity, and the doping concentration must be inferred by looking up tables or assuming a carrier mobility model. This invention, through a nano-four-probe combined with a built-in algorithm, can directly and independently extract carrier concentration and mobility, avoiding errors caused by model assumptions.

[0035] Fourth, multi-dimensional synchronous acquisition of electrical and structural parameters: This invention can not only provide junction depth and carrier concentration curves like SRP technology, but also synchronously acquire local depletion layer width and reverse saturation current, which is an integrated ultimate solution. Attached Figure Description

[0036] Figure 1 This is a schematic diagram of a transistor PN junction electrical parameter analysis device provided in an embodiment of the present invention;

[0037] Figure 2 This is a test and microscopic schematic diagram of a transistor PN junction electrical parameter analysis device provided in an embodiment of the present invention;

[0038] Figure 3 This is a schematic diagram of sample preparation and positioning (angle grinding) in an embodiment of the present invention;

[0039] Figure 4 This is a schematic diagram of the probe assembly performing nanostepping scanning along the PN junction depth profile in an embodiment of the present invention;

[0040] Figure 5 This is a gradient map of carrier concentration as a function of depth, generated by scanning and data processing according to an embodiment of the present invention.

[0041] Figure 6 This is a flowchart of a method for analyzing the electrical parameters of a transistor PN junction provided in an embodiment of the present invention. Detailed Implementation

[0042] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the invention and not all structures. Various modifications and variations can be made to the present invention without departing from its spirit or scope, which will be apparent to those skilled in the art. Therefore, the present invention is intended to cover modifications and variations falling within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the embodiments provided in the present invention can be combined with each other without contradiction.

[0043] This invention involves several technical terms, which are explained below:

[0044] 1) A nano-scale four-point probe (n-4PP) refers to an electrical testing structure consisting of four electrically isolated, equally spaced, micro / nano-scale conductive probes with independently adjustable spatial positions. Two probes are used for current injection, and the other two are used for voltage acquisition to eliminate the influence of contact resistance on the measurement results. The probe spacing of the nano-scale four-point probe described in this invention can be reduced to the nanometer scale, enabling high spatial resolution local electrical measurements.

[0045] 2) Spreading resistance refers to the equivalent resistance generated when current is injected into a semiconductor material through a tiny contact area, due to the three-dimensional diffusion distribution of the current within the material. Spreading resistance is closely related to the sheet resistance, carrier mobility, and effective contact radius of the material, and is an important physical basis for inverting carrier concentration through micro-probe contact.

[0046] 3) Electrically active dopant concentration refers to the effective dopant concentration that can participate in carrier transport and make a real contribution to the conductivity of the material, excluding chemical dopant atoms that cannot provide free carriers due to defect recombination, clustering, or deactivation. The doping parameters measured in this invention belong to the electrically active dopant concentration.

[0047] 4) A PN junction (P–N Junction) is a junction structure formed by a P-type semiconductor region and an N-type semiconductor region. It contains a depletion layer formed by carrier diffusion and recombination and a built-in electric field. It is the core functional structure of transistors and diodes.

[0048] The present invention provides a transistor PN junction electrical parameter analysis device in view of one or more of the above-mentioned problems existing in the prior art. Figure 1 This is a schematic diagram of a transistor PN junction electrical parameter analysis device provided in an embodiment of the present invention. Figure 2 This is a module and microscopic schematic diagram of a transistor PN junction electrical parameter analysis device provided in an embodiment of the present invention. Figure 3 This is a schematic diagram of sample preparation and positioning (angle grinding) in an embodiment of the present invention. Figure 4 This is a schematic diagram of the probe assembly performing nanostepping scanning along the depth profile of the PN junction in an embodiment of the present invention. Figure 5 This is a gradient map showing the change of carrier concentration with depth, generated by scanning and data processing according to an embodiment of the present invention.

[0049] in, Figure 2 Figure (a) is a schematic diagram of a transistor PN junction electrical parameter analysis device provided in an embodiment of the present invention. Figure 2Figure (b) is a microscopic schematic diagram of the surface of a transistor PN junction provided in an embodiment of the present invention.

[0050] refer to Figure 1 The transistor PN junction electrical parameter analysis device provided in this application includes a vacuum chamber 10, a nanoscale four-probe 20, and a positioning drive module ( Figure 1 (not shown in the image), signal acquisition and bias module ( Figure 1 (Not shown in the image) and data processing unit 50. The positioning drive module and the signal acquisition and bias module can be integrated with the data processing unit 50 in the same processor. The processor stores a pre-set control program to control the operation of the positioning drive module, the signal acquisition and bias module, and the data processing unit 50, respectively.

[0051] Specifically, a sample stage is provided inside the vacuum chamber 10 for fixing and positioning the transistor M under test. Exemplarily, the vacuum chamber 10 provided in this application adopts a high-vacuum sealed structure, and its interior is equipped with a three-dimensionally movable sample stage for fixing and positioning the transistor M under test. A vacuum adsorption or mechanical clamping mechanism is configured on the surface of the sample stage. Figure 1 (Not shown in the diagram) to stably clamp the transistor M under test, such as a chip or wafer. The vacuum chamber 10 is connected to a vacuum pump assembly consisting of a mechanical pump and a molecular pump (…). Figure 2 (not shown in the image), so that the working vacuum level inside the cavity is better than 10. -3 Pa, thereby reducing electron beam scattering and preventing sample surface oxidation or contamination. Simultaneously, observation windows and electrical feedthrough flanges can be provided on the cavity wall. Figure 1 (not shown in the image), used for observing the detection process and transmitting control signals and acquired data, respectively.

[0052] Combination Figure 1 and Figure 2 The nanoscale quad-probe 20 includes four electrically isolated probes 21 arranged at equal intervals for step scanning along the PN junction depth profile of the transistor M under test. The nanoscale quad-probe 20 provided in this embodiment can be fabricated using MEMS micromachining technology, and the material can be a diamond-coated or carbon nanotube-modified tungsten / beryllium copper alloy. Optionally, the probe tip radius of the probes 21 is less than 5 nm, and the probe spacing is precisely controlled within the range of 30 nm to 500 nm using a MEMS cantilever beam structure. The four probes 21 are arranged linearly or in a square pattern. As an example, the two outer sets of probes 21 form one group, and the two inner sets of probes 21 form another group, respectively forming a loop with the data processing unit 50. One group is used for current injection, and the other group is used for current and voltage signal measurement. Exemplarily, each probe 21 can be independently mounted on a piezoelectric ceramic actuator to achieve independent movement and micro-Newton-level contact force control along the depth direction of the PN junction depth profile of the transistor under test.

[0053] It should be noted that traditional SRP technology uses a two-point probe system, which measures extended resistance including a very large probe contact resistance, requiring extremely complex calibration curves to calculate the sheet resistance. This invention employs a four-probe architecture. Unlike traditional SRP with two metal probes spaced up to 20 μm apart, this device has a very small probe spacing, physically isolating current injection from voltage measurement and supporting high-precision step-by-step scanning along the bevel of the transistor or the cross-section cut by focused ion beam (FIB). This allows for direct measurement of the true sheet resistance without complex surface condition calibration, completely eliminating contact resistance interference and significantly improving accuracy.

[0054] Meanwhile, the spacing of traditional SRP probes is approximately 20 μm, which is insufficient for high-resolution lateral and longitudinal characterization of modern advanced nanoscale processes (such as FinFET and GAA structures). The nanoscale quad probe 20 provided by this invention reduces the spacing to 30-500 nm, improving the spatial resolution by nearly 100 times, achieving an order-of-magnitude leap in spatial resolution.

[0055] The positioning and driving module is used to locate the scanning start point of the nanoscale four-probe 20 on the surface of the PN junction depth profile of the transistor under test M, and to drive the nanoscale four-probe 20 to move in nanoscale steps along the PN junction depth profile of the transistor under test M. In the embodiments of this invention, the positioning and driving module can be a visual navigation system of an integrated scanning electron microscope (SEM), which automatically identifies the start point and scanning trajectory of the PN junction depth profile through an image recognition algorithm. Driven by the high-precision piezoelectric ceramic driver mentioned above, the stepping resolution can reach sub-nanometer level, and the travel range covers 100 μm to 1 mm. The positioning and driving module controls the nanoscale four-probe 20 to move point by point along the inclined plane or cross section according to the preset scanning step size (such as 50 nm or 100 nm). Simultaneously, a laser interferometer or capacitive displacement sensor can be equipped for closed-loop feedback to ensure that the stepping accuracy and repeatability are better than 10% of the step size.

[0056] The signal acquisition and bias module is connected to the nanoscale four-probe 20, used to apply a bias voltage to the probes 21 and acquire the current and voltage signals fed back by the probes. In this embodiment of the invention, the signal acquisition and bias module has ultra-high sensitivity and supports a resistivity testing range of 10. -3 ~10 3 Ω·cm, carrier concentration detection range is 10 13 ~10 20 atoms / cm 3The applied bias voltage range is -20V to +20V, and the current acquisition accuracy is in the picoampere range, enabling precise measurement of weak currents (accuracy up to 0.1 pA) and voltages in the microvolt range, covering the full range of testing from heavily doped to intrinsic semiconductors. For example, the module can integrate a multi-channel precision voltage source and picoampere / femtoampere, with a bias voltage output range of -20V to +20V and a resolution of 1 mV. Each probe has an independent voltage / current channel, and four different connection modes can be switched via a multiplexer switch, including... Figure 2 The standard four-probe method is shown (the outer two sets of probes carry current, and the inner two sets of probes measure current and voltage signals). The module incorporates a high input impedance differential amplifier (>100 GΩ) to reduce the load effect of the voltage measurement loop and supports automatic range switching.

[0057] The data processing unit 50 is connected to the signal acquisition and bias module to receive data from the signal acquisition module and the bias module 40, and calculates the sheet resistance corresponding to each depth node based on the four-probe principle, and plots the resistivity change curve with depth and the carrier concentration change curve with depth in real time; the data processing unit 50 is also used to combine the built-in electric field model of the PN junction to identify the inflection point of carrier type flipping and / or concentration decrease, and determine the electrical junction depth.

[0058] Specifically, the data processing unit 50 provided by this invention incorporates a three-dimensional electrical tomography algorithm, which uses step scan data collected along an inclined plane or cross section to plot resistivity vs. depth and carrier concentration vs. depth curves in real time. For example, the carrier concentration test range covers 10... 13 ~10 20 atoms / cm 3 .

[0059] The sheet resistance is calculated based on the four-probe principle. This embodiment of the invention provides a linear, equally spaced probe arrangement, with the sheet resistance Rs = (I / V) × (π / ln2) × correction factor. Here, I is the current value, V is the voltage value, and the correction factor comprehensively considers factors such as the finite boundary of the sample, the probe spacing, and the depth ratio. It should be noted that in the inclined plane measurement mode, geometric correction of the projected distance is also required.

[0060] Specifically, the conversion relationship between resistivity and carrier concentration is as follows:

[0061] First, the resistivity ρ is obtained using the resistivity formula ρ = Rs × d (where d is the junction depth or effective layer thickness). Then, the carrier concentration N is calculated by using the selected semiconductor material's mobility-concentration empirical model ρ = 1 / qμN. Here, μ is the semiconductor material's mobility, and q is its concentration. The data processing unit 50 incorporates mobility-concentration empirical models for various semiconductor materials (Si, SiGe, GaN, SiC), allowing selection based on the specific material being used in this embodiment.

[0062] Specifically, the junction depth identification method is as follows: A sheet resistance or carrier concentration variation curve is plotted along the depth direction of the PN junction depth profile of the transistor M under test, and its first derivative (rate of change) is calculated. The point of maximum absolute value of the derivative or the point of sign reversal is determined as the location of the electrical junction depth; alternatively, the zero-crossing point of the second derivative can be used to improve the identification robustness. This application generates sheet resistance-depth curves and carrier concentration-depth curves in real time and automatically marks the identified electrical junction depth on the interface.

[0063] The transistor PN junction electrical parameter analysis device provided in this invention, based on its in-situ nanometer electrical testing capability, introduces a depth profiling scanning mechanism similar to SRP, which can completely eliminate the interference of contact resistance through a four-probe architecture.

[0064] Based on the above embodiments, the transistor PN junction electrical parameter analysis device based on a nanoscale four-probe array provided in this invention further includes a temperature control module 60, disposed within a vacuum chamber, for regulating the sample stage temperature within a preset temperature range. Exemplarily, a micro-heater and a liquid nitrogen / Peltier cooling channel can be embedded inside the sample stage. The heater uses ceramic heating elements or resistance wires, with a maximum heating temperature of 150°C; the cooling uses circulating coolant or Peltier electric cooling, with a minimum temperature of -50°C.

[0065] A platinum resistance temperature sensor (PT100) or thermocouple is installed near the probe assembly or in a non-measurement area on the sample surface to monitor the sample surface temperature in real time. The temperature controller is connected to the data processing unit to achieve PID closed-loop temperature control with an accuracy of ±0.5℃. Temperature sequences (such as -50℃, 25℃, 85℃, 150℃) can be preset within the cabinet to automatically complete depth scan tests at each temperature point.

[0066] Based on the above embodiments, the data processing and depth profiling unit 50 provided in this embodiment of the invention is also used to simultaneously extract the depletion layer width, carrier mobility and reverse saturation current at each depth node; and to construct a multidimensional electrical characteristic distribution map of the PN junction in the depth direction based on the depletion layer width, carrier mobility and reverse saturation current.

[0067] Specifically, the depletion layer width is extracted by comparing the four-probe voltage-current response under forward and reverse bias near the PN junction. Under reverse bias, the depletion layer widens, manifested as a wider region of increased resistivity. The data processing unit calculates the local depletion layer width by fitting the transition band width of the resistivity curve (from the flat band to 10%–90% of the steep rise), combined with the material dielectric constant and doping concentration gradient model.

[0068] Specifically, in this embodiment of the invention, the carrier mobility extraction method includes the following two methods.

[0069] Method 1 (Combined with Hall effect): Based on the four-probe method, a Hall measurement function is added. By applying a magnetic field perpendicular to the sample, the transverse Hall voltage is measured, and the carrier mobility μ is calculated using the formula: μ = |V_H| / (B·I·Rs).

[0070] Where μ is the carrier mobility, representing the average drift velocity of carriers under a unit electric field. |V_H| is the absolute value of the Hall voltage (unit: V or μV), the transverse voltage measured perpendicular to the current and magnetic field directions. B is the magnetic flux density (unit: T, Tesla, 1 T = 1 V·s / m²). I is the current through the sample (unit: A or mA). It is typically the constant current injected by the outer two probes of the four probes. Rs is the sheet resistance, which can be calculated using the sheet resistance calculation formula provided in the embodiments below.

[0071] Method 2 (IV Fitting): At the same depth node, current (IV curve) is collected under different bias voltages, and the Schottky contact or Ohm contact model is used for fitting to extract series resistance and mobility parameters.

[0072] The reverse saturation current extraction method involves applying a reverse bias voltage (e.g., -5V to -20V) to the PN junction and measuring the reverse leakage current. The reverse leakage current tends to saturate in the low bias region, and this saturation current value is the reverse saturation current (Is). The data processing unit automatically identifies the flat region of the reverse IV curve and takes the average value.

[0073] The multidimensional map is constructed by using depth as the X-axis and extracting carrier concentration, depletion layer width, mobility, and reverse saturation current as the Y-axis or color mapping, respectively, to generate a two-dimensional distribution map or a three-dimensional surface map for users to visualize and analyze.

[0074] Based on the same inventive concept, embodiments of the present invention also provide a method for analyzing the electrical parameters of a transistor PN junction, using the transistor PN junction electrical parameter analysis apparatus provided in the above embodiments. Figure 6 This is a flowchart of a method for analyzing the electrical parameters of a transistor PN junction provided in an embodiment of the present invention, combined with... Figures 1-6The method for analyzing the electrical parameters of a transistor PN junction provided in this embodiment of the invention includes:

[0075] S101. The transistor under test is angularly ground or cut with a focused ion beam to expose the depth profile of the PN junction, and then fixed on the sample stage of the vacuum chamber.

[0076] Specifically, refer to Figure 3 The transistor under test is subjected to angle lapping or focused ion beam (FIB) section cutting to expose the depth profile of the PN junction of the transistor under test, and the sample is fixed on the sample stage in the vacuum chamber.

[0077] For example, such as Figure 3 In Figure (a), for planar junction devices, an angle grinder is used to grind at a small angle (e.g., 0.5°~5°) to expose a bevel from the surface to the substrate depth, as shown in Figure (a). Figure 3 Figure (b) shows the damaged layer after grinding, which can be removed by cleaning with a low-energy argon ion beam. For three-dimensional structures (FinFET, 3D NAND), use a focused ion beam (FIB) to cut along the direction perpendicular to or parallel to the channel to expose the sidewall cross-section. After cutting, clean with a low voltage (e.g., 2kV) to remove the amorphous layer. Fix the sample to the sample stage with conductive adhesive or a vacuum chuck to ensure good electrical contact.

[0078] S102, The control positioning drive module positions the scanning start point of the depth profile and drives the probe assembly to fit the depth profile, performing nanometer-scale step scanning along the depth direction of the PN junction.

[0079] refer to Figure 4 The starting point of the inclined plane is located using the positioning drive module (SEM visual navigation module). In the SEM image, the operator or an automatic recognition algorithm marks the starting point (e.g., PN junction surface or channel boundary) and ending point (e.g., deep within the substrate) of the depth profile. The scan step size is set (e.g., 50 nm), and the positioning drive module is controlled to move the nanoscale four probes above the starting point. Piezoelectric actuation causes the four probes to simultaneously (or sequentially) contact the sample surface, moving along... Figure 4 In the direction of the arrows in Figure (b), the probe is moved sequentially to each measurement point, repeating the cycle of lowering the probe, measuring, lifting the probe, and moving it again to achieve step-by-step scanning of the PN junction depth profile of the transistor M under test. Simultaneously, to prevent tip wear, the probe is kept at a height of at least 50 nm during the movement.

[0080] S103. At each scan step, the control signal acquisition and bias module applies forward and reverse bias voltages to the PN junction and acquires the current and voltage signals fed back by the four probes.

[0081] For example, refer to Figures 1-5At each scan step, the control signal acquisition and bias module executes the following scan mode:

[0082] Forward scan: from 0V to +5V (or the user-defined maximum value), with a drive voltage step size of 0.1V, recording the current and voltage data of the four probes in each step, i.e., IV data.

[0083] Reverse scan: From 0V to -20V (or user-defined), drive voltage step size 0.2V, record reverse IV data of four probes.

[0084] A single-point bias method can also be used, such as applying a fixed forward bias voltage (e.g., 0.1V) and a fixed reverse bias voltage (e.g., -5V), to quickly measure the resistance and leakage current and record the IV data.

[0085] S104, the control data processing unit acquires signal acquisition and feedback data from the bias module, calculates the sheet resistance of each depth node based on the four-probe principle, and plots the resistivity variation curve and the carrier concentration variation curve in real time based on the three-dimensional electrical tomography algorithm. Based on the resistivity variation curve and combined with the PN junction built-in electric field model, it identifies the inflection point of carrier type reversal or concentration decrease and determines the electrical junction depth.

[0086] For example, combined Figures 1-5 The data processing unit 50 receives the voltage and current signals fed back from the four probes of each depth node in real time and calculates the sheet resistance Rs of each depth node. The sheet resistance is calculated using the following formula:

[0087] Rs = (V_ab / I_cd) × (π / ln2) × C.

[0088] Where V_ab is the voltage between the inner probes, I_cd is the current of the outer probe, and C is the geometric correction factor.

[0089] Then, based on the slope angle θ or the FIB section depth d (effective layer thickness), the measurement step distance along the slope direction is converted into vertical depth.

[0090] Wherein, depth H = step length × sinθ (sloping plane method) or depth H = step length (section method).

[0091] Plot a curve of carrier concentration N versus depth H or a doping concentration gradient plot (e.g.) Figure 5 (As shown in Figure (b)). Calculate the gradient (first derivative) of the curve. The maximum gradient value corresponds to the electrical junction depth. If it is a PN junction inversion, the carrier concentration curve from P-type to N-type will show a V-shaped valley, and the valley point is the junction depth.

[0092] Based on the above embodiments, the method for analyzing the electrical parameters of a transistor PN junction provided in this invention further includes:

[0093] At each depth node, the data processing unit simultaneously extracts carrier concentration, depletion layer width, carrier mobility, and reverse saturation current.

[0094] Specifically, based on the above embodiments, the method for analyzing the electrical parameters of a transistor PN junction further includes:

[0095] At each depth node, the data processing unit simultaneously extracts carrier concentration, depletion layer width, carrier mobility, and reverse saturation current.

[0096] Specifically, at each measurement point, the data processing unit also synchronously or alternately collects the following multiple sets of electrical data:

[0097] Group A contains four-probe resistance data under low bias voltage, used to calculate sheet resistance and carrier concentration.

[0098] Group B contains leakage current data under reverse bias, used to extract reverse saturation current.

[0099] Group C contains IV curve data under different bias voltages, used to fit the mobility.

[0100] The data processing unit provided by this invention stores multiple parameters of each depth node in association, constructs a multi-data list including depth, carrier concentration, depletion layer width, mobility and reverse leakage current, and finally generates a composite map, for example, using color to map mobility, contour lines to represent carrier concentration, and arrows to indicate the distribution of depletion layer width.

[0101] Based on the above embodiments, in the method for analyzing the electrical parameters of a transistor PN junction provided in this embodiment of the invention, the method for identifying the inflection point of carrier type reversal or concentration decrease is as follows: based on the resistivity change curve with depth measured by four sets of probes, calculate its first derivative or second derivative, and determine the extreme point of the derivative as the depth position of the electrical junction.

[0102] Specifically, the depth-sheet resistance sequence is first smoothed using a filter (e.g., a filter with a window size of 5-11 points) to reduce noise. Then, the first derivative d(Rs) / dz is calculated. At the PN junction, where the resistivity changes drastically, the derivative exhibits a maximum or minimum value; this extreme point represents the electrical junction depth. Alternatively, the second derivative d2(Rs) / dz2 can be calculated, and its zero-crossing point corresponds to the junction depth. For junctions with carrier type inversion (e.g., P+ / N-well), the carrier concentration curve drops sharply from high P-type concentration to low N-type concentration at the junction; the negative maximum of the first derivative represents the junction depth. To eliminate spurious peak interference, an effective judgment threshold is set: the absolute value of the derivative must be greater than three times the average derivative.

[0103] Based on the above embodiments, the method for extracting carrier mobility is as follows: combining the sheet resistance measured by four probes with the Hall effect measurement results, or extracting mobility based on IV curve fitting under different bias conditions.

[0104] Based on the above embodiments, the method for analyzing the electrical parameters of a transistor PN junction provided in this embodiment of the invention further includes: repeating steps S102 to S104 within a preset temperature range to establish a temperature-dependent model of carrier activation rate and reverse leakage current.

[0105] For example, the temperature-dependent model is established as follows:

[0106] Preset temperature sequences, such as: -50℃, 0℃, 25℃, 75℃, 125℃, 150℃.

[0107] At each temperature point, the sample stage temperature is stabilized for at least 5 minutes using the temperature control module to ensure thermal balance.

[0108] Repeat steps S102-S104 above, i.e., perform the complete starting point location, step scan, electrical data acquisition, data processing, and junction depth determination. Summarize the carrier concentration curves and reverse leakage current values ​​obtained at each temperature. For each fixed depth point, plot the parameter variation curves with temperature.

[0109] For example, a fitted temperature-dependent model is plotted based on test data:

[0110] The carrier concentration varies with temperature: N(T) = N_0 × exp(-E_a / (kT)), where the activation energy E_a is extracted.

[0111] The reverse leakage current varies with temperature: I_s(T) = I_s0 × exp(-E_g / (kT)), from which the bandgap width E_g is extracted.

[0112] Mobility varies with temperature: μ(T) = μ_0 × T⁻ⁿ, extract the value of n (e.g., n = 1.5 for lattice scattering).

[0113] The model parameters are stored in a database for device reliability prediction or process feedback.

[0114] The following is a specific embodiment to illustrate the method for analyzing the electrical parameters of a transistor PN junction provided by the present invention.

[0115] Example 1:

[0116] The analysis apparatus and method for analyzing the electrical parameters of a transistor PN junction provided in this embodiment of the invention are used to analyze the sidewall doping of a FinFET.

[0117] Sample: 14nm FinFET device, the source and drain doping uniformity of the Fin sidewalls needs to be analyzed.

[0118] Procedure: The Fin structure was cross-sectionally cut using a focused ion beam (FIB) to expose the sidewall channels.

[0119] Test: Combination Figure 4 and Figure 5 The system controls a four-nano probe to scan the sidewall cross-section in 50nm increments and performs data extraction and processing.

[0120] Test results show that the carrier concentration at the center of the source region in the cross-section of the Fin structure is 2.5 × 10⁻⁶. 20 cm −3 The depletion layer exhibits a steep concentration gradient (abrupt junction) towards the channel, with a measured width of 12 nm. Compared to the traditional CV method (which can only measure large-area average values), this method successfully resolves the local doping inhomogeneity problem in the Fin structure.

[0121] The transistor PN junction electrical parameter analysis device and method provided in this invention, compared with the prior art:

[0122] With ultra-high spatial resolution (Nano-SRP): Traditional SRP has a step size on the micrometer scale, while this invention uses probes with a spacing of 30 nm, which can resolve the extremely shallow junctions and sidewall doping distributions of 7 nm / 5 nm process nodes, fundamentally solving the problem that traditional SRP cannot "see" the internal structure of nanodevices.

[0123] It can measure the true parameters of "electrical activity": Unlike SIMS, this device detects electrically active dopants based on the SRP principle, which can truly reflect the activation rate and annealing effect after ion implantation, and the data is closer to the actual electrical performance of the device.

[0124] Contact resistance error can be eliminated: This invention uses a four-probe method to replace the traditional dual-probe method of SRP, which in principle eliminates the influence of contact resistance between the probe and the semiconductor surface, as well as the probe tip resistance. This method significantly improves the measurement accuracy for heavily doped (low resistance) and lightly doped (high resistance) regions, with the error controlled to ≤2%.

[0125] It has a wide dynamic range: the detectable carrier concentration range covers 7 to 8 orders of magnitude (10). 13 cm −3 Up to 10 21 cm −3 It also has the capability to perform full-parameter testing of both forward conduction and reverse breakdown characteristics.

[0126] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, combinations, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. An apparatus for analyzing electrical parameters of a PN junction of a transistor, characterized in that, include: A vacuum chamber containing a sample stage for fixing and positioning the transistor under test; The nanoscale four-probe system comprises four electrically isolated probes arranged at equal intervals, used for step scanning along the PN junction depth profile of the transistor under test. The positioning and driving module is used to locate the scanning start point of the nanoscale four probes on the PN junction depth profile surface of the transistor under test, and drive the nanoscale four probes to move in nanoscale steps along the PN junction depth profile of the transistor under test. The signal acquisition and bias module is connected to the nanoscale four probes and is used to apply a bias voltage to the probes and acquire the current and voltage signals fed back by the probes. The data processing unit, connected to the signal acquisition and bias module, is used to receive data from the signal acquisition module and the bias module, and calculate the sheet resistance corresponding to each depth node based on the four-probe principle, and plot the resistivity change curve with depth and the carrier concentration change curve with depth in real time; combined with the PN junction built-in electric field model, it identifies the inflection point of carrier type flipping and / or concentration decrease, and determines the electrical junction depth.

2. The analysis device of claim 1, wherein, It also includes a temperature control module, which is located inside the vacuum chamber, for adjusting the sample stage temperature within a preset temperature range.

3. The analysis device of claim 2, wherein, The data processing and deep profiling unit is also used to simultaneously extract the depletion layer width, carrier mobility and reverse saturation current at each depth node. Based on the depletion layer width, carrier mobility, and reverse saturation current, a multidimensional electrical characteristic distribution map of the PN junction in the depth direction is constructed.

4. The analysis device of claim 1, wherein, The probe tip radius is less than 5 nm, and the probe spacing ranges from 30 nm to 500 nm.

5. The analysis device of claim 1, wherein, The signal acquisition and bias module supports a sheet resistance testing range of 10. -3 ~10 3 Ω·cm, carrier concentration detection range is 10 13 ~10 20 atoms / cm 3 The applied bias voltage range is -20V to +20V, and the current acquisition accuracy is in the picoampere range.

6. A method of analyzing the electrical parameters of a PN junction of a transistor, using the apparatus for analyzing the electrical parameters of a PN junction of a transistor according to any one of claims 1 to 5, characterized in that, include: The transistor under test is subjected to angle grinding or focused ion beam section cutting to expose the depth profile of the PN junction, and then fixed on the sample stage of the vacuum chamber. The control positioning drive module locates the scanning start point of the depth profile and drives the nanoscale four probes to adhere to the depth profile, performing nanoscale step scanning along the depth direction of the PN junction. At each scan step, the control signal acquisition and bias module applies forward and reverse bias voltages to the PN junction and acquires the current and voltage signals fed back by the four sets of probes. The control data processing unit collects feedback data from the signal acquisition and bias module, calculates the sheet resistance of each depth node based on the four-probe principle, and plots the resistivity variation curve and the carrier concentration variation curve with depth in real time based on the three-dimensional electrical tomography algorithm. The data processing unit identifies the inflection point of carrier type reversal or concentration decrease based on the resistivity-depth curve and the built-in electric field model of the PN junction, and determines the electrical junction depth.

7. The method of claim 6, wherein, Also includes: At each depth node, the data processing unit simultaneously extracts carrier concentration, depletion layer width, carrier mobility, and reverse saturation current.

8. The method of claim 6, wherein, The method for identifying the inflection point of carrier type reversal or concentration decrease is as follows: based on the resistivity change curves with depth measured by the four sets of probes, calculate the first or second derivative, and determine the extreme point of the derivative as the electrical junction depth.

9. The method of claim 6, wherein, The method for extracting carrier mobility is as follows: combining the sheet resistance measured by four probes with the Hall effect measurement results, or extracting mobility based on IV curve fitting under different bias conditions.

10. The method of claim 6, wherein, It also includes step S5: repeating steps S2 to S4 within a preset temperature range to establish a temperature-dependent model of carrier activation rate and reverse leakage current.

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