Mapping management methods, devices, computer equipment, and storage media for solid-state drives

Abstract

This invention discloses a mapping management method, apparatus, computer device, and storage medium for solid-state drives (SSDs). The method includes: establishing an SLC cache mapping table independent of the main mapping table; storing data written by the host in the SLC cache area and recording the mapping relationship between the logical page address and physical page address corresponding to the data in the SLC cache mapping table; when the SLC cache area meets the migration conditions, migrating the data in the SLC cache area to multiple programming data blocks and completing all programming steps for the data in the multiple programming data blocks; after confirming that the data has completed all programming steps in the multiple programming data blocks, deleting the mapping relationship corresponding to the data from the SLC cache mapping table and updating the mapping relationship to the main mapping table. By implementing the method of this invention, the performance and lifespan problems caused by dual mapping updates in existing QLC SSDs using SLC caching technology can be effectively solved.

Description

Technical Field

[0001] This invention relates to the field of solid-state drive (SSD) technology, and more specifically to SSD mapping management methods, devices, computer equipment, and storage media. Background Technology

[0002] Solid-state drives (SSDs), with their significant advantages in reliability and performance, have gradually replaced traditional hard disk drives (HDDs) in the personal computer (PC) market and are widely used in various data storage applications. With the continuous evolution of NAND flash memory manufacturing processes, the density of storage cells has been continuously increasing, evolving from early single-layer cells (SLC, 1 bit / cell) to multi-layer cells (MLC, 2 bits / cell), three-layer cells (TLC, 3 bits / cell), and even four-layer cells (QLC, 4 bits / cell). This evolution has greatly increased the storage capacity per unit area and reduced costs.

[0003] However, as the number of bits stored in each memory cell increases, its programming model becomes increasingly complex. For NAND flash memory types such as SLC, MLC, and TLC, data writing can typically be completed with a single programming operation, and normal reading can be performed immediately. In contrast, QLC NAND, due to its more complex internal voltage distribution, requires multiple programming operations to ensure data accuracy and reliability before stable data storage can be achieved for subsequent reading.

[0004] To ensure data reliability in the event of unexpected power loss and improve the initial write performance of QLC SSDs, the industry commonly employs SLC caching technology. Under this approach, when the host writes user data to the SSD, the data is first quickly written to SLC-mode blocks (i.e., SLC cache blocks), which are simulated by QLC NAND flash memory and offer higher reliability and faster write speeds. Subsequently, when the SSD is idle or under specific conditions, this data temporarily stored in the SLC cache is moved to the QLC blocks by a background cache migration task, completing the multiple programming processes required by QLC.

[0005] In traditional mapping management schemes, the mapping relationship between logical page addresses (LPA) and physical page addresses (PPA) requires two updates: the first is when data is written to an SLC cache block, and the mapping table entry points to the physical address of that SLC cache block; the second is after the data is successfully moved from the SLC cache to the QLC block, and the mapping table entry is updated to point to the physical address of the QLC block. This dual mapping update mechanism can lead to significant performance and durability issues in scenarios where SSD dynamic random access memory (SRAM) resources are limited and the FTLMap cache capacity is small. Specifically, each update of the mapping table may trigger an operation to flush the entire or part of the mapping table to the NAND flash memory. Therefore, within the complete write lifecycle of a piece of user data, its corresponding mapping record may be written to NAND twice. This not only increases write amplification, consuming valuable NAND write bandwidth and thus reducing the overall write performance of the SSD; at the same time, frequent mapping table writes also accelerate the wear and tear of NAND flash memory, shortening the lifespan of the SSD. Summary of the Invention

[0006] The purpose of this invention is to overcome the shortcomings of the prior art and provide a mapping management method, apparatus, computer equipment and storage medium for solid-state drives.

[0007] To achieve the above objectives, the present invention adopts the following technical solution: Solid-state drive (SSD) mapping management methods, applied to storage chips that require multiple programming iterations, include: Establish an SLC cache mapping table independent of the main mapping table to record the mapping relationship between logical page addresses and physical page addresses of data in the SLC cache area; Receive host write requests, store the data written by the host in the SLC cache, and record the mapping relationship between the logical page address and the physical page address corresponding to the data in the SLC cache mapping table; When the SLC buffer meets the relocation conditions, the data in the SLC buffer is moved to the multi-programming data block, and all programming steps for the data in the multi-programming data block are completed. After confirming that the data has completed all programming steps in multiple programming data blocks, the mapping relationship corresponding to the data is deleted from the SLC cache mapping table, and the mapping relationship is updated to the main mapping table.

[0008] The present invention also provides a mapping management device for solid-state drives, applicable to storage particles that require multiple programming operations, comprising: Establish a record unit to create an SLC cache mapping table independent of the main mapping table, which is used to record the mapping relationship between the logical page address and the physical page address of the data in the SLC cache area; The receiving storage unit is used to receive host write requests, store the data written by the host in the SLC cache area, and record the mapping relationship between the logical page address and the physical page address corresponding to the data in the SLC cache mapping table. The transfer unit is used to transfer the data in the SLC buffer to the multi-programming data block when the SLC buffer meets the transfer conditions, and to complete all programming steps of the data in the multi-programming data block. The update unit is used to delete the mapping relationship corresponding to the data from the SLC cache mapping table and update the mapping relationship to the main mapping table after confirming that the data has completed all programming steps in multiple programming data blocks.

[0009] The present invention also provides a computer device, the computer device including a memory and a processor, the memory storing a computer program, and the processor executing the computer program to implement the above-described method.

[0010] The present invention also provides a storage medium storing a computer program that, when executed by a processor, implements the above-described method.

[0011] The beneficial effects of this invention compared to existing technologies are as follows: By setting up an independent SLC cache mapping table, the temporary mapping of data in the SLC cache stage is isolated from the main mapping table. The main mapping table is only updated once after the data has been moved to multiple programming data blocks and all multiple programming operations are completed. This reduces the two mapping updates in the traditional solution to one, reducing the frequency and amount of data brushed to NAND under the mapping table. This not only effectively improves the write performance of SSD, but also reduces write amplification and NAND wear, extends the lifespan of SSD, and enhances data reliability under abnormal scenarios such as power failure.

[0012] The present invention will be further described below with reference to the accompanying drawings and specific embodiments. Attached Figure Description

[0013] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0014] Figure 1 A schematic diagram illustrating an application scenario of the solid-state drive mapping management method provided in this embodiment of the invention; Figure 2 A flowchart illustrating the solid-state drive mapping management method provided in an embodiment of the present invention; Figure 3A schematic block diagram of a solid-state drive mapping management device provided in an embodiment of the present invention; Figure 4 A schematic block diagram of a computer device provided for an embodiment of the present invention. Detailed Implementation

[0015] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0016] It should be understood that, when used in this specification and the appended claims, the terms "comprising" and "including" indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0017] It should also be further understood that the term "and / or" as used in this specification and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0018] Please see Figure 1 and Figure 2 , Figure 1 This is a schematic diagram illustrating an application scenario of the solid-state drive mapping management method provided in an embodiment of the present invention. Figure 2 This is a schematic flowchart illustrating a solid-state drive (SSD) mapping management method provided in an embodiment of the present invention. This SSD mapping management method is applied to a server that interacts with a terminal, effectively solving the performance and lifespan issues caused by dual mapping updates in existing QLCSSDs using SLC caching technology.

[0019] Figure 2 This is a flowchart illustrating the solid-state drive mapping management method provided in an embodiment of the present invention. Figure 2 As shown, the method is applied to memory chips that require multiple programming steps and includes the following steps S110 to S140.

[0020] S110. Establish an SLC cache mapping table independent of the main mapping table to record the mapping relationship between logical page addresses and physical page addresses of data in the SLC cache area. Specifically, during the SSD controller initialization phase, the firmware dynamically allocates a contiguous memory region in SRAM as the SLC Cache Map. This table uses a hash table or direct index array structure, with the key being the host logical page address (LPA) and the value being the physical page address (PPA) and a status flag (such as valid / invalid). The lifecycle of this table is tied to the SLC cache, and its size is pre-configured based on the SLC cache capacity (for example, if the SLC cache is 64MB and the logical page size is 4KB, then a total of 4096 entries are required). This table is completely independent of the main FTL mapping table's data structure and memory space, maintained by a dedicated cache management module, and does not participate in the main mapping table's flush or recovery process.

[0021] In other words, by creating a dedicated, isolated mapping structure in SRAM, the main mapping table is prevented from expanding or being frequently updated due to high-frequency cache writes, thus reducing the memory footprint and management complexity of the main mapping table. At the same time, the lightweight data structure supports O(1) or near-O(1) lookup / insertion performance, providing low-latency mapping services for cache writes.

[0022] In one embodiment, establishing an SLC cache mapping table independent of the main mapping table, used to record the mapping relationship between logical page addresses and physical page addresses of data in the SLC cache, includes: During the power-on initialization phase, a memory region is allocated from volatile memory as the storage space for the SLC cache mapping table; Specifically, after the SSD controller completes its Power-On Self-Test (POST) and enters the firmware execution phase, the system resource management module reads the firmware configuration parameters or loads system configuration information from the metadata area in the NAND (such as the Boot Block or Super Block). This information includes the SLC cache's enabled status and preset capacity (e.g., 64MB). Subsequently, the firmware calls the SRAM memory manager (usually based on a buddy system or slab allocator) to request a contiguous or non-contiguous but logically contiguous physical memory region from the operating system abstraction layer (or bare-metal memory pool). The size of this region is determined based on the subsequently calculated number of entries and the number of bytes per entry (e.g., 8 bytes per entry, requiring a total of 4096 entries). After allocation, this memory block is registered as a dedicated area for the SLC cache mapping table and memory protection attributes (such as read-only / write permission control) are set to prevent accidental access by other modules. This process occurs early in the FTL (Flash Translation Layer) initialization process, before the host I / O services start.

[0023] In other words, by reserving dedicated SRAM space at the initial stage of system startup, the SLC cache mapping table is ensured to have defined and isolated memory resources, avoiding allocation failures due to memory fragmentation or contention during runtime. Placing the mapping table in high-speed volatile memory (SRAM) provides nanosecond-level access latency for subsequent high-frequency mapping queries and updates, which is a key prerequisite for achieving high-performance writing of the SLC cache. At the same time, the establishment of dedicated memory areas strengthens the decoupling between software modules and improves system maintainability and stability.

[0024] Based on the SLC cache capacity configured in the system, determine the number of entries required for the SLC cache mapping table, and initialize all entries to an invalid state; Specifically, the firmware calculates the maximum number of pages that can be stored based on the known total capacity of the SLC cache (e.g., 64MB) and the NAND page size (e.g., 16KB): Number of entries = SLC cache capacity / page size. For example, 64MB = 64 × 1024KB, divided by 16KB = 4096 pages, meaning 4096 mapping entries are needed. Each entry typically contains a Physical Page Address (PPA, e.g., 4 bytes) and a status flag (e.g., 1 byte, used to mark "valid", "invalid", "dirty", etc.). After memory allocation, the firmware zeroes the entire mapping table memory area using memset or circular assignment, or explicitly sets the status field of each entry to "Invalid" and the PPA field to an invalid value (e.g., 0xFFFFFFFF). This initialization operation ensures that all mapping entries are in a known, safe initial state before the system begins receiving write requests, preventing incorrect mappings due to residual data.

[0025] In other words, by precisely matching the size of the mapping table to the cache capacity, both memory waste (over-allocation) and mapping table overflow (under-allocation) are avoided; the unified initialization to an invalid state eliminates the risk of residual data after power-on and ensures the correct starting point of the mapping relationship; the clear status flag mechanism provides a reliable basis for subsequent valid page identification, garbage collection and mapping updates, which is the foundation for achieving efficient cache management and data consistency control.

[0026] Configure the data structure of the mapping table to support fast lookup or writing of the corresponding physical page address using the logical page address as an index.

[0027] Specifically, the firmware selects a suitable data structure to implement the SLC cache mapping table based on the trade-off between performance and memory overhead. Specific solutions include: (1) Direct index array: If the LPA address space is continuous and the range is controllable (e.g., only the recently written LPA segment is cached), the lower N bits of LPA can be used as array subscripts to achieve O(1) access; (2) Hash table: A more general solution, using LPA as the key, mapping to buckets through hash functions (e.g., CRC32 or simple modulo operation), with each bucket using linked lists or open addressing to handle collisions; (3) Radix tree or B+ tree: Suitable for sparse LPA distribution scenarios, supporting efficient range queries. In this implementation, a hash table structure is usually adopted because it provides near O(1) insertion / search performance on average, and the memory overhead is controllable. The firmware constructs a hash bucket array during initialization and pre-allocates the node pool. When insertion is required...<LPA,PPA> When searching, the hash value is calculated, the bucket is located, and the linked list is traversed to check if the same LPA already exists (overwrite). If not, a new node is allocated to fill it; the same applies to searching. All operations are performed in SRAM without accessing NAND.

[0028] In other words, the efficient data structure design enables the SLC cache mapping table to complete mapping lookups and updates within microseconds or even nanoseconds, perfectly matching the high-speed write characteristics of the SLC cache; it avoids mapping lookups becoming a performance bottleneck and ensures low end-to-end latency in the host write path; at the same time, the reasonable structure selection achieves a balance between high throughput and low memory usage with limited SRAM resources, providing key support for the stable performance of SSDs under high load scenarios.

[0029] S120. Receive a host write request, store the data written by the host in the SLC cache, and record the mapping relationship between the logical page address and the physical page address corresponding to the data in the SLC cache mapping table. Specifically, when the host sends a write command (such as NVMe Write or SATA WRITE DMA), the SSD front-end interface module parses the LBA range and converts it to LPA. The mapping management layer queries the SLC cache free page manager (such as a free list or bitmap) and allocates a physical page (PPA_slc) in SLC mode. Data is written to the NAND SLC cache block via the DMA engine (this block has been pre-configured in SLC programming mode, using only the least significant bit of each cell). Subsequently, the firmware calls the SLC cache mapping table insertion interface to...<LPA,PPA_slc> The key-value pair is written to the SLC cache mapping table in SRAM, and the page is marked as "valid". The entire process does not access the main mapping table, nor does it trigger any metadata flushing operation.

[0030] In other words, the host write path is greatly simplified, involving only fast writes to the SLC cache and lightweight mapping updates within SRAM, fully utilizing the high write speed and low latency of SLC mode; since the main mapping table is not involved at all, it avoids SRAM bandwidth contention and potential NAND metadata writes caused by mapping updates in traditional solutions, thereby improving write IOPS and throughput.

[0031] In one embodiment, receiving a host write request, storing the data written by the host in the SLC cache, and recording the mapping relationship between the logical page address and the physical page address corresponding to the data in the SLC cache mapping table includes: Receive write commands from the host, and parse the logical page address range and the data to be written contained therein; Specifically, the front-end interface module of the SSD controller (such as the NVMe or SATA protocol engine) first receives the write command packet (e.g., NVMe NVM Write Command) sent by the host via the PCIe or SATA link. This command packet contains the starting LBA (Logical Block Address), the transfer length (Number of LBAs), and a PRP (Physical Region Page) or SGL (Scatter-Gather List) descriptor pointing to the data buffer in host memory. The firmware driver layer converts the LBAs into a sequence of consecutive logical page addresses (LPAs) according to the system-defined page size (e.g., 4KB LBAs per page, or merged into 16KB logical pages). Simultaneously, the DMA engine, based on the PRP / SGL information, moves host data from host memory to the SRAM or SRAM data buffer inside the SSD controller via the PCIe bus. The entire parsing process is completed collaboratively by the hardware accelerator and firmware, ensuring command decoding and data readiness are completed within microseconds.

[0032] In other words, the standardized command parsing process ensures compatibility with different host I / O modes; the efficient conversion of LBA to LPA provides a unified address view for subsequent mapping management; and the use of DMA to directly move data avoids CPU copy overhead and improves data path efficiency.

[0033] Allocate a free physical page from the SLC cache and write the host data to that physical page; Specifically, the mapping management layer invokes the block / page manager of the SLC cache (typically based on a free page list, bitmap, or log structure allocator). This manager maintains a dedicated SLC block pool (these NAND blocks are configured for SLC programming mode during SSD initialization, meaning each storage cell stores only 1 bit, with the remaining bits reserved) and tracks the status of used and free pages within each block. When a page of data needs to be written, the manager allocates the next available physical page address (PPA_slc) from the currently open SLC write block; if the current block is full, it closes the block and opens a new block from the SLC free block pool. Subsequently, the firmware constructs NAND programming commands, processes the host data in SRAM through the NAND channel controller and ECC encoder (such as LDPC), and writes it to the NAND page corresponding to the specified PPA_slc according to the SLC programming timing. After the write is complete, the NAND status register is read to confirm successful programming, and optional fast readback verification is performed.

[0034] In other words, by using a dedicated SLC block pool and an efficient page allocation mechanism, it is ensured that write operations always fall within the high-speed, low-latency SLC region, fully leveraging the advantages of SLC mode's fast write speed and high durability; avoiding the multi-stage programming latency and early wear caused by directly writing to QLC / TLC; ECC encoding and status confirmation ensure the initial reliability of cached data, providing high-quality source data for subsequent migration.

[0035] Obtain the physical page address of the allocated physical page and match it with the logical page address in the host write request; Specifically, after successfully allocating a physical page and completing the data write, the SLC page manager returns the complete physical page address (PPA_slc). This address is typically composed of fields such as Channel, Chip, Block, and Page, forming a globally unique physical identifier. Simultaneously, the front-end parsing module has converted the LBA in the host write command into the corresponding logical page address (LPA). The mapping management layer binds these two address values ​​in a local variable or temporary structure, forming a...<LPA,PPA_slc> Mapping pairs. This pairing process is completed synchronously within the firmware task context, ensuring the accuracy and timeliness of address mappings and preventing mismatches caused by concurrent writes.

[0036] In other words, accurate address pairing is a prerequisite for establishing a correct mapping relationship; by binding LPA and PPA immediately upon completion of writing, the risk of inconsistency in intermediate states is avoided; the use of globally unique PPAs ensures that the mapping relationship remains accurate and unambiguous even in multi-channel, multi-plane architectures, providing a reliable index for subsequent data reading and migration.

[0037] Write the mapping pair of logical page address and physical page address into the corresponding position in the SLC cache mapping table to complete the temporary record of the mapping relationship.

[0038] Specifically, the firmware calls the write interface of the SLC cache mapping table and passes in...<LPA,PPA_slc> Mapping pairs. The mapping table module calculates the hash value of the LPA based on a preset data structure (such as a hash table), locates the corresponding bucket, and then traverses the linked list within the bucket to check if there is an old entry with the same LPA (to handle overwrite scenarios). If it exists, its PPA and status flags are updated; if not, a free node is taken from the pre-allocated node pool, filled with the LPA, PPA_slc, and valid status, and inserted at the head of the linked list. The entire write operation is completed in SRAM without accessing NAND, and is typically performed atomically or with lightweight lock protection to support concurrent writes across multiple cores or tasks. After the write is complete, the mapping entry can be immediately used by subsequent read requests or migration tasks.

[0039] In other words, by recording the mapping relationship only in an independent SLC cache mapping table, the main FTL mapping table is completely bypassed, avoiding SRAM bandwidth contention and NAND metadata write overhead caused by frequent updates to the main table; the efficient hash insertion mechanism ensures extremely low mapping registration latency and does not become a bottleneck in the write path; the overwrite write processing mechanism guarantees the semantic consistency of the logical address space; the design of temporary records provides the basis for the subsequent optimization strategy of "updating the main table only after the QLC migration is completed", which is one of the core mechanisms for reducing write amplification and improving performance and lifespan.

[0040] S130. When the SLC buffer meets the relocation conditions, the data in the SLC buffer is moved to the multi-programming data block, and all programming steps for the data in the multi-programming data block are completed. Specifically, the SLC cache management module continuously monitors cache utilization, effective page ratio, and system idle time. When a threshold is triggered (e.g., utilization reaches 80%), a background task starts: first, it iterates through the SLC cache mapping table to collect all effective pages.<LPA,PPA_slc> The firmware first reads the valid page data from the SLC cache and then allocates a target QLC block (i.e., a multi-programmed data block) from the QLC free block pool. Next, the firmware sequentially reads the valid page data from the SLC cache and writes it to the QLC block in stages according to the QLC NAND programming timing requirements—for example, first combining multiple pages of data and performing Lower Page programming, then performing Upper Page programming after ECC verification, and including Extra Page programming if necessary. Each programming step requires waiting for the NAND status register to return ready and verifying the programming result. The entire migration process is hardware-accelerated by the NAND controller, but the firmware strictly controls the programming order and data integrity.

[0041] In other words, by completing the multi-stage programming of QLC in the background in a batch manner, both the SLC cache space is freed up for new writes and the physical stability of data in high-density media is ensured. The staged programming conforms to the electrical characteristics of QLC devices, avoids data errors caused by programming interference, and ensures long-term reliability. At the same time, batch migration improves NAND bandwidth utilization and reduces the unit data migration overhead.

[0042] In one embodiment, when the SLC buffer meets the relocation conditions, the data in the SLC buffer is moved to the multi-programming data block, and all programming steps for the data in the multi-programming data block are completed, including: Continuously monitor the usage status of the SLC cache to determine whether the relocation conditions are met; Specifically, the SLC cache management module in the SSD firmware periodically (e.g., every millisecond) or event-driven (e.g., after each write) collects key status metrics of the SLC cache in the background. These metrics include: (1) the percentage of SLC cache used capacity (e.g., reaching the 80% threshold); (2) the ratio of valid pages to invalid pages in the SLC cache (e.g., triggering reclamation when the validity rate is below 60%); (3) the length of system idle time (e.g., 100ms of continuous host I / O); and (4) the write lifespan of the SLC cache block is approaching its limit. The firmware maintains a state machine or scheduler that compares the above metrics with preset policies (usually stored in the firmware configuration table). When any condition is met (e.g., capacity exceeds the limit or the system is idle), the "relocation trigger flag" is set, notifying garbage collection (GC) or cache refresh tasks to start. This monitoring process is executed by a low-priority kernel thread and does not block foreground I / O.

[0043] In other words, the proactive and intelligent monitoring mechanism ensures that the SLC cache space is always available, preventing a sudden drop in host write performance due to cache exhaustion (i.e., "cache speed drop"); the judgment based on multi-dimensional conditions takes into account performance, lifespan and efficiency, and performs migration during the low period of system load to maximize resource utilization; it avoids the waste of NAND bandwidth caused by blind or premature migration and improves the overall I / O scheduling efficiency.

[0044] When the migration conditions are met, the data migration task is triggered, and the valid data pages to be migrated in the SLC buffer are read. Specifically, once the migration conditions are met, the firmware scheduler wakes up the background migration task (usually a garbage collection subtask). This task first traverses the SLC cache mapping table (such as a hash table) and filters out all instances with a status of "valid".<LPA,PPA_slc> The entries are compiled into a list of LPAs to be moved. Next, the task calls the NAND read interface to sequentially send read commands to the PPA_slc in the SLC cache block. The NAND controller reads the raw data from the specified physical page and performs error correction using an ECC decoder (such as LDPC) to recover the original host data. The read data is temporarily stored in the migration buffer in SRAM, typically organized by block or page alignment. The entire read process is accelerated using multi-channel parallel read capabilities and may skip overwritten invalid pages (determined by the mapping table status), moving only valid data.

[0045] In other words, moving only valid data reduces unnecessary NAND read operations, lowering read amplification and power consumption; ECC ensures the integrity of the source data being moved, preventing data corruption due to SLC page aging or interference; parallel reading and buffer management optimize SRAM bandwidth usage, providing a continuous and reliable data stream for subsequent QLC programming.

[0046] Select an idle multi-programming data block and write the read data to the first programming position of that multi-programming data block; Specifically, the relocation task requests a free QLC block from the FTL's block manager. The block manager selects a physical block with a low erase cycle (PE cycle) and good health from the Free Block Pool and marks it as "open for relocation". Subsequently, the firmware, according to the QLC NAND programming rules (such as Micron or Kioxia specifications), groups the read data by page and constructs the first programming (usually Lower Page or First Pass) command. For example, in a 16KB page-sized QLC, four logical pages may need to be combined into one programming unit. After ECC encoding, the data is written to the starting page address of the target block (e.g., Page 0, 4, 8…) via the NAND channel controller in QLC Lower Page timing. After writing, it waits for the NAND to return to a ready state and records the temporary physical page address (PPA_qlc_temp) for this programming.

[0047] In other words, the initial writing of high-density data is achieved through the first programming stage of QLC, making full use of the storage capacity advantage of QLC; healthy free blocks are selected to ensure long-term data reliability; only a portion of bits are written during the first programming stage, leaving a window for subsequent programming, laying the physical foundation for achieving full QLC storage; although the writing in this stage is slower than that of SLC, it is performed in batch processing, reducing the average programming latency per unit of data.

[0048] When new data is written to an adjacent logical page address or the conditions for secondary programming are met, a second programming operation is performed on the same physical block to make the data reach a stable storage state in the NAND flash memory. Specifically, QLC NAND requires that all programming stages (such as Lower + Upper Page) of the same physical page must be completed to ensure data stability. Therefore, the firmware maintains a "Pending Program Queue" to record QLC blocks that have been programmed for the first time but have not completed all stages, as well as their written page information. Secondary programming is triggered when any of the following conditions are met: (1) The new data written by the host has an LPA that is logically adjacent to the moved data (such as the same 4KB alignment cluster), which can be merged to complete the Upper Page; (2) The system enters a deep idle state and actively backfills the remaining programming; (3) The QLC block is about to be closed. At this time, the firmware extracts the required supplementary data (which may be zero-fill or newly written data) from the SRAM transfer buffer or master mapping table, constructs the Upper Page (or Second Pass) programming command, and writes the remaining bits of the same physical page again. This process must strictly follow the programming interval and voltage sequence specified by the NAND manufacturer.

[0049] In other words, by delaying and merging secondary programming, the physical programming constraints of QLC devices are satisfied, while avoiding the surge in write latency caused by immediate secondary programming. By merging writes using logical adjacency, the efficiency of QLC programming and the effective data rate are improved. It ensures that all data is eventually in a fully programmed state, preventing data loss or read failure due to incomplete programming, and guaranteeing the data durability and consistency of the SSD.

[0050] Confirm that the data has completed all the necessary programming steps in multiple programming data blocks and obtain its final physical page address.

[0051] Specifically, after the last programming operation (such as Upper Page) successfully returns to the ready state, the firmware executes a verification process: First, it reads back the data of the QLC page that was just programmed and checks whether it can be correctly recovered using the ECC decoder; if the verification passes, it is determined that the page has completed all the necessary programming steps. At this point, the physical address of the page (PPA_qlc_final) is determined as the final stable address and will not be changed. The firmware associates this PPA_qlc_final with the original LPA and updates the internal metadata structure (such as the block page mapping log), while updating the status of the QLC block from "partially programmed" to "fully programmed" or "closed". This final PPA will be used for subsequent updates to the master mapping table. The entire verification process may be accompanied by writing to the mapping log (Journal) to support power-down recovery.

[0052] In other words, the programming completion confirmation mechanism ensures the physical stability of data in the QLC medium, serving as the last line of defense for data reliability; obtaining the final PPA provides an accurate target address for atomically switching the master mapping table; and log recording ensures that even if there is a power failure after secondary programming, the correct mapping can be reconstructed through logs or scans after system restart, avoiding data corruption or loss, thereby maintaining enterprise-level data integrity requirements while increasing storage density.

[0053] S140. After confirming that the data has completed all programming steps in multiple programming data blocks, delete the mapping relationship corresponding to the data from the SLC cache mapping table and update the mapping relationship to the main mapping table.

[0054] Specifically, after all programming steps of the QLC block are successfully completed and pass ECC verification, the firmware performs an atomic mapping switch: First, it locks the entry for the corresponding LPA in the main mapping table in SRAM; then, it deletes the record for that LPA from the SLC cache mapping table and releases the original SLC physical page; next, it switches the new...<LPA,PPA_qlc> The mapping is written to the SRAM cache of the main mapping table; finally, the main mapping table entry is marked as "dirty" and awaits unified writing to the NAND mapping log or mapping page in subsequent batch flush cycles. The entire process ensures power-loss consistency through memory barriers and transaction logs (such as Journal)—if a power failure occurs during the update, the temporary mapping can be reconstructed by log replay or scanning the SLC cache after the system restarts.

[0055] In other words, by compressing the original two primary mapping updates (SLC→QLC) into a single final update, the frequency of primary mapping table modifications and the amount of NAND metadata written are significantly reduced, directly reducing write amplification (WA). The batching and delayed flushing of mapping updates further optimize NAND bandwidth allocation. The atomic switching mechanism ensures that even in the event of an abnormal power outage, the primary mapping table either points to the old QLC position or remains in an unupdated state. Combined with the recoverable SLC cache mechanism, strong data consistency is guaranteed, while extending the lifespan of the SSD and improving performance stability.

[0056] In one embodiment, the step of deleting the mapping relationship corresponding to the data from the SLC cache mapping table and updating the mapping relationship to the main mapping table after confirming that the data has completed all programming steps in multiple programming data blocks includes: After the data has been fully programmed, obtain its final physical page address in the multiple programmed data blocks; Specifically, once a page in a QLC NAND block completes its final necessary programming stage (e.g., Upper Page programming) and is confirmed ready via its internal status register, the firmware extracts the complete physical page address (PPA_qlc_final) of that page from the command context of the NAND channel controller or the local variables of the transfer task. This address, composed of fields such as Channel number, Chip Select, Block number, Page number, and possibly Plane ID, is a globally unique and stable physical identifier. This PPA has already been precisely calculated and used in constructing programming commands during the preceding transfer and secondary programming processes, so it can be directly reused upon successful programming confirmation without additional lookup. The firmware temporarily stores this PPA along with the original logical page address (LPA) in the Task Control Block as input parameters for subsequent mapping updates.

[0057] In other words, accurately obtaining the final physical address is a prerequisite for ensuring that data can be read correctly; since the address is determined in the programming command, direct reuse avoids additional address resolution or NAND scan overhead; global uniqueness ensures that even in a multi-channel, multi-plane architecture, the master mapping table can accurately point to the physical location of the data, providing a basic guarantee for system consistency.

[0058] Based on the logical page address of the data, locate and clear the corresponding mapping entry in the SLC cache mapping table, and release the table entry; Specifically, the firmware calls the delete interface of the SLC cache mapping table, passing in the LPA that has been moved. The mapping table module performs a hash operation on the LPA according to its internal data structure (such as a hash table), locates the corresponding bucket, and then traverses the linked list within the bucket to find a matching LPA entry. Once found, the firmware performs the following atomic operations: (1) sets the status flag of the entry to "Invalid"; (2) clears the PPA field to zero or sets it to an invalid value; (3) returns the node to the pre-allocated free node pool (if a linked structure is used); (4) updates the SLC cache free page counter, marking the original SLC physical page as erasable. The entire process is usually completed under the protection of lightweight spinlocks or atomic instructions to prevent concurrent read and write conflicts. After being cleared, the LPA is no longer valid in the SLC cache mapping table, and any subsequent read requests for the LPA will no longer hit the SLC cache.

[0059] In other words, timely clearing of expired entries in the SLC cache mapping table prevents old mappings from interfering with new writes or causing data misreads; releasing table entry memory resources maintains the high efficiency of the mapping table and avoids memory leaks; synchronously releasing SLC physical pages creates conditions for subsequent erasure and reuse, improving the space reclamation efficiency of the SLC cache area; and ensuring mapping consistency in a multi-task environment through atomic operations are key aspects of stable system operation.

[0060] Write the mapping relationship between the logical page address and the final physical page address into the main mapping table.

[0061] Specifically, the firmware calls the update interface of the main FTL mapping table and passes in...<LPA,PPA_qlc_final> Mapping pairs. The master mapping table typically uses a hierarchical structure (such as SRAM cache + NAND storage log or BMT). Updates are first performed in the mapping cache in SRAM: if the entry corresponding to the LPA is already in the cache, its PPA value is directly overwritten; if not, the corresponding mapping page is loaded from NAND into the cache before updating. After the update is complete, the entry is marked as "Dirty". The master mapping table manager does not immediately flush the change, but waits for a batch commit opportunity (such as when the cache is full, the system is idle, or a periodic checkpoint) to aggregate multiple "dirty" entries and write them to the NAND mapping journal or a dedicated mapping page. The entire process is protected by a transaction log (such as the Journal Log): before updating the SRAM mapping, the old PPA and the new PPA are recorded in a power-loss-safe log area to ensure that even if a power outage occurs during the update, the system can be restored to a consistent state through log replay after a restart.

[0062] In other words, the mapping relationship is ultimately solidified into the main mapping table, so that subsequent read requests from the host to this LPA can directly locate the stable data position in the QLC, completing the closed loop of the data lifecycle; delayed batch flushing significantly reduces the number of NAND metadata writes and reduces write amplification; the transaction log mechanism provides strong power failure consistency guarantee, avoiding data loss or logical-physical address mismatch caused by incomplete mapping updates; the main table is only updated after the QLC migration is completed, avoiding the dual main table updates caused by "writing to SLC first and then writing to QLC" in the traditional solution, fundamentally optimizing metadata management efficiency, extending SSD lifespan and improving long-term performance stability.

[0063] In one embodiment, after confirming that the data has completed all programming steps in multiple programming data blocks, deleting the mapping relationship corresponding to the data from the SLC cache mapping table and updating the mapping relationship to the main mapping table includes: Release and reclaim the physical storage resources of the SLC cache.

[0064] Specifically, after the corresponding entry in the SLC cache mapping table is successfully cleared and the main mapping table is atomically updated to point to the final physical page address of the QLC, the firmware's SLC cache management module initiates the resource reclamation process for the NAND block to which the original SLC physical page belonged. This process does not immediately erase a single page, but rather adopts a block-level garbage collection strategy based on the physical characteristic of NAND flash memory to erase in blocks.

[0065] First, the system maintains a dedicated SLC block pool, where each block is marked as "SLC programming mode" and configured during the initialization phase (e.g., enabling SLC operations via OTP or register settings). The state within each SLC block is tracked by a bitmap or a valid page counter. When a page's data is successfully moved to the QLC and the mapping switch is completed, the page's state within its SLC block is marked as "Invalid," and the block's valid page count is decremented by one.

[0066] When the number of valid pages in an SLC block drops to zero (i.e., all pages are invalid), or the system detects that the overall pressure on the SLC cache has eased (e.g., the number of free blocks is below a threshold), the block manager adds the completely invalid SLC block to the "Erase Queue". Subsequently, in the background task scheduling window (usually during the host I / O idle period), the erase task is triggered: the firmware sends a block erase command to the NAND controller, specifying the physical block address (PBA_slc) of the SLC block. The NAND chip performs a high-voltage erase operation, resetting all memory cells in the entire block to the erase state (usually all 1s). After the erase is complete, the NAND returns the status register value, and the firmware verifies whether it was successful (e.g., checking if the Bad Block flag is not set). If the erase is successful, the block is reclassified as an "SLC free block" and returned to the SLC free block pool, available for subsequent host write or move tasks to allocate again; if the erase fails (e.g., bad blocks are found), it is removed from the SLC pool and recorded in the bad block table (BBT), and will no longer participate in any allocation.

[0067] It is worth noting that, in order to improve efficiency, some implementations may use a "log structure" or "sequential write pointer" mechanism to manage SLC blocks: new writes are always appended to the next free page of the currently open block, and when the block is full, it is directly closed and a new block is opened. Invalid pages are only erased when the block is completely invalid, avoiding the complex page-level reclamation overhead in traditional FTL.

[0068] In other words, by using block-level erasure and free block pool management, the SLC cache area is ensured to maintain available physical space throughout long-term operation, avoiding a precipitous drop in write performance due to resource exhaustion and maintaining stable high-performance SSD performance under high load. Furthermore, while SLC mode itself has high endurance (P / E cycles exceeding 100,000), failure to promptly reclaim blocks containing invalid pages will cause frequent write pointer jumps or trigger unnecessary data migrations. By accurately identifying and centrally erasing completely invalid blocks, write amplification and NAND bandwidth usage are reduced, extending the lifespan of the SLC area and even the entire disk.

[0069] In one embodiment, releasing and reclaiming the physical storage resources of the SLC cache includes: Mark the physical pages in the SLC cache that were originally used to store this data as invalid pages; Specifically, after confirming that the data has been successfully moved to the QLC / TLC multi-programming block, the master mapping table has been updated, and the corresponding entry in the SLC cache mapping table has been cleared, the firmware immediately performs an "invalidation" operation on the original SLC physical page. This operation is not a physical erase (because NAND erases on a block-by-block basis), but rather a logical marking at the software level. Specifically, the firmware locates the SLC-specific physical block to which the previously recorded SLC physical page address (PPA_slc) belongs. Each SLC block maintains a page-level valid bitmap or a valid page counter in SRAM. The firmware sets the bit in the corresponding bitmap of the PPA_slc from "1" (valid) to "0" (invalid), or decrements the valid page count of its block by 1. This operation is usually performed under atomic context or lightweight lock protection to ensure state consistency during multi-task concurrency. After marking, the physical page is considered "logically invalid," no longer participating in any read path hits, and is no longer considered a valid data source.

[0070] In other words, it can achieve real-time logical isolation of the physical location of moved data, prevent subsequent read requests from mistakenly reading old copies, and ensure data consistency; it avoids the performance overhead caused by immediate erasure, conforms to the NAND "fast write, slow erase" characteristic, and improves system response efficiency.

[0071] Update the management metadata of the SLC cache to reflect the invalid status of the physical page; Specifically, after marking a single page as invalid, the firmware synchronously updates the multi-level management metadata structure of the SLC cache. First, at the block level, if the valid page count of an SLC block drops to zero due to this invalidation operation, the block's status changes from "partially valid" to "fully invalid," and it is added to the "erasable block queue." Second, at the region level, the overall "invalid page ratio" or "free space level" of the SLC cache is refreshed in real time for use by the upper-level scheduler. Furthermore, if the system uses log-structured writing to manage the SLC cache, the block's "write pointer" or "close flag" also needs to be updated to indicate that the block can no longer be written sequentially. All these metadata changes are recorded in the SLC Cache Control Block in SRAM, and their integrity may be ensured through checksum or version tag mechanisms. Critical metadata changes may also be asynchronously written to power-loss protected non-volatile storage areas (such as SRAM with capacitor or dedicated NAND journal) to support state recovery after unexpected power outages.

[0072] In other words, fine-grained metadata updates enable the system to accurately grasp the space health status of the SLC cache, providing a data foundation for intelligent scheduling; block-level state management supports efficient batch reclamation strategies, avoiding frequent small-granular operations; and the power-loss safety mechanism ensures that even if power is lost during reclamation, invalid pages and reusable blocks can be correctly identified after restarting, preventing data corruption or space leakage and improving system reliability.

[0073] When the number of invalid pages accumulated in the SLC cache reaches a set value, a background garbage collection or direct reuse mechanism is triggered to reinstate the physical page into the available free page pool for subsequent host write allocation.

[0074] Specifically, the firmware continuously monitors the accumulation of invalid pages in the SLC cache and can trigger different strategies through two thresholds: Low watermark threshold (e.g., invalid page percentage > 30%): Triggers a lightweight "direct reuse" mechanism. If there are open SLC blocks that have not yet been closed and still have free pages, new writes are preferentially allocated to these blocks without needing to be reclaimed; if all open blocks are full, but there are completely invalid blocks, these completely invalid blocks are directly erased. After successful erasure, they are immediately added to the SLC free block pool, and all pages within them automatically become available free pages.

[0075] High watermark thresholds (e.g., SLC cache utilization > 90%) or system idle events trigger a full "Background GC". The GC task traverses the SLC block list, selecting the valid blocks with the fewest valid pages (or the most invalid pages) as the reclaim source. It reads the valid page data (located via the SLC cache mapping table), moves it to a newly opened SLC block (or writes it directly to the QLC, depending on the strategy), and then completely erases the original block. Blocks that are successfully erased are added to the free pool, and all their pages (including the original invalid pages and the gaps left after the valid pages were moved) become available resources. The entire process is executed in a low-priority background thread, utilizing multi-channel parallel erasure and write acceleration, and is regulated by the I / O scheduler to avoid interfering with foreground performance.

[0076] Regardless of the mechanism used, once a physical block is erased and added to the free pool, all physical pages within it are considered "available free pages". When the host initiates a new write request, the SLC page allocator will allocate the next physical page address from these free blocks using a sequential or round-robin strategy, completing the closed-loop reuse of resources.

[0077] In other words, the dynamic threshold triggering mechanism enables on-demand resource reclamation, maximizing space utilization while ensuring performance; direct reuse of fully invalid blocks avoids data migration overhead, achieving "zero-cost" space reclamation and reducing write amplification of the SLC cache; the background GC mechanism processes some valid blocks to prevent "fragmentation" from causing exhaustion of available space and maintain long-term write stability; the unified management of the free page pool ensures extremely low latency for new write allocation, ensuring that the SLC cache can always respond to host writes at near-native SLC speeds and maintain a high-performance experience.

[0078] The above-described solid-state drive (SSD) mapping management method isolates the temporary mapping of data during the SLC caching stage from the main mapping table by setting up an independent SLC cache mapping table. The main mapping table is only updated once after the data has been moved to multiple programming data blocks and all multiple programming operations have been completed. This reduces the two mapping updates in the traditional solution to one, lowering the frequency and amount of data brushed to NAND under the mapping table. This not only effectively improves the SSD's write performance but also reduces write amplification and NAND wear, extends the SSD's lifespan, and enhances data reliability under abnormal scenarios such as power outages.

[0079] Figure 3 This is a schematic block diagram of a solid-state drive mapping management device 300 provided in an embodiment of the present invention. Figure 3As shown, corresponding to the above-described solid-state drive (SSD) mapping management method, the present invention also provides an SSD mapping management device 300. This SSD mapping management device 300 includes a unit for executing the above-described SSD mapping management method, and the device can be configured in a server. Specifically, please refer to... Figure 3 The solid-state drive's mapping management device 300, applied to storage particles requiring multiple programming operations, includes: Establish a record unit 301, which is used to establish an SLC cache mapping table independent of the main mapping table, and is used to record the mapping relationship between the logical page address and the physical page address of the data in the SLC cache area; The receiving storage unit 302 is used to receive host write requests, store the data written by the host in the SLC cache area, and record the mapping relationship between the logical page address and the physical page address corresponding to the data in the SLC cache mapping table. The transfer unit 303 is used to transfer the data in the SLC buffer to the multiple programming data block when the SLC buffer meets the transfer conditions, and to complete all programming steps of the data in the multiple programming data block. The update unit 304 is used to delete the mapping relationship corresponding to the data from the SLC cache mapping table and update the mapping relationship to the main mapping table after confirming that the data has completed all programming steps in multiple programming data blocks.

[0080] In one embodiment, the record establishment unit 301 includes: The allocation module is used to allocate a memory region from volatile memory during the power-on initialization phase as the storage space for the SLC cache mapping table. The determination module is used to determine the number of entries required for the SLC cache mapping table based on the SLC cache capacity configured in the system, and to initialize all entries to an invalid state; The configuration module is used to configure the data structure of the mapping table, enabling it to quickly look up or write the corresponding physical page address using the logical page address as an index.

[0081] In one embodiment, the receiving storage unit 302 includes: The receive and parsing module is used to receive write commands from the host and parse the logical page address range and the data content to be written contained therein. The allocation module is used to allocate a free physical page from the SLC cache and write host data to that physical page; The matching module is used to obtain the physical page address of the allocated physical page and match it with the logical page address in the host write request; The write module is used to write the mapping pair of logical page address and physical page address into the corresponding position in the SLC cache mapping table, thus completing the temporary record of the mapping relationship.

[0082] In one embodiment, the transferring unit 303 includes: The judgment module is used to continuously monitor the usage status of the SLC cache area and determine whether the relocation conditions are met. The trigger read module is used to trigger a data migration task and read the valid data pages to be migrated from the SLC buffer when the migration conditions are met. The select write module is used to select an idle multi-programmed data block and write the read data to the first programming position of the multi-programmed data block; The execution module is used to perform a second programming operation on the same physical block when new data is subsequently written to the adjacent logical page address or when the conditions for secondary programming are met, so that the data can reach a stable storage state in the NAND flash memory. The confirmation module is used to confirm that the data has completed all the necessary programming steps in multiple programming data blocks and to obtain its final physical page address.

[0083] In one embodiment, the update unit 304 includes: The acquisition module is used to obtain the final physical page address of the data in the multiple programming data blocks after all programming is completed; The clearing module is used to locate and clear the corresponding mapping entry in the SLC cache mapping table based on the logical page address of the data, and release the table entry; The write module is used to write the mapping relationship between the logical page address and the final physical page address into the main mapping table.

[0084] In one embodiment, the device further includes: Release the reclamation unit to release and reclaim the physical storage resources of the SLC cache.

[0085] In one embodiment, the release and recovery unit includes: The marking module is used to mark physical pages in the SLC cache that were originally used to store the data as invalid pages; The update module is used to update the management metadata of the SLC cache, reflecting the invalid status of the physical page; The recycling module is used to trigger background garbage collection or direct reuse mechanisms when the accumulated invalid pages in the SLC cache reach a set value, so that the physical page is reintegrated into the available free page pool for subsequent host write allocation.

[0086] It should be noted that those skilled in the art can clearly understand that the specific implementation process of the above-mentioned solid-state drive mapping management device 300 and each unit can be referred to the corresponding description in the foregoing method embodiments. For the sake of convenience and brevity, it will not be repeated here.

[0087] The aforementioned solid-state drive mapping management device 300 can be implemented as a computer program, which can, for example... Figure 4 It runs on the computer device shown.

[0088] Please see Figure 4 , Figure 4 This is a schematic block diagram of a computer device provided in an embodiment of this application. The computer device 500 can be a server, wherein the server can be a standalone server or a server cluster composed of multiple servers.

[0089] See Figure 4 The computer device 500 includes a processor 502, a memory, and a network interface 505 connected via a system bus 501. The memory may include a non-volatile storage medium 503 and internal memory 504.

[0090] The non-volatile storage medium 503 may store an operating system 5031 and a computer program 5032. The computer program 5032 includes program instructions that, when executed, cause the processor 502 to perform a solid-state drive mapping management method.

[0091] The processor 502 provides computing and control capabilities to support the operation of the entire computer device 500.

[0092] The internal memory 504 provides an environment for the execution of the computer program 5032 in the non-volatile storage medium 503. When the computer program 5032 is executed by the processor 502, the processor 502 can execute a solid-state drive mapping management method.

[0093] This network interface 505 is used for network communication with other devices. Those skilled in the art will understand that... Figure 4 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device 500 to which the present application is applied. The specific computer device 500 may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0094] The processor 502 is used to run a computer program 5032 stored in the memory to perform the following steps: Establish an SLC cache mapping table independent of the main mapping table to record the mapping relationship between logical page addresses and physical page addresses of data in the SLC cache area; receive host write requests, store the data written by the host in the SLC cache area, and record the mapping relationship between the logical page address and physical page address corresponding to the data in the SLC cache mapping table; when the SLC cache area meets the relocation conditions, move the data in the SLC cache area to the multi-programming data block, and complete all programming steps for the data in the multi-programming data block; after confirming that the data has completed all programming steps in the multi-programming data block, delete the mapping relationship corresponding to the data from the SLC cache mapping table, and update the mapping relationship to the main mapping table.

[0095] It should be understood that in the embodiments of this application, the processor 502 may be a central processing unit (CPU), or it may be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor.

[0096] It will be understood by those skilled in the art that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program includes program instructions and can be stored in a storage medium, which is a computer-readable storage medium. The program instructions are executed by at least one processor in the computer system to implement the process steps of the embodiments of the above methods.

[0097] Therefore, the present invention also provides a storage medium. This storage medium can be a computer-readable storage medium. The storage medium stores a computer program, wherein when executed by a processor, the computer program causes the processor to perform the following steps: Establish an SLC cache mapping table independent of the main mapping table to record the mapping relationship between logical page addresses and physical page addresses of data in the SLC cache area; receive host write requests, store the data written by the host in the SLC cache area, and record the mapping relationship between the logical page address and physical page address corresponding to the data in the SLC cache mapping table; when the SLC cache area meets the relocation conditions, move the data in the SLC cache area to the multi-programming data block, and complete all programming steps for the data in the multi-programming data block; after confirming that the data has completed all programming steps in the multi-programming data block, delete the mapping relationship corresponding to the data from the SLC cache mapping table, and update the mapping relationship to the main mapping table.

[0098] The storage medium can be any computer-readable storage medium capable of storing program code, such as a USB flash drive, portable hard drive, read-only memory (ROM), magnetic disk, or optical disk.

[0099] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0100] In the several embodiments provided by this invention, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For example, the division of each unit is merely a logical functional division, and there may be other division methods in actual implementation. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed.

[0101] The steps in the method of this invention can be adjusted, merged, or reduced in order according to actual needs. The units in the device of this invention can be merged, divided, or reduced according to actual needs. Furthermore, the functional units in the various embodiments of this invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0102] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, a terminal, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention.

[0103] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and these modifications or substitutions should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for managing mapping of a solid state drive, applied to a storage grain requiring multiple programming, characterized in that, include: Establish an SLC cache mapping table independent of the main mapping table to record the mapping relationship between logical page addresses and physical page addresses of data in the SLC cache area; Receive host write requests, store the data written by the host in the SLC cache, and record the mapping relationship between the logical page address and the physical page address corresponding to the data in the SLC cache mapping table; When the SLC buffer meets the relocation conditions, the data in the SLC buffer is moved to the multi-programming data block, and all programming steps for the data in the multi-programming data block are completed. After confirming that the data has completed all programming steps in multiple programming data blocks, the mapping relationship corresponding to the data is deleted from the SLC cache mapping table, and the mapping relationship is updated to the main mapping table.

2. The mapping management method of a solid state drive according to claim 1, wherein, The establishment of an SLC cache mapping table independent of the main mapping table, used to record the mapping relationship between logical page addresses and physical page addresses of data in the SLC cache, includes: During the power-on initialization phase, a memory region is allocated from volatile memory as the storage space for the SLC cache mapping table; Based on the SLC cache capacity configured in the system, determine the number of entries required for the SLC cache mapping table, and initialize all entries to an invalid state; Configure the data structure of the mapping table to support fast lookup or writing of the corresponding physical page address using the logical page address as an index.

3. The mapping management method of a solid state drive according to claim 1, wherein, The process of receiving a host write request involves storing the data written by the host in the SLC cache and recording the mapping relationship between the logical page address and the physical page address corresponding to the data in the SLC cache mapping table, including: Receive write commands from the host, and parse the logical page address range and the data to be written contained therein; Allocate a free physical page from the SLC cache and write the host data to that physical page; Obtain the physical page address of the allocated physical page and match it with the logical page address in the host write request; Write the mapping pair of logical page address and physical page address into the corresponding position in the SLC cache mapping table to complete the temporary record of the mapping relationship.

4. The mapping management method of a solid state drive according to claim 1, wherein, When the SLC buffer meets the relocation conditions, the data in the SLC buffer is moved to the multi-programming data block, and all programming steps for the data in the multi-programming data block are completed, including: Continuously monitor the usage status of the SLC cache to determine whether the relocation conditions are met; When the migration conditions are met, the data migration task is triggered, and the valid data pages to be migrated in the SLC buffer are read. Select an idle multi-programming data block and write the read data to the first programming position of that multi-programming data block; When new data is written to an adjacent logical page address or the conditions for secondary programming are met, a second programming operation is performed on the same physical block to make the data reach a stable storage state in the NAND flash memory. Confirm that the data has completed all the necessary programming steps in multiple programming data blocks and obtain its final physical page address.

5. The mapping management method of a solid state drive according to claim 1, wherein, After confirming that the data has completed all programming steps in multiple programming data blocks, the mapping relationship corresponding to the data is deleted from the SLC cache mapping table, and the mapping relationship is updated to the main mapping table, including: After the data has been fully programmed, obtain its final physical page address in the multiple programmed data blocks; Based on the logical page address of the data, locate and clear the corresponding mapping entry in the SLC cache mapping table, and release the table entry; Write the mapping relationship between the logical page address and the final physical page address into the main mapping table.

6. The mapping management method of a solid state drive according to claim 1, wherein, After confirming that the data has completed all programming steps in multiple programming data blocks, the step of deleting the mapping relationship corresponding to the data from the SLC cache mapping table and updating the mapping relationship to the main mapping table includes: Release and reclaim the physical storage resources of the SLC cache.

7. The mapping management method of a solid state drive according to claim 6, wherein, The process of releasing and reclaiming the physical storage resources of the SLC cache includes: Mark the physical pages in the SLC cache that were originally used to store this data as invalid pages; Update the management metadata of the SLC cache to reflect the invalid status of the physical page; When the number of invalid pages accumulated in the SLC cache reaches a set value, a background garbage collection or direct reuse mechanism is triggered to reinstate the physical page into the available free page pool for subsequent host write allocation.

8. A mapping management device for solid-state drives, applied to storage particles that require multiple programming operations, characterized in that, include: Establish a record unit to create an SLC cache mapping table independent of the main mapping table, which is used to record the mapping relationship between the logical page address and the physical page address of the data in the SLC cache area; The receiving storage unit is used to receive host write requests, store the data written by the host in the SLC cache area, and record the mapping relationship between the logical page address and the physical page address corresponding to the data in the SLC cache mapping table. The transfer unit is used to transfer the data in the SLC buffer to the multi-programming data block when the SLC buffer meets the transfer conditions, and to complete all programming steps of the data in the multi-programming data block. The update unit is used to delete the mapping relationship corresponding to the data from the SLC cache mapping table and update the mapping relationship to the main mapping table after confirming that the data has completed all programming steps in multiple programming data blocks.

9. A computer device, characterized in that, The computer device includes a memory and a processor, the memory storing a computer program, and the processor executing the computer program to implement the method as described in any one of claims 1 to 7.

10. A storage medium, characterized in that, The storage medium stores a computer program that, when executed by a processor, implements the method as described in any one of claims 1 to 7.

Images