Method for precise deposition of semiconductor chip circuit layer

Abstract

This invention proposes a method for precise deposition and fabrication of circuit layers in semiconductor chips, comprising S1. Pretreatment: stepwise wet cleaning of the substrate using a cleaning solution, cleaning of the target material using an isopropanol solution, and nitrogen drying after cleaning. The method for precise deposition and fabrication of circuit layers in semiconductor chips of this invention removes impurities such as organic matter, natural oxide layers, metal ions, and solid particles adhering to the substrate surface through stepwise wet cleaning with organic solvents, dilute acid solutions, alkaline solutions, and ultrapure water, avoiding chip quality problems caused by residual impurities. Simultaneously, the bonding properties of titanium metal buffer the difference in physical properties between the substrate and the aluminum circuit layer, improving interlayer interface compatibility and film adhesion. Annealing treatment effectively eliminates internal thermal stress and lattice defects generated during the double-layer film deposition process, optimizes the film microstructure, and ensures the service life of the circuit layer.

Description

Technical Field

[0001] This invention relates to the field of semiconductor chip technology, and in particular to a method for the precise deposition and fabrication of circuit layers in semiconductor chips. Background Technology

[0002] The circuit layer of a semiconductor chip is the core structure that enables signal transmission and power conduction, and it directly determines the electrical performance of the semiconductor chip. In semiconductor chip manufacturing, vacuum evaporation deposition is one of the mainstream processes for preparing metal circuit layers. It has advantages such as fast deposition rate, good film continuity, and wide process adaptability, and is widely used in the preparation and processing of metal conductive layers and bonding transition layers.

[0003] Existing vacuum evaporation deposition methods primarily involve directly heating a metal target within a vacuum chamber using an electric current. This heat melts and vaporizes the target, generating free metal atoms. These atoms then diffuse freely in the vacuum environment and adsorb onto the semiconductor chip substrate surface. After natural cooling and condensation, a thin metal circuit film layer is directly formed. However, directly depositing an aluminum conductive layer on the substrate surface presents challenges. Due to differences in lattice structure and other physical properties between the semiconductor substrate and the aluminum conductive layer, the interfacial compatibility and bonding stability between them are poor. Insufficient interlayer adhesion after deposition leads to problems such as circuit layer warping, delamination, and peeling during subsequent processing and use, ultimately reducing the quality of the semiconductor chip. Summary of the Invention

[0004] The present invention aims to at least partially solve one of the technical problems in the above-mentioned technologies.

[0005] Therefore, one objective of this invention is to provide a method for the precise deposition and fabrication of circuit layers in semiconductor chips, which can improve interlayer interface compatibility and film adhesion, and eliminate internal thermal stress and lattice defects generated during the deposition of double-layer films through annealing treatment, thereby improving adhesion and ensuring the conductivity stability and long-term reliability of the semiconductor chip circuit layers.

[0006] To achieve the above objectives, the first aspect of this invention proposes a method for precise deposition and fabrication of circuit layers in semiconductor chips. The method includes: S1. Pretreatment: performing stepwise wet cleaning of the substrate using a cleaning solution, cleaning of the target material using an isopropanol solution, and drying by nitrogen blowing after cleaning; S2. Deposition: fixing the dried substrate on a substrate support in a vacuum evaporation chamber, loading the target material into a tungsten heating boat, using a mechanical pump to evacuate the vacuum evaporation chamber, preheating the substrate after vacuuming, and applying a working current using a gradient voltage increase method to heat the target material, which is then transported to the substrate surface to deposit and form an adhesive layer, and further depositing a circuit layer on the surface of the adhesive layer; S3. Annealing: transferring the substrate after deposition to a vacuum thermal annealing furnace for annealing to complete the deposition and fabrication of the chip circuit layer.

[0007] In addition, the method for precise deposition and fabrication of circuit layers in semiconductor chips proposed above according to the present invention may also have the following additional technical features:

[0008] Specifically, the steps of the stepwise wet cleaning described in step S1 are as follows: using an organic solvent cleaning solution to remove organic matter and photoresist residue from the substrate surface; using a dilute acid cleaning solution to remove the natural oxide layer and heavy metal ion impurities from the substrate surface; using an alkaline cleaning solution to remove alkali metal ion contaminants from the substrate surface; and using deionized water to rinse the substrate multiple times.

[0009] Specifically, the target material includes a titanium evaporation target and an aluminum evaporation target, wherein the titanium evaporation target is used to form a titanium metal bonding transition layer by heating and evaporation; and the aluminum evaporation target is used to evaporate and deposit a metallic aluminum conductive circuit layer on the surface of the titanium bonding transition layer.

[0010] Specifically, the deposition process described in S2 involves the following steps: The dried substrate is placed on a substrate support within the vacuum evaporation chamber, with the substrate's deposition surface facing downwards towards the evaporation source. The pre-treated titanium and aluminum evaporation targets are then loaded into separate tungsten heating boats. The vacuum chamber door is closed, and the mechanical pump and chamber baking system are activated to evacuate and heat the vacuum evaporation chamber, thus completing the degassing process. After degassing, the substrate support is heated to 100-200°C to remove residual adsorbed gases from the substrate surface. Current is applied to the heating boat corresponding to the titanium evaporation target, heating it until evaporation begins. The evaporated titanium atoms are then deposited onto the substrate surface. After the binder layer is deposited, current is applied to the heating boat corresponding to the aluminum evaporation target, heating it until evaporation begins. The evaporated aluminum atoms are then deposited onto the binder layer.

[0011] Specifically, the method of applying working current using a gradient voltage increase includes: heating the titanium evaporation target to a temperature lower than the evaporation temperature of titanium, maintaining this temperature for 5-10 minutes, and then continuing to increase the current until the titanium begins to evaporate; heating the aluminum evaporation target to a temperature lower than the evaporation temperature of aluminum, maintaining this temperature for 5-10 minutes, and then continuing to increase the current until the aluminum begins to evaporate.

[0012] Specifically, during the target material heating and pre-evaporation stage, the substrate is shielded by an internal baffle plate within the cavity.

[0013] Specifically, the specific steps of the annealing process in S3 are as follows: the substrate is naturally cooled to below 45°C, and then nitrogen is introduced into the vacuum evaporation chamber until the pressure is restored to atmospheric pressure. The cooled substrate is then removed and placed in a hot annealing furnace. The temperature in the hot annealing furnace is maintained at 410-460°C for annealing.

[0014] Specifically, the thickness of the titanium bonding layer is 8-14 nm.

[0015] Specifically, the aluminum conductive circuit layer has a deposition thickness of 310nm-700nm.

[0016] Specifically, the distance between the evaporation source and the substrate is 35-45 cm.

[0017] Compared with the prior art, the present invention has the following beneficial effects: The method for precise deposition and preparation of circuit layers for semiconductor chips of the present invention removes impurities such as organic matter, natural oxide layer, metal ions and solid particles attached to the substrate surface through stepwise wet cleaning with organic solvents, dilute acid solutions, alkaline solutions and ultrapure water, avoiding chip quality problems caused by residual impurities. At the same time, the bonding properties of titanium metal are used to buffer the difference in physical properties between the substrate and the aluminum circuit layer, improve the interlayer interface compatibility and film adhesion, and the annealing treatment can effectively eliminate the internal thermal stress and lattice defects generated during the deposition of double film layers, optimize the microstructure of the film layer and ensure the service life of the circuit layer.

[0018] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0019] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein:

[0020] Figure 1 This is a schematic flowchart of a method for precise deposition and fabrication of circuit layers in a semiconductor chip according to an embodiment of the present invention. Detailed Implementation

[0021] Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention.

[0022] The method for precise deposition and fabrication of circuit layers in semiconductor chips according to embodiments of the present invention is described below with reference to the accompanying drawings.

[0023] As mentioned above, due to the differences in physical properties such as the lattice arrangement structure between the semiconductor substrate and the aluminum conductive layer, the interfacial compatibility and bonding stability between the semiconductor substrate and the aluminum conductive layer are poor. After molding, the interlayer adhesion is insufficient, which can easily lead to problems such as circuit layer warping, delamination, and peeling.

[0024] Figure 1 The illustration schematically shows a process flow diagram of a method for precise deposition and fabrication of circuit layers in a semiconductor chip according to an embodiment of the present invention. Figure 1 As shown, this embodiment of the invention provides a method for precise deposition of circuit layers in semiconductor chips. The method includes: S1. Pretreatment: The substrate is wet-cleaned stepwise with a cleaning solution, and the target is cleaned with an isopropanol solution. After cleaning, the target is dried by nitrogen blowing; S2. Deposition: The dried substrate is fixed on a substrate support in a vacuum evaporation chamber, the target is placed in a tungsten heating boat, and a vacuum is evacuated using a mechanical pump. After vacuuming, the substrate is preheated, and a working current is applied using a gradient voltage increase method to heat the target. The target is then transported to the substrate surface to deposit a bonding layer, and a circuit layer is further deposited on the bonding layer surface; S3. Annealing: The substrate after deposition is transferred to a vacuum thermal annealing furnace for annealing to complete the deposition of the chip circuit layer.

[0025] For example, after the vacuum evaporation chamber is evacuated to a background vacuum level controlled within the range of 1×10⁻³-5×10⁻³ Pa, the substrate preheating is started. The substrate preheating temperature is kept constant at 125-140℃ to eliminate residual moisture inside the substrate. At the same time, gradient pressure is used to increase the heating current in three stages to avoid problems such as target material melting and splashing.

[0026] The specific steps of the stepwise wet cleaning in step S1 of the preferred embodiment of the present invention are as follows: using an organic solvent cleaning solution to remove organic matter and photoresist residue from the substrate surface; using a dilute acid cleaning solution to remove the natural oxide layer and heavy metal ion impurities from the substrate surface; using an alkaline cleaning solution to remove alkali metal ion contaminants from the substrate surface; and using deionized water to rinse the substrate multiple times.

[0027] To illustrate, by cleaning in sequence according to the types of contaminants—organic pollutants, inorganic oxide layers, and metal ion impurities—neutralization reactions between different cleaning agents can be avoided to prevent the formation of precipitates and secondary contaminants from adhering to the substrate surface. At the same time, each cleaning is performed by rinsing with deionized water to remove residual chemicals from the substrate surface, preventing cracking of the circuit layer film caused by impurities and chemical residues on the substrate surface, and improving the bonding effect between the film and the substrate during subsequent vacuum evaporation deposition.

[0028] Following the above example, the organic solvent cleaning solution is a mixture of acetone and anhydrous ethanol, the dilute acid cleaning solution is a low-concentration diluted hydrofluoric acid solution, and the alkaline cleaning solution is a mixture of ammonia and hydrogen peroxide. This can achieve graded removal of contaminants, avoid secondary pollution caused by mixing solutions, and improve the quality of substrate pretreatment.

[0029] In a preferred embodiment of the present invention, the target material includes a titanium evaporation target and an aluminum evaporation target, wherein the titanium evaporation target is used to form a titanium metal bonding transition layer by heating and evaporation; and the aluminum evaporation target is used to evaporate and deposit a metallic aluminum conductive circuit layer on the surface of the titanium bonding transition layer.

[0030] As an example, titanium can be used as a buffer transition layer to eliminate interfacial stress, improve the adhesion between the metal circuit layer and the substrate, avoid problems such as poor film adhesion and interfacial delamination, and thus improve the service life of the chip circuit layer.

[0031] The specific steps of the deposition operation in S2 of the preferred embodiment of the present invention are as follows: The dried substrate is placed on a substrate support in a vacuum evaporation chamber, with the substrate's deposition surface facing downwards towards the evaporation source. The pretreated titanium and aluminum evaporation targets are then loaded into separate tungsten heating boats. The vacuum chamber door is then closed, and the mechanical pump and chamber baking system are started to evacuate and heat the vacuum evaporation chamber, thereby completing the degassing process. After degassing, the substrate support is heated to 100-200°C to remove residual adsorbed gas from the substrate surface. Current is applied to the heating boat corresponding to the titanium evaporation target, heating it until evaporation begins. The evaporated titanium atoms are then deposited onto the substrate surface. After the binder layer is deposited, current is applied to the heating boat corresponding to the aluminum evaporation target, heating it until evaporation begins. The evaporated aluminum atoms are then deposited onto the binder layer.

[0032] As illustrated by the example, by isolating the titanium and aluminum targets from each other, the heating current and evaporation state of the two types of metal targets can be individually controlled, ensuring a clear distinction between the interface of the adhesive layer and the conductive circuit layer. Simultaneously, the inverted mounting structure with the substrate facing downwards reduces issues such as pinholes and protrusions in the thin film. Furthermore, by venting residual moisture and air from the cavity, oxidation of the evaporated metal atoms is prevented, improving the adhesion and ensuring the overall flatness and consistency of the deposited circuit layer.

[0033] The preferred embodiment of the present invention uses a gradient voltage increase method to apply the working current, which includes: heating the titanium evaporation target to a temperature lower than the evaporation temperature of titanium, maintaining it for 5-10 minutes, and then continuing to increase the current until the titanium begins to evaporate; heating the aluminum evaporation target to a temperature lower than the evaporation temperature of aluminum, maintaining it for 5-10 minutes, and then continuing to increase the current until the aluminum begins to evaporate.

[0034] To illustrate, unlike the conventional method of directly applying the rated evaporation current, the step-by-step heating method, which involves first preheating at a low temperature and then evaporating at a second current, allows the target material to be heated evenly. This reduces the problem of thermal stress concentration caused by the instantaneous impact of high current, and avoids phenomena such as cracking of the target material, local overheating and splashing of particles. At the same time, by using constant temperature insulation, gaseous impurities adsorbed inside the target material can be discharged, reducing metal vapor oxidation inclusions, and further improving the fabrication quality and reliability of the semiconductor chip circuit layer.

[0035] In a preferred embodiment of the present invention, during the target material heating and pre-evaporation stage, the substrate is shielded by an internal baffle plate.

[0036] For example, during the preheating and initial pre-evaporation process of the target material, the substrate is shielded by an internal baffle to isolate the unstable and impure initial evaporation material, preventing the evaporation material from adhering to the substrate surface. After the purity of the metal vapor meets the deposition requirements, the baffle is removed to carry out the thin film deposition operation, ensuring the uniformity of the film formation and the cleanliness of the interface between the circuit layer and the adhesive layer, and improving the deposition accuracy.

[0037] The specific steps of the annealing process in S3 of the preferred embodiment of the present invention are as follows: the substrate is naturally cooled to below 45°C, and then nitrogen is introduced into the vacuum evaporation chamber until the pressure is restored to atmospheric pressure. The cooled substrate is then taken out and placed in a hot annealing furnace. The temperature in the hot annealing furnace is maintained at 410-460°C for annealing.

[0038] For example, after deposition, the substrate is first allowed to cool naturally at a low temperature to prevent the high-temperature substrate from directly contacting the outside air and causing rapid oxidation of the metal film. At the same time, high-purity nitrogen is used to restore the chamber pressure, isolating the oxygen and water vapor in the air and preventing the formation of oxidation impurities on the surface of the titanium bonding layer and aluminum circuit layer, thus ensuring the cleanliness of the film surface. Furthermore, the medium-temperature annealing range of 410-460℃ will not cause the aluminum circuit layer to overheat and soften, eliminating residual interfacial stress and internal lattice defects from the thin film deposition process, optimizing the metal grain arrangement structure, reducing the overall resistivity of the circuit layer, further improving adhesion, and ensuring the conductivity stability and long-term reliability of the semiconductor chip circuit layer.

[0039] In a preferred embodiment of the present invention, the thickness of the titanium bonding layer is 8-14 nm.

[0040] For example, when the thickness of the titanium bonding layer is less than 8nm, the film continuity is insufficient, and local film voids and coverage defects are prone to occur, which interfere with the lattice difference between the substrate and the upper aluminum circuit layer. When the thickness of the titanium bonding layer is greater than 14nm, the high impedance titanium metal layer will increase the contact resistance of the circuit and easily cause thin film warping deformation.

[0041] In a preferred embodiment of the present invention, the aluminum conductive circuit layer deposition thickness is 310nm-700nm.

[0042] As an example, by controlling the deposition thickness of the aluminum conductive circuit layer, the conductivity of the aluminum circuit layer can be ensured, thereby meeting the conduction requirements of the semiconductor chip circuit. If the thickness of the aluminum conductive circuit layer is less than 310nm, the conduction cross-sectional area of ​​the conductive line is insufficient, which will cause chip signal transmission delay and increased power consumption. If the thickness is greater than 700nm, the accumulated stress inside the metal film layer will increase, which will easily cause problems such as film wrinkling and peeling, and will increase the deposition time and raw material loss, affecting subsequent photolithography and etching processes.

[0043] In a preferred embodiment of the present invention, the distance between the evaporation source and the substrate is 35-45 cm.

[0044] This example illustrates how controlling the distance between the evaporation source and the substrate allows metal vapor to uniformly cover the substrate while reducing the interference of thermal radiation from the evaporation source on the substrate temperature. If the distance between the evaporation source and the substrate is less than 35 cm, the metal vapor diffusion angle is limited, which can easily lead to excessive differences in film thickness between the center and the edge of the substrate. At the same time, the large amount of thermal radiation generated by the evaporation source will directly act on the substrate, exacerbating the internal thermal stress of the film. If the distance is greater than 45 cm, the metal vapor transport loss increases, the deposition rate decreases, the preparation time is lengthened, and the film density is reduced.

[0045] In summary, the method for precise deposition of circuit layers in semiconductor chips of the present invention removes impurities such as organic matter, natural oxide layers, metal ions, and solid particles adhering to the substrate surface through stepwise wet cleaning with organic solvents, dilute acid solutions, alkaline solutions, and ultrapure water, thus avoiding chip quality problems caused by residual impurities. At the same time, the bonding properties of titanium metal are used to buffer the difference in physical properties between the substrate and the aluminum circuit layer, improving the interlayer interface compatibility and film adhesion. Furthermore, annealing treatment can effectively eliminate internal thermal stress and lattice defects generated during the deposition of double-layer films, optimize the microstructure of the film layer, and ensure the service life of the circuit layer.

[0046] In the description of this specification, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0047] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0048] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A method for precise deposition and fabrication of circuit layers in semiconductor chips, characterized in that, The method includes: S1. Pretreatment: The substrate is wet-cleaned in steps using a cleaning solution, and the target is cleaned using an isopropanol solution. After cleaning, the target is dried by nitrogen blowing. S2. Deposition process: The dry substrate is fixed on the substrate support in the vacuum evaporation chamber, the target material is loaded into the tungsten heating boat, and the vacuum evaporation chamber is evacuated using a mechanical pump. After the vacuum is completed, the substrate is preheated and the working current is applied in a gradient voltage increase manner to heat the target material. Then it is transported to the substrate surface to deposit and form an adhesive layer. A circuit layer is further deposited on the surface of the adhesive layer. S3. Annealing process: After the deposition process is completed, the substrate is transferred to a vacuum thermal annealing furnace for annealing to complete the chip circuit layer deposition and preparation.

2. The method for precise deposition and fabrication of circuit layers in semiconductor chips according to claim 1, characterized in that, The specific steps of the step-by-step wet cleaning described in step S1 are as follows: Organic solvent cleaning solution is used to remove organic matter and photoresist residue from the substrate surface; Dilute acid cleaning solution is used to remove the natural oxide layer and heavy metal ion impurities on the substrate surface; Alkaline cleaning solution is used to remove alkali metal ion contaminants from the substrate surface; The substrate was rinsed multiple times with deionized water.

3. The method for precise deposition and fabrication of circuit layers in semiconductor chips according to claim 1, characterized in that, The target material includes titanium evaporation target and aluminum evaporation target, wherein... The titanium evaporation target is used to form a titanium metal bonding transition layer by heating and evaporation. The aluminum evaporation target is used to evaporate and deposit a metallic aluminum conductive line layer on the surface of the titanium bonding transition layer.

4. The method for precise deposition and fabrication of circuit layers in semiconductor chips according to claim 3, characterized in that, The specific steps of the deposition operation described in S2 are as follows: The dried substrate is placed on the substrate support in the vacuum evaporation chamber with the substrate to be deposited facing down and directly facing the evaporation source below. Then, the pretreated titanium evaporation target and aluminum evaporation target are respectively loaded into independent tungsten heating boats. Then, the door of the vacuum chamber is closed, and the mechanical pump and chamber baking system are started to evacuate and heat the vacuum evaporation chamber to complete the degassing process. After degassing, the substrate support is heated to 100~200℃ to remove the adsorbed gas remaining on the substrate surface. Current is applied to the heating boat corresponding to the titanium evaporation target to heat it until evaporation begins. Then, the evaporated titanium atoms are deposited onto the surface of the substrate. After the binder layer is deposited, an electric current is applied to the heating boat corresponding to the aluminum evaporation target to heat it and start evaporation. Then, the evaporated aluminum atoms are deposited onto the binder layer.

5. The method for precise deposition and fabrication of circuit layers in semiconductor chips according to claim 4, characterized in that, The method of applying operating current using a gradient boost voltage method includes: Heat the titanium evaporation target to a temperature below the evaporation temperature of titanium and maintain it for 5-10 minutes. Then, continue to increase the current until the titanium begins to evaporate. Heat the aluminum evaporation target to a temperature below the evaporation temperature of aluminum and maintain this temperature for 5-10 minutes. Then, continue to increase the current until the aluminum begins to evaporate.

6. The method for precise deposition and fabrication of circuit layers in semiconductor chips according to claim 5, characterized in that, During the target material heating and pre-evaporation stage, the substrate is shielded by an internal baffle plate.

7. The method for precise deposition and fabrication of circuit layers in semiconductor chips according to claim 6, characterized in that, The specific steps of the annealing process described in S3 are as follows: The substrate is allowed to cool naturally to below 45°C. Then, nitrogen gas is introduced into the vacuum evaporation chamber until the pressure returns to atmospheric pressure. The cooled substrate is then removed and placed in a hot annealing furnace. The temperature in the hot annealing furnace is maintained at 410-460°C for annealing.

8. The method for precise deposition and fabrication of circuit layers in semiconductor chips according to claim 7, characterized in that, The thickness of the titanium bonding layer is 8-14 nm.

9. The method for precise deposition and fabrication of circuit layers in semiconductor chips according to claim 8, characterized in that, The thickness of the aluminum conductive circuit layer is 310nm-700nm.

10. The method for precise deposition and fabrication of circuit layers in semiconductor chips according to claim 9, characterized in that, The distance between the evaporation source and the substrate is 35-45 cm.

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