A gallium nitride device and method of manufacturing the same

Abstract

The application provides a gallium nitride device, which comprises a closed ring-shaped gate structure, a dielectric layer, a source field plate, at least a part of the source field plate being formed on one of inner and outer side walls of the dielectric layer, a residual field plate, the residual field plate being formed on the other of the inner and outer side walls of the dielectric layer, the residual field plate being left on the dielectric layer after an etching process for forming the source field plate, and a gap between the source field plate and the residual field plate, so that there is no physical contact and no electrical connection between the source field plate and the residual field plate. The gap is naturally formed between the residual field plate and the source field plate, and there is no physical contact and no electrical connection, so that the contribution of the residual field plate to the gate-source capacitance Cgs is eliminated, the switching loss of the device is significantly reduced, and the switching frequency is improved.

Description

Technical Field

[0001] This application relates to the semiconductor field, and more particularly to a gallium nitride device and a method for manufacturing the same. Background Technology

[0002] The description in this section provides only background information relevant to the disclosure of this application and does not constitute prior art.

[0003] With the rapid development of industry and the AI ​​sector, the requirements for power supply efficiency and power density are constantly increasing. The performance requirements for gallium nitride (GaN) devices are also becoming increasingly stringent, with a desire to continuously reduce the on-resistance, improve the FOM (Feature Factor) value, and simultaneously lower the cost.

[0004] The urgent need for increased power density in power systems has led to continuously increasing switching frequencies in gallium nitride (GaN) devices, resulting in a rise in switching losses. Therefore, reducing switching losses is a key issue for GaN devices. This is especially true for low-voltage GaN devices, where current applications have already exceeded MHz in switching frequency, making the reduction of switching losses crucial.

[0005] Gate-source capacitance (Cgs) is a key parameter in gallium nitride (GaN) devices, determining their switching frequency and drive losses. Lower Cgs results in higher switching frequencies and lower drive losses. GaN devices have a lateral device structure. To reduce the surface electric field and improve the device's breakdown voltage, one or more source field plates (SFP) are typically introduced to optimize the surface electric field. Specifically, the SFP wraps around the gate structure to optimize the electric field at the P-GaN corner. The overlap between the SFP structure, the gate metal, and the P-GaN structure introduces Cgs capacitance, such as... Figure 1 As shown.

[0006] As the switching frequency of gallium nitride (GaN) devices continues to increase, optimizing Cgs (current voltage) becomes crucial. To reduce Cgs, common industry practices include reducing the overlap area between the source field plate (SFP) and the gate structure, or increasing the thickness of the dielectric layer between them. Since the gate structure and source fingers are at the same potential when a GaN device is turned off, the portion of the source field plate SFP between the gate structure and the source fingers is removed to minimize overlap. (Refer to...) Figure 2A As shown, after the gate metal and P-GaN structure are etched, a full-layer dielectric is deposited. Following dielectric deposition, an SFP metal layer is deposited. To reduce Cgs capacitance, the SFP only partially covers the GM (typically covering half). (Refer to...) Figure 2B and Figure 3AAs shown, SFP photolithography will then be performed. After development, the area masked by the photoresist is the part that needs to be retained in the SFP process. (Refer to...) Figure 2C As shown, SFP etching is then performed, and the part of the SFP that is not covered by photoresist will be etched away. Then the photoresist is removed, thereby exposing the SFP metal that was originally covered by photoresist.

[0007] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0008] Through the inventor's ingenious discovery, due to the gradient between the gate metal GM and the P-GaN structure (i.e., the width of the P-GaN structure is greater than that of the gate metal GM), the dielectric layer and source field plate (SFP) deposition will be thicker at the sidewalls of the gate structure. While SFP etching processes (dry / wet etching) can cleanly etch the source field plate (SFP) in the flat areas, SFP residue (residual field plate) will remain at the sidewalls of the gate structure. In existing technologies, the residual field plate exists on all four sidewalls of the gate structure.

[0009] Reference Figure 4A and Figure 4B As shown, in the existing gallium nitride (GaN) layout, the gate structure is an interdigitated finger structure, with each finger independently distributed. In this layout, regardless of whether the source field plate (SFP) is shorter than the gate structure (see reference...), Figure 4A (as shown) or longer than the gate structure (refer to) Figure 4B As shown in the figure, as long as there is an overlap between the source field plate SFP and the gate structure, the residual SFP (residual field plate) will be electrically connected to the source field plate SFP, thus contributing Cgs.

[0010] Based on the aforementioned deficiencies in the prior art, the gallium nitride device and its manufacturing method disclosed in this application can effectively eliminate the parasitic capacitance caused by the residual field plate remaining on the gate sidewall and reduce Cgs.

[0011] To achieve the above objectives, this application provides the following technical solution: a gallium nitride device, comprising: A gate structure in the form of a closed ring; A dielectric layer having an inner sidewall covering the inside of the gate structure and an outer sidewall covering the outside of the gate structure, the inner sidewall of the dielectric layer defining an enclosed internal region and the outer sidewall of the dielectric layer defining an external region. A source field plate, at least a portion of which is formed on one of the inner and outer sidewalls of the dielectric layer; A residual field plate, which is formed on one of the inner and outer sidewalls of the dielectric layer, and is left on the dielectric layer after an etching process performed to form the source field plate; There is a gap between the source field plate and the residual field plate, so that there is no physical contact and no electrical connection between the source field plate and the residual field plate.

[0012] Preferably, the residual field plate has a closed ring structure, and the residual field plate continuously surrounds the corresponding inner or outer sidewall of the medium layer.

[0013] Preferably, it further includes source electrode fingers, which are disposed in different regions of the internal region and the external region, respectively, along with the source electrode field plate.

[0014] Preferably, the dielectric layer further includes a top wall covering the gate structure, the top wall connecting the inner sidewall and the outer sidewall; one end of the source field plate facing the source finger terminates horizontally directly above the top wall of the gate structure.

[0015] Preferably, it further includes source fingers and drain fingers: The source electrode fingers are disposed in the outer region, and the drain electrode fingers are disposed in the inner region; At least a portion of the source field plate is disposed in the internal region, and the source field plate is in the form of a closed ring. The residual field plate is formed on the outer side wall; The gate structure and the dielectric layer together act as a physical barrier, causing the residual field plate to be in an electrically floating state.

[0016] Preferably, it further includes source fingers and drain fingers: The source electrode fingers are disposed in the inner region, and the drain electrode fingers are disposed in the outer region; At least a portion of the source field plate is disposed in the external region; The residual field plate is formed on the inner sidewall; The gallium nitride device further includes an isolation region located in the external region. The isolation region is disposed in a two-dimensional electron gas region between the drain finger and the source field plate, and is used to isolate the drain finger and the source field plate.

[0017] Preferably, the source field plate is an elongated strip structure extending along a first direction, which is parallel to the extension direction of the source field plate.

[0018] Preferably, the length of the source field plate along the first direction is greater than, equal to, or less than the length of the annular gate structure along the first direction.

[0019] Preferably, the inner and / or outer walls of the dielectric layer are stepped.

[0020] This application discloses a method for manufacturing a gallium nitride device, including the following steps: A ring-shaped gate structure is formed on the epitaxial substrate, and the gate structure encloses a closed space. A dielectric layer is deposited on the gate structure. Source field plate material is deposited on the dielectric layer, and then etched to form the source field plate.

[0021] The beneficial effects of this application, based on the above technical solutions, are as follows: 1. By setting the gate as a closed ring structure and placing the source field plate on one sidewall of the gate dielectric layer, a natural gap is formed between the residual field plate remaining on the other sidewall after etching and the source field plate. There is no physical contact or electrical connection, thereby eliminating the contribution of the residual field plate to the gate-source capacitance Cgs, significantly reducing the switching loss of the device and increasing the switching frequency.

[0022] 2. In one embodiment, the source fingers are located on the outside of the annular gate and the drain fingers are located on the inside of the annular gate. Self-isolation is achieved by utilizing the gate itself, eliminating the need for additional ion implantation processes and reducing manufacturing costs.

[0023] 3. In another embodiment, the source fingers are located inside the annular gate and the drain fingers are located outside the annular gate. By setting an isolation region, reliable isolation between the drain fingers and the source field plate is achieved, ensuring the normal operation of the device.

[0024] 4. In one embodiment, an opening is provided in both the gate metal and the P-GaN structure directly below the contact hole. The dielectric layer and the source field plate cover the sidewall and bottom wall of the hole, thereby reducing the height of the contact surface between the source field plate and the contact metal (i.e., the height of the bottom of the contact hole), thus improving the compatibility of the contact hole etching process.

[0025] Specific embodiments of this application are disclosed in detail with reference to the following description and accompanying drawings, illustrating how the principles of this application can be employed. It should be understood that the embodiments of this application are not limited in scope. Within the spirit and scope of the appended claims, the embodiments of this application include many changes, modifications, and equivalents.

[0026] Features described and / or illustrated for one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0027] It should be emphasized that the term "including / comprises" as used herein refers to the presence of a feature, whole, step, or component, but does not exclude the presence or addition of one or more other features, wholes, steps, or components. Attached Figure Description

[0028] The accompanying drawings described herein are for illustrative purposes only and are not intended to limit the scope of this application in any way. Furthermore, the shapes and scales of the components in the drawings are merely illustrative to aid in understanding this application and do not specifically limit the shapes and scales of the components. Those skilled in the art, guided by the teachings of this application, can select various possible shapes and scales to implement this application according to specific circumstances. In the drawings: Figure 1 The diagram shows a schematic of the gate structure and source field plate SFP structure of a gallium nitride device in the prior art.

[0029] Figures 2A-2C This diagram illustrates the manufacturing process flow of a gallium nitride device from its gate structure to its source field plate (SFP) in the prior art.

[0030] Figure 3A It shows Figure 2B A schematic cross-sectional view of section A.

[0031] Figure 3B It shows Figure 2C A schematic cross-sectional view of section B.

[0032] Figure 4A A schematic diagram of the layout of a gallium nitride device in the prior art is shown, in which the source field plate is shorter than the gate structure.

[0033] Figure 4B A schematic diagram of the layout of a gallium nitride device in the prior art is shown, in which the source field plate is longer than the gate structure.

[0034] Figure 5 A schematic diagram of the layout of a gallium nitride device in an embodiment of this application is shown.

[0035] Figure 6 It shows Figure 5 A schematic cross-sectional view of section C.

[0036] Figures 7A-7C It shows Figure 5 Flowchart of source field plate manufacturing process for gallium nitride devices.

[0037] Figure 8AIt shows Figure 5 A schematic diagram of the layout of the first interconnect structure for gallium nitride devices.

[0038] Figure 8B It shows Figure 8A A schematic diagram of the cross section D.

[0039] Figure 9A It shows Figure 5 A schematic diagram of the layout of the second interconnect structure for gallium nitride devices.

[0040] Figure 9B It shows Figure 9A A schematic diagram of the cross section E.

[0041] Figure 10 A schematic diagram of the layout of a gallium nitride device in an embodiment of this application is shown.

[0042] Figures 11A-11C It shows Figure 10 Flowchart of source field plate manufacturing process for gallium nitride devices.

[0043] Figure 12A This illustrates a case where the source field plate of a gallium nitride device in an embodiment of this application is shorter than the gate structure.

[0044] Figure 12B This illustrates a case where the source field plate of a gallium nitride device is longer than the gate structure in an embodiment of this application.

[0045] The reference numerals in the above figures are as follows: 1. Epitaxial substrate; 2. Gate structure; 21. P-GaN structure; 22. Gate metal; 3. Source finger; 4. Drain finger; 5. Source field plate; 6. Residual field plate; 7. Dielectric layer; 8. Internal region; 9. External region; 10. Contact hole. Detailed Implementation

[0046] To enable those skilled in the art to better understand the technical solutions in this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this application.

[0047] It should be noted that when an element is referred to as being "set on" another element, it can be directly on the other element or there may be an intervening element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or there may be an intervening element. The terms "vertical," "horizontal," "left," "right," and similar expressions used herein are for illustrative purposes only and do not represent the only embodiments.

[0048] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0049] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on describing the differences from other embodiments. In particular, the system embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.

[0050] It should be noted that in the description of this application, the terms "first," "second," etc., are used only for descriptive purposes and to distinguish similar objects; there is no order between them, nor should they be construed as indicating or implying relative importance. Furthermore, in the description of this application, unless otherwise stated, "multiple" means two or more.

[0051] Figure 5 This diagram illustrates the layout of a gallium nitride device according to an embodiment of this application. (Refer to...) Figure 5 As shown, the gallium nitride device in this embodiment includes a plurality of source fingers 3, drain fingers 4, and a gate structure 2 formed on an epitaxial substrate 1. The plurality of source fingers 3 and the plurality of drain fingers 4 are all along a first direction (…). Figure 5 The length direction of the paper (generally the length direction of the device) extends, and multiple finger strips and multiple drain finger strips 4 extend along the second direction ( Figure 5 The drain fingers 4 are arranged in an interlaced pattern along the width direction of the paper (generally the width direction of the device). A closed-loop gate structure 2 is correspondingly disposed on the outer periphery of at least one or any of the drain fingers 4. That is, the drain fingers 4 are located within the inner region 8. The source fingers 3 are located on the side of the gate structure 2 opposite to the drain fingers 4. That is, the source fingers 3 are located within the outer region 9. In this embodiment, the gate structure 2 is a closed rectangle. Of course, in other optional embodiments, the closed shape of the gate structure 2 can also be set according to actual needs.

[0052] Combination Figure 6 As shown, the gallium nitride device in this embodiment further includes an epitaxial substrate 1. The epitaxial substrate 1 may include components along a third direction ( Figure 6 A buffer layer is formed on the substrate along the length direction of the paper (generally the height direction of the device), a channel layer is formed on the buffer layer along a third direction, and a barrier layer is formed on the channel layer.

[0053] Similar to existing technologies, the substrate can be a silicon (Si) substrate, or a substrate composed of several materials such as silicon on insulator (SOI). The substrate thickness typically ranges from 300µm to 3000µm. When using a Si substrate, its resistivity ranges from 0.001 to 5000 Ω·cm.

[0054] The buffer layer can be made of different materials depending on the substrate and specific requirements. For example, when using a silicon substrate, it can consist of an AlN nucleation layer, one or more AlGaN transition layers, a superlattice buffer layer formed by alternating AlN and AlGaN layers, and a high-carbon layer (carbon concentration greater than 10). 18 cm -3 It can be composed of GaN layers, or sequentially of AlN nucleation layers, one or more AlGaN layers, and high carbon (carbon concentration greater than 10). 18 cm -3 It consists of GaN layers.

[0055] The channel layer can be formed from semiconductor materials, such as low-carbon materials (carbon concentration less than 10). 18 cm -3 The barrier layer can be formed from semiconductor materials, such as compounds based on gallium nitride ternary or quaternary alloys, like Al. x Ga 1x N, AlInGaN, In x Ga 1x N, Al x In 1x Al, AlScN.

[0056] In this embodiment, the gate structure 2 includes a P-GaN structure 21 formed on the barrier layer along a third direction and a gate metal 22 formed on the P-GaN structure 21 along a third direction. The P-GaN structure 21 is typically doped with magnesium, etc. The gate metal 22 can be a combination of TiN, Ti-related materials, Ni / Au, or other similar metal combinations. Either the source finger 3 or the drain finger 4 forms an ohmic contact with the channel layer through the barrier layer.

[0057] Since the gate structure 2 is annular, it has corresponding inner and outer sides. Along a third direction, a dielectric layer 7 is deposited on top of the gate structure 2. Typically, the width of the P-GaN structure 21 differs from the width of the gate metal 22; generally, the width of the P-GaN structure 21 is greater than the width of the gate metal 22, and the vertical projection of the gate metal 22 falls within the area of ​​the P-GaN structure 21. Therefore, both the inner and outer sides of the gate structure 2 are stepped. Correspondingly, the inner and outer sidewalls of the dielectric layer 7 are also stepped. The inner sidewall of the dielectric layer 7 defines a closed internal region 8. The outer sidewall of the dielectric layer 7 defines an external region 9.

[0058] Combination Figure 6 As shown, in this embodiment, a portion of the source field plate 5 is formed and terminated on the top wall of the dielectric layer 7, and this portion of the source field plate 5 is generally used as a field plate connection. Another portion of the source field plate 5 is formed on the inner sidewall of the dielectric layer 7 (in a fitted stepped shape). Yet another portion of the source field plate 5 is formed on the upper surface of the dielectric layer 7 located in the inner region 8, and this portion of the source field plate 5 generally serves as the main body of the field plate.

[0059] As mentioned in the invention description, the typical etching process for the source field plate 5 can only cleanly etch the source field plate 5 SFP in the flat area. However, after the etching process to form the source field plate 5, residual field plate 6 usually remains on the outer wall of the dielectric layer 7.

[0060] Since the gate structure 2 is a closed ring, the source field plate 5 and the residual field plate 6 are also closed rings. Therefore, after etching, there is a gap between the source field plate 5 and the residual field plate 6, so that there is no physical contact and no electrical connection between the source field plate 5 and the residual field plate 6.

[0061] Therefore, the residual field plate 6 of the gallium nitride device using this structure is in a floating state, without introducing additional Cgs capacitance. Furthermore, since the annular gate structure 2 completely surrounds the drain fingers 4, self-isolation can be achieved, reducing the need for isolation processes in the gallium nitride device manufacturing process and thus lowering manufacturing costs.

[0062] Reference Figure 7A As shown, after the gate metal 22 and the PGAN structure are etched, the dielectric layer 7 is deposited in its entirety. After the dielectric layer 7 is deposited, the SFP metal layer is deposited in its entirety, as shown in the figure. Figure 7B As shown, SFP photolithography will then be performed. After development, the area masked by the photoresist is the part that needs to be retained in the SFP process. (Refer to...) Figure 7C As shown, SFP etching is then performed, and the SFP that is not blocked by photoresist will be etched away. Finally, the photoresist is removed.

[0063] Figure 8A and Figure 8B This is a schematic diagram of the SFP contact interconnection of the gallium nitride device of the present invention. The interconnection position of the source field plate 5 and the source electrode is close to the terminal position of the gate structure 2 along the first direction, and a contact hole 10 is formed in the dielectric layer 7 between the overlapping area of ​​the source field plate 5, which serves as a field plate connection, and the source field plate 5 and the source electrode are electrically connected through the first metal layer M1. The contact hole 10 interconnection process of the gallium nitride device needs to realize the electrical lead-out between the source finger strip 3, drain finger strip 4, gate structure 2, and source field plate 5. To ensure the yield and stability of the contact hole 10 etching process, the difference in etching depth of each contact hole 10 should be minimized. (Refer to...) Figure 9A As shown, a P-GAN layer, a gate metal GM layer, and a dielectric layer 7 are stacked sequentially below the interconnect position of the source field plate 5. This results in a relatively high height of the source field plate 5 at this position, making it easy to etch through the source field plate 5 during the etching of the contact hole 10, thus causing instability in the device's electrical signal. Therefore, referring to... Figure 9B As shown, a hole-punching process can be performed at the gate structure 2 (GM / PGAN) around the SFP contact hole 10 to reduce the etching height at the SFP contact hole 10 position, reduce the etching depth difference of the contact hole 10, thereby improving the compatibility of the contact hole 10 etching process and the device yield.

[0064] Figure 10 A layout schematic diagram of a gallium nitride device according to another embodiment of this application is shown. (Refer to...) Figure 10 As shown, the gallium nitride device in this embodiment includes a plurality of source fingers 3, drain fingers 4, and a gate structure 2 formed on an epitaxial substrate 1. Similar to the previous embodiment, the plurality of source fingers 3 and drain fingers 4 are all along a first direction (…). Figure 5 The length direction of the paper (generally the length direction of the device) extends, and multiple finger strips and multiple drain finger strips 4 extend along the second direction ( Figure 5 The paper (generally the width direction of the device) is arranged in an interdigitated pattern.

[0065] Unlike the previous embodiment, a closed-loop gate structure 2 is correspondingly disposed on the outer periphery of at least one or any of the source fingers 3. That is, the source fingers 3 are located within the inner region 8. The drain fingers 4 are located on the side of the gate structure 2 opposite to the source fingers 3. That is, the drain fingers 4 are located within the outer region 9. Along a third direction, a dielectric layer 7 is deposited on the gate structure 2 above it. In this embodiment, a portion of the source field plate 5 is formed and terminates on the top wall of the dielectric layer 7, and this portion of the source field plate 5 is generally used as a field plate connection. Another portion of the source field plate 5 is formed on the outer wall of the dielectric layer 7 (in a fitted stepped shape). Yet another portion of the source field plate 5 is formed on the upper surface of the dielectric layer 7 located in the outer region 9, and this portion of the source field plate 5 generally serves as the field plate body.

[0066] As mentioned in the invention description, the typical etching process for the source field plate 5 can only cleanly etch the source field plate 5 SFP in the flat area. However, after the etching process to form the source field plate 5, residual field plate 6 usually remains on the inner sidewall of the dielectric layer 7.

[0067] Since the gate structure 2 is a closed ring, the residual field plates 6 are also all closed rings. The source field plate 5 is generally an elongated strip extending along the first direction. Therefore, after etching, there is a gap between the source field plate 5 and the residual field plate 6, so that there is no physical contact and no electrical connection between the source field plate 5 and the residual field plate 6.

[0068] Therefore, the residual field plate 6 of the gallium nitride device using this structure is in a floating state and does not introduce additional Cgs capacitance.

[0069] Since both the drain finger 4 and the source field plate 5 are located within the outer region 9, and the source finger 3 is located within the inner region 8 of the ring, the two-dimensional electron gas region between the drain and the source field plate 5 (connected to the source potential) within the outer region 9 needs to be isolated; otherwise, a short circuit between the drain and the source will occur. Therefore, in this embodiment, an isolation region is provided in the two-dimensional electron gas region of the outer region 9 between the drain and the source field plate 5. This isolation region is formed by ion implantation (such as implantation of argon, nitrogen, iron, etc.) to destroy the 2DEG conductivity of this region and achieve electrical isolation.

[0070] Reference Figure 11A As shown, after the gate metal 22 and the PGAN structure are etched, the dielectric layer 7 is deposited in its entirety. After the dielectric layer 7 is deposited, the SFP metal layer is deposited in its entirety, as shown in the figure. Figure 11B As shown, SFP photolithography will then be performed. After development, the area masked by the photoresist is the part that needs to be retained in the SFP process. (Refer to...) Figure 11C As shown, SFP etching is then performed, and the SFP that is not blocked by photoresist will be etched away. Finally, the photoresist is removed.

[0071] Figure 12A and Figure 12B The layout diagram of the gallium nitride device in this embodiment is shown. It is feasible whether the source field plate 5SFP is longer or shorter than the gate structure 2.

[0072] It should be understood that the above description is for illustrative purposes and not for limitation. Many embodiments and applications beyond the provided examples will be apparent to those skilled in the art upon reading the above description. Therefore, the scope of this teaching should not be determined by reference to the above description, but rather by reference to the foregoing claims and the full scope of their equivalents. For purposes of completeness, all articles and references, including patent applications and publications, are incorporated herein by reference. The omission of any aspect of the subject matter disclosed herein in the foregoing claims is not intended as a waiver of that subject matter, nor should it be construed as an indication that the applicant has not considered that subject matter as part of the disclosed application subject matter.

Claims

1. A gallium nitride device, characterized in that, include: A gate structure in the form of a closed ring; A dielectric layer having an inner sidewall covering the inside of the gate structure and an outer sidewall covering the outside of the gate structure, the inner sidewall of the dielectric layer defining an enclosed internal region and the outer sidewall of the dielectric layer defining an external region. A source field plate, at least a portion of which is formed on one of the inner and outer sidewalls of the dielectric layer; A residual field plate, which is formed on one of the inner and outer sidewalls of the dielectric layer, and is left on the dielectric layer after an etching process performed to form the source field plate; There is a gap between the source field plate and the residual field plate, so that there is no physical contact and no electrical connection between the source field plate and the residual field plate.

2. The gallium nitride device according to claim 1, characterized in that, The residual field plate has a closed ring structure and continuously surrounds the corresponding inner or outer sidewall of the medium layer.

3. The gallium nitride device according to claim 1, characterized in that, It also includes source electrode fingers, which are respectively disposed in different regions of the internal region and the external region.

4. The gallium nitride device according to claim 3, characterized in that, The dielectric layer also includes a top wall covering the gate structure, the top wall connecting the inner sidewall and the outer sidewall; the end of the source field plate facing the source finger terminates horizontally directly above the top wall of the gate structure.

5. The gallium nitride device according to claim 1, characterized in that, It also includes source and drain finger strips: The source electrode fingers are disposed in the outer region, and the drain electrode fingers are disposed in the inner region; At least a portion of the source field plate is disposed in the internal region, and the source field plate is in the form of a closed ring. The residual field plate is formed on the outer side wall; The gate structure and the dielectric layer together act as a physical barrier, causing the residual field plate to be in an electrically floating state.

6. The gallium nitride device according to claim 1, characterized in that, It also includes source and drain finger strips: The source electrode fingers are disposed in the inner region, and the drain electrode fingers are disposed in the outer region; At least a portion of the source field plate is disposed in the external region; The residual field plate is formed on the inner sidewall; The gallium nitride device further includes an isolation region located in the external region. The isolation region is disposed in a two-dimensional electron gas region between the drain finger and the source field plate, and is used to isolate the drain finger and the source field plate.

7. The gallium nitride device according to claim 6, characterized in that, The source electrode field plate is an elongated strip structure extending along a first direction, which is parallel to the extension direction of the source electrode strip.

8. The gallium nitride device according to claim 6, characterized in that, The length of the source field plate along the first direction is greater than, equal to, or less than the length of the annular gate structure along the first direction.

9. The gallium nitride device according to claim 1, characterized in that, The inner and / or outer walls of the medium layer are stepped.

10. A method for manufacturing a gallium nitride device, characterized in that, Includes the following steps: A ring-shaped gate structure is formed on the epitaxial substrate, and the gate structure encloses a closed space. A dielectric layer is deposited on the gate structure. Source field plate material is deposited on the dielectric layer, and then etched to form the source field plate.

Images