Method for increasing winding density using longitudinal slit of spacer layer

Abstract

This application provides a method for increasing winding density using longitudinal slots in a spacer layer, comprising: Step 1, providing a substrate and forming an interlayer dielectric layer on the substrate; Step 2, performing a first etching to form a first trench in the interlayer dielectric layer for filling an M1 metal layer; Step 3, performing a second etching to form a second trench in the interlayer dielectric layer for filling a spacer layer that blocks the M1 metal layer and a third trench for achieving interconnection between portions of the M1 metal layers; Step 4, depositing a spacer layer in the second and third trenches, forming a longitudinal slot in the spacer layer located in the third trench; Step 5, filling the first trench and the longitudinal slot with an M1 metal layer. The longitudinal slots formed by the spacer layer deposition enable interconnection between metal lines in the same layer, replacing traditional upper metal layers and vias, saving traces for back-end layout and wiring, reducing process costs, reducing parasitic capacitance and resistance, and improving chip performance.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically to a method for increasing winding density by utilizing the longitudinal gaps in a spacer layer. Background Technology

[0002] In semiconductor manufacturing processes, as critical dimensions shrink and process layouts become increasingly complex, the limits of photolithography are often pushed. This necessitates limiting the underlying metal layers to unidirectional designs. To achieve interconnects in different directions, multiple metal layers need to be stacked. These multi-layer metal interconnect structures typically connect different metal lines via vias. For example... Figure 1 As shown, for connecting two M1s, the traditional process requires the use of an upper metal layer, M2, and via V1 to complete the connection of M1s. This involves additional photolithography, etching, and metal filling steps, which can easily lead to incomplete filling and interconnection failure. Furthermore, it may introduce parasitic capacitance and resistance, affecting signal transmission rate and power consumption.

[0003] In addition, such as Figure 1 As shown, when a metal layer has a cut, if the cut linewidth exceeds the process window, a longitudinal seam is easily formed in the central region of the cut during spacer layer deposition, leading to cut failure during subsequent metal layer deposition. Existing technologies typically treat this seam as a process defect, requiring special repair using optical proximity correction (OPC), which complicates the fabrication process and increases costs. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this application is to provide a method for increasing the winding density by utilizing the longitudinal gaps of the spacer layer, in order to solve the problem of interconnection failure that occurs when the upper metal layer is used to partially interconnect the lower metal layer in the prior art.

[0005] To achieve the above and other related objectives, this application provides a method for increasing winding density using longitudinal gaps in a spacer layer, comprising: Step 1: Provide a substrate and form an interlayer dielectric layer on the substrate; Step 2: Perform the first etching to form a first trench in the interlayer dielectric layer for filling the M1 metal layer; Step 3: Perform a second etching to form a second trench in the interlayer dielectric layer for filling the spacer layer that blocks the M1 metal layer and a third trench for realizing the interconnection between some of the M1 metal layers; Step 4: Deposit spacer layers in the second and third trenches, and form longitudinal slots in the spacer layers located in the third trench; Step 5: Fill the first trench and longitudinal gap with M1 metal layers to achieve interconnection between some of the M1 metal layers.

[0006] Preferably, the width of the third trench is greater than the width of the second trench, and the width of the second trench is sufficient to fill the second trench during subsequent deposition of the spacer layer.

[0007] Preferably, the width of the third trench is greater than 320 Å.

[0008] Preferably, an interlayer is deposited in the second and third trenches using an atomic layer deposition process.

[0009] Preferably, the width of the longitudinal gap formed in the spacer layer is controlled by controlling the thickness of the spacer layer on both sides of the third trench.

[0010] Preferably, the width of the longitudinal slit is 150 Å-200 Å.

[0011] Preferably, the spacer layer is made of titanium oxide.

[0012] Preferably, in step two, a first mask layer with a first trench pattern is first formed on the interlayer dielectric layer by photolithography and etching processes, and then the first etching is performed using the first mask layer as a mask to form the first trench in the interlayer dielectric layer. After that, the first mask layer is removed.

[0013] Preferably, in step three, a second mask layer with a second trench and a third trench pattern is first formed on the interlayer dielectric layer by photolithography and etching processes. Then, the second mask layer is used as a mask to perform the second etching to form the second trench and the third trench in the interlayer dielectric layer. After that, the second mask layer is removed.

[0014] Preferably, after step five, chemical mechanical polishing is performed to make the surface of the M1 metal layer smooth while exposing the spacer layer.

[0015] As described above, the method for increasing winding density by utilizing the longitudinal gaps of the spacer layer provided in this application has the following beneficial effects: the longitudinal gaps formed by the deposition of the spacer layer realize the interconnection between metal lines in the same layer, replacing the traditional upper metal layer and vias, saving routing paths for back-end layout and wiring, not only enabling metal lines to bend under advanced processes and reducing process costs, but also reducing parasitic capacitance and parasitic resistance, and improving chip performance. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0017] Figure 1The diagram shows a cross-sectional structure and layout of a device after partial interconnection of the M1 metal layer using existing technology. Figure 2 The flowchart shown is a method for increasing winding density by utilizing the longitudinal gaps of the spacer layer provided in an embodiment of this application. Figure 3 The diagram shows a cross-sectional structure and layout of a device after partial interconnection of the M1 metal layer based on the method of increasing winding density by utilizing the longitudinal gaps of the spacer layer provided in the embodiments of this application. Detailed Implementation

[0018] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this invention.

[0019] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0020] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," indicating orientation or positional relationships, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0021] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0022] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0023] Please see Figure 2 The diagram illustrates a flowchart of a method for increasing winding density using longitudinal gaps in a spacer layer, as provided in an embodiment of this application.

[0024] like Figure 2 As shown, the method for increasing winding density by utilizing the longitudinal gaps in the spacer layer includes the following steps: Step 1: Provide a substrate and form an interlayer dielectric layer on the substrate; Step 2: Perform the first etching to form a first trench in the interlayer dielectric layer for filling the M1 metal layer; Step 3: Perform a second etching to form a second trench in the interlayer dielectric layer for filling the spacer layer that blocks the M1 metal layer and a third trench for realizing the interconnection between some of the M1 metal layers; Step 4: Deposit spacer layers in the second and third trenches, and form longitudinal slots in the spacer layers located in the third trench; Step 5: Fill the first trench and longitudinal gap with M1 metal layers to achieve interconnection between some of the M1 metal layers.

[0025] In step one, the substrate may optionally be a silicon substrate, a germanium substrate, or a silicon-on-insulator substrate; alternatively, the substrate material may include other materials, such as gallium arsenide or other III-V compounds. Those skilled in the art can select the substrate material based on the type of device structure formed on the substrate; therefore, the type of substrate should not limit the scope of protection of this invention.

[0026] Multiple isolation components are formed on the substrate, dividing the substrate into multiple regions. The isolation components can be composed of any insulating material such as silicon dioxide (SiO2), or a "high-k" dielectric with a high dielectric constant, for example, greater than 3.9. In some cases, the isolation components can be composed of oxide materials. Suitable materials for constituting the isolation components include, for example, silicon dioxide (SiO2), hafnium oxide (HfO2), bauxite (Al2O3), yttrium oxide (Y2O3), tantalum oxide (Ta2O5), titanium dioxide (TiO2), praseodymium oxide (Pr2O3), zirconium oxide (ZrO2), erbium oxide (ErOx), and other materials with similar properties, either currently known or developed later.

[0027] For example, the isolation component is formed by a shallow trench isolation process (STI), which includes, but is not limited to, shallow trench etching, oxide filling, and oxide planarization.

[0028] Shallow trench etching includes, but is not limited to, isolating oxide layers, nitride deposition, shallow trench isolation using masks, and STI shallow trench etching. STI oxide filling includes, but is not limited to, trench liner silicon oxide, trench CVD (chemical vapor deposition) oxide filling, or PVD (physical vapor deposition) oxide filling. Silicon wafer surface planarization can be achieved through various methods. Planarization can be achieved by using SOG (spin-on-glass) to fill the gaps. SOG can be composed of 80% solvent and 20% silicon dioxide. After deposition, the SOG is baked to evaporate the solvent, leaving the silicon dioxide in the gaps. Alternatively, the entire surface can be reverse-etched to reduce the overall wafer thickness. Planarization can also be effectively achieved through CMP (chemical mechanical polishing) processes, including but not limited to polishing the trench oxides (using chemical mechanical polishing) and nitride removal.

[0029] Various semiconductor devices, such as MOSFETs and diodes, are formed in different regions of the substrate.

[0030] As an example, an interlayer dielectric layer is formed on a substrate by a deposition process. The material of the interlayer dielectric layer is, for example, but not limited to: silicon nitride (Si3N4), silicon oxide (SiO2), fluorinated SiO2 (FSG), hydrogenated carbon silicon oxide (SiCOH), porous SiCOH, borosilicate glass (BPSG), silsesquioxane, carbon (C) doped oxides (i.e., organosilicones) including silicon (Si), carbon (C), oxygen (O) and / or hydrogen (H) atoms, thermosetting polyarylene ethers, or other materials with low dielectric constants (<3.9).

[0031] In step two, a first mask layer with a first trench pattern is first formed on the interlayer dielectric layer through photolithography and etching processes. Then, the first mask layer is used as a mask to perform the first etching to form the first trench in the interlayer dielectric layer. After that, the first mask layer is removed.

[0032] In step three, a second mask layer with a second trench and a third trench pattern is first formed on the interlayer dielectric layer through photolithography and etching processes. Then, the second mask layer is used as a mask to perform the second etching to form the second trench and the third trench in the interlayer dielectric layer. After that, the second mask layer is removed.

[0033] The width of the third trench is greater than that of the second trench. After repeated experiments, it was found that when the width of the trench is greater than 320 Å, the step coverage of the spacer layer on the sidewall of the trench drops to less than 65%, resulting in voids at the bottom of the trench. The width of the second trench must be sufficient to fill the second trench when the spacer layer is deposited subsequently.

[0034] For example, the top width of the third trench is 480 Å.

[0035] In step four, an atomic layer deposition (ALD) process is used to deposit spacer layers in the second and third trenches. The width of the longitudinal slots formed in the spacer layers is controlled by adjusting the thickness of the spacer layers on both sides of the third trench. As an example, the width of the longitudinal slots is 150 Å-200 Å.

[0036] For example, the spacer layer may be made of titanium oxide (TiO).

[0037] In step five, the M1 metal layer is filled into the first trench and longitudinal gap using an electroplating process. After step five is completed, chemical mechanical polishing is performed to smooth the surface of the M1 metal layer and expose the spacer layer.

[0038] contrast Figure 1 and Figure 3 To achieve partial interconnection of the M1 metal layer, it is not necessary to form an upper M2 metal layer and a via connecting the M2 metal layer and the M1 metal layer. The interconnection of partial M1 metal layers is achieved through the longitudinal gaps formed in the spacer layer.

[0039] The method provided in this application for increasing winding density by utilizing the longitudinal gaps in the spacer layer replaces the traditional upper metal wiring and via structures (M2 and V1) with the process defect (cut seam) caused by the excessively wide trench during the blocking process of forming the metal layer. This turns the cut seam into a valuable resource, achieving "intra-layer interconnection replacing cross-layer vias". This overcomes the problem of the contradiction between process complexity and performance in traditional structures, reducing the process flow and improving performance. It is especially suitable for the high-density interconnection requirements of advanced processes.

[0040] Through testing and verification, while keeping the total chip area unchanged, the performance of key circuits is optimized, the utilization rate of V1 / M2 is reduced, the difficulty of OPC splitting is reduced, the utilization rate of wiring resources is improved, and the advantages of PPA (performance, power consumption and size) are fully demonstrated.

[0041] Dyn. Power (uW) 50.82 50.91 0.18% Frequency (GHz) 91.28 91.99 0.78% Area (um^2) 0.109 0.109 0% It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of this application. Therefore, the drawings only show the components related to this invention and are not drawn according to the actual number, shape and size of the components. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0042] In summary, the method for increasing winding density using longitudinal gaps in the spacer layer provided in this application achieves interconnection between metal lines in the same layer by utilizing the longitudinal gaps formed by the deposition of the spacer layer, replacing the traditional upper metal layer and vias. This saves routing paths for back-end layout and wiring, not only enabling metal lines to bend in advanced processes and reducing process costs, but also reducing parasitic capacitance and resistance, thus improving chip performance. Therefore, this application effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0043] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this invention should still be covered by the claims of this application.

Claims

1. A method for increasing winding density using longitudinal gaps in a spacer layer, characterized in that, The method includes: Step 1: Provide a substrate and form an interlayer dielectric layer on the substrate; Step 2: Perform the first etching to form a first trench in the interlayer dielectric layer for filling the M1 metal layer; Step 3: Perform a second etching to form a second trench in the interlayer dielectric layer for filling the spacer layer that blocks the M1 metal layer and a third trench for realizing partial interconnection between the M1 metal layers; Step four: Deposit spacer layers in the second trench and the third trench, and form longitudinal gaps in the spacer layers located in the third trench; Step 5: Fill the first trench and the longitudinal gap with the M1 metal layer to achieve interconnection between some of the M1 metal layers.

2. The method according to claim 1, characterized in that, The width of the third trench is greater than the width of the second trench, and the width of the second trench is required to ensure that the spacer layer is filled during subsequent deposition.

3. The method according to claim 1 or 2, characterized in that, The width of the third trench is greater than 320 Å.

4. The method according to claim 1, characterized in that, The spacer layer is deposited in the second trench and the third trench using an atomic layer deposition process.

5. The method according to claim 1, characterized in that, The width of the longitudinal slit is adjusted by controlling the thickness of the spacer layers on both sides of the third trench.

6. The method according to claim 1 or 5, characterized in that, The width of the longitudinal slit is 150 Å-200 Å.

7. The method according to claim 1 or 4, characterized in that, The spacer layer is made of titanium oxide.

8. The method according to claim 1, characterized in that, In step two, a first mask layer with the first trench pattern is first formed on the interlayer dielectric layer by photolithography and etching processes. Then, the first etching is performed using the first mask layer as a mask to form the first trench in the interlayer dielectric layer. After that, the first mask layer is removed.

9. The method according to claim 1, characterized in that, In step three, a second mask layer with the second trench and the third trench pattern is first formed on the interlayer dielectric layer by photolithography and etching processes. Then, the second etching is performed using the second mask layer as a mask to form the second trench and the third trench in the interlayer dielectric layer. After that, the second mask layer is removed.

10. The method according to claim 1, characterized in that, After step five is completed, chemical mechanical polishing is performed to make the surface of the M1 metal layer flat while exposing the spacer layer.

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