A register allocation method, apparatus, device, medium and product

Abstract

The application discloses a register allocation method, device, equipment, medium and product, and the method comprises the steps of obtaining an operation instruction to be allocated, determining an operation width identifier of the operation instruction to be allocated; determining a register allocation mode of the operation instruction to be allocated according to the operation width identifier and a register sharing condition, wherein the register allocation mode comprises a shared register allocation mode and a separate allocation mode; performing physical register allocation on the operation instruction to be allocated based on the register allocation mode, and generating an enhanced renaming table, and each 64-bit physical register is divided into a high 32-bit sub-register and a low 32-bit sub-register. By splitting a single 64-bit physical register into two independent 32-bit sub-registers and realizing shared use, the shared or separate allocation mode is dynamically selected based on the instruction width, space waste caused by using only 32 bits but occupying a complete 64-bit register can be avoided, dynamic power consumption is reduced, and the register utilization rate is significantly improved.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to a register allocation method, apparatus, device, medium, and product. Background Technology

[0002] Modern high-performance 64-bit processors commonly employ register renaming and out-of-order execution techniques to improve instruction-level parallelism. In these processors, the Physical Register File (PRF) is one of the key resources.

[0003] Traditional physical register management schemes mainly include full-width allocation and segmented register files. Full-width allocation maps each architecture register to a complete 64-bit physical register, allocating a full 64-bit physical register regardless of instruction operand width. The renameAliasTable simply records the simple mapping relationship between architecture registers and physical registers. Segmented register files divide the 64-bit physical register into two regions, a high 32-bit region and a low 32-bit region, but still allocate and release them as a whole, not supporting shared modes used by different instructions simultaneously.

[0004] However, this traditional management method has the following drawbacks: allocating a full 64-bit physical register for 32-bit operations results in approximately 50% wasted storage space. The physical register file typically occupies 15-20% of the total processor area, and increasing the number of registers to support a sufficiently large reordering window significantly increases chip cost. Summary of the Invention

[0005] This invention provides a register allocation method, apparatus, device, medium, and product to improve register utilization and reduce the overhead of physical register file area by sharing physical registers.

[0006] According to a first aspect of the present invention, a register allocation method is provided, comprising:

[0007] Obtain the operation instruction to be assigned, and determine the operation width identifier of the operation instruction to be assigned;

[0008] Based on the operation width identifier and register sharing conditions, the register allocation mode of the operation instruction to be allocated is determined. The register allocation mode includes a shared register allocation mode and a separate allocation mode.

[0009] Based on the register allocation mode, the physical registers of the operation instructions to be allocated are allocated, and an enhanced renaming table is generated. Each 64-bit physical register is divided into a high 32-bit sub-register and a low 32-bit sub-register.

[0010] According to a second aspect of the present invention, a register allocation apparatus is provided, comprising:

[0011] The identifier determination module is used to acquire the operation instruction to be assigned and determine the operation width identifier of the operation instruction to be assigned.

[0012] The mode determination module is used to determine the register allocation mode of the operation instruction to be allocated based on the operation width identifier and the register sharing condition. The register allocation mode includes a shared register allocation mode and a separate allocation mode.

[0013] The register allocation module is used to allocate physical registers to the operation instructions to be allocated based on the register allocation mode, and generate an enhanced renaming table, in which each 64-bit physical register is divided into a high 32-bit sub-register and a low 32-bit sub-register.

[0014] According to another aspect of the present invention, an electronic device is provided, the electronic device comprising:

[0015] At least one processor; and

[0016] A memory communicatively connected to the at least one processor; wherein,

[0017] The memory stores a computer program that can be executed by the at least one processor, the computer program being executed by the at least one processor to enable the at least one processor to perform the register allocation method according to any embodiment of the present invention.

[0018] According to another aspect of the present invention, a computer-readable storage medium is provided, the computer-readable storage medium storing computer instructions for causing a processor to execute and implement the register allocation method described in any embodiment of the present invention.

[0019] According to another aspect of the present invention, embodiments of the present invention also provide a computer program product, the computer program product including a computer program, which, when executed by a processor, implements the register allocation method of any embodiment of the present invention.

[0020] The technical solution of this invention splits a single 64-bit physical register into two independent 32-bit sub-registers and enables their shared use. Based on the instruction width, it dynamically selects the shared or independent allocation mode, which avoids the space waste caused by using only 32 bits but occupying the entire 64-bit register. This significantly improves register utilization, reduces unnecessary 64-bit register access, and reduces dynamic power consumption.

[0021] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a flowchart of a register allocation method provided according to Embodiment 1 of the present invention;

[0024] Figure 2 This is a flowchart of a register allocation method provided according to Embodiment 2 of the present invention;

[0025] Figure 3 This is a schematic diagram of a register allocation device according to Embodiment 3 of the present invention;

[0026] Figure 4 A schematic diagram of the structure of an electronic device implementing an embodiment of the present invention. Detailed Implementation

[0027] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0028] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0029] Example 1

[0030] Figure 1 This is a flowchart illustrating a register allocation method according to Embodiment 1 of the present invention. This embodiment is applicable to the allocation of physical registers. The method can be executed by a register allocation device, which can be implemented in hardware and / or software and can be configured in an electronic device. Figure 1 As shown, the method includes:

[0031] S110. Obtain the operation instruction to be assigned and determine the operation width identifier of the operation instruction to be assigned.

[0032] In this embodiment, the instruction to be allocated can be understood as an instruction that enters the processor renaming stage and requires physical register mapping allocation. The operation width identifier is an instruction type marker identified during the decoding stage, used to distinguish between 32-bit and 64-bit operation instructions.

[0033] Specifically, the processor can acquire the operation instructions to be allocated in the renaming stage, identify the instruction operand width in the decoding stage, and generate the corresponding 32-bit or 64-bit operation width identifier.

[0034] S120. Determine the register allocation mode of the operation instruction to be allocated based on the operation width identifier and register sharing conditions. The register allocation mode includes shared register allocation mode and separate allocation mode.

[0035] In this embodiment, the register sharing condition is used to determine whether the current pending operation instruction can share a physical register with other pending operation instructions. For example, if multiple ordered pending operation instructions can be received each time, the register sharing condition can be that the current pending operation instruction and the previous pending operation instruction are both 32-bit operations, and their target architecture registers are different. Register allocation modes can be understood as rules used to indicate where instructions are allocated to physical registers. Shared register allocation mode refers to the mode of allocating two adjacent 32-bit instructions to different 32-bit sub-registers of the same 64-bit physical register. Separate allocation mode refers to the mode of allocating a complete 64-bit physical register for an instruction and occupying it independently.

[0036] Specifically, the processor can jointly determine whether two instructions meet the register sharing condition based on the operation width identifier of the instruction adjacent to the instruction to be allocated. Based on the determination result, it determines whether the current instruction adopts the shared register allocation mode or the separate allocation mode, so as to obtain the register allocation mode of the instruction to be allocated.

[0037] S130. Based on the register allocation mode, physical registers are allocated for the instruction to be allocated, and an enhanced renaming table is generated. Each 64-bit physical register is divided into a high 32-bit sub-register and a low 32-bit sub-register.

[0038] In this embodiment, the enhanced renaming table is a renaming mapping table that adds a shared identifier and a half-domain selection identifier to the traditional mapping table. The high 32-bit sub-register and the low 32-bit sub-register are two independently accessible storage areas obtained by dividing a single 64-bit physical register into bits [63:32] and bits [31:0].

[0039] Specifically, the processor can perform physical register allocation according to a defined allocation mode. In the shared register allocation mode, the high 32-bit sub-register and low 32-bit sub-register of the same physical register are reused. In the separate allocation mode, a brand new complete 64-bit physical register is allocated. At the same time, an enhanced renaming table is generated according to the architecture register, physical register number and register allocation method. The entire process relies on the hardware structure that divides each 64-bit physical register into a high 32-bit sub-register and two low 32-bit sub-registers to complete resource allocation and mapping records.

[0040] The technical solution of this invention splits a single 64-bit physical register into two independent 32-bit sub-registers and enables their shared use. Based on the instruction width, it dynamically selects the shared register allocation mode or the independent allocation mode, which can avoid the space waste caused by using only 32 bits but occupying the entire 64-bit register. This significantly improves register utilization, reduces unnecessary 64-bit register access, and reduces dynamic power consumption.

[0041] As a first optional embodiment of this embodiment, after performing physical register allocation on the instruction to be allocated based on the register allocation mode and generating an enhanced renaming table, the method further includes:

[0042] The state of the physical register state machine to be modified is modified, including the occupied state, the idle state, and the state waiting for the other half to be released.

[0043] In this embodiment, the physical register to be modified refers to a 64-bit physical register that has been allocated for use by instructions and requires a state update. The physical register state machine manages the state transition logic for the physical register's lifecycle and reclamation timing. The occupied state indicates that the physical register is being used by an instruction. The idle state indicates that the physical register has not been allocated and is available for new instruction allocation. The waiting-for-the-other-half-release state indicates that the physical register is shared by two 32-bit instructions and only one instruction has completed releasing it.

[0044] Specifically, after the physical registers for the operation instructions to be allocated are allocated in either shared register allocation mode or separate allocation mode, and an enhanced renaming table is generated, the processor can modify the state of the corresponding physical register state machine according to the allocation results and instruction usage.

[0045] Furthermore, based on the above embodiments, the steps for modifying the state of the physical register state machine to be modified can be refined as follows:

[0046] When a physical register to be modified is shared by two operation instructions and one of its sub-registers is released, the state of the physical register state machine of the physical register to be modified is changed to the waiting for the other half to be released state; when a physical register to be modified is shared by two operation instructions and both sub-registers are released, the state of the physical register state machine of the physical register to be modified is changed to the idle state; when a physical register to be modified is released while in a fully occupied 64-bit state, the state of the physical register state machine of the physical register to be modified is changed to the idle state; when a physical register to be modified is occupied, the state of the physical register state machine of the physical register to be modified is changed to the occupied state.

[0047] In this embodiment, a sub-register refers to the high 32-bit sub-register and the low 32-bit sub-register obtained by dividing the 64-bit physical register. While waiting for the other half to be released, one sub-register has been released while the other sub-register is still in use.

[0048] Specifically, during the physical register release and state update phase, if a physical register is in shared register allocation mode, and its high and low sub-registers are used by two 32-bit operation instructions respectively, and only one sub-register is released, the state of its physical register state machine is changed to the waiting-for-the-other-half-release state. If both sub-registers in the shared register allocation mode have been released, the processor can change the state of the physical register state machine from the waiting-for-the-other-half-release state to the idle state. If the physical register is in a 64-bit independent fully occupied state, the state of the physical register state machine is directly changed to the idle state after the instruction execution is completed and the register is released. When a physical register is allocated and used by a new instruction, its state machine is uniformly changed to the occupied state, thereby completing the state switching and resource reclamation across all scenarios.

[0049] In the first optional embodiment of this embodiment, by adding a waiting state for the other half to be released to the physical register state machine, the shared logic is closed-loop and reliable, ensuring that the shared physical register is not prematurely reclaimed, ensuring data security and correct instruction execution, and achieving truly efficient sharing.

[0050] Example 2

[0051] Figure 2This is a flowchart of a register allocation method provided in Embodiment 2 of the present invention. This embodiment is a further refinement of the above embodiment. Figure 2 As shown, the method includes:

[0052] S201. Obtain the operation instruction to be assigned and determine the operation width identifier of the operation instruction to be assigned.

[0053] S202. Determine whether the operation width identifiers of adjacent pending operation instructions are both 32 bits and whether the target architecture registers of adjacent pending operation instructions are different.

[0054] In this embodiment, adjacent instructions to be allocated can be understood as two instructions in the processor instruction line that are back-to-back and enter the renaming stage consecutively within the same clock cycle. The target architecture register can be understood as the architecture register where the result needs to be written after the instruction is executed.

[0055] Specifically, during the instruction renaming phase, the processor can first determine whether the operation width identifiers of the two adjacent instructions to be assigned are both 32 bits, and at the same time determine whether the target architecture registers of the two instructions to be assigned are different.

[0056] S203. If yes, then the register sharing condition is met, and the register allocation mode of the adjacent instruction to be allocated is determined to be the shared register allocation mode.

[0057] Specifically, if both conditions are met simultaneously, the instruction to be allocated is determined to meet the register sharing condition, and the register allocation mode of these two adjacent instructions is determined to be the shared register allocation mode.

[0058] S204. If not, then the register sharing condition is not met, and the instruction to be allocated is determined to be in separate allocation mode.

[0059] Specifically, if any one of these conditions is not met, the register sharing condition is determined to be unmet, and the register allocation mode of the corresponding instruction is set to separate allocation mode, and physical registers are allocated according to the traditional separate allocation method.

[0060] S205. For two adjacent unallocated operation instructions in the shared register allocation mode, allocate the first unallocated operation instruction to the lower 32 bits of the first target physical register in the idle state.

[0061] In this embodiment, the first instruction to be allocated refers to the instruction that is the first in line and enters the allocation process first among a group of adjacent instructions to be allocated that meet the sharing conditions. The first target physical register refers to a 64-bit physical register that is in an idle state and is used by two instructions to be allocated in the shared register allocation mode. The lower 32 bits of the sub-register are an independently accessible area divided into bits [31:0].

[0062] Specifically, for two adjacent instruction requests that satisfy the shared register allocation mode, the processor can sequentially allocate the first instruction request to the lower 32 bits of the first target physical register that is in an idle state.

[0063] S206. Allocate the next pending operation instruction to the high 32-bit sub-register of the first target physical register.

[0064] In this embodiment, the next pending allocation instruction refers to the last pending allocation instruction in a group of adjacent pending allocation instructions that meet the sharing conditions, and the one that enters the allocation process last. The high 32-bit sub-register is an independently accessible area of ​​the 64-bit physical register divided into bits [63:32].

[0065] Specifically, the processor can allocate the next adjacent instruction to be allocated to the high 32-bit sub-register of the same first destination physical register.

[0066] S207. The registers in the separate allocation mode are independently allocated to the second target physical register in the idle state.

[0067] In this embodiment, the second target physical register refers to the free 64-bit physical register allocated to the instruction in the separate allocation mode. It can be a 64-bit physical register divided into two sub-registers or an independent 64-bit physical register.

[0068] Specifically, for instructions in separate allocation mode, the processor can directly allocate a second target physical register that is in an idle state to them independently.

[0069] S208. Generate an enhanced renaming table based on the destination register number, the allocated physical register number, and the sub-registers in each operation instruction to be allocated.

[0070] In this embodiment, the destination register number can be understood as the architecture register number of the result to be written in the instruction. Sub-registers refer to the lower 32-bit sub-registers and the higher 32-bit sub-registers obtained by dividing the 64-bit physical registers.

[0071] Specifically, the processor can generate an enhanced renaming table containing a shared identifier and a half-domain selection identifier based on the destination register number corresponding to each instruction to be allocated, the allocated physical register number, and the location of the sub-register used.

[0072] Furthermore, based on the above embodiments, the steps for generating an enhanced renaming table according to the destination register number, the allocated physical register number, and the sub-registers in each operation instruction to be allocated can be refined as follows:

[0073] Determine the architecture register number based on the destination register number in each instruction to be allocated; determine the half-domain selection identifier based on the allocated sub-register; determine the sharing identifier based on the register allocation mode; and determine the enhanced renaming table based on the architecture register number, physical register number, half-domain selection identifier, and sharing identifier.

[0074] In this embodiment, the half-domain selection flag is used to indicate whether to use the lower 32-bit sub-register or the higher 32-bit sub-register. The sharing flag is used to identify whether the current architecture registers use physical registers independently or share physical registers.

[0075] Specifically, the processor can extract the destination register number from the instruction to be allocated and directly identify it as the corresponding architecture register number. The processor can determine the half-domain selection flag based on whether the instruction allocates a lower 32-bit or higher 32-bit sub-register. Based on whether the instruction uses a shared register allocation mode or a separate allocation mode, the processor determines whether the sharing flag is in a shared state or an independent state. The processor can combine the determined architecture register number, physical register number, half-domain selection flag, and sharing flag to generate and write an enhanced renaming table, completing the full mapping configuration.

[0076] For example, entries in the enhanced renaming table include: ATAG (Destination Register Number), PTAG (Physical Register Number). Share (Shared Identifier): 0 indicates independent use, 1 indicates shared use. HalfSel (Half-Field Selection Identifier): 0 = Low32bit, 1 = High32bit.

[0077] Table 1 Enhanced Renaming Table

[0078]

[0079] Table 1 above shows that destination registers numbered 1, 2, 4, 30, and 31, identified by the Share identifier, use a shared register allocation mode. Destination registers 1 and 30 share physical register 16, with destination register 1 occupying the lower 32 bits of physical register 16 and destination register 30 occupying the upper 32 bits. Destination registers 4 and 31 share physical register 10, with destination register 4 occupying the lower 32 bits of physical register 10 and destination register 31 occupying the upper 32 bits.

[0080] The technical solution of this invention divides a 64-bit physical register into independently accessible high 32-bit sub-registers and low 32-bit sub-registers. This enables a single physical register to be shared by two 32-bit instructions, avoiding the resource waste caused by 32-bit instructions occupying the entire 64-bit register and significantly improving physical register utilization. Adding a sharing identifier and a half-domain selection identifier to the renaming mapping table accurately distinguishes between independent and shared usage states and clarifies the location of sub-register usage, providing a reliable mapping basis for physical register sharing allocation and ensuring hardware logic implementation. Enabling shared register allocation mode when adjacent instructions are both 32-bit and the target architecture registers are different allows for safe triggering of sharing while simplifying hardware design, avoiding sharing conflicts and data errors, and improving resource allocation flexibility. Allocating the first 32-bit instruction to the low 32-bit sub-register and the next adjacent 32-bit instruction to the high 32-bit sub-register allows for the orderly and conflict-free sharing of the same physical register by two instructions, expanding the effective register capacity without increasing the number of registers. This invention adopts a mode that is compatible with both shared and individual allocation, which can improve resource utilization while being fully compatible with traditional 64-bit instruction execution. It is transparent to software, compilers and operating systems, and maintains processor architecture compatibility and scalability.

[0081] Example 3

[0082] Figure 3 This is a schematic diagram of a register allocation device provided in Embodiment 3 of the present invention. Figure 3 As shown, the device includes:

[0083] The identifier determination module 31 is used to obtain the operation instruction to be assigned and determine the operation width identifier of the operation instruction to be assigned.

[0084] The mode determination module 32 is used to determine the register allocation mode of the operation instruction to be allocated based on the operation width identifier and the register sharing condition. The register allocation mode includes a shared register allocation mode and a separate allocation mode.

[0085] The register allocation module 33 is used to allocate physical registers to the operation instruction to be allocated based on the register allocation mode, and generate an enhanced renaming table, in which each 64-bit physical register is divided into a high 32-bit sub-register and a low 32-bit sub-register.

[0086] The technical solution of this invention splits a single 64-bit physical register into two independent 32-bit sub-registers and enables their shared use. Based on the instruction width, it dynamically selects the shared register allocation mode or the independent allocation mode, which can avoid the space waste caused by using only 32 bits but occupying the entire 64-bit register. This significantly improves register utilization, reduces unnecessary 64-bit register access, and reduces dynamic power consumption.

[0087] Furthermore, the pattern determination module 32 is specifically used for:

[0088] Determine whether the operation width identifiers of adjacent pending operation instructions are both 32 bits and whether the target architecture registers of adjacent pending operation instructions are different.

[0089] If so, the register sharing condition is met, and the register allocation mode of the adjacent instruction to be allocated is determined to be the shared register allocation mode.

[0090] If not, the register sharing condition is not met, and the instruction to be allocated is determined to be in individual allocation mode.

[0091] Furthermore, the register allocation module 33 includes:

[0092] The first determining unit is used to allocate the first operation instruction to the lower 32-bit sub-register of the first target physical register in the idle state for two adjacent operation instructions to be allocated in the shared register allocation mode.

[0093] The second determining unit is used to allocate the next operation instruction to be allocated to the high 32-bit sub-register of the first target physical register.

[0094] The third determining unit is used to independently allocate the registers of the separate allocation mode to the second target physical register in the idle state;

[0095] The fourth determining unit is used to generate an enhanced renaming table based on the destination register number, the allocated physical register number, and the sub-register in each of the operation instructions to be allocated.

[0096] Specifically, the fourth determining unit is used for:

[0097] The architecture register number is determined based on the destination register number in each of the operation instructions to be allocated;

[0098] Determine the half-domain selection flag based on the allocated sub-register;

[0099] Determine the shared identifier based on the register allocation mode;

[0100] The enhanced renaming table is determined based on the architecture register number, the physical register number, the half-domain selection identifier, and the shared identifier.

[0101] Optionally, the device further includes:

[0102] The state modification module is used to modify the state of the physical register state machine of the physical register to be modified after the physical register is allocated based on the register allocation mode and an enhanced renaming table is generated. The state includes an occupied state, an idle state, and a waiting-for-the-other-half-release state.

[0103] Furthermore, the state modification module is specifically used for:

[0104] Modify the state of the physical register state machine that needs to be modified, including:

[0105] When the physical register to be modified is shared by two operation instructions and one of the sub-registers is released, the state of the physical register state machine of the physical register to be modified is changed to the waiting for the other half to be released state;

[0106] When the physical register to be modified is shared by two operation instructions and both sub-registers are released, the state of the physical register state machine of the physical register to be modified is changed to the idle state;

[0107] When the physical register to be modified is fully occupied by 64 bits and then released, the state of the physical register state machine of the physical register to be modified is changed to the idle state.

[0108] When the physical register to be modified is occupied, the state of the physical register state machine of the physical register to be modified is changed to the occupied state.

[0109] The register allocation apparatus provided in the embodiments of the present invention can execute the register allocation method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the execution method.

[0110] Example 4

[0111] Figure 4 A schematic diagram of an electronic device 40 that can be used to implement embodiments of the present invention is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices (e.g., helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein.

[0112] like Figure 4As shown, the electronic device 40 includes at least one processor 41 and a memory, such as a read-only memory (ROM) 42 and a random access memory (RAM) 43, communicatively connected to the at least one processor 41. The memory stores computer programs executable by the at least one processor. The processor 41 can perform various appropriate actions and processes based on the computer program stored in the ROM 42 or loaded from storage unit 48 into the RAM 43. The RAM 43 can also store various programs and data required for the operation of the electronic device 40. The processor 41, ROM 42, and RAM 43 are interconnected via a bus 44. An input / output (I / O) interface 45 is also connected to the bus 44.

[0113] Multiple components in electronic device 40 are connected to I / O interface 45, including: input unit 46, such as keyboard, mouse, etc.; output unit 47, such as various types of monitors, speakers, etc.; storage unit 48, such as disk, optical disk, etc.; and communication unit 49, such as network card, modem, wireless transceiver, etc. Communication unit 49 allows electronic device 40 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0114] Processor 41 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processor 41 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. Processor 41 performs the various methods and processes described above, such as register allocation methods.

[0115] In some embodiments, the register allocation method may be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 48. In some embodiments, part or all of the computer program may be loaded and / or installed on electronic device 40 via ROM 42 and / or communication unit 49. When the computer program is loaded into RAM 43 and executed by processor 41, one or more steps of the register allocation method described above may be performed. Alternatively, in other embodiments, processor 41 may be configured to execute the register allocation method by any other suitable means (e.g., by means of firmware).

[0116] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0117] Computer programs used to implement the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the processor, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be performed. The computer programs may be executed entirely on a machine, partially on a machine, or as a standalone software package, partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0118] In the context of this invention, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination thereof. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0119] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0120] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or middleware components (e.g., application servers), or frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0121] A computing system can include clients and servers. Clients and servers are generally located far apart and typically interact through communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a hosting product within the cloud computing service system to address the shortcomings of traditional physical hosts and VPS services, such as high management difficulty and weak business scalability.

[0122] In one embodiment, the present invention further includes a computer program product, which includes a computer program that, when executed by a processor, implements the register allocation method of any embodiment of the present invention.

[0123] In implementing the computer program product, computer program code for performing the operations of this invention can be written in one or more programming languages ​​or a combination thereof. Programming languages ​​include object-oriented programming languages ​​such as Java, Smalltalk, and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0124] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0125] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A register allocation method, characterized in that, include: Obtain the operation instruction to be assigned, and determine the operation width identifier of the operation instruction to be assigned; Based on the operation width identifier and register sharing conditions, the register allocation mode of the operation instruction to be allocated is determined. The register allocation mode includes a shared register allocation mode and a separate allocation mode. Based on the register allocation mode, the physical registers of the operation instructions to be allocated are allocated, and an enhanced renaming table is generated. Each 64-bit physical register is divided into a high 32-bit sub-register and a low 32-bit sub-register.

2. The method according to claim 1, characterized in that, The step of determining the register allocation mode of the operation instruction to be allocated based on the operation width identifier and register sharing conditions includes: Determine whether the operation width identifiers of adjacent pending operation instructions are both 32 bits and whether the target architecture registers of adjacent pending operation instructions are different. If so, the register sharing condition is met, and the register allocation mode of the adjacent instruction to be allocated is determined to be the shared register allocation mode. If not, the register sharing condition is not met, and the instruction to be allocated is determined to be in individual allocation mode.

3. The method according to claim 1, characterized in that, The step of physically allocating physical registers for the operation instruction to be allocated based on the register allocation mode and generating an enhanced renaming table includes: For two adjacent unallocated operation instructions in the shared register allocation mode, the first unallocated operation instruction is allocated to the lower 32 bits of the lower sub-register of the first target physical register in the idle state; The next instruction to be allocated is assigned to the high 32 bits of the sub-register of the first target physical register; The registers in the separate allocation mode are independently allocated to the second target physical registers in the idle state; An enhanced renaming table is generated based on the destination register number, the allocated physical register number, and the sub-registers in each of the operation instructions to be allocated.

4. The method according to claim 3, characterized in that, The step of generating an enhanced renaming table based on the destination register number, the allocated physical register number, and the sub-registers in each of the operation instructions to be allocated includes: The architecture register number is determined based on the destination register number in each of the operation instructions to be allocated; Determine the half-domain selection flag based on the allocated sub-register; Determine the shared identifier based on the register allocation mode; The enhanced renaming table is determined based on the architecture register number, the physical register number, the half-domain selection identifier, and the shared identifier.

5. The method according to claim 1, characterized in that, After performing physical register allocation on the instruction to be allocated based on the register allocation mode and generating an enhanced renaming table, the method further includes: The state of the physical register state machine to be modified is modified, including the occupied state, the idle state, and the waiting-for-the-other-half-release state.

6. The method according to claim 5, characterized in that, Modifying the state of the physical register state machine to be modified includes: When the physical register to be modified is shared by two operation instructions and one of the sub-registers is released, the state of the physical register state machine of the physical register to be modified is changed to the waiting for the other half to be released state; When the physical register to be modified is shared by two operation instructions and both sub-registers are released, the state of the physical register state machine of the physical register to be modified is changed to the idle state; When the physical register to be modified is released from a 64-bit fully occupied state, the state of the physical register state machine of the physical register to be modified is changed to an idle state. When the physical register to be modified is occupied, the state of the physical register state machine of the physical register to be modified is changed to the occupied state.

7. A register allocation device, characterized in that, include: The identifier determination module is used to acquire the operation instruction to be assigned and determine the operation width identifier of the operation instruction to be assigned. The mode determination module is used to determine the register allocation mode of the operation instruction to be allocated based on the operation width identifier and the register sharing condition. The register allocation mode includes a shared register allocation mode and a separate allocation mode. The register allocation module is used to allocate physical registers to the operation instructions to be allocated based on the register allocation mode, and generate an enhanced renaming table, in which each 64-bit physical register is divided into a high 32-bit sub-register and a low 32-bit sub-register.

8. An electronic device, characterized in that, The electronic device includes: At least one processor; and A memory communicatively connected to the at least one processor; wherein, The memory stores a computer program that can be executed by the at least one processor, the computer program being executed by the at least one processor to enable the at least one processor to perform the register allocation method according to any one of claims 1-6.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that cause a processor to execute the register allocation method according to any one of claims 1-6.

10. A computer program product, characterized in that, The computer program product includes a computer program that, when executed by a processor, implements the register allocation method according to any one of claims 1-6.

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