A three-level full-bridge dual active bridge converter and neutral point potential balance control method

Abstract

The application discloses a three-level full-bridge dual active bridge converter and a midpoint potential balance control method. The converter comprises a high-frequency transformer, a DC input voltage source is arranged on the primary side of the high-frequency transformer, and series-connected upper and lower capacitors are connected between the positive and negative electrodes of the DC input voltage source. Three-level half-bridge A and three-level half-bridge B are connected in parallel, a node between the upper and lower capacitors is connected to the midpoint of two clamping diodes of the two three-level half-bridges, the center point of the three-level half-bridge A is connected to one end of the primary side of the high-frequency transformer through a power transmission inductor, and the center point of the three-level half-bridge A is connected to the other end of the primary side of the high-frequency transformer through a DC isolation capacitor. In the control method, the primary side power device is divided into a fixed 50% duty ratio basic bridge arm and a non-symmetrical duty ratio adjusting bridge arm, a PI voltage balance loop is constructed by taking the voltage difference of the two capacitors as feedback, the duty ratio of the adjusting bridge arm is dynamically adjusted, the average value of the midpoint current is changed, and the midpoint potential balance is realized.

Description

Technical Field

[0001] This invention relates to the field of power electronic converter control technology, specifically to a three-level full-bridge dual active bridge converter and a midpoint potential balance control method. Background Technology

[0002] Dual Active Bridge (DAB) converters are widely used in new energy power generation, energy storage systems, electric vehicle charging, and DC distribution networks due to their advantages such as electrical isolation, bidirectional power transmission, wide soft-switching range, and high power density. With the continuous evolution of medium- and high-voltage, high-power application scenarios, traditional two-level DAB converters suffer from problems such as high voltage stress on power devices and severe electromagnetic interference. Three-level DAB converters, by connecting power devices in series, can reduce the voltage stress on each power device to half of the DC bus voltage, thereby improving the converter's voltage and power ratings.

[0003] Three-level DAB converters suffer from midpoint potential offset, which hinders their reliable operation. In actual operation, the two capacitors connected in series on the DC side can experience voltage imbalance due to inconsistencies in power device characteristics, dead time, and load fluctuations. This can lead to voltage stress exceeding the rated value for some power devices, resulting in output waveform distortion, decreased converter efficiency, and even damage to the power devices. Therefore, a midpoint potential balancing control method for three-level DAB converters is needed that features simple control logic, requires no additional hardware, decouples voltage equalization and power control, and has a fast response time. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to overcome the shortcomings of the prior art and achieve fast and accurate midpoint potential balance in the midpoint potential balance control process of a three-level dual active bridge converter without additional hardware circuits, by simply adjusting the drive logic, and completely decoupled from power control.

[0005] To solve the above-mentioned technical problems, the present invention adopts the following technical solution:

[0006] A three-level full-bridge dual active bridge converter includes a high-frequency transformer T, and a DC input voltage source V_dc is included on the primary side of the high-frequency transformer T. An upper capacitor C1 and a lower capacitor C2 connected in series are connected between the positive and negative terminals of the DC input voltage source V_dc.

[0007] Three-level half-bridge A and three-level half-bridge B are connected in parallel. The node between the upper capacitor C1 and the lower capacitor C2 is connected to the midpoint of the two clamping diodes of the two three-level half-bridges. The center point of three-level half-bridge A is connected to one end of the primary side of the high-frequency transformer T through the power transfer inductor Lr. The center point of three-level half-bridge A is connected to the other end of the primary side of the high-frequency transformer T through the DC blocking capacitor Cr1.

[0008] The three-level half-bridge A includes power device S1, power device S2, power device S3, and power device S4 connected in series. The node between power device S1 and power device S2 is connected to the negative terminal of clamping diode D1 and the negative terminal of clamping diode D2 in sequence, and then connected to the node between power device S3 and power device S4.

[0009] The three-level half-bridge B includes power devices S5, S6, S7, and S8 connected in series. The node between power devices S5 and S6 is connected to the negative terminals of clamping diodes D3 and D4 in sequence, and then connected to the node between power devices S7 and S8.

[0010] The aforementioned three-level full-bridge dual active bridge converter includes, on the secondary side of the high-frequency transformer T, a first power device group and a second power device group connected in parallel. The first power device group includes power device Q1 and power device Q2 connected in series, and the second power device group includes power device Q3 and power device Q4 connected in series. The output capacitor C3 is connected in parallel with the first and second power device groups. The node between power device Q1 and power device Q2 is connected to one end of the secondary side of the high-frequency transformer T, and the node between power device Q3 and power device Q4 is connected to the other end of the secondary side of the high-frequency transformer T through DC blocking capacitor Cr2. The two ends of the output capacitor C3 are the output voltage terminals.

[0011] In the aforementioned three-level full-bridge dual active bridge converter, all power devices are semiconductor power devices (MOSFETs).

[0012] In the aforementioned three-level full-bridge dual active bridge converter, the turns ratio of the high-frequency isolation transformer is N:1.

[0013] A method for controlling the midpoint potential balance of a three-level full-bridge dual active bridge converter includes:

[0014] Step 1: Set the driving logic for each power device and define the phase shift angle. = The phase angle difference between the initial phase angles of the two pulse signals from power device j and power device k. , These are the phase angles of the driving pulses k and j of the power device, respectively;

[0015] Step 2, construct the midpoint potential equalization control loop, including: collecting the voltage V1 of the upper capacitor C1 and the voltage V2 of the lower capacitor C2, and calculating the voltage difference ΔV=V1-V2; using ΔV as the feedback quantity and 0 as the given value, output the duty cycle adjustment quantity d through the PI regulator;

[0016] Step 3, construct the output power control loop, including: acquiring the output DC voltage Vo, using the rated output voltage Vref as the setpoint, and outputting the primary and secondary side phase shift angles through a PI regulator. That is, the phase angle difference between power device Q1 and power device S1;

[0017] Step 4, based on the driving logic of Step 1, the duty cycle d of Step 2, and the outward phase shift angle of Step 3. It generates 12 power device drive signals to control the on and off states of the primary three-level bridge arm and the secondary two-level bridge arm.

[0018] In step 1, the driving logic for each power device includes: power device S1 and power device S4 are complementaryly connected, power device S5 and power device S8 are complementaryly connected, power device S2 and power device S3 are complementaryly connected, and power device S6 and power device S7 are complementaryly connected. Under normal operating conditions, the duty cycle of all power devices is 0.5. Under the midpoint potential balance control mode, the duty cycle of power device S1 is defined as d, then the duty cycle of power device S4 is 1-d, the duty cycle of power device S5 is d, and the duty cycle of power device S8 is 1-d.

[0019] In step 1, the phase angle of the drive pulse of power device S1 , Compared to the shift of power device j and power device k, 1-d; The shift ratio is equal to the duty cycle d for power devices S1 and S5.

[0020] In step 1, the outer phase angle is shifted. =(Time difference Δt between the two device drive signals / Time t of one cycle) * 2π.

[0021] The beneficial effects achieved by this invention are as follows: The control method of this invention requires no additional hardware costs. It achieves midpoint potential balance simply by adjusting the driving duty cycle of the primary-side power devices, without adding any additional voltage equalization circuits. The system structure is simple and highly reliable. The power devices are divided into a base bridge arm with a fixed duty cycle and an adjustable bridge arm with an adjustable duty cycle. Voltage equalization control can be achieved through a single variable 'd', resulting in simple and clear control logic that is easy to implement in engineering. Voltage equalization and power control are completely decoupled. Voltage equalization control is achieved by changing the duration of the zero-level mode, without affecting the transformer's volt-second product. The output power can still be independently controlled by shifting the phase angle, and the two control loops do not interfere with each other. Simulation results also show that this invention can converge the capacitor voltage difference to within 1V, with steady-state voltage fluctuations of less than 0.5V. It exhibits excellent dynamic and steady-state performance, fast response speed, and high steady-state accuracy.

[0022] The three-level full-bridge dual active bridge converter of this invention replaces each arm of the traditional two-level full-bridge with a three-level half-bridge structure, which can significantly reduce the voltage stress on the switching transistors. Each transistor only bears half of the bus voltage, thereby allowing the use of power devices with lower on-resistance and reducing conduction losses. At the same time, due to the increase in the number of output levels, the waveform of the transformer primary voltage is closer to a sine wave, and the harmonic content is reduced. This not only reduces the core losses of the transformer and inductor, but also increases the degree of control freedom, enabling the converter to maintain high efficiency over a wide input voltage and load range. It is suitable for medium and high voltage DC buses and high-power bidirectional transmission scenarios. Compared with the two-level scheme, it has higher power density and thermal balance at the same power, and achieves a comprehensive performance improvement of high efficiency, high reliability, and wide soft-switching range. Attached Figure Description

[0023] To more clearly illustrate the technical solutions and advantages of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below.

[0024] Figure 1 This is a circuit diagram of a three-level full-bridge dual active bridge converter as described in Embodiment 1 of the present invention;

[0025] Figure 2 This is a schematic diagram of the switching states allowed to be used in a single three-level half-bridge circuit on the primary side of the converter in Embodiment 1 of the present invention;

[0026] Figure 3 This is a waveform diagram of the primary-side output voltage of the three-level dual active bridge converter in Embodiment 1 of the present invention;

[0027] Figure 4 This is a schematic diagram of the midpoint potential balance control principle of the three-level dual active bridge converter in Embodiment 1 of the present invention;

[0028] Figure 5 This is a waveform diagram of the capacitor voltage when the midpoint potential balance algorithm is applied in Embodiment 1 of the present invention;

[0029] Figure 6 This is a schematic diagram of the driving signals for the primary and secondary power devices in Embodiment 1 of the present invention. Detailed Implementation

[0030] Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0031] Example 1

[0032] like Figure 1 As shown, this embodiment provides a three-level full-bridge dual active bridge converter, including: a high-frequency transformer T, a DC input voltage source V_dc on the primary side of the high-frequency transformer T, and an upper capacitor C1 and a lower capacitor C2 connected in series between the positive and negative terminals of the DC input voltage source V_dc.

[0033] Three-level half-bridge A and three-level half-bridge B are connected in parallel. The node between the upper capacitor C1 and the lower capacitor C2 is connected to the midpoint of the two clamping diodes of the two three-level half-bridges. The center point of three-level half-bridge A is connected to one end of the primary side of the high-frequency transformer T through the power transfer inductor Lr. The center point of three-level half-bridge A is connected to the other end of the primary side of the high-frequency transformer T through the DC blocking capacitor Cr1.

[0034] The three-level half-bridge A includes power device S1, power device S2, power device S3, and power device S4 connected in series. The node between power device S1 and power device S2 is connected to the negative terminal of clamping diode D1 and the negative terminal of clamping diode D2 in sequence, and then connected to the node between power device S3 and power device S4.

[0035] The three-level half-bridge B includes power devices S5, S6, S7, and S8 connected in series. The node between power devices S5 and S6 is connected to the negative terminal of clamping diode D3 and the negative terminal of clamping diode D4 in sequence, and then connected to the node between power devices S7 and S8.

[0036] On the secondary side of the high-frequency transformer T, there are a first power device group and a second power device group connected in parallel. The first power device group includes power device Q1 and power device Q2 connected in series. Power device Q1 and power device Q2 are both semiconductor power devices (MOSFETs), and clamping diode D1 is a diode, which is a passive device. The second power device group includes power device Q3 and power device Q4 connected in series. The output capacitor C3 is connected in parallel with the first power device group and the second power device group. The node between power device Q1 and power device Q2 is connected to one end of the secondary side of the high-frequency transformer T, and the node between power device Q3 and power device Q4 is connected to the other end of the secondary side of the high-frequency transformer T through DC blocking capacitor Cr2. The two ends of the output capacitor C3 are the output voltage terminals.

[0037] A high-frequency isolation transformer T is used to achieve electrical isolation and voltage conversion at both ends. The turns ratio of the high-frequency isolation transformer is N:1. The power transmission inductor Lr is usually integrated with the leakage inductance of the high-frequency transformer. DC blocking capacitors Cr1 and Cr2 are used to suppress DC bias in the high-frequency transformer.

[0038] Figure 2 The schematic diagram shows the allowed switching states of a single three-level half-bridge circuit on the primary side. Figure 2 In the diagram, (a) indicates that power devices S1 and S2 are turned on, while power devices S3 and S4 are turned off, and the bridge arm output potential U is... AO For U dc / 2, define the switch state as P; in Figure 2 In (b), power devices S1 and S2 are turned off, while power devices S3 and S4 are turned on, resulting in a bridge arm output potential U. AO For -U dc / 2, define the switch state as N; in Figure 2 In (c), power device 1 S1 and power device 4 S4 are turned off, power device 2 S2 and power device 3 S3 are turned on, the bridge arm output potential UAO is 0, and the state of this switch is defined as O.

[0039] Figure 3 The waveform of the primary-side output voltage of a three-level dual active bridge converter is shown in Figure U. AO U BO The voltage levels of the two half-bridge outputs include the switching states P, N, and O; U AB This is the primary-side full-bridge output voltage, with a total of 5 level states, namely U dc U dc / 2 , 0, -U dc / 2 -U dc Voltage U ABIt acts on the primary winding of the high-frequency isolation transformer.

[0040] The control principle of this invention is as follows: by using the asymmetric duty cycle modulation of the primary side three-level bridge arm, the average value of the midpoint current within one cycle is changed by adjusting the conduction time of power device S1 and power device S5, thereby achieving voltage balance between the upper capacitor C1 and the lower capacitor C2; at the same time, the power transmission is controlled by shifting the phase angle of the primary and secondary sides to achieve constant output voltage.

[0041] Figure 4 This is a schematic diagram of the midpoint potential balance control principle of a three-level dual active bridge converter. It employs a dual-loop coordinated control method, combining output voltage closed-loop and midpoint potential balance closed-loop control. Two independent PI regulators respectively achieve output voltage regulation and midpoint potential balance control of the DC-side upper and lower voltage divider capacitors. The outer loop of the output voltage works by: setting the output voltage reference value V... ref The difference between the real-time sampled output voltage Vo and the error signal is fed into the PI controller to generate the phase shift angle φ of the primary and secondary bridge arms, which is then processed by D. S1Q1 =φ / 2π completes the parameter conversion from phase shift angle to equivalent phase shift ratio. Stable closed-loop control of the DAB converter output voltage is achieved by adjusting the phase shift angle of the primary and secondary sides. The working principle of the midpoint potential balance control loop is as follows: First, the upper and lower capacitor voltages V1 and V2 of the DC bus are collected, and the voltage deviation e = V1−V2 is calculated. With zero deviation e... ref =0 is used as the given reference for potential balance. The deviation e is sent to another PI regulator to obtain the variable duty cycle coefficient d. Combined with the duty cycle allocation rules of each power device, the pulse duty cycle of the corresponding switching device of the primary side three-level bridge arm is dynamically fine-tuned to accurately compensate for the midpoint charge imbalance. The shift ratio and duty cycle command output from the two control branches are sent to the PWM pulse generation module together, and finally output the drive pulses of all power transistors S1~S8 and Q1~Q4. Under the premise of not disturbing the steady-state accuracy of the converter output voltage, the DC side midpoint potential drift is dynamically suppressed, realizing the integrated control of output voltage regulation and midpoint potential balance of the three-level full-bridge DAB.

[0042] The midpoint potential balance control method for the three-level full-bridge dual active bridge converter in this embodiment includes the following steps:

[0043] Step 1: Set the driving logic for each power device, including: Power device 1 S1 and power device 4 S4 are complementary in conduction, power device 5 S5 and power device 8 S8 are complementary in conduction, power device 2 S2 and power device 3 S3 are complementary in conduction, and power device 6 S6 and power device 7 S7 are complementary in conduction. Under normal operation, the duty cycle of all power devices is 0.5. Under the midpoint potential balance control mode, the duty cycle of power device 1 S1 is defined as d, then the duty cycle of power device 4 S4 is 1-d, the duty cycle of power device 5 S5 is d, and the duty cycle of power device 8 S8 is 1-d.

[0044] Define phase shift angle = The phase angle difference between the initial phase angles of the two pulse signals from power devices j and k is given by the phase angle of the driving pulse from power device S1. , Compared to the shift of power device j and power device k, 1-d; , These are the phase angles of the driving pulses k and j of the power device, respectively; The shift ratio of power device S1 and power device S5 can be represented numerically by the duty cycle d.

[0045] Outward phase angle =(Time difference Δt between the two device drive signals / Time t of one cycle) * 2π.

[0046] Step 2, construct the midpoint potential equalization control loop, including: collecting the voltage V1 of the upper capacitor C1 and the voltage V2 of the lower capacitor C2, and calculating the voltage difference ΔV=V1-V2; using ΔV as the feedback quantity and 0 as the given value, output the duty cycle adjustment quantity d through the PI regulator;

[0047] Step 3, construct the output power control loop, including: acquiring the output DC voltage Vo, using the rated output voltage Vref as the setpoint, and outputting the primary and secondary side phase shift angles through a PI regulator. That is, the phase angle difference between power device Q1 and power device S1;

[0048] Step 4, based on the driving logic of Step 1, the duty cycle d of Step 2, and the outward phase shift angle of Step 3. It generates 12 power device drive signals to control the on and off states of the primary three-level bridge arm and the secondary two-level bridge arm.

[0049] Figure 5 The image shows the capacitor voltage waveform when the midpoint potential balancing algorithm of this invention is applied. At the initial moment, there is an error in the series capacitor voltage. After the balancing algorithm is applied, the capacitor voltage difference converges rapidly, thus proving the effectiveness of the proposed algorithm.

[0050] Figure 6 This diagram illustrates the drive signals for the primary and secondary power devices. The primary side consists of a base bridge arm switch and an adjusting bridge arm switch. The duty cycle of the drive signal for the base bridge arm switch is always 0.5, while the duty cycle d of the drive signal for the adjusting bridge arm switch can be dynamically adjusted. A reference signal for the change in duty cycle d is provided by the midpoint potential balance control loop. The duty cycle of the drive signal for the secondary power devices is also fixed at 0.5, but its phase difference with the primary drive signal can be dynamically adjusted. A reference signal for the change in phase shift D is provided by the power control loop.

[0051] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0052] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0053] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0054] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A three-level full-bridge dual active bridge converter, characterized in that, The system includes a high-frequency transformer T, and on the primary side of the high-frequency transformer T, there is a DC input voltage source V_dc. The upper capacitor C1 and the lower capacitor C2, which are connected in series, are connected between the positive and negative terminals of the DC input voltage source V_dc. Three-level half-bridge A and three-level half-bridge B are connected in parallel. The node between the upper capacitor C1 and the lower capacitor C2 is connected to the midpoint of the two clamping diodes of the two three-level half-bridges. The center point of three-level half-bridge A is connected to one end of the primary side of the high-frequency transformer T through the power transfer inductor Lr. The center point of three-level half-bridge A is connected to the other end of the primary side of the high-frequency transformer T through the DC blocking capacitor Cr1. The three-level half-bridge A includes power device S1, power device S2, power device S3, and power device S4 connected in series. The node between power device S1 and power device S2 is connected to the negative terminal of clamping diode D1 and the negative terminal of clamping diode D2 in sequence, and then connected to the node between power device S3 and power device S4. The three-level half-bridge B includes power devices S5, S6, S7, and S8 connected in series. The node between power devices S5 and S6 is connected to the negative terminals of clamping diodes D3 and D4 in sequence, and then connected to the node between power devices S7 and S8.

2. A three-level full-bridge dual active bridge converter according to claim 1, characterized in that, On the secondary side of the high-frequency transformer T, there are a first power device group and a second power device group connected in parallel. The first power device group includes power device Q1 and power device Q2 connected in series, and the second power device group includes power device Q3 and power device Q4 connected in series. The output capacitor C3 is connected in parallel with the first power device group and the second power device group. The node between power device Q1 and power device Q2 is connected to one end of the secondary side of the high-frequency transformer T, and the node between power device Q3 and power device Q4 is connected to the other end of the secondary side of the high-frequency transformer T through DC blocking capacitor Cr2. The two ends of the output capacitor C3 are the output voltage terminals.

3. A three-level full-bridge dual active bridge converter according to claim 1, characterized in that, All power devices use semiconductor power devices (MOSFETs).

4. A three-level full-bridge dual active bridge converter according to claim 1, characterized in that, The turns ratio of the high-frequency isolation transformer is N:

1.

5. A method for controlling the midpoint potential balance of a three-level full-bridge dual active bridge converter, characterized in that, include: Step 1: Set the driving logic for each power device and define the phase shift angle. = The phase angle difference is the initial phase angle between the two pulse signals of power device j and power device k. , These are the phase angles of the driving pulses k and j of the power device, respectively; Step 2, construct the midpoint potential equalization control loop, including: collecting the voltage V1 of the upper capacitor C1 and the voltage V2 of the lower capacitor C2, and calculating the voltage difference ΔV=V1-V2; using ΔV as the feedback quantity and 0 as the given value, output the duty cycle adjustment quantity d through the PI regulator; Step 3, construct the output power control loop, including: acquiring the output DC voltage Vo, using the rated output voltage Vref as the setpoint, and outputting the primary and secondary side phase shift angles through a PI regulator. That is, the phase angle difference between power device Q1 and power device S1; Step 4, based on the driving logic of Step 1, the duty cycle d of Step 2, and the outward phase shift angle of Step 3. It generates 12 power device drive signals to control the on and off states of the primary three-level bridge arm and the secondary two-level bridge arm.

6. The method for midpoint potential balance control of a three-level full-bridge dual active bridge converter according to claim 5, characterized in that, In step 1, the driving logic for each power device includes: power device S1 and power device S4 are complementaryly connected, power device S5 and power device S8 are complementaryly connected, power device S2 and power device S3 are complementaryly connected, and power device S6 and power device S7 are complementaryly connected. Under normal operating conditions, the duty cycle of all power devices is 0.

5. Under the midpoint potential balance control mode, the duty cycle of power device S1 is defined as d, then the duty cycle of power device S4 is 1-d, the duty cycle of power device S5 is d, and the duty cycle of power device S8 is 1-d.

7. The method for midpoint potential balance control of a three-level full-bridge dual active bridge converter according to claim 5, characterized in that, In step 1, the phase angle of the driving pulse of power device S1 , Compared to the shift of power device j and power device k, 1-d; The shift ratio is equal to the duty cycle d for power devices S1 and S5.

8. The method for controlling the midpoint potential balance of a three-level full-bridge dual active bridge converter according to claim 5, characterized in that, In step 1, the outer phase angle is shifted. =(Time difference Δt between the two device drive signals / Time t of one cycle) * 2π.

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