One-way anti-overlap control circuit and method based on capacitor splitting architecture

Abstract

The application discloses a one-way anti-overlapping control circuit and method based on a capacitor splitting architecture, which comprises a differential positive-end capacitor type digital-to-analog converter, a differential negative-end capacitor type digital-to-analog converter, a comparator and a successive approximation control logic circuit; the differential positive-end capacitor type digital-to-analog converter is connected with the positive input end of the comparator, the differential negative-end capacitor type digital-to-analog converter is connected with the negative input end of the comparator, and the output end of the comparator is connected with the successive approximation control logic circuit; the differential positive-end capacitor type digital-to-analog converter and the differential negative-end capacitor type digital-to-analog converter each comprise a first split capacitor array and a second split capacitor array; the successive approximation control logic circuit controls the one-way switching of the bottom plate of the first split capacitor array from a reference voltage to a reference ground voltage and the one-way switching of the bottom plate of the second split capacitor array from the reference ground voltage to the reference voltage by adjusting an input voltage. The application controls the switching of the two groups of capacitor arrays, avoids electric leakage, and improves the sampling rate and conversion precision.

Description

Technical Field

[0001] This invention relates to the field of analog integrated circuit design and manufacturing, and in particular to a unidirectional anti-overlap control circuit and method based on a capacitor splitting architecture. Background Technology

[0002] In high-speed, high-precision SAR ADC (Successive Approximation Analog-to-Digital Converter) designs, capacitor splitting switching technology based on common-mode voltage (VCM) is commonly used to reduce overall system power consumption and save chip area. This technique splits the capacitor arrays at both ends of the fully differential capacitor ADC into two independent sub-capacitor arrays. One sub-capacitor array is pre-charged to the reference voltage, and the other is pre-charged to the reference ground voltage. This eliminates the need for an additional common-mode voltage buffer, enabling high-precision quantization.

[0003] Conventional successive approximation analog-to-digital converters employ general anti-overlap logic circuits with a break-before-turn mechanism to prevent shoot-through leakage caused by momentary conduction between the reference voltage path and the reference ground path during multiplexer switching. However, traditional anti-overlap logic is designed for bidirectional symmetrical capacitor switching scenarios, and its internal dead time is uniformly fixed.

[0004] However, in the capacitor splitting architecture of common-mode voltage, the quantization conversion stage is unidirectional. That is, the bottom plate of one capacitor subarray only switches from the reference voltage to the reference ground voltage in a unidirectional downward direction, and the bottom plate of another capacitor subarray only switches from the reference ground voltage to the reference voltage in a unidirectional upward direction. There is no bidirectional back-and-forth switching between the two sets of sub-capacitor arrays.

[0005] In advanced manufacturing processes, there is an inherent asymmetry in the turn-on and turn-off propagation delays of PMOS and NMOS transistors. If the traditional bidirectional symmetrical anti-overlap logic is directly used in this unidirectional switching architecture, an excessively long redundant dead time is required to be compatible with worst-case process, voltage, and temperature conditions.

[0006] Excessively long fixed redundancy dead zones consume a significant amount of capacitor charge settling time, compress the quantization operation window, and directly limit further improvements in the analog-to-digital converter's sampling rate. Simultaneously, due to the asymmetric characteristics of transistor switching speeds, uniform dead zone parameters cannot match the differentiated switching timing requirements of the two subarrays. Under extreme conditions, residual shoot-through leakage current still exists due to the mismatch in switching action timing. Leakage losses increase the circuit's static power consumption, disturb the capacitor plate charge balance, introduce quantization errors, and reduce the conversion accuracy of the analog-to-digital converter. Summary of the Invention

[0007] The purpose of this invention is to provide a unidirectional anti-overlap control circuit and method based on a capacitor splitting architecture, which solves the technical problems existing in the current capacitor splitting successive approximation analog-to-digital converter, such as dead time redundancy, easy shoot-through leakage during switching, and limited sampling rate improvement.

[0008] To solve the above-mentioned technical problems, on the one hand, the present invention provides a unidirectional anti-overlap control circuit based on a capacitor splitting architecture, including a differential positive terminal capacitor-type digital-to-analog converter, a differential negative terminal capacitor-type digital-to-analog converter, a comparator, and a successive approximation control logic circuit; The differential positive-terminal capacitive digital-to-analog converter is connected to the positive input terminal of the comparator, the differential negative-terminal capacitive digital-to-analog converter is connected to the negative input terminal of the comparator, and the output terminal of the comparator is connected to the successive approximation control logic circuit. Both the differential positive-terminal capacitive digital-to-analog converter and the differential negative-terminal capacitive digital-to-analog converter include a first adjustment unit and a second adjustment unit. The first adjustment unit includes a first split capacitor array, and the second adjustment unit includes a second split capacitor array. The successive approximation control logic circuit controls the unidirectional switching of the bottom plate of the first split capacitor array from the reference voltage to the reference ground voltage, and the unidirectional switching of the bottom plate of the second split capacitor array from the reference ground voltage to the reference voltage, by adjusting the input voltages of the first split capacitor array and the second split capacitor array.

[0009] Furthermore, both the first adjustment unit and the second adjustment unit further include multiple multiplexers; Both the first split capacitor array and the second split capacitor array include multiple binary weighted capacitors, and the multiple multiplexers include multiple 3-to-1 multiplexers; each binary weighted capacitor is connected to each of the 3-to-1 multiplexers in a one-to-one correspondence.

[0010] Furthermore, the first input terminal of the three-to-one selector is connected to the reference voltage, the second input terminal is connected to the input signal, the third input terminal is connected to the reference ground voltage, and the output terminal is connected to the bottom plate of the binary weighted capacitor. The top plate of the binary weighted capacitor is connected to the positive input terminal of the comparator.

[0011] Furthermore, the differential negative-terminal capacitive digital-to-analog converter has the same structure as the differential positive-terminal capacitive digital-to-analog converter and is differentially symmetrically arranged; In the differential negative-terminal capacitive digital-to-analog converter, the top plate of the binary weighting capacitor is connected to the negative input terminal of the comparator.

[0012] Furthermore, the successive approximation control logic circuit includes a first control link and a second control link that are physically isolated from each other; The first control link is used to control the unidirectional switching of the bottom plate of the binary weighted capacitor in the first split capacitor array from the reference voltage to the reference ground voltage. The second control link is used to control the unidirectional switching of the bottom plate of the binary weighted capacitor in the second split capacitor array from the reference ground voltage to the reference voltage.

[0013] Furthermore, the first control link includes a first NAND gate, a first inverter, a second inverter, a second NAND gate, a third inverter, and a first NOR gate; The first input terminal of the first NAND gate is connected to the output signal of the comparator, the second input terminal is connected to the decision signal of the comparator, and the output terminal outputs the first intermediate node signal; The input terminal of the first inverter is connected to the first intermediate node signal, and the output terminal is connected to the input terminal of the second inverter. The output terminal of the second inverter outputs the first delay signal. The first input of the second NAND gate is connected to the clock signal, the second input is connected to the first intermediate node signal, the third input is connected to the first delay signal, and the output output is the first reference voltage control signal. The input terminal of the third inverter is connected to the clock signal; The first input terminal of the first NOR gate is connected to the first intermediate node signal, the second input terminal is connected to the first delay signal, the third input terminal is connected to the output terminal of the third inverter, and the output terminal outputs the first reference ground voltage control signal.

[0014] Furthermore, the second control link includes a fourth inverter, a second NOR gate, a fifth inverter, a sixth inverter, a third NOR gate, a third NAND gate, a seventh inverter, and a fourth NAND gate; The input terminal of the fourth inverter is connected to the output signal of the comparator; The first input terminal of the second NOR gate is connected to the decision signal of the comparator, the second input terminal is connected to the output terminal of the fourth inverter, and the output terminal outputs the second intermediate node signal. The input terminal of the fifth inverter is connected to the second intermediate node signal, and the output terminal is connected to the input terminal of the sixth inverter. The output terminal of the sixth inverter outputs a second delayed signal; The first input terminal of the third NOR gate is connected to the second intermediate node signal, and the second input terminal is connected to the second delay signal; The first input terminal of the third NAND gate is connected to the clock signal, and the second input terminal is connected to the output terminal of the third NOR gate. The input terminal of the seventh inverter is connected to the output terminal of the third NAND gate, and the output terminal outputs the second reference ground voltage control signal. The first input of the fourth NAND gate is connected to the clock signal, the second input is connected to the second intermediate node signal, the third input is connected to the second delay signal, and the output output is the second reference voltage control signal.

[0015] On the other hand, this application proposes a unidirectional anti-overlap control method based on a capacitor splitting architecture, including the following steps: Based on the phase signal, the comparator's output signal, and the comparator's decision signal, switching commands are sent to the first control link and the second control link, respectively. The first control link controls the voltage of the bottom plate in the first split capacitor array, switching it unidirectionally from the reference voltage to the reference ground voltage; The second control link controls the voltage of the bottom plate in the second split capacitor array, unidirectionally switching it from the reference ground voltage to the reference voltage.

[0016] Furthermore, the step of the first control link controlling the voltage of the bottom plate in the first split capacitor array to unidirectionally switch from the reference voltage to the reference ground voltage specifically includes: The first NAND gate performs logical operations on the output signal and the decision signal of the comparator to output the first intermediate node signal; The first intermediate node signal is delayed by a first inverter and a second inverter connected in series, and then output as a first delayed signal. When the first intermediate node signal undergoes a level transition, the second NAND gate immediately outputs a first reference voltage control signal based on the first intermediate node signal after the level transition, so as to control the reference voltage path of the multiplexer configured in the differential positive terminal capacitive digital-to-analog converter to be turned off. After the reference voltage path is turned off, and the first delayed signal completes its level flip, the first NOR gate performs logical operations based on the clock signal, the first intermediate node signal after the level jump, and the first delayed signal after the level flip, and outputs the first reference ground voltage control signal, which delays and turns on the reference ground voltage path of the multiplexer configured in the differential positive terminal capacitive digital-to-analog converter.

[0017] Furthermore, the step of controlling the voltage of the bottom plate in the second split capacitor array to unidirectionally switch from the reference ground voltage to the reference voltage via the second control link specifically includes: The second NOR gate performs a logical operation on the decision signal of the comparator and the inverted signal of the output signal of the comparator, and outputs the second intermediate node signal; The second intermediate node signal is delayed by a fifth inverter and a sixth inverter connected in series, and then output as a second delayed signal. When the second intermediate node signal undergoes a level transition, the third NOR gate and the third NAND gate immediately output the second reference ground voltage control signal based on the changed second intermediate node signal and the clock signal, so as to control the reference ground voltage path of the multiplexer configured in the differential negative terminal capacitive digital-to-analog converter to be turned off. After the reference ground voltage path is turned off, and after the fifth inverter and the sixth inverter complete the transmission delay, the fourth NAND gate performs logical operations based on the output clock signal, the second intermediate node signal after the level transition, and the second delay signal after the level flip, and outputs the second reference voltage control signal to delay and turn on the reference voltage path of the multiplexer configured in the differential negative terminal capacitive digital-to-analog converter.

[0018] Compared with the prior art, the present invention has at least the following beneficial effects: This invention manages the switching action of the bottom plate of the differential positive and differential negative capacitor-type digital-to-analog converters (DACs) separately through successive approximation control logic circuits. This ensures that the differential positive capacitor-type DAC performs only unidirectional switching from reference voltage to reference ground voltage, and the differential negative capacitor-type DAC performs only unidirectional switching from reference ground voltage to reference voltage. This precisely adapts to the fixed unidirectional switching characteristics of the two capacitor arrays under the capacitor split architecture, without requiring compatibility with the unified timing constraints of bidirectional switching scenarios. The dead time can be optimized separately for each switching direction, eliminating the redundant timing introduced by traditional bidirectional anti-overlap logic, effectively extending the capacitor charge establishment window, and significantly improving the sampling rate of the DAC. At the same time, unidirectional independent control can accurately achieve the timing coordination of disconnection before connection, avoiding shoot-through leakage caused by the instantaneous connection between reference voltage and reference ground voltage during switching, and stably maintaining the charge balance of the differential capacitor plates. This reduces the overall power consumption of the circuit and also reduces the quantization error caused by transient current disturbances, improving the accuracy of analog-to-digital conversion. Attached Figure Description

[0019] Figure 1 This is a structural block diagram of a unidirectional anti-overlap control circuit in one embodiment of the present invention; Figure 2 This is a schematic diagram of the specific structure of a unidirectional anti-overlap control circuit in one embodiment of the present invention; Figure 3 This is a schematic diagram of the structure of the first control link in one embodiment of the present invention; Figure 4 This is a schematic diagram of the structure of the second control link in one embodiment of the present invention; Figure 5 This is a flowchart illustrating a unidirectional anti-overlap control method in one embodiment of the present invention.

[0020] Reference numerals: Q, comparator output signal; D, comparator decision signal; Y, first intermediate node signal; Y_dly, first delay signal; Phs, clock signal; SW_REF1, first reference voltage control signal; SW_GND1, first reference ground voltage control signal; X, second intermediate node signal; X_dly, second delay signal; SW_REF2, second reference voltage control signal; SW_GND2, second reference ground voltage control signal; CA, first split capacitor array; CB, second split capacitor array; P-CDAC, differential positive-terminal capacitive digital-to-analog converter; N-CDAC, differential negative-terminal capacitive digital-to-analog converter; VREF, reference voltage; VIN, input signal; VGND, reference ground voltage; Comp, comparator; SAR Logic, successive approximation control logic circuit. Detailed Implementation

[0021] Based on the teachings of this specification, those skilled in the art can form new technical solutions by combining different implementation methods without creating technical contradictions. Such variations should be considered to fall within the protection scope of this application.

[0022] The following is a more detailed description of a unidirectional anti-overlap control circuit and method based on a capacitor splitting architecture according to the present invention, with reference to the schematic diagrams. Preferred embodiments of the invention are shown. It should be understood that those skilled in the art can modify the invention described herein while still achieving its advantageous effects. Therefore, the following description should be understood as being of general knowledge to those skilled in the art and is not intended to limit the invention.

[0023] The invention is described more specifically by way of example in the following paragraphs with reference to the accompanying drawings. The advantages and features of the invention will become clearer from the following description. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the invention.

[0024] The solution proposed in this application can be adapted to common-mode voltage capacitor-split successive approximation analog-to-digital converters with different resolutions. Taking a 20 MHz sampling rate and 12-bit precision application scenario as an example, this application provides a detailed explanation of the specific implementation of the unidirectional anti-overlap control circuit and method based on the capacitor-split architecture.

[0025] Example 1

[0026] like Figure 1 As shown, this embodiment of the invention proposes a unidirectional anti-overlap control circuit based on a capacitor splitting architecture. The unidirectional anti-overlap control circuit includes a differential positive-terminal capacitive digital-to-analog converter (P-CDAC), a differential negative-terminal capacitive digital-to-analog converter (N-CDAC), a comparator Comp, and a successive approximation control logic circuit (SAR Logic).

[0027] Specifically, such as Figure 2 As shown, the differential positive-terminal capacitive digital-to-analog converter (P-CDAC) is connected to the positive input terminal of the comparator Comp, and the differential negative-terminal capacitive digital-to-analog converter (N-CDAC) is connected to the negative input terminal of the comparator Comp. The output terminal of the comparator Comp is connected to the successive approximation control logic circuit SAR Logic. The differential structure allows for equal-amplitude, opposite-directional potential changes at the positive and negative terminals during charge redistribution. The differential swing is twice that of the single-ended converter, achieving a higher signal-to-noise ratio with the same capacitor area. Simultaneously, it provides excellent common-mode rejection of power supply noise and substrate coupling noise, effectively improving the overall accuracy of the analog-to-digital conversion.

[0028] Both the differential positive-terminal capacitive digital-to-analog converter P-CDAC and the differential negative-terminal capacitive digital-to-analog converter N-CDAC include a first adjustment unit and a second adjustment unit. The first adjustment unit includes a first split capacitor array CA, and the second adjustment unit includes a second split capacitor array CB.

[0029] The successive approximation control logic circuit (SAR Logic) controls the switching of the bottom plate of the first split capacitor array CA from the reference voltage VREF to the reference ground voltage VGND, and controls the switching of the bottom plate of the second split capacitor array CB from the reference ground voltage VGND to the reference voltage VREF, by adjusting the voltages input to the differential positive terminal capacitive digital-to-analog converter (P-CDAC) and the differential negative terminal capacitive digital-to-analog converter (N-CDAC). These two types of switching are opposite in direction and unidirectional, a physical characteristic that forms the basis for the unidirectional anti-overlap control implemented in this application. During the conversion phase of the high-speed SAR ADC, after each comparison decision, the successive approximation control logic circuit (SAR Logic) immediately drives the corresponding bottom plate to switch. The switching speed directly determines the available setup time of the DAC (analog-to-digital converter) array, thus limiting the maximum sampling rate of the entire converter.

[0030] In this embodiment, both the first adjustment unit and the second adjustment unit further include multiple multiplexers. Both the first split capacitor array CA and the second split capacitor array CB include multiple binary weighted capacitors, and the multiple multiplexers include multiple 3-to-1 multiplexers; each binary weighted capacitor is connected to each 3-to-1 multiplexer in a one-to-one correspondence, meaning that the differential positive-terminal capacitive digital-to-analog converter P-CDAC and the differential negative-terminal capacitive digital-to-analog converter N-CDAC have the same structure.

[0031] The binary weighted capacitors of the first split capacitor array CA are arranged in a binary weighted manner, and are 2 in number. 1 Cu, 2 2Cu、...、2 n-1 Cu, the binary weighted capacitor pages of the second split capacitor array are arranged in a binary weighted manner, and are 2 in number. 0 Cu, 2 0 Cu, 2 1 Cu, 2 2 Cu、...、2 n-1 Cu, where Cu is the unit capacitance and n is the number of bits in the analog-to-digital converter. Different numbers of bits correspond to different numbers of binary weight capacitors, and high-precision successive approximation quantization is achieved by superimposing the charges of multiple capacitors.

[0032] In this embodiment, the first input terminal of the 3-to-1 selector is connected to the reference voltage VREF, the second input terminal is connected to the input signal VIN, the third input terminal is connected to the reference ground voltage VGND, and the output terminal is connected to the bottom plate of the binary weighted capacitor; the top plate of the binary weighted capacitor is connected to the positive input terminal of the comparator Comp.

[0033] The 3-to-1 multiplexer switches the bottom plate to the input signal VIN during the sampling phase, thus sampling the input signal VIN. During the conversion phase, based on the decision result of the successive approximation control logic circuit SAR Logic, the multiplexer switches the bottom plate to either the reference voltage VREF or the reference ground voltage VGND, driving a corresponding change in the potential at the positive input of the comparator Comp, thereby completing the digital approximation process. The bottom and top plates are coupled via binary weighted capacitors; the potential change of the top plate is proportional to the switching amplitude of the bottom plate and the capacitor weight, thereby achieving precise charge redistribution.

[0034] Due to the unidirectional constraint of the capacitor splitting architecture, during the switching phase, the bottom plate of the first split capacitor array CA will only switch downward from the reference voltage VREF to the reference ground voltage VGND, while the bottom plate of the second split capacitor array CB will only switch upward from the reference ground voltage VGND to the reference voltage VREF. This physical characteristic is the fundamental starting point for the unidirectional anti-overlap control of this application.

[0035] In this embodiment, the differential negative-terminal capacitive digital-to-analog converter N-CDAC has the same structure as the differential positive-terminal capacitive digital-to-analog converter P-CDAC and is differentially symmetrically arranged; the top plate of the binary weight capacitor in the differential negative-terminal capacitive digital-to-analog converter N-CDAC is connected to the negative input terminal of the comparator Comp.

[0036] The differential symmetry configuration enables the capacitor arrays at the positive and negative ends to generate equal-amplitude and opposite-axis potential changes during charge redistribution. The differential swing at the positive and negative ends is twice that of the single-ended configuration, resulting in a higher signal-to-noise ratio for the same capacitor area. At the same time, it has good common-mode suppression capability for power supply noise and substrate coupling noise.

[0037] In this embodiment, the successive approximation control logic circuit SAR Logic includes a first control link and a second control link that are physically isolated from each other.

[0038] The first control link is used to control the unidirectional switching of the bottom plate of the binary weighted capacitor in the first split capacitor array CA from the reference voltage VREF to the reference ground voltage VGND, and the second control link is used to control the unidirectional switching of the bottom plate of the binary weighted capacitor in the second split capacitor array CB from the reference ground voltage VGND to the reference voltage VREF.

[0039] The two control links are physically isolated and perform logic operations and control signals in parallel and independently. The level switching timing of the two sets of split capacitor arrays does not interfere with each other, breaking the limitation of the traditional general-purpose bidirectional anti-overlap (Break-Before-Make, BBM) logic, which is forced to set an excessively redundant dead time due to the need to be compatible with both directions at the same time, thus supporting a higher sampling rate.

[0040] In this embodiment, as Figure 3 As shown, the first control link includes a first NAND gate, a first inverter, a second inverter, a second NAND gate, a third inverter, and a first NOR gate.

[0041] Specifically, the first input of the first NAND gate is connected to the output signal Q of the comparator, the second input is connected to the decision signal D of the comparator, and the output is the first intermediate node signal Y. The logical expression of the first intermediate node signal Y is as follows: The first NAND gate performs a logical operation to determine the current bit and outputs a valid comparator output signal Q and a comparator decision signal D. At this time, the first intermediate node signal Y changes accordingly; that is, when Phs=1, Q=1, and D=1, the first intermediate node signal Y changes from high to low, triggering the first split capacitor array CA to switch from the reference voltage VREF to the reference ground voltage VGND. In other states, the first intermediate node signal Y remains high, and the internal switches of the multiplexer maintain the preset initial operating state during the sampling phase.

[0042] Table 1

[0043] Based on Table 1 above, the operating states of the first split capacitor array CA are described below: When the clock signal Phs is low, the first reference voltage control signal SW_REF1 outputs a high level, the first reference ground voltage control signal SW_GND1 outputs a low level, and the bottom plate of the capacitor is continuously connected to the reference voltage VREF, stably maintaining the sampling state of pre-charged to the reference voltage VREF.

[0044] When the clock signal Phs is high and the comparator output signal Q is low, the first reference voltage control signal SW_REF1 and the first reference ground voltage control signal SW_GND1 synchronously output low levels, the capacitor bottom plate is connected to the reference voltage VREF, and the reference ground connection is simultaneously disconnected, and the capacitor plate is in a high-impedance waiting state.

[0045] When the clock signal Phs is high, the comparator output signal Q is high, and the comparator decision signal D is high, the second reference voltage control signal SW_REF2 and the second reference ground voltage control signal SW_GND2 continuously output high levels, the bottom plate of the capacitor remains in the conducting state with the reference ground voltage VGND, and the circuit does not perform level switching operation.

[0046] Only when the clock signal Phs is high, the comparator output signal is high, and the comparator decision signal is switched to low, the second intermediate node signal X flips from low to high, thereby initiating the switching process of the second split capacitor array CB from reference ground to reference voltage VREF, and driving the subsequent asymmetric dead-time timing control unit to complete the path on / off control.

[0047] The input of the first inverter is connected to the first intermediate node signal Y, and its output is connected to the input of the second inverter. The output of the second inverter outputs a first delayed signal Y_dly. The first and second inverters are connected in series to form an even-stage inverter delay chain. While maintaining the signal polarity consistent with the first intermediate node signal Y, a controllable propagation delay is introduced. This delay time is the physical source of the anti-overlapping dead time of the first control link. By adjusting the number of inverters in series or the driving capability of each inverter, the required dead time width can be precisely set across the entire process, power supply voltage, and temperature range.

[0048] The first input of the second NAND gate is connected to the clock signal Phs, the second input is connected to the first intermediate node signal Y, the third input is connected to the first delay signal Y_dly, and the output gate outputs the first reference voltage control signal SW_REF1. The logical expression of the first reference voltage control signal SW_REF1 is as follows: .

[0049] The second NAND gate switching decision logic and anti-overlap dead time control are implemented in the same logic gate level, avoiding the additional area overhead and dynamic switching power consumption caused by cascading multiple levels of basic logic gates.

[0050] The first reference voltage control signal SW_REF1 is used to control the on / off state of the reference voltage VREF path in the 3-to-1 selector. When the first reference voltage control signal SW_REF1 is low, the 3-to-1 selector connects to the reference voltage VREF, opening the reference voltage VREF transmission path and causing the capacitor's bottom plate to be connected to the reference voltage VREF potential. When the first reference voltage control signal SW_REF1 is high, the 3-to-1 selector disconnects the reference voltage VREF transmission path, electrically isolating the capacitor's bottom plate from the reference voltage VREF.

[0051] When the first intermediate node signal Y transitions from high to low, the first intermediate node signal Y connected to the three input ports of the second NAND gate synchronously completes its level update. The level switch directly changes the output level of the second NAND gate, and the operation is not limited by the real-time level state of the first delay signal Y_dly. Regardless of whether the first delay signal Y_dly completes a full level transition, the output of the second NAND gate will synchronously switch to a high level, driving the first reference voltage control signal SW_REF1 to instantly switch to a high level. This, in turn, controls the immediate disconnection of the reference voltage VREF transmission path within the three-to-one selector, quickly establishing electrical isolation between the capacitor's bottom plate and the reference voltage VREF.

[0052] The aforementioned path disconnection operation is executed synchronously with the level transition of the first intermediate node signal Y, so that the timing start time of the anti-overlap dead zone is consistent with the decision signal transition time. Unlike the traditional general disconnect-before-connect logic, it is no longer necessary to reserve a redundant timing interval for waiting for the bidirectional signal to switch synchronously, thereby releasing more effective time for the capacitor array to complete charge establishment.

[0053] The input of the third inverter is connected to the clock signal Phs. The first input of the first NOR gate is connected to the first intermediate node signal Y, the second input is connected to the first delay signal Y_dly, and the third input is connected to the output of the third inverter. The output outputs the first reference ground voltage control signal SW_GND1. The logical expression of the first reference ground voltage control signal SW_GND1 is as follows: .

[0054] The first reference ground voltage control signal SW_GND1 is used to control the on / off state of the reference ground voltage VGND path in the three-way selector. When the first reference ground voltage control signal SW_GND1 is high, the three-way selector is connected to the reference ground voltage VGND, conducting the reference ground voltage VGND transmission path, so that the bottom plate of the capacitor is connected to the reference ground voltage VGND potential. When the first reference ground voltage control signal SW_GND1 is low, the three-way selector cuts off the reference ground voltage VGND transmission path, so that the bottom plate of the capacitor is electrically isolated from the reference ground voltage VGND.

[0055] The first NOR gate has a multi-input level constraint characteristic; its output can only flip to a high level when all input ports remain low. During the period before the first delayed signal Y_dly completes its level flip, Y_dly remains high. Constrained by this level, the output of the first NOR gate stably remains low, keeping the reference ground voltage VGND transmission path in the 3-to-1 selector continuously disconnected. Only when the first delayed signal Y_dly completes its level flip through the delay link formed by two cascaded inverters and the clock signal Phs, inverted by the third inverter, is synchronously low, will the first reference ground voltage control signal SW_GND1 output by the first NOR gate jump to a high level, thus delaying the conduction of the reference ground transmission path in the 3-to-1 selector.

[0056] Therefore, the time difference between the level transition of the first intermediate node signal Y and the level reversal of the first delayed signal Y_dly naturally forms an anti-overlapping dead zone at the circuit timing level. Within the timing corresponding to the dead zone, the reference voltage VREF transmission path of the 3-to-1 selector is completely cut off, the reference ground transmission path has not yet been opened, and the capacitor bottom plate is electrically isolated from both the reference voltage VREF and the reference ground voltage VGND, thus avoiding the shoot-through leakage phenomenon caused by the instantaneous connection between the reference voltage VREF and the reference ground voltage VGND from the root of the timing problem.

[0057] In this embodiment, as Figure 4 As shown, the second control link includes a fourth inverter, a second NOR gate, a fifth inverter, a sixth inverter, a third NOR gate, a third NAND gate, a seventh inverter, and a fourth NAND gate.

[0058] Specifically, the input of the fourth inverter is connected to the output signal Q of the comparator; the first input of the second NOR gate is connected to the decision signal D of the comparator, the second input is connected to the output of the fourth inverter, and the output outputs the second intermediate node signal X. The logical expression of the second intermediate node signal X is as follows: , equivalent to .

[0059] The second intermediate node signal X and the first intermediate node signal Y in the first control link are in a dual correspondence at the logic level. The two types of signals can completely cover all feasible level switching conditions of the two sets of split capacitor arrays in the quantization conversion stage.

[0060] Table 2

[0061] As shown in Table 2 above, the operating states of the second split capacitor array CB are described below: When the clock signal Phs is low, the second reference voltage control signal SW_REF2 outputs a high level, and the second reference ground voltage control signal SW_GND2 outputs a low level. The bottom plate of the capacitor is continuously connected to the reference ground transmission path, and the initial sampling state of being pre-charged to the reference ground potential is stably maintained.

[0062] When the clock signal Phs is high and the comparator output signal Q is low, the second reference voltage control signal SW_REF2 and the second reference ground voltage control signal SW_GND2 synchronously output high levels, and the bottom plate of the capacitor remains connected to the reference ground voltage VGND.

[0063] When the clock signal Phs is high, the comparator output signal Q is high, and the comparator decision signal D is low, the second reference voltage control signal SW_REF2 and the second reference ground voltage control signal SW_GND2 synchronously output low levels, and the capacitor bottom plate completes the unidirectional switching operation from the reference ground voltage VGND potential to the reference voltage VREF potential.

[0064] When the clock signal Phs is high, the comparator output signal Q is high, and the comparator decision signal D is high, the second reference voltage control signal SW_REF2 and the second reference ground voltage control signal SW_GND2 continuously output high levels, and the bottom plate of the capacitor maintains the conducting state with the reference ground voltage VGND.

[0065] When the clock signal Phs is high, the comparator output signal is high, and the comparator decision signal is low, the second intermediate node signal X flips from low to high, thereby initiating the complete timing process of the second split capacitor array CB switching from reference ground to reference voltage VREF, and driving the subsequent asymmetric dead-time timing control unit to complete the path on / off control.

[0066] The input of the fifth inverter is connected to the second intermediate node signal X, and the output is connected to the input of the sixth inverter. The output of the sixth inverter outputs the second delayed signal X_dly. The fifth and sixth inverters are connected in series to form an even-stage inverter delay chain, which is the same as the even-stage series inverter delay chain in the first control link. While keeping the logic polarity of the second intermediate node signal X unchanged, a controllable propagation delay is introduced to form a timing difference between the second intermediate node signal X and the second delayed signal X_dly. This timing difference is the physical source of the anti-overlap dead time of the second control link.

[0067] It should be noted that when the second split capacitor array CB switches from reference ground voltage VGND to reference voltage VREF, the timing control requirements are completely opposite to those of the first split capacitor array CA when switching from reference voltage VREF to reference ground voltage VGND. When the first split capacitor array CA switches, the reference voltage VREF transmission path is first cut off, and the reference ground transmission path is then delayed. When the second split capacitor array CB switches, the reference ground transmission path needs to be cut off instantaneously, and the reference voltage VREF transmission path is then delayed. The timing constraints of the two unidirectional switching scenarios are inversely related. Therefore, the delay parameter of the second control link can be set independently of the delay parameter of the first control link, without needing to adapt to the path switching timing constraints of the other array. Through the independently adjustable design of the two sets of delay link parameters, the timing requirements corresponding to the two unidirectional switching scenarios can be matched separately, compressing the anti-overlap dead time of each of the two split capacitor arrays to the theoretical minimum limit, avoiding redundant timing losses caused by uniform delay parameters.

[0068] The first input of the third NOR gate is connected to the second intermediate node signal X, and the second input is connected to the second delayed signal X_dly. The input of the seventh inverter is connected to the output of the third NAND gate, and the output outputs the second reference ground voltage control signal SW_GND2. The logical expression of the second reference ground voltage control signal SW_GND2 is as follows: .

[0069] The second reference ground voltage control signal SW_GND2 is used to control the on / off state of the reference ground voltage VGND transmission path in the three-way selector. When the second reference ground voltage control signal SW_GND2 is high, the three-way selector is connected to the reference ground voltage VGND, and the reference ground voltage VGND transmission path is turned on, so that the bottom plate of the capacitor is connected to the reference ground voltage VGND. When the second reference ground voltage control signal SW_GND2 is low, the three-way selector cuts off the reference ground constant voltage transmission path, so that the bottom plate of the capacitor is electrically isolated from the reference ground voltage VGND.

[0070] When the second intermediate node signal X transitions from low to high, the third NOR gate instantly senses the level change and outputs a low level. After this level signal is transmitted through the combinational logic link formed by the third NAND gate and the seventh inverter, the second reference ground voltage control signal SW_GND2 instantaneously switches to low, driving the reference ground voltage VGND transmission path in the three-to-one selector to be immediately cut off, breaking the charge transmission path between the capacitor bottom plate and the reference ground voltage VGND, thereby blocking the direct leakage path between the reference voltage VREF and the reference ground voltage VGND. This fast response process of the level signal does not require waiting for the second delayed signal X_dly to complete a full level transition. The timing design concept corresponds symmetrically with the response mechanism of the instantaneous shutdown of the reference voltage VREF transmission path in the first control link. The two cooperate with each other to form the core logical basis of the first-to-break-then-turn timing control mechanism of this application.

[0071] The first input of the third NAND gate is connected to the clock signal Phs, and the second input is connected to the output of the third NOR gate. The first input of the fourth NAND gate is connected to the clock signal Phs, the second input is connected to the second intermediate node signal X, the third input is connected to the second delay signal X_dly, and the output is the second reference voltage control signal SW_REF2. The logical expression of the second reference voltage control signal SW_REF2 is as follows: .

[0072] The second reference voltage control signal SW_REF2 is used to control the on / off state of the reference voltage VREF transmission path in the three-way selector. When the second reference voltage control signal SW_REF2 is low, the three-way selector connects to the reference voltage VREF, conducting the reference voltage VREF transmission path, so that the bottom plate of the capacitor is connected to the reference voltage VREF potential. When the second reference voltage control signal SW_REF2 is high, the three-way selector disconnects the reference voltage VREF transmission path, so that the bottom plate of the capacitor is electrically isolated from the reference voltage VREF.

[0073] The fourth NAND gate integrates the switching decision logic and the anti-overlap dead zone duration control function into the same level of logic gate, which simplifies the overall combination logic link, reduces the layout area occupied by multi-level logic gate stacking, and reduces the dynamic power consumption overhead caused by multiple signal level flips.

[0074] Furthermore, the fourth NAND gate has a multi-input level constraint characteristic. Its output can only flip to a low level and conduct the reference voltage VREF transmission path when the clock signal Phs, the second intermediate node signal X, and the second delay signal X_dly are all simultaneously at a high level. During the period before the second delay signal X_dly completes its level flip, it remains at a low level. Constrained by this level, the output of the fourth NAND gate stably maintains a high level, and the internal reference voltage VREF transmission path of the 3-to-1 selector remains disconnected. Only after the second delay signal X_dly completes its level flip through the delay link formed by two cascaded inverters, and all three inputs simultaneously meet the high-level condition, will the second reference voltage control signal SW_REF2 jump to a low level, delaying the conduction of the reference voltage VREF transmission path of the 3-to-1 selector.

[0075] The time difference between the level transition of the second intermediate node signal X and the level reversal of the second delayed signal X_dly naturally forms a dedicated anti-overlap dead zone for the second control link at the circuit timing level. Within this dead zone, the reference ground transmission path in the 3-to-1 selector is completely cut off, the reference voltage VREF transmission path is not yet open, and the capacitor bottom plate is synchronously electrically isolated from the reference voltage VREF and the reference ground voltage VGND, thus completely avoiding the risk of shoot-through short-circuit current caused by the instantaneous connection between the reference voltage VREF and the reference ground voltage VGND from the timing source.

[0076] Example 2

[0077] like Figure 5 As shown, this embodiment proposes a unidirectional anti-overlap control method based on a capacitor splitting architecture, applied to the unidirectional anti-overlap control circuit based on a capacitor splitting architecture described in Embodiment 1, including the following steps: Step 1: Based on the phase signal, the comparator's output signal Q, and the comparator's decision signal D, send switching commands to the first control link and the second control link respectively.

[0078] Step 2: The first control link controls the voltage of the bottom plate in the first split capacitor array CA, switching unidirectionally from the reference voltage VREF to the reference ground voltage VGND.

[0079] Step 3: The second control link controls the voltage of the bottom plate in the second split capacitor array CB, unidirectionally switching it from the reference ground voltage VGND to the reference voltage VREF.

[0080] Step one relies on successive approximation control logic to synchronously acquire and logically distinguish multiple decision signals, using the phase signal as a global timing reference to coordinate the switching timing of the two sets of split capacitor arrays. The same set of decision signals is distributed in parallel to two independent control links to ensure synchronized switching action timing of the two subarrays within the same quantization period, avoiding differential errors introduced by asynchronous charge updates between the two capacitors. Simultaneously, multiple signals are used to jointly determine and filter valid switching opportunities, issuing switching commands only after valid bit decisions are completed, thus avoiding charge disturbances and leakage losses caused by erroneous path switching.

[0081] Step two leverages the unidirectional switching characteristic of the first split capacitor array CA, which can only switch from the reference voltage VREF to the reference ground. It utilizes independent delay logic set in the first control link to generate a dedicated anti-overlap timing sequence. During switching, the reference voltage VREF transmission path is instantaneously cut off first. After passing through the independent dead-time window formed by the link delay unit, the reference ground transmission path is then turned on, achieving complete isolation of the two voltage paths' conduction timing. Step two allows for independent optimization of the dead-time duration, eliminating the need for redundant timing settings for reverse switching conditions. This releases more capacitor charge build-up time, improving the analog-to-digital converter's sampling rate. Simultaneously, the timing isolation mechanism prevents the reference voltage VREF path and the reference ground path from conducting simultaneously, preventing shoot-through leakage during switching and maintaining capacitor plate charge balance, thus reducing quantization errors.

[0082] Step 3, based on the application scenario of the second split capacitor array CB switching unidirectionally from reference ground to reference voltage VREF, the second control link has a completely independent delay adjustment capability, and the timing constraints are designed in reverse symmetry with Step 2. During the switching execution phase, the reference ground transmission path is first quickly disconnected, and after waiting for the dead time independently generated by this link, the reference voltage VREF transmission path is then connected. The delay in this step can be adjusted completely separately from Step 2, adapting to the process characteristics of asymmetrical path opening and closing rates under the two switching directions, eliminating the timing waste caused by a uniform fixed dead time; at the same time, the two voltage paths are simultaneously disconnected within the dead time window, avoiding transient short-circuit current from the root of timing, reducing the overall power consumption of the circuit, ensuring accurate charge distribution of the two sets of split capacitor arrays, and improving the conversion accuracy of the analog-to-digital converter.

[0083] In this embodiment, the step of the first control link controlling the voltage of the bottom plate in the first split capacitor array CA to unidirectionally switch from the reference voltage VREF to the reference ground voltage VGND specifically includes: The first NAND gate performs logical operations on the comparator's output signal Q and the comparator's decision signal D to output the first intermediate node signal Y.

[0084] The first intermediate node signal Y is delayed by a first inverter and a second inverter connected in series, and then outputs a first delayed signal Y_dly.

[0085] When the first intermediate node signal Y undergoes a level transition, the second NAND gate immediately outputs the first reference voltage control signal SW_REF1 based on the level transition of the first intermediate node signal Y, so as to control the VREF path of the reference voltage of the multiplexer configured in the differential positive terminal capacitive digital-to-analog converter P-CDAC to be turned off.

[0086] After the reference voltage VREF path is turned off, and the first delayed signal Y_dly completes its level flip, the first NOR gate performs logical operations based on the clock signal Phs, the first intermediate node signal Y after the level jump, and the first delayed signal Y_dly after the level flip, and outputs the first reference ground voltage control signal SW_GND1, which delays and turns on the reference ground voltage VGND path of the multiplexer configured in the differential positive terminal capacitive digital-to-analog converter P-CDAC.

[0087] Based on the time-sequential coordination of logic gates at each level, independent timing control can be achieved for the unidirectional switching characteristics of the first split capacitor array CA. That is, the effective switching trigger signal is first screened by NAND gates, and then a delay signal is generated at low cost using two-stage inverters to realize the instantaneous shutdown of the reference voltage VREF path and the delayed conduction of the reference ground path, forming an isolation dead zone to eliminate short-circuit leakage. At the same time, traditional timing redundancy is eliminated, and the dead zone can be optimized to a minimum, taking into account chip area, conversion speed and quantization accuracy.

[0088] In this embodiment, the step of the second control link controlling the voltage of the bottom plate in the second split capacitor array CB to unidirectionally switch from the reference ground voltage VGND to the reference voltage VREF specifically includes: The second NOR gate performs a logical operation on the inverted signals of the comparator's decision signal D and the comparator's output signal Q, and outputs the second intermediate node signal X.

[0089] The second intermediate node signal X is delayed by the fifth and sixth inverters connected in series, and then outputs the second delayed signal X_dly.

[0090] When the second intermediate node signal X undergoes a level transition, the third NOR gate and the third NAND gate immediately output the second reference ground voltage control signal SW_GND2 based on the changed second intermediate node signal X and the clock signal Phs, to control the shut-off of the reference ground voltage VGND path of the multiplexer configured in the differential negative-terminal capacitive digital-to-analog converter N-CDAC. After the reference ground voltage VGND path is shut off, and after the fifth inverter and the sixth inverter complete their transmission delay, the fourth NAND gate performs logical operations based on the output clock signal Phs, the level-transitioned second intermediate node signal X, and the level-flipped second delay signal X_dly, and outputs the second reference voltage control signal SW_REF2, which delays and turns on the reference voltage VREF path of the multiplexer configured in the differential negative-terminal capacitive digital-to-analog converter N-CDAC.

[0091] During this switching process, the second split capacitor array CB is controlled unidirectionally by the coordinated action of digital logic gates at all levels. First, the switching trigger signal is precisely screened by NOR gates, and two-stage inverters generate a delay signal at low cost. The logic combination circuit instantly cuts off the reference ground path to eliminate timing redundancy. After the delayed signal flips, the reference voltage VREF path is turned on. The timing difference is used to form an isolation dead zone to avoid shoot-through leakage and stabilize capacitor charge. The delay parameters can be adjusted independently, reducing chip area while ensuring the converter's high speed, low power consumption and high precision performance.

[0092] In summary, this application manages the bottom plate switching action of the differential positive and differential negative capacitor-type digital-to-analog converters (DACs) separately through successive approximation control logic circuits. This ensures that the differential positive capacitor-type DAC performs only unidirectional switching from reference voltage to reference ground voltage, and the differential negative capacitor-type DAC performs only unidirectional switching from reference ground voltage to reference voltage. This precisely adapts to the fixed unidirectional switching characteristics of the two capacitor arrays under the capacitor split architecture, without requiring compatibility with the unified timing constraints of bidirectional switching scenarios. The dead time can be optimized separately for each switching direction, eliminating redundant timing introduced by traditional bidirectional anti-overlap logic, effectively extending the capacitor charge establishment window, and significantly improving the sampling rate of the DAC. At the same time, unidirectional independent control can accurately achieve the timing coordination of disconnection before connection, avoiding shoot-through leakage caused by instantaneous connection between reference voltage and reference ground voltage during switching, and stably maintaining the charge balance of the differential capacitor plates. This reduces the overall power consumption of the circuit and also reduces the quantization error caused by transient current disturbances, improving the accuracy of analog-to-digital conversion.

[0093] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A unidirectional anti-overlap control circuit based on a capacitor splitting architecture, characterized in that, It includes a differential positive-terminal capacitive digital-to-analog converter, a differential negative-terminal capacitive digital-to-analog converter, a comparator, and a successive approximation control logic circuit; The differential positive-terminal capacitive digital-to-analog converter is connected to the positive input terminal of the comparator, the differential negative-terminal capacitive digital-to-analog converter is connected to the negative input terminal of the comparator, and the output terminal of the comparator is connected to the successive approximation control logic circuit. Both the differential positive-terminal capacitive digital-to-analog converter and the differential negative-terminal capacitive digital-to-analog converter include a first adjustment unit and a second adjustment unit. The first adjustment unit includes a first split capacitor array, and the second adjustment unit includes a second split capacitor array. The successive approximation control logic circuit controls the unidirectional switching of the bottom plate of the first split capacitor array from the reference voltage to the reference ground voltage, and the unidirectional switching of the bottom plate of the second split capacitor array from the reference ground voltage to the reference voltage by adjusting the input voltages of the first split capacitor array and the second split capacitor array. Both the first adjustment unit and the second adjustment unit further include multiple multiplexers; Both the first split capacitor array and the second split capacitor array include multiple binary weighted capacitors, and the multiple multiplexers include multiple 3-to-1 multiplexers; each binary weighted capacitor is connected to each of the 3-to-1 multiplexers in a one-to-one correspondence.

2. The unidirectional anti-overlap control circuit based on capacitor splitting architecture as described in claim 1, characterized in that, The first input terminal of the three-to-one selector is connected to the reference voltage, the second input terminal is connected to the input signal, the third input terminal is connected to the reference ground voltage, and the output terminal is connected to the bottom plate of the binary weighted capacitor. The top plate of the binary weighted capacitor is connected to the positive input terminal of the comparator.

3. The unidirectional anti-overlap control circuit based on capacitor splitting architecture as described in claim 1, characterized in that, The differential negative-terminal capacitive digital-to-analog converter has the same structure as the differential positive-terminal capacitive digital-to-analog converter and is differentially symmetrically arranged. In the differential negative-terminal capacitive digital-to-analog converter, the top plate of the binary weighting capacitor is connected to the negative input terminal of the comparator.

4. The unidirectional anti-overlap control circuit based on capacitor splitting architecture as described in claim 1, characterized in that, The successive approximation control logic circuit includes a first control link and a second control link that are physically isolated from each other. The first control link is used to control the unidirectional switching of the bottom plate of the binary weighted capacitor in the first split capacitor array from the reference voltage to the reference ground voltage. The second control link is used to control the unidirectional switching of the bottom plate of the binary weighted capacitor in the second split capacitor array from the reference ground voltage to the reference voltage.

5. The unidirectional anti-overlap control circuit based on capacitor splitting architecture as described in claim 4, characterized in that, The first control link includes a first NAND gate, a first inverter, a second inverter, a second NAND gate, a third inverter, and a first NOR gate; The first input terminal of the first NAND gate is connected to the output signal of the comparator, the second input terminal is connected to the decision signal of the comparator, and the output terminal outputs the first intermediate node signal; The input terminal of the first inverter is connected to the first intermediate node signal, and the output terminal is connected to the input terminal of the second inverter. The output terminal of the second inverter outputs the first delay signal. The first input of the second NAND gate is connected to the clock signal, the second input is connected to the first intermediate node signal, the third input is connected to the first delay signal, and the output output is the first reference voltage control signal. The input terminal of the third inverter is connected to the clock signal; The first input terminal of the first NOR gate is connected to the first intermediate node signal, the second input terminal is connected to the first delay signal, the third input terminal is connected to the output terminal of the third inverter, and the output terminal outputs the first reference ground voltage control signal.

6. The unidirectional anti-overlap control circuit based on capacitor splitting architecture as described in claim 4, characterized in that, The second control link includes a fourth inverter, a second NOR gate, a fifth inverter, a sixth inverter, a third NOR gate, a third NAND gate, a seventh inverter, and a fourth NAND gate; The input terminal of the fourth inverter is connected to the output signal of the comparator; The first input terminal of the second NOR gate is connected to the decision signal of the comparator, the second input terminal is connected to the output terminal of the fourth inverter, and the output terminal outputs the second intermediate node signal. The input terminal of the fifth inverter is connected to the second intermediate node signal, and the output terminal is connected to the input terminal of the sixth inverter. The output terminal of the sixth inverter outputs a second delayed signal; The first input terminal of the third NOR gate is connected to the second intermediate node signal, and the second input terminal is connected to the second delay signal; The first input terminal of the third NAND gate is connected to the clock signal, and the second input terminal is connected to the output terminal of the third NOR gate. The input terminal of the seventh inverter is connected to the output terminal of the third NAND gate, and the output terminal outputs the second reference ground voltage control signal. The first input of the fourth NAND gate is connected to the clock signal, the second input is connected to the second intermediate node signal, the third input is connected to the second delay signal, and the output output is the second reference voltage control signal.

7. A unidirectional anti-overlap control method based on a capacitor splitting architecture, applied to the unidirectional anti-overlap control circuit based on a capacitor splitting architecture as described in any one of claims 1-6, characterized in that, Includes the following steps: Based on the phase signal, the comparator's output signal, and the comparator's decision signal, switching commands are sent to the first control link and the second control link, respectively. The first control link controls the voltage of the bottom plate in the first split capacitor array, switching it unidirectionally from the reference voltage to the reference ground voltage; The second control link controls the voltage of the bottom plate in the second split capacitor array, unidirectionally switching it from the reference ground voltage to the reference voltage.

8. The unidirectional anti-overlap control method based on capacitor splitting architecture as described in claim 7, characterized in that, The steps of the first control link controlling the voltage of the bottom plate in the first split capacitor array to unidirectionally switch from the reference voltage to the reference ground voltage specifically include: The first NAND gate performs logical operations on the output signal and the decision signal of the comparator to output the first intermediate node signal; The first intermediate node signal is delayed by a first inverter and a second inverter connected in series, and then output as a first delayed signal. When the first intermediate node signal undergoes a level transition, the second NAND gate immediately outputs a first reference voltage control signal based on the first intermediate node signal after the level transition, so as to control the reference voltage path of the multiplexer configured in the differential positive terminal capacitive digital-to-analog converter to be turned off. After the reference voltage path is turned off, and the first delayed signal completes its level flip, the first NOR gate performs logical operations based on the clock signal, the first intermediate node signal after the level jump, and the first delayed signal after the level flip, and outputs the first reference ground voltage control signal, which delays and turns on the reference ground voltage path of the multiplexer configured in the differential positive terminal capacitive digital-to-analog converter.

9. The unidirectional anti-overlap control method based on capacitor splitting architecture as described in claim 7, characterized in that, The steps of the second control link controlling the voltage of the bottom plate in the second split capacitor array to unidirectionally switch from the reference ground voltage to the reference voltage specifically include: The second NOR gate performs a logical operation on the decision signal of the comparator and the inverted signal of the output signal of the comparator, and outputs the second intermediate node signal; The second intermediate node signal is delayed by a fifth inverter and a sixth inverter connected in series, and then output as a second delayed signal. When the second intermediate node signal undergoes a level transition, the third NOR gate and the third NAND gate immediately output the second reference ground voltage control signal based on the changed second intermediate node signal and the clock signal, so as to control the reference ground voltage path of the multiplexer configured in the differential negative terminal capacitive digital-to-analog converter to be turned off. After the reference ground voltage path is turned off, and after the fifth inverter and the sixth inverter complete the transmission delay, the fourth NAND gate performs logical operations based on the output clock signal, the second intermediate node signal after the level transition, and the second delay signal after the level flip, and outputs the second reference voltage control signal to delay and turn on the reference voltage path of the multiplexer configured in the differential negative terminal capacitive digital-to-analog converter.

Images