Printed circuit board

Abstract

The present disclosure provides a printed circuit board including a first insulating layer, a first wiring layer disposed on the first insulating layer, and a first insulating film disposed on the first insulating layer, the first insulating film covering at least a portion of each of an upper surface and a side surface of the first wiring layer and conforming to a shape of the first wiring layer. The first insulating layer has a first recess around the first wiring layer. A depth of the first recess is greater than 0 µm and less than 1.0 µm.

Description

[0001] This application claims the benefit of priority to Korean Patent Application No. 10-2025-0023889, filed on February 24, 2025, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to a printed circuit board. Background Technology

[0003] Recently, technologies for placing multiple semiconductor chips on Si interposers and connecting them via high-density interconnects have been actively developed. However, in the case of Si interposers, semiconductor technologies such as through-silicon vias (TSVs) can typically be applied, which can lead to high process costs. To address this issue, embedding Si bridging elements within the package substrate has been proposed to reduce process ratios (e.g., reduce process complexity). However, even in this case, from a cost perspective, it may only be suitable for high-cost electronic devices. Therefore, a new packaging technology is needed that can achieve high-density interconnects between chips while reducing costs. Summary of the Invention

[0004] One aspect of this disclosure is to provide a printed circuit board that can reduce costs and achieve a fine wiring substrate with excellent reliability.

[0005] According to one aspect of this disclosure, a printed circuit board is provided, the printed circuit board comprising: a first insulating layer, a first wiring layer disposed on the first insulating layer, and a first insulating film disposed on the first insulating layer, the first insulating layer having a first region and a second region, the first insulating film covering at least a portion of each of the upper surface and side surface of the first wiring layer and conforming to the shape of the first wiring layer. The first insulating layer may have a first recess surrounding the first wiring layer. The depth of the first recess may be greater than 0 μm and less than 1.0 μm.

[0006] According to another aspect of this disclosure, a printed circuit board is provided, the printed circuit board comprising: a first insulating layer, a plurality of wirings disposed on the first insulating layer, and an insulating film disposed on the first insulating layer, the first insulating layer having a first region and a second region, the insulating film covering each of the plurality of wirings and conforming to the shape of each of the plurality of wirings. Each of the plurality of wirings may include a first metal portion and a second metal portion disposed on the first metal portion, the second metal portion being thicker than the first metal portion. In cross-section, the width of the first metal portion may be greater than the width of the second metal portion. The first insulating layer may have a recess between the first metal portions of at least two adjacent wirings of the plurality of wirings.

[0007] According to exemplary embodiments of this disclosure, printed circuit boards can reduce costs and achieve fine wiring substrates with excellent reliability. Attached Figure Description

[0008] The above and other aspects, features and advantages of this disclosure will become clearer from the following detailed embodiments, taken in conjunction with the accompanying drawings, in which: Figure 1 This is a schematic block diagram of an example electronic device system; Figure 2 This is a schematic cross-sectional view of an example of a printed circuit board; Figure 3 and Figure 4 yes Figure 2 A schematic cross-sectional view illustrating the manufacturing process of a printed circuit board; Figure 5 This is a schematic cross-sectional view of another example of a printed circuit board; Figure 6 yes Figure 5 A schematic cross-sectional view of an implementation example of region A of a printed circuit board; Figure 7 yes Figure 5 A schematic cross-sectional view of an implementation example of region B of a printed circuit board; Figure 8 This is a schematic cross-sectional view of an example of a semiconductor package; and Figure 9 This is a schematic cross-sectional view of another example of a semiconductor package. Detailed Implementation

[0009] The present disclosure will be described below with reference to the accompanying drawings. In the drawings, for clarity, the shape, size, etc., of the components may be exaggerated or reduced.

[0010] Figure 1 This is a schematic block diagram of an example electronic device system.

[0011] Reference Figure 1 Electronic device 1000 can house motherboard 1010. Chip-related components 1020, network-related components 1030, and other components 1040 can be physically and / or electrically connected to motherboard 1010. These electronic components can be connected to other electronic components described below via various signal lines 1090.

[0012] Chip-related components 1020 may include: memory chips, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM) or flash memory); application processor chips, such as central processing units (e.g., central processing units (CPUs)), graphics processors (e.g., graphics processing units (GPUs)), digital signal processors, encryption processors, microprocessors, or microcontrollers; and logic chips, such as analog-to-digital converters or application-specific integrated circuits (ASICs). However, chip-related components 1020 are not limited to these and may include other types of chip-related components. Furthermore, chip-related components 1020 may be combined with each other. Chip-related components 1020 may be in the form of a package including the aforementioned chips and / or electronic components.

[0013] Network-related components 1030 may include components compatible with or operating according to protocols such as: Wi-Fi (IEEE 802.11 series, etc.), WiMAX (IEEE 802.16 series, etc.), IEEE 802.20, LTE, Ev-DO, HSPA+, HSDPA+, HSUPA+, GSM+, EDGE+, GPS, GPRS, CDMA, TDMA, DECT, Bluetooth. ® The network-related component 1030 may include wireless local area networks (WLANs), third-generation mobile communication technology (3G) protocols, fourth-generation mobile communication technology (4G) protocols, and fifth-generation mobile communication technology (5G) protocols, as well as any other wireless and wired protocols specified after the aforementioned protocols. However, the network-related component 1030 is not limited to these and may also include components compatible with or operating according to various other wireless or wired standards or protocols. Furthermore, the network-related component 1030 may be combined with the aforementioned chip-related component 1020.

[0014] Other components 1040 may include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, low-temperature co-fired ceramic (LTCC) components, electromagnetic interference (EMI) filters, multilayer ceramic capacitors (MLCCs), etc. However, other components 1040 are not limited to these and may also include passive components for various other purposes. Furthermore, other components 1040 may be combined with the aforementioned chip-related components 1020 and / or network-related components 1030.

[0015] Depending on the type of electronic device 1000, it may include other electronic components that are physically and / or electrically connected to the motherboard 1010 or not physically and / or electrically connected to the motherboard 1010. These other electronic components may include, for example, a camera 1050, an antenna 1060, a display 1070, a battery 1080, etc. However, these other electronic components are not limited to these and may include audio codecs, video codecs, power amplifiers, compasses, accelerometers, gyroscopes, speakers, mass storage units (e.g., hard disk drives), optical discs (CDs), digital versatile discs (DVDs), etc. Furthermore, depending on the type of electronic device 1000, it may also include other electronic components for various purposes.

[0016] Electronic device 1000 can be a smartphone, personal digital assistant (PDA), digital camera, digital video camera, network system, computer, monitor, tablet PC, laptop PC, netbook PC, television, video game console, smartwatch, automotive component, etc. However, electronic device 1000 is not limited to these and can be any other electronic device used for processing data.

[0017] Figure 2 This is a schematic cross-sectional view of an example printed circuit board.

[0018] Reference Figure 2The printed circuit board 100A according to the example may include: a plurality of insulating layers 111, 112, 113, 114 and 115; a plurality of wiring layers 121, 122, 123 and 124 disposed in the plurality of insulating layers 111, 112, 113, 114 and 115 respectively; and a plurality of insulating films 131, 132, 133 and 134 disposed between the plurality of insulating layers 111, 112, 113, 114 and 115 respectively. 32, 133, and 134 respectively cover at least a portion of the plurality of wiring layers 121, 122, 123, and 124 and conform to the shape of the plurality of wiring layers 121, 122, 123, and 124; and a plurality of via layers 141, 142, and 143 are respectively disposed in the plurality of insulating layers 111, 112, 113, 114, and 115, the plurality of via layers 141, 142, and 143 connecting the plurality of wiring layers 121, 122, 123, and 124 to each other. For example, the printed circuit board 100A may have a coreless multilayer substrate structure, but this disclosure is not limited thereto. As needed, the printed circuit board 100A according to the example may have a low-layer substrate structure including only one insulating layer and one wiring layer or including two insulating layers and / or two wiring layers. In addition, as needed, a core layer and / or a stacked layer may be disposed on the underside of the plurality of insulating layers 111, 112, 113, 114, and 115.

[0019] Each of the plurality of insulating layers 111, 112, 113, 114, and 115 may comprise a photosensitive organic insulating material. For example, each of the plurality of insulating layers 111, 112, 113, 114, and 115 may comprise one or more of polyimide resins, phenolic resins, and polybenzoxazole resins. In this case, the patterning process is simpler and more cost-effective compared to silicon interposers or silicon bridges according to the prior art. Furthermore, at least some of the plurality of wiring layers 121, 122, 123, and 124 and the plurality of via layers 141, 142, and 143 formed in the plurality of insulating layers 111, 112, 113, 114, and 115 can be formed with high-density wiring and / or fine pitch. Therefore, a fine wiring substrate can be provided, and the fine wiring substrate can be easily applied to the interposer. Therefore, for example, the printed circuit board 100A can be used to manufacture intermediaries for various applications in high-performance artificial intelligence (AI) and networking, such as central processing units (CPUs), graphics processing units (GPUs), and tensor processing units (TPUs), for example, chip-on-wafer-on-substrate (CoWoS) and high-bandwidth memory (HBM). Furthermore, the printed circuit board 100A can also be readily used in interconnect bridges; for example, the printed circuit board 100A can be embedded in a package substrate for chip-to-chip connections.

[0020] Each of the plurality of insulating films 131, 132, 133, and 134 may comprise an inorganic insulating material. For example, each of the plurality of insulating films 131, 132, 133, and 134 may comprise one or more of silicon nitrides (such as silicon nitride), aluminum nitrides (such as aluminum nitride), boron nitrides (such as boron nitride), aluminum oxides (such as aluminum oxide), and silicon oxides (such as silicon oxide). In this case, an inorganic insulating film can be formed on the surface of the fine wiring substrate, thereby easily preventing moisture penetration even under high temperature and high humidity environments (such as unbiased high accelerated stress testing (uHAST) and biased high accelerated stress testing (bHAST)). Therefore, stable electrical performance can be maintained without migration of fine wiring. Therefore, the plurality of insulating films 131, 132, 133, and 134 can be readily applied to various types of packaged fine wiring substrates requiring high reliability. Multiple insulating films 131, 132, 133, and 134 may be formed on both multiple insulating layers 111, 112, 113, 114, and 115 and multiple wiring layers 121, 122, 123, and 124, but this disclosure is not limited thereto. The multiple insulating films 131, 132, 133, and 134 may be selectively formed only on layers requiring high reliability.

[0021] Multiple insulating layers 111, 112, 113, and 114 may have multiple recesses r1, r2, r3, and r4. For example, the first insulating layer 111 may have a first recess r1 surrounding the first wiring layer 121, the second insulating layer 112 may have a second recess r2 surrounding the second wiring layer 122, the third insulating layer 113 may have a third recess r3 surrounding the third wiring layer 123, and the fourth insulating layer 114 may have a fourth recess r4 surrounding the fourth wiring layer 124. For example, the upper surface of the region where the first wiring layer 121 is disposed in the first insulating layer 111 and the upper surface of the region where the first wiring layer 121 is not disposed in the first insulating layer 111 may have a stepped portion corresponding to the first recess r1; the upper surface of the region where the second wiring layer 122 is disposed in the second insulating layer 112 and the upper surface of the region where the second wiring layer 122 is not disposed in the second insulating layer 112 may have a stepped portion corresponding to the second recess r2; the upper surface of the region where the third wiring layer 123 is disposed in the third insulating layer 113 and the upper surface of the region where the third wiring layer 123 is not disposed in the third insulating layer 113 may have a stepped portion corresponding to the third recess r3; and the upper surface of the region where the fourth wiring layer 124 is disposed in the fourth insulating layer 114 and the upper surface of the region where the fourth wiring layer 124 is not disposed in the fourth insulating layer 114 may have a stepped portion corresponding to the fourth recess r4. Here, the term "stepped portion" may refer to a sudden change in surface height or a difference in the thickness, height, or vertical / horizontal dimension of a layer (such as an insulating layer). For example, as described below, each of the first wiring layer 121, the second wiring layer 122, the third wiring layer 123, and the fourth wiring layer 124 may include a seed metal layer formed by a deposition process, for example, a portion of the seed metal layer including titanium may be selectively removed by dry etching. In this process, a portion of the first insulating layer 111, a portion of the second insulating layer 112, a portion of the third insulating layer 113, and a portion of the fourth insulating layer 114 may be removed, thereby forming a first recess r1, a second recess r2, a third recess r3, and a fourth recess r4. In this case, the contact area between the plurality of insulating layers 111, 112, 113, 114, and 115 and the plurality of insulating films 131, 132, 133, and 134 may be increased, thus further improving reliability. The outermost fifth insulating layer 115 may not have a recess, but this disclosure is not limited thereto. The outermost fifth insulating layer 115 may have a recess if desired.

[0022] Multiple insulating films 131, 132, 133 and 134 can conformally cover multiple wiring layers 121, 122, 123 and 124 and / or multiple recesses r1, r2, r3 and r4 with substantially constant thickness. For example, the first insulating film 131 may cover at least a portion of each of the upper surface and side surface of the first wiring layer 121 and at least a portion of each of the lower surface and side surface of the first recess r1 and conform to the shape of the first wiring layer 121 and the first recess r1; the second insulating film 132 may cover at least a portion of each of the upper surface and side surface of the second wiring layer 122 and at least a portion of each of the lower surface and side surface of the second recess r2 and conform to the shape of the second wiring layer 122 and the second recess r2; the third insulating film 133 may cover at least a portion of each of the upper surface and side surface of the third wiring layer 123 and at least a portion of each of the lower surface and side surface of the third recess r3 and conform to the shape of the third wiring layer 123 and the third recess r3; and the fourth insulating film 134 may cover at least a portion of each of the upper surface and side surface of the fourth wiring layer 124 and at least a portion of each of the lower surface and side surface of the fourth recess r4 and conform to the shape of the fourth wiring layer 124 and the fourth recess r4. In this case, it is easier to achieve reliability improvements.

[0023] The thickness of each of the plurality of insulating films 131, 132, 133, and 134 may be less than the depth of each of the plurality of recesses r1, r2, r3, and r4. For example, the thickness of the first insulating film 131 may be less than the depth of the first recess r1, the thickness of the second insulating film 132 may be less than the depth of the second recess r2, the thickness of the third insulating film 133 may be less than the depth of the third recess r3, and the thickness of the fourth insulating film 134 may be less than the depth of the fourth recess r4. For example, each of the plurality of recesses r1, r2, r3, and r4 may have a depth greater than 0 μm and less than 1.0 μm or greater than 0.01 μm and less than 0.5 μm, and the thickness of each of the plurality of insulating films 131, 132, 133, and 134 may be greater than 10 μm. And less than 10000 The thickness of each of the plurality of recesses r1, r2, r3, and r4 is less than the thickness of each of the plurality of recesses r1, r2, r3, and r4. As described, the plurality of recesses r1, r2, r3, and r4 can be formed with a smaller depth, and the plurality of insulating films 131, 132, 133, and 134 can be formed with a smaller thickness. In this case, reliability can be improved more effectively while minimizing other negative effects such as undulation.

[0024] Multiple wiring layers 121, 122, 123, and 124 may include one or more wirings W1, W2, W3, and W4. For example, the first wiring layer 121 and the third wiring layer 123 may each include one or more first wirings W1 and one or more third wirings W3, respectively, and the second wiring layer 122 and the fourth wiring layer 124 may each include multiple second wirings W2 and multiple fourth wirings W4. In this case, the multiple second wirings W2 and multiple fourth wirings W4 may be relatively finer wirings compared to one or more first wirings W1 and one or more third wirings W3, respectively. For example, the line width, spacing, etc., of the wirings may be further reduced. For example, the multiple wiring layers 121, 122, 123, and 124 may have a structure in which the second wiring layer 122 and the fourth wiring layer 124, including high-density wiring, and the first wirings W1 and the third wirings W3, including low-density wiring, are alternately arranged in the stacking direction. In this case, grounding can be provided on the upper and lower parts of the fine wiring to effectively prevent electromagnetic interference.

[0025] Multiple routing layers 121, 122, 123, and 124 may include multiple pads P1, P2, P3, and P4. Additionally, multiple via layers 141, 142, and 143 may include multiple connection vias V1, V2, and V3 connecting the multiple pads P1, P2, P3, and P4 to each other. For example, a first via layer 141 may include a first connection via V1 connecting the first pad P1 of the first routing layer 121 and the second pad P2 of the second routing layer 122 to each other; a second via layer 142 may include a second connection via V2 connecting the second pad P2 of the second routing layer 122 and the third pad P3 of the third routing layer 123 to each other; and a third via layer 143 may include a third connection via V3 connecting the third pad P3 of the third routing layer 123 and the fourth pad P4 of the fourth routing layer 124 to each other. In this configuration, the region of the first pad P1 connected to the first connection via V1 may have a first groove g1, the region of the second pad P2 connected to the second connection via V2 may have a second groove g2, and the region of the third pad P3 connected to the third connection via V3 may have a third groove g3. For example, as described below, a via hole for one of the corresponding one of the first connection via V1, second connection via V2, and third connection via V3 may be formed in each of the second insulating layer 112, the third insulating layer 113, and the fourth insulating layer 114. Then, the first insulating film 131, the second insulating film 132, and the third insulating film 133, along with other metal oxide films (byproducts occurring during the manufacturing process), in the via hole can be removed by dry etching or the like, thereby exposing the first pad P1, the second pad P2, and the third pad P3. In this process, a portion of each of the first pad P1, the second pad P2, and the third pad P3 may be removed to form the first groove g1, the second groove g2, and the third groove g3 in the first pad P1, the second pad P2, and the third pad P3, respectively. The first connecting via V1, the second connecting via V2, and the third connecting via V3 can respectively fill the first groove g1, the second groove g2, and the third groove g3, and each of the first insulating film 131, the second insulating film 132, and the third insulating film 133 can contact the side surface of a corresponding one of the first connecting via V1, the second connecting via V2, and the third connecting via V3. In this case, the contact area between the first connecting via V1, the second connecting via V2, and the third connecting via V3 and the first pad P1, the second pad P2, and the third pad P3 can be increased, thus further improving reliability.

[0026] As needed, the printed circuit board 100A according to the example may further include: an outermost wiring layer 125 disposed on the uppermost fifth insulating layer 115 among a plurality of insulating layers 111, 112, 113, 114, and 115; and an outermost via layer 144 disposed in the uppermost fifth insulating layer 115, the outermost via layer 144 connecting the uppermost fourth wiring layer 124 among a plurality of wiring layers 121, 122, 123, and 124 to the outermost wiring layer 125. The outermost wiring layer 125 may include a plurality of external connection pads P5. The outermost via layer 144 may include a fourth connection via V4 connecting the fourth pad P4 and the external connection pads P5 to each other. In this case, the region of the fourth pad P4 connected to the fourth connection via V4 may have a fourth groove g4. For example, as described below, a via hole for the fourth connection via V4 can be formed in the fifth insulating layer 115. The fourth insulating film 134 and other metal oxide films in this via hole can then be removed by dry etching or the like, thereby exposing the fourth pad P4. In this process, a portion of the fourth pad P4 can be removed, allowing a fourth groove g4 to be formed within the fourth pad P4. The fourth connection via V4 can fill the fourth groove g4, and the fourth insulating film 134 can contact the side surface of the fourth connection via V4. In this case, the contact area between the fourth connection via V4 and the fourth pad P4 can be increased, thus further improving reliability.

[0027] The structure shown in the accompanying drawings can be at least a portion of a substrate structure to which a printed circuit board 100A according to an example embodiment is applied. For example, as described above, the structure shown in the drawings can be further vertically extended by additionally forming a core layer or stacked layer. The structure shown in the drawings can also be further horizontally extended so that wiring or patterns embedded in the various insulating layers are not exposed to the outside.

[0028] In the following description, the components of the printed circuit board 100A according to an exemplary embodiment will be described in more detail with reference to the accompanying drawings.

[0029] The plurality of insulating layers 111, 112, 113, 114, and 115 may comprise organic insulating materials. The organic insulating materials may include photosensitive organic insulating materials. For example, the plurality of insulating layers 111, 112, 113, 114, and 115 may each comprise polyimide resins, phenolic resins, and / or polybenzoxazole resins, but this disclosure is not limited thereto. Other polymeric materials that can simplify the patterning process may also be used. The plurality of insulating layers 111, 112, 113, 114, and 115 may comprise substantially the same insulating material, but this disclosure is not limited thereto. The plurality of insulating layers 111, 112, 113, 114, and 115 may comprise different insulating materials as needed. There is no limitation on the number of insulating layers 111, 112, 113, 114, and 115.

[0030] Multiple wiring layers 121, 122, 123, and 124, as well as the outermost wiring layer 125, may each comprise metal. For example, the multiple wiring layers 121, 122, 123, and 124, as well as the outermost wiring layer 125, may each comprise a first metal portion and a second metal portion disposed on the first metal portion, the second metal portion being thicker than the first metal portion. The first metal portion may comprise a seed metal layer S, and the seed metal layer S may have a multilayer structure comprising a first layer and a second layer disposed on the first layer. The first layer may comprise titanium (Ti), tantalum (Ta), nickel (Ni), chromium (Cr), and / or molybdenum (Mo), and may preferably comprise titanium (Ti) for ease of dry etching, but this disclosure is not limited thereto. The second layer may comprise titanium (Ti), tantalum (Ta), nickel (Ni), chromium (Cr), copper (Cu), and / or molybdenum (Mo), and may preferably comprise copper (Cu) for ease of plating, but this disclosure is not limited thereto. The second metal portion may comprise a plating metal layer M, and the plating metal layer M may comprise a third layer. The third layer may include copper (Cu), aluminum (Al), nickel (Ni), tungsten (W), and / or molybdenum (Mo), and preferably includes copper (Cu) for ease of plating, but this disclosure is not limited thereto. The plurality of wiring layers 121, 122, 123, and 124, and the outermost wiring layer 125, may perform various functions according to their design. For example, the plurality of wiring layers 121, 122, 123, and 124, and the outermost wiring layer 125, may respectively include signal transmission patterns, power transmission patterns, and / or ground transmission patterns. The aforementioned patterns may have various pattern forms, such as lines, traces, planes, pads, etc. Pads may include solder pads. That is, the wiring W1, W2, W3, and W4 and pads P1, P2, P3, P4, and P5 of each of the plurality of wiring layers 121, 122, 123, and 124, and the outermost wiring layer 125, may have the various pattern forms described above, and the number of patterns is not limited. There is no limit to the number of wiring layers 121, 122, 123, and 124.

[0031] The plurality of insulating films 131, 132, 133, and 134 may comprise inorganic insulating materials. The inorganic insulating materials may comprise nitrides and / or oxides. For example, the plurality of insulating films 131, 132, 133, and 134 may comprise silicon nitrides (such as silicon nitride), aluminum nitrides (such as aluminum nitride), boron nitrides (such as boron nitride), aluminum oxides (such as aluminum oxide), and / or silicon oxides (such as silicon oxide), but this disclosure is not limited thereto. The plurality of insulating films 131, 132, 133, and 134 may comprise another inorganic insulating material capable of preventing moisture penetration in high-temperature and high-humidity environments and capable of being formed into a thin film. The plurality of insulating films 131, 132, 133, and 134 may comprise substantially the same insulating material, but this disclosure is not limited thereto. The plurality of insulating films 131, 132, 133, and 134 may comprise different insulating materials as needed. There is no limitation on the number of layers of the plurality of insulating films 131, 132, 133, and 134.

[0032] Multiple via layers 141, 142, and 143, as well as the outermost via layer 144, may each comprise metal. For example, the multiple via layers 141, 142, and 143, as well as the outermost via layer 144, may each comprise a third metal portion and a fourth metal portion disposed on the third metal portion, the third metal portion and the fourth metal portion filling the via holes. The third metal portion may include the aforementioned seed metal layer S, and the seed metal layer S may have a multilayer structure including a first layer and a second layer disposed on the first layer. The first layer may include titanium (Ti), tantalum (Ta), nickel (Ni), chromium (Cr), and / or molybdenum (Mo), and preferably includes titanium (Ti) for ease of dry etching, but this disclosure is not limited thereto. The second layer may include titanium (Ti), tantalum (Ta), nickel (Ni), chromium (Cr), copper (Cu), and / or molybdenum (Mo), and preferably includes copper (Cu) for ease of plating, but this disclosure is not limited thereto. The fourth metal portion may include the aforementioned plating metal layer M, and the plating metal layer M may include the third layer. The third layer may include copper (Cu), aluminum (Al), nickel (Ni), tungsten (W), and / or molybdenum (Mo), and preferably copper (Cu) for ease of plating, but this disclosure is not limited thereto. The connecting vias V1, V2, V3, and V4 of the plurality of via layers 141, 142, and 143 and the outermost via layer 144 may include signal transmission vias, power transmission vias, and / or ground transmission vias. The connecting vias V1, V2, V3, and V4 of the plurality of via layers 141, 142, and 143 and the outermost via layer 144 may have a tapered shape in the same direction. For example, in cross-section, the connecting vias V1, V2, V3, and V4 may have a tapered shape in which the upper width is greater than the lower width. There is no limitation on the number of connecting vias V1, V2, V3, and V4 of the plurality of via layers 141, 142, and 143 and the outermost via layer 144. There is no limit to the number of via layers 141, 142, and 143.

[0033] Figure 3 and Figure 4 yes Figure 2 A schematic cross-sectional view illustrating a manufacturing example of a printed circuit board.

[0034] Reference Figure 3 and Figure 4 First, a first insulating layer 111 can be formed on the carrier 210. Additionally, a first wiring layer 121, including a first wiring W1 and a first pad P1, can be formed on the first insulating layer 111. Furthermore, a first insulating film 131 covering the first insulating layer 111 and the first wiring layer 121 can be formed. For example, the first insulating layer 111 can be formed on the carrier 210 by coating or laminating a photosensitive organic insulating material. Furthermore, a seed metal layer S can be formed on the first insulating layer 111 by a deposition process. A plating metal layer M can be formed on the seed metal layer S using a dry film or the like by a plating process. The dry film can be removed, and the seed metal layer S in the area where the dry film has been removed can be removed sequentially by wet etching and dry etching to form the first wiring layer 121 including the first wiring W1 and the first pad P1. During the dry etching process, a first recess r1 can be formed in the first insulating layer 111. Additionally, a first insulating film 131 that substantially conformally covers the first wiring layer 121 and the first recess r1 can be formed by a deposition process of an inorganic insulating material or the like. The carrier 210 can be formed using various materials, such as a glass carrier, a silicon carrier, a polymer carrier, etc. In addition, a plurality of metal films 211 and 212 and a release layer 213 disposed between the plurality of metal films 211 and 212 can be disposed on the surface of the carrier 210, but this disclosure is not limited thereto.

[0035] Subsequently, a second insulating layer 112 covering the first insulating film 131 can be formed on the first insulating layer 111. Furthermore, a first via hole v1 can be formed in the second insulating layer 112. For example, the second insulating layer 112 can be formed on the first insulating layer 111 by coating or laminating an organic insulating material. Additionally, the first via hole v1 penetrating the second insulating layer 112 can be formed in the region corresponding to the first pad P1 of the first wiring layer 121 by an exposure process and a development process, etc.

[0036] Subsequently, the first insulating film 131 exposed through the first via hole v1 on the first pad P1 can be removed. For example, the first insulating film 131 and other metal oxides exposed through the first via hole v1 on the first pad P1 can be removed by dry etching or the like. During the dry etching process, a first groove g1 penetrating a portion of the upper side of the first pad P1 can be formed in the first pad P1.

[0037] Subsequently, a second wiring layer 122 including the second wiring W2 and the second pad P2, and a first via layer 141 including the first connection via V1, can be formed on and within the second insulating layer 112, respectively. For example, a seed metal layer S can be formed on the second insulating layer 112, the first via v1, and the first pad P1 exposed through the first via v1 by a deposition process. A plating metal layer M can be formed on the seed metal layer S using a plating process such as a dry film. The dry film can be removed, and the seed metal layer S in the area where the dry film has been removed can be removed sequentially by wet etching and dry etching, thereby forming the second wiring layer 122 including the second wiring W2 and the second pad P2, and the first via layer 141 including the first connection via V1. During the dry etching process, a second recess r2 can be formed in the second insulating layer 112. The first groove g1 of the first pad P1 can be filled through the first connection via V1.

[0038] Subsequently, a second insulating film 132 covering the second insulating layer 112 and the second wiring layer 122 can be formed. For example, the second insulating film 132 that substantially conformally covers the second wiring layer 122 and the second recess r2 can be formed by a deposition process of inorganic insulating material or the like.

[0039] Subsequently, a third insulating layer 113 covering the second insulating film 132 can be formed on the second insulating layer 112. Furthermore, a second via hole v2 can be formed in the third insulating layer 113. For example, the third insulating layer 113 can be formed on the second insulating layer 112 by coating or laminating an organic insulating material. Additionally, the second via hole v2 penetrating the third insulating layer 113 can be formed in the region corresponding to the second pad P2 of the second wiring layer 122 by an exposure process and a development process, etc.

[0040] Subsequently, the second insulating film 132 exposed through the second via hole v2 on the second pad P2 can be removed. For example, the second insulating film 132 and other metal oxides exposed through the second via hole v2 on the second pad P2 can be removed by dry etching or the like. During the dry etching process, a second groove g2 penetrating a portion of the upper side of the second pad P2 can be formed in the second pad P2.

[0041] Subsequently, a third wiring layer 123, including a third wiring W3 and a third pad P3, and a second via layer 142, including a second connection via V2, can be formed on and within the third insulating layer 113. Additionally, a third recess r3 can be formed in the third insulating layer 113. The detailed description is substantially the same as the description of forming a second wiring layer 122, including a second wiring W2 and a second pad P2, and a first via layer 141, including a first connection via V1, on and within the second insulating layer 112.

[0042] Subsequently, the above-described deposition process can be performed substantially repeatedly to further form the desired deposition layers. For example, a fourth insulating layer 114, a fourth wiring layer 124 including a fourth wiring W4 and a fourth pad P4, a third via v3, a third via layer 143 including a third connecting via V3, a third trench g3, a fourth insulating film 134, and a fourth recess r4 can be further formed. Thereafter, a fifth insulating layer 115, an outermost wiring layer 125 including an outer connecting pad P5, a fourth via v4, an outermost via layer 144 including a fourth connecting via V4, and a fourth trench g4 can be further formed using a similar process.

[0043] Subsequently, the carrier 210 can be removed. For example, the release layer 213 can be used to separate the plurality of metal films 211 and 212 on the surface of the carrier 210 from each other, and the metal films 212 remaining on the board can be removed by etching, but this disclosure is not limited thereto. The printed circuit board 100A according to the example can be manufactured through a series of processes. Other descriptions are substantially the same as those for the printed circuit board 100A according to the example.

[0044] Figure 5 This is a schematic cross-sectional view of another example of a printed circuit board.

[0045] Figure 6 yes Figure 5 A schematic cross-sectional view of an implementation example of region A of a printed circuit board.

[0046] Figure 7 yes Figure 5 A schematic cross-sectional view of an implementation example of region B of a printed circuit board.

[0047] Reference Figures 5 to 7Compared to the printed circuit board 100A according to the example, in the printed circuit board 100B according to another example, the area on which the seed metal layer S is disposed on the side surface of each of the plurality of wiring layers 121, 122, 123, and 124 may protrude further outward relative to the remaining area of ​​the side surface of each of the plurality of wiring layers 121, 122, 123, and 124. For example, the side surface of each of the wirings W1, W2, W3, and W4 and / or pads P1, P2, P3, and P4 of the plurality of wiring layers 121, 122, 123, and 124 may have a stepped portion. For example, the second wiring layer 122 may include a plurality of second wirings W2 disposed on the second insulating layer 112, and each of the plurality of second wirings W2 may include a first metal portion PM1 and a second metal portion PM2 disposed on the first metal portion PM1, the second metal portion PM2 being thicker than the first metal portion PM1. In this case, in cross-section, the first metal portion PM1 may have a width greater than the width of the second metal portion PM2. Here, for example, a cross-section may refer to a cross-section obtained by cutting along the thickness direction of the printed circuit board 100A or the stacking direction of multiple layers, but is not limited thereto; a cross-section may also refer to a cross-section obtained by cutting along the horizontal direction of the printed circuit board 100A. The second insulating layer 112 may have a second recess r2 between the first metal portions PM1 of at least two adjacent wirings W2 in a plurality of second wirings W2. Therefore, the upper surface of the region of the second insulating layer 112 in which the plurality of second wirings W2 are disposed and the upper surface of the region in which the plurality of second wirings W2 are not disposed may have a stepped portion corresponding to the second recess r2. The second insulating film 132 may cover the plurality of second wirings W2 and the second recess r2 and conform to the shape of the plurality of second wirings W2 and the second recess r2.

[0048] The first metal portion PM1 may include a seed metal layer S, which includes a first layer comprising titanium (Ti) and a second layer disposed on the first layer, the second layer comprising copper (Cu). The second metal portion PM2 may include a plating metal layer M, which includes a third layer comprising copper (Cu), the third layer being thicker than each of the first and second layers. In this case, when the second layer of the seed metal layer S is removed by wet etching, the second layer may be partially retained at the lower end of each of the plurality of second wirings W2. Therefore, when the first layer is subsequently removed by dry etching, the first layer may also be partially retained due to the partially retained second layer. As a result, the side surface of each of the plurality of second wirings W2 on the second insulating layer 112 may have a stepped portion. In this case, the seed metal layer S (specifically, the first layer which may include titanium) may be retained at the lower end of each of the plurality of second wirings W2. Therefore, in a high temperature and high humidity environment, the migration path of fine wirings due to moisture can be extended, which can delay moisture penetration into the wiring. As a result, reliability can be further improved.

[0049] Other descriptions are substantially the same as those for the printed circuit board 100A according to the example. Additionally, in the manufacturing example of the printed circuit board 100A according to the example, a printed circuit board 100B according to another example can be manufactured when stepped portions are formed on the side surfaces of each of the wirings W1, W2, W3, and W4 of the plurality of wiring layers 121, 122, 123, and 124 and / or pads P1, P2, P3, and P4.

[0050] Figure 8 This is a schematic cross-sectional view of an example of a semiconductor package.

[0051] Reference Figure 8 The semiconductor package 500 according to the example may include a package substrate 250 and a first semiconductor chip 410 and a second semiconductor chip 420 mounted on the package substrate 250. A bridging substrate 260 including fine wiring interconnecting the first semiconductor chip 410 and the second semiconductor chip 420 may be embedded in the package substrate 250. The bridging substrate 260 may include at least one of the aforementioned printed circuit boards 100A and 100B as an internal structure. The package substrate 250 may be a multilayer printed circuit board according to the prior art, and its specific structure is not limited. As needed, at least one of the aforementioned printed circuit boards 100A and 100B may be included as an internal structure of the package substrate 250. Each of the first semiconductor chip 410 and the second semiconductor chip 420 may be a memory chip, an application processor chip, and / or a logic chip. The first semiconductor chip 410 and the second semiconductor chip 420 may be chips of the same type or chips of different types. Other descriptions may be substantially the same as those described above, and their repetition will be omitted.

[0052] Figure 9 This is a schematic cross-sectional view of another example of a semiconductor package.

[0053] Reference Figure 9According to another example, a semiconductor package 600 may include a package substrate 300 and a first semiconductor chip 410 and a second semiconductor chip 420 mounted on the package substrate 300. A fine wiring layer 310, including fine wiring interconnecting the first semiconductor chip 410 and the second semiconductor chip 420, may be disposed on the outermost side of the package substrate 300. The fine wiring layer 310 may include at least one of the printed circuit boards 100A and 100B described above. The package substrate 300 may be a multilayer printed circuit board according to the prior art, and its specific structure is not limited. As needed, at least one of the printed circuit boards 100A and 100B described above may be included as an internal structure of the package substrate 300. Each of the first semiconductor chip 410 and the second semiconductor chip 420 may be a memory chip, an application processor chip, and / or a logic chip. The first semiconductor chip 410 and the second semiconductor chip 420 may be chips of the same type or chips of different types. Other descriptions may be substantially the same as those described above, and repeated descriptions are omitted.

[0054] As used herein, the term "cover" can include not only complete coverage but also partial coverage, and not only direct coverage but also indirect coverage. Furthermore, the term "fill" can include not only complete filling but also partial filling and substantial filling. For example, the term can include situations where gaps, holes, etc., are present. Furthermore, the term "surround" can include not only complete surrounding but also partial surrounding and substantial surrounding. Furthermore, the term "expose" can include not only exposing the entire structure but also exposing a portion of the structure, and the term "expose" can mean exposing another component from which a component is buried. For example, an opening in an exposed pad can expose the pad from the outermost insulating layer, and a surface treatment layer, etc., can be further disposed on the exposed pad.

[0055] As used herein, "basically" can be defined to include process errors, positional deviations, measurement errors, etc., that occur during the manufacturing process. For example, "set at substantially the same height" can include not only cases where "set at exactly the same position" but also cases where "set at approximately the same position." Similarly, "basically having a specific shape" can include not only cases where "completely having a specific shape" but also cases where "approximately having a specific shape." For example, such a determination can be based on the overall shape. Furthermore, "the same insulating material" can mean not only exactly the same insulating material but also the same type of insulating material. Therefore, the composition of the insulating material can be substantially the same, but its specific composition ratio can vary slightly.

[0056] As used herein, cross-sectional shape can refer to the shape of an object when it is vertically cut, or the shape of an object when viewed in a side view. Additionally, planar shape can refer to the shape of an object when it is horizontally cut, or the shape of an object when viewed in a top or bottom view.

[0057] As used herein, for convenience, "upper" in terms such as upper side, upper part, upper surface, etc., indicates the upward direction of the cross-section based on the drawings, and "lower" in terms such as lower side, lower part, lower surface, etc., indicates the opposite direction. However, the above directions are defined for ease of description. Therefore, it should be understood that the scope of the claims is not specifically limited by the above directions, and the concepts of "upper" and "lower" may be changed at any time.

[0058] As used herein, the term "connection" can refer not only to a "direct connection" but also to an "indirect connection" such as through an adhesive layer. The term "electrical connection" can include cases where components are "physically connected" and cases where components are "not physically connected." Furthermore, the terms "first," "second," etc., are used to distinguish one component from another and may not imply any particular order and / or importance, or other order and / or importance related to the components. In some cases, without departing from the scope of the exemplary embodiments, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component.

[0059] As used herein, thickness, width, length, depth, linewidth, spacing, pitch, distance, and surface roughness can be measured using a scanning electron microscope or optical microscope based on a cross-section obtained by polishing or cutting the printed circuit board. The cross-section can be vertical or horizontal, and each value can be measured based on the desired cross-section. When the values ​​measured for the printed circuit board are not constant, the values ​​for the printed circuit board can be determined as the average of the values ​​measured at any five points.

[0060] As used herein, the term "example" does not mean the same example implementation and is provided to emphasize distinct features. However, the examples presented above do not preclude implementations in combination with features from other examples. For example, if a particular feature is described in one example but not in another, it may still be understood to apply to the other example unless there is an explicit contradiction or inconsistency with what is described in that other example.

[0061] The terminology used herein describes specific examples only, and this disclosure is not limited thereto. As used herein, unless the context clearly indicates otherwise, the singular form is intended to include the plural form as well.

Claims

1. A printed circuit board, comprising: The first insulating layer has a first region and a second region; The first wiring layer is disposed on the first insulating layer; as well as A first insulating film is disposed on the first insulating layer, the first insulating film covering at least a portion of each of the upper surface and side surfaces of the first wiring layer and conforming to the shape of the first wiring layer. Wherein, the first insulating layer has a first recess surrounding the first wiring layer, and The depth of the first recess is greater than 0 μm and less than 1.0 μm.

2. The printed circuit board as claimed in claim 1, wherein, The first wiring layer is disposed only on the first region of the first insulating layer, and The upper surface of the first region of the first insulating layer and the upper surface of the second region of the first insulating layer have stepped portions corresponding to the first recess.

3. The printed circuit board as claimed in claim 1, wherein, The first insulating film also covers at least a portion of the lower surface and side surface of each of the first recess and conforms to the shape of the first recess, and The thickness of the first insulating film is less than the depth of the first recess.

4. The printed circuit board of claim 1, further comprising: A second insulating layer is disposed on the first insulating layer and has a third region and a fourth region, the second insulating layer covering the first insulating film; The second wiring layer is disposed on the second insulating layer; A second insulating film is disposed on the second insulating layer, the second insulating film covering at least a portion of each of the upper surface and side surface of the second wiring layer and conforming to the shape of the second wiring layer; as well as A first via layer is disposed between the first wiring layer and the second wiring layer, and the first via layer penetrates the first insulating layer. The second insulating layer has a second recess surrounding the second wiring layer.

5. The printed circuit board as claimed in claim 4, wherein, The second wiring layer is disposed only on the third region of the second insulating layer, and The upper surface of the third region of the second insulating layer and the upper surface of the fourth region of the second insulating layer have stepped portions corresponding to the second recess.

6. The printed circuit board as claimed in claim 4, wherein, The second insulating film also covers at least a portion of the lower surface and side surface of each of the second recess and conforms to the shape of the second recess, and The thickness of the second insulating film is less than the depth of the second recess.

7. The printed circuit board as claimed in claim 4, wherein, The first insulating layer and the second insulating layer each comprise a photosensitive organic insulating material, and The first insulating film and the second insulating film each comprise inorganic insulating materials.

8. The printed circuit board of claim 7, wherein: The photosensitive organic insulating material includes one or more of polyimide resins, phenolic resins, and polybenzoxazole resins, and The inorganic insulating material includes one or more of silicon nitride, aluminum nitride, boron nitride, aluminum oxide, and silicon oxide.

9. The printed circuit board as claimed in claim 4, wherein: The first wiring layer, the second wiring layer, and the first via layer each include a seed metal layer, and The seed metal layer includes a first layer and a second layer disposed on the first layer, wherein the first layer includes titanium and the second layer includes copper.

10. The printed circuit board of claim 9, wherein, The area on the side surface of each of the first wiring layer and the second wiring layer where the seed metal layer is disposed protrudes further outward relative to the remaining area of ​​the side surface of each of the first wiring layer and the second wiring layer.

11. The printed circuit board of claim 4, wherein: The first wiring layer includes a plurality of first wirings. The second wiring layer includes one or more second wirings, and The plurality of first wirings are finer than the one or more second wirings.

12. The printed circuit board of claim 4, wherein: The first wiring layer and the second wiring layer each include a first pad and a second pad. The first via layer includes connection vias that connect the first pad and the second pad to each other. The area of ​​the first pad that connects to the connecting via has a groove, and The connecting via fills the groove.

13. The printed circuit board of claim 12, wherein, The first insulating film is in contact with the side surface of the connection via.

14. The printed circuit board of claim 4, wherein the printed circuit board comprises: Multiple insulating layers; Multiple wiring layers are respectively disposed in the multiple insulating layers; Multiple insulating films are disposed between the multiple insulating layers, and the multiple insulating films respectively cover at least a portion of the multiple wiring layers and conform to the shape of the multiple wiring layers; as well as Multiple via layers are respectively disposed in the multiple insulating layers, and the multiple via layers respectively connect the multiple wiring layers to each other. The plurality of insulating layers include the first insulating layer and the second insulating layer. The plurality of wiring layers includes the first wiring layer and the second wiring layer. The plurality of insulating films include the first insulating film and the second insulating film, and The plurality of via layers includes the first via layer.

15. The printed circuit board of claim 14, further comprising: The outermost wiring layer is disposed on the uppermost insulating layer among the plurality of insulating layers; as well as The outermost via layer is disposed within the uppermost insulating layer, and the outermost via layer connects the uppermost wiring layer and the outermost wiring layer among the plurality of wiring layers. The outermost wiring layer includes multiple external connection pads.

16. A printed circuit board, comprising: The first insulating layer has a first region and a second region; Multiple wirings are disposed on the first insulating layer; as well as An insulating film is disposed on the first insulating layer, the insulating film covering each of the plurality of wires and conforming to the shape of each of the plurality of wires. Each of the plurality of wirings includes a first metal portion and a second metal portion disposed on the first metal portion, wherein the second metal portion is thicker than the first metal portion. In the cross-section, the width of the first metal portion is greater than the width of the second metal portion, and The first insulating layer has a recess, which is disposed between the first metal portions of at least two adjacent wires in the plurality of wires.

17. The printed circuit board of claim 16, wherein: The first metal portion includes a first layer and a second layer disposed on the first layer, wherein the first layer includes titanium and the second layer includes copper. The second metal portion includes a third layer, the third layer comprising copper, and The third layer is thicker than each of the first and second layers.

18. The printed circuit board of claim 16, wherein, The plurality of wirings are disposed only in the first region of the first insulation layer, and The upper surface of the first region of the first insulating layer and the upper surface of the second region of the first insulating layer have stepped portions corresponding to the recesses.

19. The printed circuit board of claim 16, wherein: The insulating film covers at least a portion of the recess and conforms to the shape of the recess, and The thickness of the insulating film is less than the depth of the recess.

20. The printed circuit board of claim 16, further comprising: A second insulating layer is disposed on the first insulating layer, and the second insulating layer covers at least a portion of the insulating film. The first insulating layer and the second insulating layer each comprise a photosensitive organic insulating material, wherein the photosensitive organic insulating material comprises one or more of polyimide resins, phenolic resins, and polybenzoxazole resins. The insulating film comprises an inorganic insulating material, which includes one or more of silicon nitride, aluminum nitride, boron nitride, aluminum oxide, and silicon oxide.

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