Semiconductor etching process predictive control method, system, medium, program product and terminal

Abstract

The application provides a semiconductor etching process prediction control method, system, medium, program product and terminal. The application realizes accurate control of etching morphology, improves process efficiency and stability by acquiring and analyzing in-situ process parameters and finished measurement data of a front film deposition process in real time, constructing a high-precision etching morphology prediction model, and adaptively adjusting etching process parameters before the etching process starts. The application can break down the barriers between processes and realize forward-looking optimization control of the subsequent process by using the data of the previous process.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to methods, systems, media, process products and terminals for predictive control of semiconductor etching processes. Background Technology

[0002] Currently, in advanced semiconductor manufacturing processes, thin film deposition (such as CVD (Chemical Vapor Deposition), PVD (Physical Vapor Deposition), and ALD (Atomic Layer Deposition)) and photolithography / etching are two key and closely linked process steps. The quality of thin film deposition directly affects the final morphology of subsequent etching processes. In current production processes, although both thin film and etching processes have independent Advanced Process Control (APC) systems, they are often isolated from each other. Existing technologies have the following shortcomings:

[0003] (1) Feedback lag: After the current thin film process is completed, key parameters such as film thickness, refractive index, and stress need to be obtained through offline measurement (such as SEM, OCD). This measurement data is usually used to determine whether the film is qualified, but it is rarely used directly and in real time to guide the formulation of the next etching process.

[0004] (2) Lack of forward-looking prediction: The parameters of the etching process (such as gas flow rate, power, pressure, and time) are usually executed based on a preset recipe and a single etching endpoint detection. It cannot know the precise characteristics of the thin film material to be etched in advance (such as slight thickness inhomogeneity, density changes, and compositional fluctuations), and therefore cannot cope with the etching morphology variations caused by fluctuations in the previous process (such as insufficient etching, over-etching, sidewall angle deviation, and micro-loading effects).

[0005] (3) Poor ability to handle variations: Differences between wafers or cavities can lead to small changes in film properties. When these changes accumulate in the etching process, they may cause significant etching morphology deviations, affecting product yield and consistency.

[0006] Therefore, it is necessary to provide a technical solution for optimizing and controlling semiconductor etching processes to solve the aforementioned problems in the existing technology. Summary of the Invention

[0007] In view of the shortcomings of the prior art, the present invention provides a semiconductor etching process prediction and control method, system, medium, program product and terminal to solve at least one of the technical problems in the prior art.

[0008] To achieve the above and other related objectives, a first aspect of this application provides a semiconductor etching process prediction and control method, comprising: acquiring in-situ process parameters and completion measurement data of a wafer to be etched after a front-end thin film deposition process; inputting the in-situ process parameters and completion measurement data into a pre-trained etching morphology prediction model to obtain predicted etching morphology features of the wafer to be etched; comparing the predicted etching morphology features of the wafer to be etched with target etching morphology features, adjusting the etching process parameters of the wafer to be etched according to the comparison result until the comparison result meets a preset accuracy requirement and the optimal etching process parameters are obtained; and performing an etching process on the wafer to be etched based on the optimal etching process parameters.

[0009] In some embodiments of the first aspect of this application, the predicted etching morphology features of the wafer to be etched are compared with the target etching morphology features. The etching process parameters of the wafer to be etched are adjusted according to the comparison results until the comparison results meet the preset accuracy requirements and the optimal etching process parameters are obtained. The specific process includes: comparing and calculating the predicted etching morphology features of the wafer to be etched with the target etching morphology features to obtain difference data; if the difference data does not meet the preset accuracy requirements, an optimization algorithm is used to solve the etching morphology prediction model. The objective function is to make the difference data between the predicted etching morphology features of the wafer to be etched and the target etching morphology features meet the preset accuracy requirements. The etching process parameters are adjusted through iterative calculation until the difference data meets the preset accuracy requirements and the iteration stops, thus obtaining the optimal etching process parameters.

[0010] In some embodiments of the first aspect of this application, the method further includes: obtaining the measured etching morphology features of the wafer to be etched after the etching process is performed, and updating and retraining the etching morphology prediction model based on the measured etching morphology features of the wafer to be etched, the in-situ process parameters and completion measurement data after the front-end thin film deposition process is completed, and the optimal etching process parameters as feedback data.

[0011] In some embodiments of the first aspect of this application, the process of constructing the etching morphology prediction model includes: collecting historical in-situ process parameters and historical completion measurement data of each wafer after the thin film deposition process, as well as historical etching morphology features after the etching process, to construct a training sample dataset; using a machine learning algorithm, taking the historical in-situ process parameters and historical completion measurement data after the thin film deposition process as model input, and the historical etching morphology features after the etching process as model output, to construct an etching morphology prediction model that integrates the physical mechanism of the etching process; and using the training sample dataset to train the constructed etching morphology prediction model to obtain a pre-trained etching morphology prediction model.

[0012] In some embodiments of the first aspect of this application, the in-situ process parameters include at least one of temperature, pressure, gas flow rate, radio frequency power, spectrometer data, and impedance data; the finished measurement data includes at least one of film thickness, refractive index, stress, and uniformity.

[0013] In some embodiments of the first aspect of this application, the predicted etching morphology features include at least one of critical dimensions, sidewall angles, etching depth, selectivity, and roughness.

[0014] To achieve the above and other related objectives, a second aspect of this application provides a semiconductor etching process prediction and control system, comprising: a data acquisition module for acquiring in-situ process parameters and completion measurement data of a wafer to be etched after the completion of a front-end thin film deposition process; a feature prediction module for inputting the in-situ process parameters and completion measurement data into a pre-trained etching morphology prediction model to obtain predicted etching morphology features of the wafer to be etched; a parameter adjustment module for comparing the predicted etching morphology features of the wafer to be etched with target etching morphology features, adjusting the etching process parameters of the wafer to be etched according to the comparison result until the comparison result meets a preset accuracy requirement and the optimal etching process parameters are obtained; and a process execution module for executing an etching process on the wafer to be etched based on the optimal etching process parameters.

[0015] To achieve the above and other related objectives, a third aspect of this application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the semiconductor etching process predictive control method.

[0016] To achieve the above and other related objectives, a fourth aspect of this application provides a computer program product including computer program code, which, when run on a computer, enables the computer to implement the semiconductor etching process predictive control method.

[0017] To achieve the above and other related objectives, a fifth aspect of this application provides an electronic terminal, including a memory, a processor, and a computer program stored in the memory; the processor executes the computer program to implement the semiconductor etching process predictive control method.

[0018] As described above, the semiconductor etching process predictive control method, system, medium, program product, and terminal provided in this application have the following beneficial effects:

[0019] This application constructs a high-precision etching morphology prediction model by acquiring and analyzing in-situ process parameters and completion measurement data of the preceding thin film deposition process in real time. It then adaptively adjusts the etching process parameters before the etching process begins, thereby achieving precise control over the etching morphology and improving process efficiency and stability. This application breaks down inter-process barriers and utilizes preceding process data to achieve proactive optimization control of subsequent processes. Attached Figure Description

[0020] Figure 1 The diagram shown is a flowchart illustrating a predictive control method for semiconductor etching processes according to an embodiment of this application.

[0021] Figure 2 The diagram shown is a flowchart illustrating another semiconductor etching process predictive control method in one embodiment of this application.

[0022] Figure 3 The diagram shown is a schematic representation of a semiconductor etching process predictive control system according to an embodiment of this application.

[0023] Figure 4 The diagram shown is a structural schematic of an electronic terminal according to an embodiment of this application. Detailed Implementation

[0024] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, unless otherwise specified, the following embodiments and features in the embodiments can be combined with each other.

[0025] In the embodiments of this application, the terms "first" and "second" are used to distinguish identical or similar items with essentially the same function and effect. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and that the terms "first" and "second" do not necessarily imply that they are different.

[0026] It should be noted that, in the embodiments of this application, the words "exemplary" or "for example" indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0027] In this application embodiment, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0028] Before providing a further detailed description of the present invention, the nouns and terms used in the embodiments of the present invention are explained, and the nouns and terms used in the embodiments of the present invention are subject to the following interpretations:

[0029] <1> Critical Dimension (CD): CD refers to the width or length of a specific structure in the semiconductor manufacturing process, especially those tiny dimensions that directly affect device performance. CD is a core indicator for evaluating the accuracy and consistency of manufacturing processes.

[0030] <2> Sidewall Angle (SWA): SWA is a key process parameter in semiconductor manufacturing used to describe the angle between the sidewall of the etched or lithographic pattern and the horizontal wafer surface.

[0031] To facilitate understanding of the embodiments of this application, firstly, in conjunction with Figure 1 Detailed explanation. Figure 1 A flowchart illustrating a predictive control method for semiconductor etching processes according to an embodiment of the present invention is shown. The predictive control method for semiconductor etching processes in this embodiment mainly includes the following steps:

[0032] Step S11: Obtain in-situ process parameters and completion measurement data of the wafer to be etched after the previous thin film deposition process.

[0033] In one embodiment, the in-situ process parameters include at least one of temperature, pressure, gas flow rate, RF power, spectrometer data, and impedance data; the final measurement data includes at least one of film thickness, refractive index, stress, and uniformity. It should be understood that after executing and completing the preceding thin film deposition process to obtain the current wafer to be etched, the corresponding in-situ process parameters, such as temperature, pressure, gas flow rate, RF power, spectrometer data, and impedance data, are obtained during the thin film deposition process. After completing the thin film deposition process, the obtained wafer to be etched is measured offline to obtain final measurement data, such as film thickness, refractive index, stress, and uniformity.

[0034] Specifically, scanning technologies such as SEM and OCD can be used to collect finished measurement data of the wafer to be etched. SEM (Scanning Electron Microscope) is a high-resolution analytical instrument that uses a focused electron beam to scan the sample surface and detects signals such as secondary electrons and backscattered electrons generated by the interaction between electrons and the sample to obtain information on the microscopic morphology, composition, and structure of the sample surface. SEM has advantages such as high resolution, large depth of field, and strong stereoscopic image quality. OCD (Optical Critical Dimension) is a non-contact, non-destructive metrology technology based on the principle of optical scattering, widely used in semiconductor manufacturing for high-precision measurement of critical dimensions of nanoscale structures (such as linewidth, sidewall angles, and height).

[0035] It should be noted that the parameters of the wafer to be etched after the completion of the previous thin film deposition process will affect the etching results of the next etching process, potentially causing significant deviations in the etching morphology. Therefore, in this embodiment, the in-situ process parameters and completion measurement data of the wafer to be etched after the completion of the previous thin film deposition process are collected in real time to adjust the parameters of the subsequent etching process, so as to achieve precise control of the etching morphology, thereby improving process efficiency and stability. The aim is to break down the barriers between processes and use the data from the previous process to achieve forward-looking optimization and control of the subsequent process.

[0036] Step S12: Input the in-situ process parameters and the completed measurement data into the pre-trained etching morphology prediction model to obtain the predicted etching morphology features of the wafer to be etched.

[0037] In one embodiment, the predicted etching morphology features include at least one of critical dimensions, sidewall angles, etching depth, selectivity, and roughness.

[0038] In one embodiment, a pre-trained etching morphology prediction model is used to predict the etching morphology features of the wafer after the etching process. It should be noted that the construction process of the etching morphology prediction model includes: collecting historical in-situ process parameters and historical completion measurement data of each wafer after the thin film deposition process, as well as historical etching morphology features after the etching process, to construct a training sample dataset; employing a machine learning algorithm, using the historical in-situ process parameters and historical completion measurement data after the thin film deposition process as model input, and the historical etching morphology features after the etching process as model output, to construct an etching morphology prediction model that integrates the physical mechanism of the etching process; and training the constructed etching morphology prediction model using the training sample dataset to obtain the pre-trained etching morphology prediction model.

[0039] It's important to clarify that historical in-situ process parameters refer to process parameters collected in real-time by equipment sensors during the thin film deposition process, such as temperature, pressure, gas flow rate, and RF power. These parameters reflect the dynamic process of deposition, capturing equipment status and process fluctuations. Historical completion measurement data refers to measurement data of the wafer after the thin film deposition process, such as film thickness, uniformity, refractive index, and stress. Historical etching morphology features refer to key features obtained by measuring the three-dimensional morphology of the etched structure after the etching process. Using data from the same wafer after the thin film deposition process as input features and the corresponding etching morphology features after the etching process as output labels, a sample is formed. Multiple wafer samples constitute the training sample dataset.

[0040] Furthermore, when constructing the etching morphology prediction model using machine learning algorithms, the physical mechanism of the etching process is introduced as a constraint or prior knowledge. For example, if the physical mechanism of the etching process includes formulas for etching rate and RF power, gas chemical composition, etc., then corresponding feature relationships are constructed in the etching morphology prediction model. The physical mechanism of the etching process includes inherent process laws such as etching gas, power, pressure, temperature, cavity state, reaction rate, mask occlusion, lateral etching, and longitudinal etching rate, which are embedded in the model constraint logic and are not limited here. The machine learning algorithms include, but are not limited to, random forest, gradient boosting tree, BP neural network, CNN, LSTM, etc. The constructed etching morphology prediction model is trained using a training sample dataset to obtain a pre-trained etching morphology prediction model. The etching morphology prediction model in this application, which integrates the physical mechanism of the etching process, combines the real reaction principle of semiconductor etching and the constraints of equipment process laws, resulting in stronger model generalization ability, avoiding prediction distortion caused by pure data-driven overfitting, and adapting to the complex etching changes in semiconductors.

[0041] Step S13: Compare the predicted etching morphology features of the wafer to be etched with the target etching morphology features. Adjust the etching process parameters of the wafer to be etched based on the comparison results until the comparison results meet the preset accuracy requirements and the optimal etching process parameters are obtained. The etching process parameters include etching time, the proportion of each gas, and radio frequency power.

[0042] In one embodiment, the predicted etching morphology features of the wafer to be etched are compared with the target etching morphology features. The etching process parameters of the wafer to be etched are adjusted based on the comparison results until the comparison results meet a preset accuracy requirement, and the optimal etching process parameters are obtained. The specific process includes: comparing and calculating the predicted etching morphology features of the wafer to be etched with the target etching morphology features to obtain difference data; if the difference data does not meet the preset accuracy requirement, an optimization algorithm is used to solve the etching morphology prediction model. The objective function is that the difference data between the predicted and target etching morphology features of the wafer to be etched meets the preset accuracy requirement. The etching process parameters are adjusted through iterative calculation until the difference data meets the preset accuracy requirement, at which point the iteration stops, and the optimal etching process parameters are obtained. The predicted etching morphology features include at least one of critical dimensions, sidewall angles, etching depth, selectivity, and roughness.

[0043] Specifically, the predicted etching morphology features of the wafer to be etched are compared with the target etching morphology features, and the difference values ​​of the two in each feature are calculated to form the difference data. The target etching morphology features are set according to actual production needs and product specifications, and are not limited here. Then, it is determined whether the difference data meets the preset accuracy requirements. For example, if the difference value of the critical dimension is less than the critical dimension difference threshold, the difference value of the sidewall angle is less than the sidewall angle difference threshold, the difference value of the etching depth is less than the etching depth difference threshold, and so on, until the difference value of all features is less than the corresponding difference threshold, then the preset accuracy requirements are met, indicating that the predicted etching morphology features of the wafer to be etched are qualified process parameters. Alternatively, if the difference value of any one or more features is greater than or equal to the corresponding difference threshold, then the accuracy requirements are not met, indicating that the predicted etching morphology features of the wafer to be etched are unqualified process parameters. The preset accuracy requirements are set according to the product accuracy requirements and the error tolerance range of the production process, and are not limited here.

[0044] When the detected difference data does not meet the preset accuracy requirement, the process proceeds to the next step. An optimization algorithm is used to solve the etching morphology prediction model. The objective function is to ensure that the difference data between the predicted etching morphology features of the wafer to be etched and the target etching morphology features meets the preset accuracy requirement. The etching process parameters in the etching morphology prediction model are used as optimization variables, along with constraints set according to actual wafer production conditions. The optimization algorithm performs iterative calculations, adjusting the values ​​of the optimization variables in each iteration. The etching morphology prediction model re-obtains the predicted etching morphology features of the wafer to be etched based on the adjusted etching process parameters, and then calculates the difference data between the current predicted etching morphology features and the target etching morphology features. Iteration stops when the difference data meets the preset accuracy requirement. The etching process parameters corresponding to the point where iteration stops are taken as the optimal etching process parameters.

[0045] Step S14: Perform the etching process on the wafer to be etched based on the optimal etching process parameters.

[0046] The optimal etching process parameters obtained through the above steps are applied to the actual etching process of the wafer. That is, the etching equipment performs the etching process on the wafer to be etched according to the optimal etching process parameters, and finally obtains the wafer after etching. This achieves precise control of the etching morphology and improves process efficiency and stability.

[0047] In one embodiment of this application, as Figure 2 As shown, the method further includes: acquiring the measured etching morphology features of the wafer to be etched after the etching process, and updating and retraining the etching morphology prediction model based on the measured etching morphology features of the wafer to be etched, the in-situ process parameters and completion measurement data after the front-end thin film deposition process, and the optimal etching process parameters as feedback data.

[0048] Specifically, after the etching process is completed, the wafer is measured to obtain the actual etching morphology characteristics. The in-situ process parameters and completed measurement data of the wafer after the previous thin film deposition process, as well as the optimal etching process parameters, are used as feedback data. The etching morphology prediction model is continuously learned and updated based on the feedback data in the actual production process to form a closed-loop optimization.

[0049] It should be emphasized that the semiconductor etching process predictive control method provided in this application has the following beneficial effects:

[0050] This application constructs a high-precision etching morphology prediction model by acquiring and analyzing in-situ process parameters and completion measurement data of the preceding thin film deposition process in real time. It then adaptively adjusts the etching process parameters before the etching process begins, thereby achieving precise control over the etching morphology and improving process efficiency and stability. This application breaks down inter-process barriers and utilizes preceding process data to achieve proactive optimization control of subsequent processes.

[0051] Figure 3 This is a schematic block diagram of the semiconductor etching process predictive control system provided in an embodiment of this application. Figure 3 As shown, the system 300 includes a data acquisition module 310, a feature prediction module 320, a parameter adjustment module 330, and a process execution module 340.

[0052] Data acquisition module 310 is used to acquire in-situ process parameters and completion measurement data of the wafer to be etched after the front-end thin film deposition process is completed;

[0053] The feature prediction module 320 is used to input the in-situ process parameters and finished measurement data into a pre-trained etching morphology prediction model to obtain the predicted etching morphology features of the wafer to be etched.

[0054] The parameter adjustment module 330 is used to compare the predicted etching morphology features of the wafer to be etched with the target etching morphology features, and adjust the etching process parameters of the wafer to be etched according to the comparison results until the comparison results meet the preset accuracy requirements and the optimal etching process parameters are obtained.

[0055] The process execution module 340 is used to perform an etching process on the wafer to be etched based on the optimal etching process parameters.

[0056] It should be understood that the specific process of each module performing the above-mentioned steps has been described in detail in the above method embodiments, and will not be repeated here for the sake of brevity.

[0057] It should also be understood that the module division in the embodiments of this application is illustrative and only represents a logical functional division; in actual implementation, there may be other division methods. Furthermore, the functional modules in the various embodiments of this application can be integrated into a single processor, exist as separate physical entities, or be integrated into a single module. The integrated modules described above can be implemented in hardware or as software functional modules.

[0058] Figure 4 This is a schematic block diagram of the electronic terminal provided in an embodiment of this application. Figure 4As shown, the electronic terminal 400 includes at least one processor 401, a memory 402, at least one network interface 403, and a user interface 405. The various components in the electronic terminal 400 are coupled together via a bus system 404. It is understood that the bus system 404 is used to implement communication between these components. In addition to a data bus, the bus system 404 also includes a power bus, a control bus, and a status signal bus. However, for clarity, in… Figure 4 The general will label all buses as bus systems.

[0059] The user interface 405 may include a monitor, keyboard, mouse, trackball, clicker, button, touchpad, or touch screen.

[0060] It is understood that memory 402 can be volatile memory or non-volatile memory, or both. Non-volatile memory can be read-only memory (ROM) or programmable read-only memory (PROM), which serves as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM) and synchronous static random access memory (SSRAM). The memories described in the embodiments of this invention are intended to include, but are not limited to, these and any other suitable categories of memory.

[0061] In this embodiment of the invention, the memory 402 is used to store various types of data to support the operation of the electronic terminal 400. Examples of this data include: any executable program for operation on the electronic terminal 400, such as the operating system 4021 and application program 4022; the operating system 4021 contains various system programs, such as the framework layer, core library layer, driver layer, etc., for implementing various basic services and handling hardware-based tasks. The application program 4022 may contain various applications, such as a media player, browser, etc., for implementing various application services. The semiconductor etching process predictive control method provided in this embodiment of the invention can be included in the application program 4022.

[0062] The methods disclosed in the above embodiments of the present invention can be applied to processor 401, or implemented by processor 401. Processor 401 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the integrated logic circuit of the hardware in processor 401 or by instructions in the form of software. The processor 401 may be a general-purpose processor, a digital signal processor (DSP), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Processor 401 can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of the present invention. General-purpose processor 401 may be a microprocessor or any conventional processor, etc. The steps of the accessory optimization method provided in the embodiments of the present invention can be directly reflected as being executed by a hardware decoding processor, or being executed by a combination of hardware and software modules in the decoding processor. The software module may be located in a storage medium, which is located in a memory. The processor reads the information in the memory and combines it with its hardware to complete the steps of the aforementioned method.

[0063] In an exemplary embodiment, the electronic terminal 400 may be used to execute the aforementioned method by one or more application-specific integrated circuits (ASICs), DSPs, programmable logic devices (PLDs), or complex programmable logic devices (CPLDs).

[0064] According to the method provided in the embodiments of this application, this application also provides a computer program product, which includes: computer program code, which, when run on a computer, causes the computer to perform the method of any of the embodiments described above.

[0065] According to the method provided in the embodiments of this application, this application also provides a computer-readable storage medium storing program code, which, when run on a computer, causes the computer to perform the method of any of the embodiments described above.

[0066] As used in this specification, the terms "component," "module," "system," etc., are used to refer to computer-related entities, hardware, firmware, combinations of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable file, an execution thread, a program, and / or a computer. As illustrated, applications running on computing devices and computing devices can both be components. One or more components may reside in a process and / or an execution thread, and components may be located on a single computer and / or distributed among two or more computers. Furthermore, these components can be executed from various computer-readable media on which various data structures are stored. Components can communicate, for example, via local and / or remote processes based on signals having one or more data packets (e.g., data from two components interacting with another component between a local system, a distributed system, and / or a network, such as the Internet interacting with other systems via signals).

[0067] Those skilled in the art will recognize that the various illustrative logical blocks and steps described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this application.

[0068] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0069] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0070] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0071] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0072] In the above embodiments, the functions of each functional unit can be implemented entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. A computer program product includes one or more computer instructions (programs). When the computer program instructions (programs) are loaded and executed on a computer, all or part of the flow or function according to the embodiments of this application is generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. Computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. Available media can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., high-density digital video discs (DVDs)), or semiconductor media (e.g., solid-state disks (SSDs)).

[0073] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0074] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0075] In summary, the semiconductor etching process prediction and control method, system, medium, program product, and terminal provided in this application include: acquiring in-situ process parameters and completion measurement data of the wafer to be etched after the front-end thin film deposition process; inputting the in-situ process parameters and completion measurement data into a pre-trained etching morphology prediction model to obtain the predicted etching morphology features of the wafer to be etched; comparing the predicted etching morphology features of the wafer to be etched with the target etching morphology features, adjusting the etching process parameters of the wafer to be etched according to the comparison results until the comparison results meet the preset accuracy requirements and the optimal etching process parameters are obtained; and executing the etching process based on the optimal etching process parameters. This application constructs a high-precision etching morphology prediction model by acquiring and analyzing the in-situ process parameters and completion measurement data of the front-end thin film deposition process in real time, and adaptively adjusting its etching process parameters before the etching process begins, thereby achieving precise control of the etching morphology and improving process efficiency and stability. This application can break down inter-process barriers and use front-end process data to achieve forward-looking optimization control of the back-end process. Therefore, this application effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0076] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this application should still be covered by the claims of this application.

Claims

1. A method for predictive control of semiconductor etching processes, characterized in that, include: Obtain in-situ process parameters and completion measurement data of the wafer to be etched after the previous thin film deposition process is completed; The in-situ process parameters and finished measurement data are input into a pre-trained etching morphology prediction model to obtain the predicted etching morphology features of the wafer to be etched. The predicted etching morphology features of the wafer to be etched are compared with the target etching morphology features. The etching process parameters of the wafer to be etched are adjusted according to the comparison results until the comparison results meet the preset accuracy requirements and the optimal etching process parameters are obtained. The etching process is performed on the wafer to be etched based on the optimal etching process parameters.

2. The semiconductor etching process predictive control method according to claim 1, characterized in that, The predicted etching morphology of the wafer to be etched is compared with the target etching morphology. The etching process parameters of the wafer to be etched are adjusted according to the comparison results until the comparison results meet the preset accuracy requirements and the optimal etching process parameters are obtained. The specific process includes: The predicted etching morphology features of the wafer to be etched are compared with the target etching morphology features to obtain the difference data. If the difference data does not meet the preset accuracy requirements, an optimization algorithm is used to solve the etching morphology prediction model. The objective function is to make the difference data between the predicted etching morphology features of the wafer to be etched and the target etching morphology features meet the preset accuracy requirements. The etching process parameters are adjusted through iterative calculation until the difference data meets the preset accuracy requirements, and then the iteration stops to obtain the optimal etching process parameters.

3. The semiconductor etching process predictive control method according to claim 1, characterized in that, The method further includes: The measured etching morphology features of the wafer to be etched after the etching process are obtained, and the etching morphology prediction model is updated and retrained based on the measured etching morphology features of the wafer to be etched, the in-situ process parameters and completion measurement data after the front-end thin film deposition process, and the optimal etching process parameters as feedback data.

4. The semiconductor etching process predictive control method according to claim 1, characterized in that, The process of constructing the etching morphology prediction model includes: Collect historical in-situ process parameters and historical completion measurement data of each wafer after the thin film deposition process, as well as historical etching morphology features after the etching process, to construct a training sample dataset. A machine learning algorithm was used to construct an etching morphology prediction model that integrates the physical mechanism of the etching process. The model input was the historical in-situ process parameters and historical measurement data after the thin film deposition process, and the model output was the historical etching morphology features after the etching process. The pre-trained etching morphology prediction model is obtained by training the training sample dataset to train the constructed etching morphology prediction model.

5. The semiconductor etching process predictive control method according to claim 1, characterized in that, The in-situ process parameters include at least one of temperature, pressure, gas flow rate, radio frequency power, spectrometer data, and impedance data; the finished measurement data include at least one of film thickness, refractive index, stress, and uniformity.

6. The semiconductor etching process predictive control method according to claim 1, characterized in that, The predicted etching morphology features include at least one of the following: critical dimension, sidewall angle, etching depth, selectivity, and roughness.

7. A semiconductor etching process predictive control system, characterized in that, include: The data acquisition module is used to acquire in-situ process parameters and completion measurement data of the wafer to be etched after the front-end thin film deposition process is completed. The feature prediction module is used to input the in-situ process parameters and finished measurement data into a pre-trained etching morphology prediction model to obtain the predicted etching morphology features of the wafer to be etched. The parameter adjustment module is used to compare the predicted etching morphology features of the wafer to be etched with the target etching morphology features, and adjust the etching process parameters of the wafer to be etched according to the comparison results until the comparison results meet the preset accuracy requirements and the optimal etching process parameters are obtained. The process execution module is used to perform the etching process on the wafer to be etched based on the optimal etching process parameters.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the semiconductor etching process prediction and control method according to any one of claims 1 to 6.

9. A computer program product, characterized in that, The computer program product includes computer program code, which, when run on a computer, causes the computer to implement the semiconductor etching process predictive control method as described in any one of claims 1 to 6.

10. An electronic terminal, comprising a memory, a processor, and a computer program stored in the memory, characterized in that, The processor executes the computer program to implement the semiconductor etching process predictive control method according to any one of claims 1 to 6.

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