A through silicon via test structure, wafer, and method for testing through silicon via offset

Abstract

The application provides a through silicon via test structure, a wafer and a method for testing a through silicon via offset, and relates to the technical field of semiconductors. The through silicon via test structure is used for testing the offset of a through silicon via in a wafer. The wafer comprises a semiconductor substrate, an active region and a cutting region arranged between the active region. The through silicon via test structure is arranged in the cutting region. The through silicon via test structure comprises: at least one test through silicon via; and a conductive structure, which is arranged apart from the test through silicon via in a plane. The test through silicon via and the conductive structure are separated by a dielectric layer to form a capacitor. The through silicon via test structure is configured to characterize the offset of the test through silicon via based on the measurement result of the capacitor. The through silicon via test structure and the test method provided by the application are not only beneficial to discovering the abnormality of a through silicon via and the distribution trend of the offset, but also can provide a basis for process parameter optimization and layout design adjustment, thereby improving the stability of a through silicon via process and the yield of products.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a through-silicon via (TSV) test structure, wafer, and method for testing TSV offset. Background Technology

[0002] Currently, 3D integrated packaging commonly employs through-silicon vias (TSVs) combined with hybrid bonding to achieve face-to-face or face-to-back chip stacking. Depending on the TSV process timing, there are generally two process routes: "front-side TSV" and "back-side TSV." Front-side TSVs typically involve pre-embedding large-size TSVs (e.g., with a diameter of approximately micrometers) during the front-end process, followed by the completion of subsequent active devices and multi-layer metal interconnects. The introduction of this type of TSV imposes additional constraints on the front-end device layout, stress, and metal wiring density, and introduces a process loading effect, adversely affecting subsequent photolithography, etching, and planarization steps. Back-side TSVs, on the other hand, are created after the front-end and front-side interconnect processes are completed, with thinning, windowing, etching, and metal filling performed on the back of the wafer. This relatively reduces the loading effect of TSVs on the front-end devices and interconnect processes, and is more conducive to controlling the front-end process window.

[0003] When using back-side TSV (Transformer Valves) technology, TSV alignment typically requires reference to alignment marks or metal structures already formed on the front side. However, since the alignment process is performed on the back side of the wafer, the alignment marks on the front side cannot be directly seen. Indirect alignment is often required through intermediate layers or process compensation, making it difficult to precisely control back-side alignment overlap (OVL) errors. Regardless of whether it's a Face-to-Face or Face-to-Back structure, using back-side fabrication of TSVs carries the risk of OVL misalignment between the TSV and the front-end conductive structure in planar position. This misalignment can reduce the spacing between the TSV and the target metal pads or adjacent metal lines, potentially leading to electrical failures, reduced yield, and increased demands on the precision of critical equipment such as exposure and etching, as well as process control. This significantly increases the difficulty of process development and mass production debugging. Summary of the Invention

[0004] The purpose of this application is to overcome at least one deficiency of the prior art and to provide a through-silicon via (TSV) testing structure, wafer, and TSV testing method.

[0005] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description or may be learned by practice of this application.

[0006] According to one aspect of this application, a through-silicon via (TSV) test structure is provided. This structure is used to test the offset of TSVs within a wafer, the wafer including a semiconductor substrate, an active region, and a dicing region disposed between the active region. The TSV test structure is disposed in the dicing region and includes: at least one test TSV; a conductive structure spaced apart from the test TSV in a plane, the conductive structure and the conductive structure being separated by a dielectric layer to form a capacitor; wherein the TSV test structure is configured to characterize the offset of the test TSV based on a measurement of the capacitor.

[0007] In some embodiments of this disclosure, the conductive structure includes at least two metal plates symmetrically arranged with respect to the test through-silicon via (TSV), and forming capacitors with opposite sides of the TSV under the isolation of the dielectric layer.

[0008] In some embodiments of this disclosure, at least two of the metal plates include straight sections extending along their length.

[0009] In some embodiments of this disclosure, the metal plate further includes at least one inclined segment; the inclined segment is disposed at one end of the straight segment and connected to the straight segment; in a plane parallel to the semiconductor substrate, with the extension direction of the metal plate as a reference line, the distance between the end of the inclined segment near the straight segment and the test through-silicon via gradually decreases towards the end of the inclined segment away from the straight segment and the test through-silicon via.

[0010] In some embodiments of this disclosure, the minimum distance between the straight section and the periphery of the test through-silicon via is greater than or equal to the minimum distance between the inclined section and the periphery of the test through-silicon via.

[0011] In some embodiments of this disclosure, the conductive structure includes a first metal plate and a second metal plate; the first metal plate and the second metal plate are symmetrically arranged about the test through-silicon via along a first direction, wherein the first metal plate is disposed on one side of the test through-silicon via along the first direction, and the second metal plate is disposed on the other side of the test through-silicon via along the first direction, and the first metal plate and the second metal plate respectively form a capacitor with the test through-silicon via under the isolation of the dielectric layer.

[0012] In some embodiments of this disclosure, the first metal plate and the second metal plate are electrically connected to their corresponding test pads.

[0013] In some embodiments of this disclosure, the conductive structure includes a third metal plate and a fourth metal plate; the third metal plate and the fourth metal plate are symmetrically arranged about the test through-silicon via (TSV) along a second direction, wherein the third metal plate is disposed on one side of the TSV along the second direction, and the fourth metal plate is disposed on the other side of the TSV along the second direction, the second direction being perpendicular to the first direction, and the third metal plate and the fourth metal plate respectively form a capacitor with the TSV under the isolation of the dielectric layer.

[0014] In some embodiments of this disclosure, the third metal plate and the fourth metal plate are electrically connected to their corresponding test pads.

[0015] In some embodiments of this disclosure, the wafer further includes a first metal structure disposed on the semiconductor substrate; the first metal structure includes a plurality of first metal layers and a top conductive layer stacked along the thickness direction of the semiconductor substrate; the test silicon via is electrically connected to the top conductive layer; adjacent first metal layers are electrically connected through metal vias; wherein the first metal layers and the metal vias are disposed on the same layer as at least a portion of the metal plate.

[0016] In some embodiments of this disclosure, the wafer further includes a second metal structure disposed on the semiconductor substrate; the second metal structure includes a bottom conductive layer stacked on the semiconductor substrate and a second metal layer disposed on the bottom conductive layer; the test through-silicon via is electrically connected to the bottom conductive layer; the second metal layer is disposed in the same layer as at least a portion of the metal plate in the conductive structure.

[0017] In some embodiments of this disclosure, the second metal layer includes a gate sublayer; wherein the gate sublayer is disposed in the same layer as at least a portion of the metal plate in the conductive structure.

[0018] In some embodiments of this disclosure, the second metal layer includes a metal interconnect sublayer; the metal interconnect sublayer is disposed in the same layer as at least a portion of the metal plate in the conductive structure.

[0019] According to a second aspect of this application, a wafer is provided, including the aforementioned through-silicon via (TSV) test structure.

[0020] According to a third aspect of this application, a method for testing the offset of a through-silicon via (TSV) is provided. The method employs a TSV test structure disposed in a diced area of ​​a wafer for testing. The TSV test structure includes at least one test TSV and a conductive structure spaced apart from the test TSV on a plane. The test TSV and the conductive structure are separated by a dielectric layer to form a capacitor. The testing method includes: measuring the capacitance value formed between the conductive structure and the test TSV; and determining the offset of the test TSV based on the capacitance value.

[0021] In some embodiments of this disclosure, the conductive structure includes at least two metal plates, which are symmetrically arranged about the test through-silicon via (TSV). Measuring the capacitance between the conductive structure and the TSV includes measuring the capacitance between the at least two metal plates and the TSV. Determining the offset of the TSV based on the capacitance includes determining the offset of the TSV along the arrangement direction of the two metal plates based on the difference in capacitance between the two metal plates symmetrically arranged about the TSV.

[0022] In this application, the through-silicon via (TSV) test structure arranges at least one test TSV and a conductive structure spaced apart from it by a dielectric layer within the wafer dicing area. This creates a measurable capacitance between the test TSV and the conductive structure, allowing for precise characterization of the TSV's offset and direction within the wafer plane based on capacitance changes. This structure, located within the dicing area, does not occupy active area layout resources and does not affect the normal operation of functional circuits. Furthermore, during process development or mass production, simple capacitance testing enables online monitoring and quantitative analysis of TSV alignment offset, facilitating timely detection and location of process anomalies, guiding the optimization of alignment parameters and layout design, thereby improving TSV process stability and product yield.

[0023] Furthermore, statistical analysis of test results from different wafers and batches can be used to evaluate the stability of the back-side through-silicon via process window and key alignment equipment, providing a quantitative basis for equipment maintenance and process window setting. Attached Figure Description

[0024] The above and other features and advantages of this application will become more apparent from a detailed description of exemplary embodiments thereof with reference to the accompanying drawings.

[0025] Figure 1 This is a schematic diagram of the first step in the front-side through-silicon via (TSV) process in related technologies.

[0026] Figure 2 This is a schematic diagram of the second step in the front-side through-silicon via (TSV) process in related technologies.

[0027] Figure 3 This is a schematic diagram of the third step in the front-side through-silicon via (TSV) process in related technologies.

[0028] Figure 4 This is a schematic diagram of the fourth step in the front-side through-silicon via (TSV) process in related technologies.

[0029] Figure 5 This is a schematic diagram of the fifth step in the front-side through-silicon via (TSV) process in related technologies.

[0030] Figure 6 This is a schematic diagram of the sixth step in the front-side through-silicon via (TSV) process in related technologies.

[0031] Figure 7 This is a schematic diagram of the first step in the back-side through-silicon via (TSV) process in related technologies.

[0032] Figure 8 This is a schematic diagram of the second step in the back-side through-silicon via (TSV) process in related technologies.

[0033] Figure 9 This is a schematic diagram of the third step in the back-side through-silicon via (TSV) process in related technologies.

[0034] Figure 10 This is a schematic diagram of the fourth step in the back-side through-silicon via (TSV) process in related technologies.

[0035] Figure 11 This is a schematic diagram of the fifth step in the back-side through-silicon via (TSV) process in related technologies.

[0036] Figure 12 This is a schematic diagram showing the distribution of the wafer and the test through-silicon vias in this application.

[0037] Figure 13 This is a schematic diagram of the through-silicon via (TSV) testing structure in this application. Figure 1 .

[0038] Figure 14 This is a schematic diagram of the through-silicon via (TSV) testing structure in this application. Figure 2 .

[0039] Figure 15 This is the hierarchical structure of the through-silicon via (TSV) testing structure in this application. Figure 1 .

[0040] Figure 16 This is the hierarchical structure of the through-silicon via (TSV) testing structure in this application. Figure 2 .

[0041] Figure 17 This is a schematic diagram of the steps of the through-silicon via offset testing method in this application.

[0042] Explanation of reference numerals in the attached figures: 1. Test through-silicon via (TSV); 2. Conductive structure; 21. Metal plate; 211. Straight section; 212. Inclined section; 22. First metal plate; 23. Second metal plate; 24. Third metal plate; 25. Fourth metal plate; 3. Wafer; 31. Active region; 32. Cut area; 33. Semiconductor substrate; 4. First metal structure; 41. Top conductive layer; 42. First metal layer; 43. Metal via; 5. Second metal structure; 51. Bottom conductive layer; 52. Second metal layer; 521. Gate sublayer; 522. Metal interconnect sublayer; 6. First wafer; 7. Second wafer; 8. Dielectric layer; 9. TSV; X, First direction; Y, Second direction. Detailed Implementation

[0043] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this application will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore their detailed description will be omitted.

[0044] The features, structures, or characteristics described above can be combined in any suitable manner in one or more embodiments, and where possible, the features discussed in the various embodiments are interchangeable. In the above description, numerous specific details are provided to give a full understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details described, or other methods, components, materials, etc., can be employed. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0045] Although this application uses relative terms, such as "up" and "down," to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as the orientation of the examples shown in the accompanying drawings. It is understood that if the icon's arrangement is flipped so that it is upside down, the component described as "up" will become the component described as "down." Other relative terms, such as "high," "low," "top," "bottom," "front," "back," "left," and "right," also have similar meanings. When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0046] In this application, the terms “a,” “an,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “comprising,” “including,” and “having” are used to indicate an open-ended inclusion meaning and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.

[0047] See Figures 1 to 6 The diagram illustrates the process steps for a front-side through-silicon via (TSV). The following is a detailed description of the front-side TSV process: The process flow can be as follows: First, a first wafer 6 is provided, and a dielectric layer 8 is formed on the front side of the first wafer 6. Conductive material is etched and filled in the dielectric layer 8 and the semiconductor substrate 33 below it to obtain through-silicon vias 9 that partially extend into the substrate. Subsequently, the dielectric layer 8 is deposited on the front side of the first wafer 6, and the deposition and patterning of multilayer metal interconnects are completed sequentially, so that a tree-like multilayer metal interconnect structure is formed extending from the top of the through-silicon via 9 along the thickness direction. Then, a second wafer 7 is provided, and the dielectric layer 8, through-silicon vias 9, and the multilayer metal interconnect structure connected thereto are also formed on the front side of the second wafer 7. Afterward, the first wafer 6 is flipped so that the front side of the first wafer 6 faces down, and aligned and bonded with the front side of the second wafer 7 through the intermediate dielectric layer 8, forming a structure in which two sets of tree-like metal interconnects are interlocked at the bonding interface. After bonding is completed, the back side of the first wafer 6 is thinned so that some of the through-silicon vias 9 are exposed from the back side. Finally, a dielectric layer 8 and a metal interconnect structure are formed on the thinned new surface side, and a vertical metal path and a back pad for external chip connection are formed at the top opening of the through-silicon via 9, thereby obtaining a three-dimensional integrated chip structure using the front through-silicon via 9 process.

[0048] The above-mentioned front-side through-silicon via (TSV) 9 process has the following drawbacks: Firstly, TSV 9 and complex multilayer metal interconnects need to be completed on the first wafer 6 and the second wafer 7 respectively. Then, the first wafer 6 is flipped and front-to-front bonding is performed. Subsequently, the back side of the first wafer 6 is thinned over a large area, and the back metal is further processed on its residual interconnect stack. The overall process is long and involves many steps. Key steps such as flipping the first wafer 6, precise alignment bonding, and thinning require high equipment capabilities and process windows. It is easy to introduce residual stress and failure risks such as wafer cracking during the thinning process, resulting in high manufacturing costs and significant pressure on yield. On the other hand, the through-silicon vias 9 on the front side need to be etched and filled in an early stage of the process flow. Large through-silicon vias 9 (e.g., with a diameter of about 3μm) will occupy a large silicon area and be close to the active device area, introducing stress and parasitic effects, which will have an adverse effect on transistor performance. At the same time, large through-silicon vias 9 and their surrounding openings will also cause significant pattern loading effects in etching, deposition and other stages. That is, due to the difference in pattern density and opening area in different areas, the etching / deposition rate will be inconsistent, which will interfere with the consistency and controllability of subsequent processes.

[0049] See Figures 7 to 11 The diagram illustrates the 9-step process for back-side through-silicon vias (TSVs). The following is a detailed explanation of the back-side TSV process: The process flow can be as follows: First, a first wafer 6 is provided. The front side of the first wafer 6 has a device region and a multilayer metal interconnect structure already formed. The multilayer metal interconnect structure is embedded in the dielectric layer 8 on the front side of the first wafer 6. Then, a second wafer 7 is provided, which serves as a carrier wafer 3. Next, the front side of the first wafer 6 faces the second wafer 7, and the first wafer 6 and the second wafer 7 are bonded together through an intermediate dielectric layer 8, thereby obtaining a stacked structure with the second wafer 7 as the carrier substrate and the first wafer 6 stacked on top of it. Next, the silicon substrate of the first wafer 6 is thinned from the back side, removing the silicon substrate of the first wafer 6 to a predetermined thickness. After thinning, through-holes are etched into the remaining silicon substrate from the thinned back side of the first wafer 6, extending the through-holes to the predetermined metal interconnect layer positions in the depth direction; then, conductive material is filled into the through-holes to electrically connect the through-holes to the corresponding metal interconnect layers, thereby forming a through-silicon via (TSV) 9 structure on the back side of the first wafer 6. Finally, a dielectric layer 8 is deposited on the back side of the first wafer 6 and a patterned opening is made. Back metal wiring and pads are formed at the top opening of the through silicon via 9, so that the multilayer metal interconnects inside the first wafer 6 are electrically connected to the back pads through the back silicon via 9, thereby completing the back silicon via 9 process and realizing the back lead-out of the chip.

[0050] The above-mentioned back-side through-silicon via (TSV) 9 process has the following drawbacks: On the one hand, this scheme also requires the fabrication of the device area and multilayer metal interconnects on the first wafer 6, and then bonding with the second wafer 7. The silicon substrate of the first wafer 6 is also subject to large-scale thinning. Subsequently, deep holes are etched, liner is deposited and metal is filled on the back side of the thinned first wafer 6. The overall process flow is long and there are many key steps. The bonding quality, thinning thickness uniformity and deep silicon etching morphology all place high demands on equipment capabilities and process windows. Slight imperfections may introduce warping, wafer cracking or TSV 9 filling defects, which will put great pressure on yield and manufacturing costs. On the other hand, the back-side through-silicon via 9 is formed by etching from the back side after all the front-side devices and front-end interconnects of the first wafer 6 are completed. Alignment requires reference to the metal interconnects or alignment marks already formed on the front side. However, the front-side marks cannot be directly seen during the back-side process. Back-side alignment can only be achieved indirectly by means of infrared transmission, alignment mark transfer, etc. The offset (OVL) of the through-silicon via 9 relative to the underlying metal interconnect is difficult to control precisely. It is easy for the through-silicon via 9 to not fall completely on the target metal pad or to partially invade the adjacent metal line area. This affects the reliability of electrical connection and limits the further reduction of the aperture and spacing of the through-silicon via 9, increasing the layout design margin and process control difficulty.

[0051] Therefore, in large-size memory chips, in order to avoid the impact of introducing large-size through-silicon vias (TSVs) 9 on transistor characteristics and subsequent process load effects in the front-end process stage, the back-side TSV 9 process route is usually adopted. However, the back-side TSV 9 needs to be aligned from the back of the wafer 3 without seeing the front alignment marks. The stacking error between the TSV 9 and the front-end metal / device is difficult to control precisely, which can easily lead to connection failure, and thus become a key factor restricting the improvement of yield of large-size memory products.

[0052] Based on this, see Figure 12 This application provides a through-silicon via (TSV) test structure. This TSV test structure is used to test the offset of a TSV 9 within a wafer 3. The wafer 3 includes a semiconductor substrate 33, an active region 31, and a dicing region 32 disposed between the active regions 31. The TSV test structure is disposed in the dicing region 32. The TSV test structure includes: at least one test TSV 1 and a conductive structure 2; the conductive structure 2 and the test TSV 1 are spaced apart on a plane, and the test TSV 1 and the conductive structure 2 are separated by a dielectric layer 8 to form a capacitor; wherein, the TSV test structure is configured to characterize the offset of the test TSV 1 based on capacitance measurement results.

[0053] Understandably, in wafer 3D design, the area used to arrange devices and functional circuits is usually called the active region 31, and the area between adjacent chips used for subsequent dicing is called the dicing region 32 (also known as the dicing track or street area). The active region 31 integrates transistors, interconnect metals, and functional circuit structures, and has high requirements for layout density and device performance; the dicing region 32 is located between adjacent active regions 31 and is cut off in the finished chip. It can be used to arrange various test structures without occupying the area of ​​the active region 31 or affecting the normal operation of the chip.

[0054] In this application, the test via 1 located in the dicing region 32 is fabricated using the same or substantially the same process flow as the working via 9 in the active region 31. For example, the steps of opening the via, forming the dielectric layer 8, etching the substrate, and depositing the pad metal and fill metal are completed together on the same wafer 3, and the same layout design rules and critical dimension control are adopted. As a result, the test via 1 in the dicing region 32 has the same or highly similar characteristics as the via 9 in the active region 31 in terms of geometry, material stacking, and process stress. Therefore, based on the measurement results of the capacitance between the test via 1 and the conductive structure 2, the offset of the via 9 in the active region 31 can be accurately reflected without introducing significant systematic errors.

[0055] Furthermore, it should be noted that the statement regarding "at least one test through-silicon via 1" in this application is only used to illustrate that one or more test through-silicon vias 1 can be set in the through-silicon via test structure to adapt to different test accuracy and layout requirements, and does not limit the number of test through-silicon vias 1 to a specific number. The number and arrangement of test through-silicon vias 1 given in the relevant embodiments are only illustrative examples. Those skilled in the art can add, subtract, or adjust them according to specific product dimensions, process windows, and test requirements, all of which should fall within the protection scope of this application, and will not be elaborated further here.

[0056] In this embodiment, the method for offset testing using a through-silicon via (TSV) test structure may include: placing the wafer 3 under test on a test stage, electrically connecting the TSV 1 and the corresponding conductive structure 2 to the lead-out pads via probe cards; applying a predetermined test voltage between the TSV 1 and the conductive structure 2, and obtaining the actual capacitance value between them using a capacitance meter; comparing the measured capacitance value with a target capacitance value obtained according to the layout design or a pre-calibrated reference capacitance value; when the capacitance value deviates from a preset range, determining that the TSV 1 is offset relative to the conductive structure 2 in a predetermined direction, and calculating the offset of the TSV 9 by combining the capacitance and distance relationship. For embodiments with multiple TSV 1, capacitance measurements can also be performed on TSV 1 at different positions or in different directions to obtain the distribution of the TSV 9 offset on the entire wafer 3.

[0057] Thus, by employing the aforementioned capacitance-based through-silicon via (TSV) offset testing scheme, test TSVs 1 with process conditions essentially identical to those of TSVs 9 in the active region 31 are arranged in the dicing area 32, forming a capacitor with the conductive structure 2. Only conventional electrical testing is required to non-destructively characterize the relative alignment offset of the TSVs 9 at the wafer level 3. The testing process is simple and efficient. Furthermore, since the test TSVs 1 and the active region TSVs 9 have high consistency in geometry and material stacking, they can accurately reflect the offset of the actual product's TSVs 9, thereby improving the accuracy and representativeness of the offset test results. Further, by measuring and statistically analyzing the capacitance between the test TSVs 1 and the conductive structure 2 at multiple locations, the distribution characteristics of the TSV 9 offset throughout the entire wafer 3 and even the entire batch of processes can be obtained. This provides a quantitative basis for optimizing alignment parameters and evaluating equipment stability in the back-side TSV 9 process, helping to reduce alignment errors introduced by the back-side TSV 9 process and improve the yield of large-size memory chips.

[0058] In some embodiments of this disclosure, see Figure 13 The conductive structure 2 includes at least two metal plates 21, which are symmetrically arranged with respect to the test silicon via 1 and form capacitors with the opposite sides of the test silicon via 1 under the isolation of the dielectric layer 8.

[0059] As an example, see Figure 13 The conductive structure 2 includes two metal plates 21, which are symmetrically arranged in a plane relative to the test through-silicon via 1, for example, distributed on opposite sides of the test through-silicon via 1 along the first direction X, and forming capacitors with the test through-silicon via 1 under the isolation of the dielectric layer 8. Since the offset of the test through-silicon via 1 relative to the theoretical center position of the layout in the first direction X will cause a difference in the spacing between it and the two metal plates 21, the two capacitance values ​​will have a measurable deviation. Therefore, by measuring and calculating the magnitude, difference, or ratio of the capacitance values ​​on both sides, the offset amount and offset direction of the test through-silicon via 1 in the first direction X can be derived, and the quantitative characterization of the fabrication offset of the through-silicon via 9 in a single direction can be achieved.

[0060] As another example, the number of metal plates 21 in the conductive structure 2 can be adjusted according to the requirements of test accuracy and offset dimension. For example, it can be set to two, three, or four metal plates 21. Taking three metal plates 21 as an example, the three metal plates 21 can be arranged at intervals around the test through-silicon via 1, for example, at approximately 120° intervals. By measuring the capacitance between the test through-silicon via 1 and the three metal plates 21 respectively, and combining it with the preset calibration relationship, the offset trend of the test through-silicon via 1 in the plane can be judged more precisely. Taking four metal plates 21 as an example, the four metal plates 21 can be arranged at the top, bottom, left, and right positions of the test through-silicon via 1, so that a pair of opposite metal plates 21 along the first direction X is used to characterize the offset in the first direction X, and another pair of opposite metal plates 21 along the second direction Y, which is orthogonal to the first direction X, is used to characterize the offset in the second direction Y. By combining the measurement results of the four capacitances, the two-dimensional offset of the test through-silicon via 1 can be accurately characterized.

[0061] It should be noted that the number of metal plates 21 in the conductive structure 2 is not limited to the above example. Those skilled in the art can increase, decrease or modify the number and arrangement of metal plates 21 according to the specific layout size, test sensitivity and process constraints, all of which fall within the protection scope of this disclosure.

[0062] Further, see Figure 13 At least two metal plates 21 include straight segments 211 extending along their length. In this embodiment, at least two of the metal plates 21 each include a straight segment 211 extending along their length. For example, each metal plate 21 has a substantially linearly extending straight edge on the side facing the test via 1, and the straight segment 211 is arranged approximately parallel to the predetermined test direction in a plane. For a pair of symmetrically arranged metal plates 21, the straight segments 211 of both are mirror images of the test via 1, making the relationship between the spacing change between the test via 1 and the two straight segments 211 more linear and regular when the test via 1 is offset in this direction, which is beneficial for analyzing and calibrating the offset through capacitance changes. For multiple metal plates 21 circumferentially spaced around the test via 1, straight segments 211 can also be provided on the side facing the test via 1, making the dielectric gap between the test via 1 and each straight segment 211 simple in shape and clear in boundary.

[0063] The metal plate 21 structure with the straight section 211 described above has several advantages: Firstly, the straight structure of the side of the metal plate 21 facing the test via 1 results in a regular layout shape and simple control over linewidth and spacing. This allows for the direct reuse of design rules and masks for conventional interconnect metals, avoiding the need for separate design and adjustment of layouts for complex curves or irregularly shaped electrodes. This reduces mask complexity and quantity, thus saving mask costs. Secondly, the electric field and capacitance relationship between the straight section 211 and the test via 1 is easier to model analytically or calibrate through simulation. This makes the correspondence between capacitance changes and the offset of the test via 1 more linear and predictable, improving the sensitivity and accuracy of test results. Furthermore, the regular shape of the metal plate 21 and the ease of controlling edge effects also improve the consistency and yield of pattern forming in mass production processes, further reducing the additional burden on the process from monitoring the offset of the back via 9.

[0064] See also other embodiments of this disclosure. Figure 14 The metal plate 21 may further include at least one inclined segment 212; the inclined segment 212 is disposed at one end of the straight segment 211 and connected to the straight segment 211. In a plane parallel to the semiconductor substrate 33, with the extension direction of the metal plate 21 as the reference line, the distance between the end of the inclined segment 212 near the straight segment 211 and the test through-silicon via 1 gradually decreases towards the end away from the straight segment 211 and the test through-silicon via 1.

[0065] For example, in one embodiment, a straight section 211 is first formed along a predetermined test direction on the side of the metal plate 21 facing the test through silicon via 1. An inclined section 212, which is inclined at a predetermined angle, is further extended from the end of the straight section 211, so that the inclined section 212 gradually approaches the test through silicon via 1 from the end of the straight section 211, thereby forming a combined structure on the layout that transitions from equidistant parallel gaps to gradually narrowing gaps.

[0066] By employing the aforementioned structure of the metal plate 21 with the inclined section 212, the sensitivity of the capacitance to the offset of the test through-silicon via 1 can be significantly improved. On the one hand, when the test through-silicon via 1 is slightly offset, the change in the distance between it and the straight section 211 is relatively limited, while the change in the local distance between it and the inclined section 212 is more drastic. This makes the equivalent capacitance between the test through-silicon via 1 and the metal plate 21 as a whole more sensitive to small offsets, and can amplify the amount of capacitance change. On the other hand, the gradually decreasing distance between the inclined section 212 and the test through-silicon via 1 causes the electric field distribution to produce a nonlinear enhancement effect with the offset. A distinguishable capacitance difference can be obtained within a small offset range, thereby improving the resolution and accuracy of the offset measurement. This is beneficial for accurately characterizing the fabrication offset of the through-silicon via 9 under mass production process conditions.

[0067] In some embodiments of this disclosure, the minimum distance between the straight section 211 and the periphery of the test via 1 is greater than or equal to the minimum distance between the inclined section 212 and the periphery of the test via 1. That is, the narrowest gap formed around the test via 1 is defined by a local region between the inclined section 212 and the periphery of the test via 1, while the straight section 211 and the test via 1 always maintain a relatively larger distance. This arrangement allows the straight section 211 to primarily provide a relatively smooth, near-linear reference capacitance response, while the inclined section 212, being closer to the test via 1, is more sensitive to small offsets and is used to amplify the magnitude of capacitance changes with offset.

[0068] Based on the above distance relationship, on the one hand, under the premise of meeting the layout design rules and dielectric reliability, the minimum electrode spacing can be concentrated in the inclined section 212 region, thereby significantly improving the sensitivity of the capacitor to the slight offset of the test silicon via 1 and improving the resolution and accuracy of offset detection; on the other hand, the flat section 211 and the test silicon via 1 maintain a large distance, which is conducive to increasing pattern forming, reducing the risk of failure caused by process fluctuations, simplifying layout verification and mask design, and reducing manufacturing costs.

[0069] In some embodiments of this disclosure, see Figure 13 The conductive structure 2 may include a first metal plate 22 and a second metal plate 23 (having two metal plates 21); the first metal plate 22 and the second metal plate 23 are symmetrically arranged about the test through-silicon via 1 along a first direction X, wherein the first metal plate 22 is disposed on one side of the test through-silicon via 1 along the first direction X, and the second metal plate 23 is disposed on the other side of the test through-silicon via 1 along the first direction X. The first metal plate 22 and the second metal plate 23 form capacitors with the test through-silicon via 1 under the isolation of the dielectric layer 8. The first metal plate 22 and the second metal plate 23 are electrically connected to their corresponding test pads.

[0070] Specifically, when the conductive structure 2 includes a first metal plate 22 and a second metal plate 23, the testing method includes: fixing the wafer 3 to be tested on the testing platform, and electrically connecting it to the test pads corresponding to the first metal plate 22 and the test pads corresponding to the second metal plate 23 through probe cards; applying a predetermined test signal, such as applying an AC test voltage, between the test via 1 and the first metal plate 22 and the second metal plate 23, and measuring the capacitance values ​​between the test via 1 and the first metal plate 22 and the test via 1 and the second metal plate 23 using a capacitance meter. According to the layout design, when the test via 1 is in a relatively ideal aligned position and no offset occurs, the first metal plate 22 and the second metal plate 23 are symmetrically arranged about the test via 1, and the first capacitance and the second capacitance should theoretically be basically equal; when the test via 1 is offset along the first direction X, the distance between it and the first metal plate 22 and the second metal plate 23 decreases or increases, thereby causing a measurable difference between the first capacitance and the second capacitance. By comparing the magnitude relationship and difference between the first capacitor and the second capacitor, and combining this with the pre-calibrated capacitance-offset correspondence, the offset amount and offset direction of the test silicon via 1 along the first direction X can be deduced.

[0071] In one embodiment, the first metal plate 22 and the second metal plate 23 are both straight segments 211 extending along a first direction X on the side facing the test through-silicon via 1, and the first metal plate 22 and the second metal plate 23 are symmetrically arranged relative to the test through-silicon via 1 along the first direction X. The testing method in this case includes: fixing the wafer 3 to be tested on a test platform; electrically connecting the test pads corresponding to the first metal plate 22 and the test pads corresponding to the second metal plate 23 via probe cards; applying a predetermined test signal, such as an AC test voltage, between the test through-silicon via 1 and the first metal plate 22 and the second metal plate 23; and measuring the first capacitance between the test through-silicon via 1 and the first metal plate 22 and the second capacitance between the test through-silicon via 1 and the second metal plate 23 using a capacitance meter. According to the layout design, when the test through-silicon via 1 is in the ideal alignment position, the first metal plate 22 and the second metal plate 23 are symmetrical about the test through-silicon via 1, and the first capacitor and the second capacitor are theoretically basically equal. When the test through-silicon via 1 is offset along the first direction X, the distance between it and the first metal plate 22 and the second metal plate 23 decreases or increases respectively, thereby causing a measurable difference between the first capacitor and the second capacitor. By comparing the magnitude relationship and difference between the two, and combining them with the pre-calibrated capacitance-offset correspondence, the amount and direction of the offset of the test through-silicon via 1 along the first direction X can be deduced.

[0072] In another embodiment, both the first metal plate 22 and the second metal plate 23 include a straight section 211 and an inclined section 212 connected to the straight section 211 on the side facing the test through-silicon via 1. The straight section 211 extends along the first direction X and is symmetrically arranged about the test through-silicon via 1. The inclined section 212 is disposed at one end of each straight section 211 and is arranged at a predetermined angle relative to the first direction X in a plane parallel to the semiconductor substrate 33, so that the inclined section 212 gradually approaches the test through-silicon via 1 from the end of the straight section 211, thereby forming a structure on both sides that transitions from an equidistant gap to a gradually decreasing gap. During testing, the probe card is electrically connected to the corresponding test pads of the first metal plate 22 and the second metal plate 23, and a predetermined test signal is applied to measure the corresponding first capacitance and second capacitance, respectively. When the test through-silicon via 1 is ideally aligned, the combined equivalent capacitance on both sides is basically the same. When the test through-silicon via 1 is slightly offset along the first direction X, the local spacing change between it and the inclined sections 212 on both sides is more significant, resulting in a more sensitive difference between the first capacitance and the second capacitance. By measuring and calibrating the difference between the first capacitor and the second capacitor, the offset and direction of the test silicon via 1 along the first direction X can be obtained at a higher resolution, thereby improving the sensitivity and accuracy of offset detection in this direction.

[0073] In some embodiments of this disclosure, see Figure 13 The conductive structure 2 may further include a third metal plate 24 and a fourth metal plate 25; the third metal plate 24 and the fourth metal plate 25 are symmetrically arranged relative to the test through-silicon via 1 along the second direction Y, wherein the third metal plate 24 is located on one side of the test through-silicon via 1 along the second direction Y, and the fourth metal plate 25 is located on the other side of the test through-silicon via 1 along the second direction Y, the second direction Y is perpendicular to the first direction X, the third metal plate 24 and the fourth metal plate 25 form capacitors with the test through-silicon via 1 under the isolation of the dielectric layer 8, and are respectively led out through the corresponding test pads. During testing, probe cards are electrically connected to the test pads corresponding to the third metal plate 24 and the fourth metal plate 25, respectively. A predetermined test signal is applied to measure the third capacitance between the test through-silicon via 1 and the third metal plate 24, and the fourth capacitance between the test through-silicon via 1 and the fourth metal plate 25. Under ideal alignment, the third and fourth capacitances are basically equal. When the test through-silicon via 1 is offset along the second direction Y, the distance between it and the third metal plate 24 and the fourth metal plate 25 differs, resulting in a measurable difference between the third and fourth capacitances. By comparing the magnitude of the third and fourth capacitances and the difference, and combining this with the pre-calibrated capacitance-offset correspondence, the amount and direction of the offset of the test through-silicon via 1 along the second direction Y can be deduced.

[0074] The scheme of symmetrically arranging the third metal plate 24 and the fourth metal plate 25 along the second direction Y and performing capacitance tests on them respectively can directly characterize the alignment offset of the test through-silicon via 1 in the second direction Y without adding cross-sectional observation or complex alignment measurement equipment, and realize the quantitative test of the offset of the back through-silicon via 9 in the direction perpendicular to the first direction X. Furthermore, when the first metal plate 22 and the second metal plate 23 are used to test the offset in the first direction X, and the third metal plate 24 corresponding to the third capacitor and the fourth metal plate 25 corresponding to the fourth capacitor are used to test the offset in the second direction Y, the offset information of the test through-silicon via 1 in two orthogonal directions can be obtained at the same time, thereby realizing the accurate characterization of the two-dimensional offset of the through-silicon via 9, which is beneficial to comprehensively evaluate the alignment performance of the back through-silicon via 9 process and improve product yield.

[0075] In one embodiment of this disclosure, the third metal plate 24 and the fourth metal plate 25 are both straight segments 211 extending along the second direction Y on the side facing the test through-silicon via 1. The third metal plate 24 and the fourth metal plate 25 are symmetrically arranged relative to the test through-silicon via 1 along the second direction Y. The third metal plate 24 is located on one side of the test through-silicon via 1 along the second direction Y, and the fourth metal plate 25 is located on the other side of the test through-silicon via 1 along the second direction Y. The second direction Y is perpendicular to the first direction X. The third metal plate 24 and the fourth metal plate 25 form capacitors with the test through-silicon via 1 under the isolation of the dielectric layer 8, and are respectively led out through the corresponding test pads. During testing, probe cards are electrically connected to the test pads corresponding to the third metal plate 24 and the fourth metal plate 25, respectively. Predetermined test signals are applied to measure the third capacitance between the test via 1 and the third metal plate 24, and the fourth capacitance between the test via 1 and the fourth metal plate 25. Under ideal alignment, the third and fourth capacitances are essentially equal. When the test via 1 shifts along the second direction Y, the distance between it and the third and fourth metal plates 24 and 25 differs, resulting in a measurable difference between the third and fourth capacitances. By comparing the magnitude of the third and fourth capacitances and their difference, and combining this with a pre-calibrated capacitance-shift correspondence, the offset and direction of the test via 1 along the second direction Y can be deduced. This allows for quantitative testing of the offset of the back-side via 9 in the direction perpendicular to the first direction X, facilitating direct characterization of alignment shifts in this direction without requiring additional cross-sectional observation or complex alignment measurement equipment.

[0076] In another embodiment of this disclosure, see [link to relevant documentation]. Figure 14The third metal plate 24 and the fourth metal plate 25 each include a straight section 211 extending along the second direction Y and an inclined section 212 connected to the straight section 211 on the side facing the test silicon via 1. The straight section 211 is symmetrically arranged with respect to the test silicon via 1 along the second direction Y. The inclined section 212 is disposed at one end of each of the straight sections 211 and is arranged at a predetermined angle with respect to the second direction Y in a plane parallel to the semiconductor substrate 33, so that the inclined section 212 gradually approaches the test silicon via 1 from the end of the straight section 211, thereby forming a structure on both sides that transitions from an equidistant gap to a gradually narrowing gap. During the test, the probe card is electrically connected to the test pads corresponding to the third metal plate 24 and the fourth metal plate 25, and a predetermined test signal is applied to measure the third and fourth capacitances respectively. When the through-silicon via 1 is ideally aligned, the equivalent third and fourth capacitances contributed by the straight section 211 and the inclined section 212 are basically the same. When the through-silicon via 1 is slightly offset along the second direction Y, the local spacing change between it and the inclined sections 212 on both sides is more significant, making the difference between the third and fourth capacitances more sensitive. By measuring and calibrating the difference between the third and fourth capacitances, the offset amount and direction of the through-silicon via 1 along the second direction Y can be obtained at a higher resolution, thereby improving the sensitivity and accuracy of offset detection in this direction. Combined with the test results in the first direction X, the two-dimensional offset of the through-silicon via 9 can be accurately characterized, which is beneficial for comprehensively evaluating the alignment performance of the back-side through-silicon via 9 process and improving product yield.

[0077] In some embodiments of this disclosure, see Figure 13 The conductive structure 2 may include a first metal plate 22, a second metal plate 23, a third metal plate 24, and a fourth metal plate 25. The first metal plate 22 and the second metal plate 23 are symmetrically arranged about the test through-silicon via 1 along a first direction X, wherein the first metal plate 22 is disposed on one side of the test through-silicon via 1 along the first direction X, and the second metal plate 23 is disposed on the other side of the test through-silicon via 1 along the first direction X. The first metal plate 22 and the second metal plate 23 form capacitors with the test through-silicon via 1 under the isolation of the dielectric layer 8. The third metal plate 24 and the fourth metal plate 25 are symmetrically arranged about the test through-silicon via 1 along a second direction Y, wherein the third metal plate 24 is located on one side of the test through-silicon via 1 along the second direction Y, and the fourth metal plate 25 is located on the other side of the test through-silicon via 1 along the second direction Y. The second direction Y is perpendicular to the first direction X. The third metal plate 24 and the fourth metal plate 25 form capacitors with the test through-silicon via 1 under the isolation of the dielectric layer 8.

[0078] Specifically, the method for testing using the conductive structure 2 comprising the first metal plate 22, the second metal plate 23, the third metal plate 24, and the fourth metal plate 25 may include: fixing the wafer 3 to be tested on the test platform, electrically connecting it to the test pads corresponding to the first metal plate 22, the second metal plate 23, the third metal plate 24, and the fourth metal plate 25 respectively through probe cards, and establishing an electrical connection with the reference potential terminal of the test through-silicon via 1; applying a predetermined test signal, such as an AC test voltage or a small signal excitation superimposed with a DC bias, between the test through-silicon via 1 and each metal plate 21, and measuring the first capacitance between the test through-silicon via 1 and the first metal plate 22, the second capacitance between the test through-silicon via 1 and the second metal plate 23, the third capacitance between the test through-silicon via 1 and the third metal plate 24, and the fourth capacitance between the test through-silicon via 1 and the fourth metal plate 25 respectively. According to the layout design, under ideal alignment, the first capacitor and the second capacitor are essentially equal, and the third capacitor and the fourth capacitor are essentially equal. When the test via 1 is offset along the first direction X, the first capacitor and the second capacitor will show a difference. The amount and direction of the offset along the first direction X can be deduced from the difference or ratio between the two. When the test via 1 is offset along the second direction Y, the third capacitor and the fourth capacitor will show a difference. The amount and direction of the offset along the second direction Y can be deduced from the difference or ratio between the two. By combining the test results of the first capacitor, the second capacitor, the third capacitor and the fourth capacitor, the offset vector of the test via 1 in the two-dimensional plane can be obtained.

[0079] A conductive structure 2 is constructed by symmetrically arranging a first metal plate 22 and a second metal plate 23 along a first direction X, and a third metal plate 24 and a fourth metal plate 25 along a second direction Y perpendicular to the first metal plate 23. The corresponding capacitance values ​​are measured by electrical means. This not only enables non-destructive detection of the offset of the through-silicon via (TSV) 9 at the wafer level, but also allows for simultaneous and independent characterization of the offset of the TSV 9 in two orthogonal directions. This achieves precise quantification of the two-dimensional alignment error of the TSV 9. Compared with the scheme of setting test electrodes in only one direction, this embodiment can provide more comprehensive offset information, which is beneficial for identifying systematic deviations of the process equipment in different directions, guiding the optimization and compensation of the alignment parameters of the back TSV 9, improving the stability of the back TSV 9 process, and further improving the yield of large-size memory chips.

[0080] In one embodiment of this disclosure, the conductive structure 2 includes a first metal plate 22, a second metal plate 23, a third metal plate 24, and a fourth metal plate 25, and the four metal plates 21 facing the test through-silicon via 1 are all straight segments 211 extending in the corresponding direction; the first metal plate 22 and the second metal plate 23 are symmetrically arranged with respect to the test through-silicon via 1 along the first direction X, the first metal plate 22 is located on one side of the test through-silicon via 1 along the first direction X, and the second metal plate 23 is located on the other side of the test through-silicon via 1 along the first direction X, and respectively form a first capacitor and a second capacitor with the test through-silicon via 1 under the isolation of the dielectric layer 8; the third metal plate 24 and the fourth metal plate 25 are symmetrically arranged with respect to the test through-silicon via 1 along the second direction Y, the third metal plate 24 is located on one side of the test through-silicon via 1 along the second direction Y, and the fourth metal plate 25 is located on the other side of the test through-silicon via 1 along the second direction Y, the second direction Y is perpendicular to the first direction X, and the third metal plate 24 and the fourth metal plate 25 respectively form a third capacitor and a fourth capacitor with the test through-silicon via 1 under the isolation of the dielectric layer 8. During testing, the wafer 3 to be tested is fixed on the test platform. The probe card is electrically connected to the test pads corresponding to the four metal plates 21, and an electrical connection is established with the reference potential terminal of the through-silicon via 1. A predetermined test signal is applied between the through-silicon via 1 and each metal plate 21, and the first capacitor, the second capacitor, the third capacitor and the fourth capacitor are measured respectively. Under ideal alignment, the first capacitor and the second capacitor are basically equal, and the third capacitor and the fourth capacitor are basically equal. When the through-silicon via 1 is offset along the first direction X, the first capacitor and the second capacitor show a difference. When it is offset along the second direction Y, the third capacitor and the fourth capacitor show a difference. The offset amount and offset direction of the through-silicon via 1 in the two orthogonal directions can be deduced from the difference or ratio between the above capacitor pairs, thereby obtaining the offset vector of the through-silicon via 1 in the two-dimensional plane. By arranging straight sections 211 of metal plates 21 in pairs symmetrically in the first direction X and the second direction Y and performing capacitance measurements, the alignment error of the through-silicon via 9 in both directions can be characterized simultaneously at wafer level 3 in a non-destructive manner. Compared with the scheme of setting test electrodes in only one direction, it can provide more comprehensive offset information, which is conducive to identifying systematic deviations of process equipment in different directions, guiding the optimization and compensation of alignment parameters of the back through-silicon via 9, and improving the stability of the back through-silicon via 9 process and the yield of large-size memory chips.

[0081] In another embodiment of this disclosure, the first metal plate 22, the second metal plate 23, the third metal plate 24, and the fourth metal plate 25 each include a straight section 211 extending in a corresponding direction and an inclined section 212 connected to the straight section 211 on the side facing the test through-silicon via 1. The straight sections 211 of the first metal plate 22 and the second metal plate 23 are symmetrically arranged with respect to the test through-silicon via 1 along the first direction X, and each of them extends an inclined section 212 at a predetermined angle relative to the first direction X, so that the inclined section 212 gradually approaches the test through-silicon via 1 from the end of the straight section 211. The straight sections 211 of the third metal plate 24 and the fourth metal plate 25 are symmetrically arranged with respect to the test through-silicon via 1 along the second direction Y, and each of them extends an inclined section 212 at a predetermined angle relative to the second direction Y, so that the inclined section 212 gradually approaches the test through-silicon via 1 from the end of the straight section 211. The four metal plates 21 form a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor with the test through-silicon via 1 under the isolation of the dielectric layer 8. The testing procedure is similar to that described above. A probe card is electrically connected to the test pads corresponding to the four metal plates 21, a predetermined test signal is applied, and the four capacitance values ​​are measured. When the via 1 is in the ideal alignment position, the equivalent first and second capacitances, and the third and fourth capacitances contributed by the combined straight section 211 and inclined section 212 are essentially equal. When the via 1 experiences a slight offset in the first direction X and / or the second direction Y, the local spacing change between it and the inclined sections 212 on both sides becomes more significant, making the difference between the corresponding capacitance pairs more sensitive to the offset. By measuring and calibrating the differences between the first and second capacitances and the third and fourth capacitances, the offset and direction of the via 1 in the two orthogonal directions can be obtained at a higher resolution. This achieves high sensitivity and accurate characterization of the two-dimensional offset of the via 9, further improving the accuracy of the back-side via 9 offset detection while considering layout feasibility and process reliability, providing strong support for process window optimization and yield improvement.

[0082] It should be noted that for at least two symmetrically arranged metal plates 21 within the conductive structure 2, the side facing the test silicon via 1 can adopt different specific forms: in some embodiments, the symmetrical metal plates 21 are all configured as straight segments 211 extending along a predetermined direction; in other embodiments, the symmetrical metal plates 21 are all configured as a combination structure consisting of a straight segment 211 extending along a predetermined direction and an inclined segment 212 connected thereto; wherein, for any pair of metal plates 21 symmetrically arranged with respect to the test silicon via 1, it is preferable to adopt the same segment combination and geometric parameters to ensure the symmetry and comparability of the structural layout and capacitance response.

[0083] The layer distribution of metal plate 21 is described in detail below: In some embodiments of this disclosure, see Figure 12 , Figure 15 The wafer 3 includes a first metal structure 4 disposed on a semiconductor substrate 33; the first metal structure 4 includes a plurality of first metal layers 42 and a top conductive layer 41 stacked along the thickness direction of the semiconductor substrate 33; the test silicon via 1 is electrically connected to the top conductive layer 41; adjacent first metal layers 42 are electrically connected through metal vias 43; wherein the first metal layers 42 and metal vias 43 are disposed on the same layer as at least a portion of the metal plate 21.

[0084] It should be noted that wafer 3 includes an active region 31 and a dicing region 32 located between the active regions 31. Wafer 3 includes a first metal structure 4 disposed on a semiconductor substrate 33. The first metal structure 4 forms a plurality of first metal layers 42 for realizing circuit interconnection in the active region 31 and a top conductive layer 41 located on the uppermost layer. Metal plates 21 for constituting capacitor electrodes are formed in the dicing region 32.

[0085] Specifically, the first metal structure 4 is stacked with multiple first metal layers 42 along the thickness direction of the semiconductor substrate 33. The test through-silicon via 1 is electrically connected to the top conductive layer 41, and adjacent first metal layers 42 are electrically connected through metal vias 43. In the dicing region 32, the metal plate 21 is composed of metal patterns on the same layer as the first metal layers 42 and / or metal vias 43, and the first metal layers 42 and metal vias 43 are disposed on the same layer as at least a portion of the metal plate 21. Thus, the first metal structure 4 is integrally formed in the active region 31 and the dicing region 32: the active region 31 provides functional circuit interconnection, and the dicing region 32 forms the metal plate 21 electrode that cooperates with the test through-silicon via 1, which helps to ensure the process consistency and alignment accuracy between the test area and the active region 31.

[0086] In this embodiment, by stacking multiple first metal layers 42 along the thickness direction on the semiconductor substrate 33 and connecting them through metal vias 43, the test silicon via 1 can be directly placed on the top conductive layer 41, which can obtain a larger equivalent conductive cross section and a lower series resistance. At the same time, the top conductive layer 41 is used as an effective stop layer for etching the test silicon via 1, thereby improving the reliability of the test silicon via 1 landing.

[0087] Furthermore, by setting the first metal layer 42 and its metal via 43 on the same layer as at least part of the metal plate 21, the metal layer and mask can be shared with the product interconnection, avoiding additional process steps, reducing manufacturing costs, and making the OVL offset reflected by the capacitance between the metal plate 21 and the test through-silicon via 1 closer to the actual alignment when the test through-silicon via 1 is connected to the high-layer metal, thereby improving the accuracy of offset monitoring and helping to improve yield.

[0088] Furthermore, the first metal layer 42, metal vias 43, and metal plate 21 can be fabricated in the same metal interconnect process in one step: for example, a dielectric layer 8 is deposited on wafer 3, and photolithography and etching are performed simultaneously in the active region 31 and the dicing region 32. An opening is made in the active region 31 to form a metal via connecting the upper and lower metal layers, and an opening is made in the dicing region 32 to form a metal plate 21 region that cooperates with the test silicon via 1. Subsequently, the first metal layer 42 and metal vias 43 are formed in the active region 31, and the metal plate 21 pattern corresponding to the test silicon via 1 is formed in the dicing region 32. Then, the steps of upper dielectric deposition, via opening, metal deposition, and patterning are repeated in sequence to obtain multiple first metal layers 42 and a top conductive layer 41 stacked along the thickness direction of the semiconductor substrate 33, wherein the portion located in the dicing region 32 is designed as a metal plate 21, which is used as the electrode plate of the test capacitor. This fabrication method allows for the simultaneous formation of product interconnects in the active region 31 and a test metal plate 21 in the cutting region 32 without adding additional metal layers or masks, achieving process sharing and plate sharing. Figure 1 It exhibits good consistency and ensures that the test structure is consistent with the actual interconnect structure in terms of hierarchy and materials.

[0089] In other embodiments of this disclosure, see [link to relevant documentation]. Figure 12 , Figure 16 The wafer 3 also includes a second metal structure 5 located in the active region 31 and disposed on the semiconductor substrate 33; the second metal structure 5 includes a bottom conductive layer 51 stacked on the semiconductor substrate 33 and a second metal layer 52 disposed on the bottom conductive layer 51; the test silicon via 1 is electrically connected to the bottom conductive layer 51; the second metal layer 52 is disposed in the same layer as at least a portion of the metal plate 21 in the conductive structure 2.

[0090] It should be noted that wafer 3 includes an active region 31 and a dicing region 32 located between the active regions 31. Wafer 3 also includes a second metal structure 5 disposed on a semiconductor substrate 33. The second metal structure 5 forms a bottom conductive layer 51 for realizing circuit interconnection in the active region 31 and a second metal layer 52 disposed on the bottom conductive layer 51. A metal plate 21 for constituting the conductive structure 2 is formed in the dicing region 32.

[0091] Specifically, the second metal structure 5 includes a bottom conductive layer 51 stacked on the semiconductor substrate 33 and a second metal layer 52 disposed on the bottom conductive layer 51. The test via 1 is electrically connected to the bottom conductive layer 51, and the second metal layer 52 is disposed on the same layer as at least a portion of the metal plate 21 in the conductive structure 2. This structure allows the second metal structure 5 to be integrally formed in the active region 31 and the dicing region 32: the active region 31 is used for circuit interconnection, and the dicing region 32 is used to form the metal plate 21 electrode that cooperates with the test via 1. This helps to ensure the consistency of the metal wiring process and the relative positional accuracy between the test area and the active region 31.

[0092] As an example, the second metal layer 52 includes a gate sublayer 521; wherein the gate sublayer 521 is disposed on the same layer as at least a portion of the metal plate 21 in the conductive structure 2. In this way, on the one hand, by using the front-end gate sublayer 521 itself as a reference layer and capacitor plate for testing the stacking offset of the through-silicon via 1, the alignment error of the through-silicon via 9 relative to key front-end structures such as the transistor gate can be directly reflected; on the other hand, the test metal plate 21 and the front-end gate sublayer 521 are co-fabricated, eliminating the need to design an additional test layer separately. Without increasing the layout and process complexity, accurate stacking offset characterization of the through-silicon via 9 relative to the lower-layer interconnects and gate structure can be achieved, which is beneficial for optimizing the alignment window between the through-silicon via 9 and the core device and improving device performance and yield.

[0093] As another example, the second metal layer 52 includes a metal interconnect sublayer 522; the metal interconnect sublayer 522 is disposed in the same layer as at least a portion of the metal plate 21 in the conductive structure 2. By integrally fabricating the metal interconnect sublayer 522 and the metal plate 21 in the same metal layer, the test structure and the actual signal interconnect can be kept consistent in terms of material system, thickness, and layout design rules. On the one hand, this avoids adding a separate metal layer or layout mask for the test structure, simplifying the process flow and reducing manufacturing costs. On the other hand, it makes the capacitance between the metal plate 21 and the test through-silicon via 1 more accurately reflect the stacking offset of the through-silicon via 9 relative to the actual metal interconnect, thereby improving the representativeness and guiding significance of the offset test results for the product interconnect structure, which is conducive to the precise optimization of the alignment process of the through-silicon via 9 and improving the chip yield.

[0094] According to a second aspect of this application, a wafer 3 is also provided. The wafer 3 includes the through-silicon via (TSV) testing structure as described above. By utilizing this TSV testing structure, the alignment offset and distribution of the TSV 9 in the active region 31 along the first direction X and the second direction Y can be measured at the wafer level under non-destructive conditions. This enables monitoring and correction of the TSV 9 process alignment capability, reduces stacking errors, improves the stability of the back-side TSV 9 process, and increases the overall yield of large-size memory chips.

[0095] According to the third aspect of this application, see Figure 17 Furthermore, a method for testing the offset of through-silicon vias (TSVs) is provided. This method uses a TSV test structure located in a diced region 32 of wafer 3. The TSV test structure includes at least one test TSV 1 and conductive structures 2 arranged at intervals on a plane from the test TSV 1. The test TSV 1 and the conductive structures 2 are separated by a dielectric layer 8 to form a capacitor. The test method includes: S1: Measure the capacitance between the conductive structure 2 and the test silicon via 1.

[0096] S2: Determine the offset of test through-silicon via 1 based on the capacitance value.

[0097] In some embodiments of this disclosure, the conductive structure 2 includes at least two metal plates 21, which are symmetrically arranged about the test through-silicon via 1.

[0098] Measuring the capacitance between the conductive structure 2 and the test through-silicon via 1 includes: measuring the capacitance between at least two metal plates 21 and the test through-silicon via 1 respectively; The offset of the test through-silicon via (TSV) is determined based on the capacitance value, including: determining the offset of the test TSV 1 along the arrangement direction of the two metal plates 21 based on the difference in capacitance values ​​corresponding to the two metal plates 21 symmetrically arranged about the test TSV 1.

[0099] Furthermore, the specific testing steps are as follows: The metal plate 21 is electrically connected to the corresponding test pad. Before testing, the wafer 3 to be tested is fixed on the test platform with its test surface facing upwards, and an electrical connection is established between the test probe card and the test pad on the surface of the wafer 3. Specifically, each metal plate 21 symmetrically arranged along the first direction X and the second direction Y in the conductive structure 2 is led out to the corresponding test pad through metal traces. During testing, the test probes on the probe card are positioned on each test pad, so that the metal plate 21 is connected to the external test equipment through the test pad; at the same time, the reference potential terminal of the test through-silicon via 1 is connected to the reference terminal or ground terminal of the test instrument, thereby forming a test circuit that can be used for capacitance measurement.

[0100] Based on the metal plates 21 symmetrically arranged along the first direction X, the capacitance values ​​between each metal plate 21 and the test through-silicon via 1 are measured. After completing the electrical connection, the test channel corresponding to the metal plate 21 symmetrically arranged along the first direction X is selected, and a predetermined test signal, such as an AC test voltage with set amplitude and frequency, is applied between the test through-silicon via 1 and the metal plate 21 on one side of the first direction X using a capacitance meter. The first capacitance value between the test through-silicon via 1 and the metal plate 21 is measured. Then, the test channel is switched, and the same test conditions are used to measure the second capacitance value between the test through-silicon via 1 and the metal plate 21 on the other side of the first direction X. During the test, the test environment, signal parameters, and reference potential are kept consistent to ensure the comparability of the two measurement results.

[0101] By comparing the values ​​of two capacitors symmetrically positioned along the first direction X, the offset of the test via 1 in the first direction X is determined. For two metal plates 21 symmetrically positioned along the first direction X, under ideal alignment in the layout design, the geometric relationship between the test via 1 and the two metal plates 21 is symmetrical, and the corresponding first and second capacitor values ​​should theoretically be approximately equal. If there is a difference between the two measured capacitor values, it indicates that the test via 1 has shifted relative to its theoretical center position in the first direction X. Based on the pre-established capacitance-spacing relationship model and the capacitance-offset curve obtained through calibration, the offset and direction of the test via 1 relative to the geometric center of the first direction X can be calculated using the difference or ratio between the first and second capacitor values, thereby obtaining the offset of the test via 1 in the first direction X.

[0102] Based on the metal plates 21 symmetrically arranged along the second direction Y, the capacitance values ​​between each metal plate 21 and the test through-silicon via 1 are measured. Then, the test channels corresponding to the metal plates 21 symmetrically arranged along the second direction Y are selected, where the second direction Y is perpendicular to the first direction X. Using the same test method and conditions as in step S2, the third capacitance value between the test through-silicon via 1 and the metal plate 21 on one side of the second direction Y, and the fourth capacitance value between the via 1 and the metal plate 21 on the other side of the second direction Y, are measured. To ensure test accuracy, multiple test units can be repeatedly measured on the same wafer 3 and averaged or statistically processed to reduce the impact of test noise and process fluctuations.

[0103] By comparing the values ​​of two capacitors symmetrically positioned along the second direction Y, the offset of the test through-silicon via 1 in the second direction Y is determined. Similar to the determination method in the first direction X, under ideal alignment, the metal plates 21 on both sides of the second direction Y are geometrically symmetrical with the test through-silicon via 1, and the corresponding third and fourth capacitance values ​​should be approximately equal. If there is a deviation between the actual measured third and fourth capacitance values, it indicates that the test through-silicon via 1 also has an offset in the second direction Y. Based on the pre-calibrated relationship between capacitance and offset, the offset and direction of the test through-silicon via 1 in the second direction Y can be calculated using the difference or ratio between the third and fourth capacitance values. Combining the offset result in the first direction X obtained in step S3 and the offset result in the second direction Y obtained in step S5, the two-dimensional offset of the test through-silicon via 1 in the wafer 3 plane can be determined, providing a quantitative basis for evaluating and optimizing the process alignment performance of the through-silicon via 9 in the active region.

[0104] It should be noted that in practical applications, the offset determination method can be flexibly selected according to process monitoring requirements. For example, when only the alignment accuracy of the through-silicon via 1 in the first direction X needs to be evaluated, the offset in the first direction X can be obtained by comparing and converting the first capacitance value and the second capacitance value obtained in steps S2 and S3. When only the alignment accuracy in the second direction Y needs to be considered, the offset in the second direction Y can be determined by analyzing the third capacitance value and the fourth capacitance value obtained in steps S4 and S5. In addition, the capacitance measurement results on both sides of the first direction X and the second direction Y can be used simultaneously to comprehensively calculate the offset in the first direction X obtained in step S3 and the offset in the second direction Y obtained in step S5 to obtain the comprehensive offset and offset direction of the through-silicon via 1 in the wafer 3 plane, thereby achieving a comprehensive characterization of the through-silicon via alignment error.

[0105] It should be understood that this application is not limited to the detailed structure and arrangement of the components proposed in this application. This application can have other embodiments and can be implemented and executed in various ways. The foregoing variations and modifications fall within the scope of this application. It should be understood that the disclosure and definition of this application extends to all alternative combinations of two or more individual features mentioned or apparent in the text and / or drawings. All these different combinations constitute multiple alternative aspects of this application. The embodiments described in this application illustrate the best known mode for implementing this application and will enable those skilled in the art to utilize this application.

Claims

1. A through-silicon via (TSV) testing structure for testing the offset of TSVs within a wafer, the wafer comprising a semiconductor substrate, an active region, and a dicing region disposed between the active regions, characterized in that, The through-silicon via (TSV) test structure is disposed in the dicing area, and the TSV test structure includes: At least one test through-silicon via; A conductive structure is provided, wherein the conductive structure and the test through-silicon via are arranged at intervals on a plane, and the test through-silicon via and the conductive structure are separated by a dielectric layer to form a capacitor; The through-silicon via (TSV) test structure is configured to characterize the offset of the test TSV based on the capacitance measurement results; The conductive structure includes: four metal plates arranged symmetrically around and relative to the test through-silicon via (TSV), each forming a capacitor with respect to the opposite sides of the TSV under the isolation of the dielectric layer; each metal plate includes a straight section extending along its length and two inclined sections, the two inclined sections being respectively located at both ends of the straight section and connected to the straight section, the inclined sections gradually approaching the TSV from the end of the straight section; wherein, the two inclined sections arranged adjacent to each other along the circumference of the TSV and connected to different metal plates are arranged face-to-face.

2. The through-silicon via (TSV) testing structure according to claim 1, characterized in that, In a plane parallel to the semiconductor substrate, with the extension direction of the metal plate as a reference line, the distance between the inclined segment near the straight segment and the test through-silicon via gradually decreases from the end of the inclined segment away from the straight segment to the end of the inclined segment away from the straight segment.

3. The through-silicon via (TSV) testing structure according to claim 2, characterized in that, The minimum distance between the straight section and the periphery of the test through-silicon via is greater than or equal to the minimum distance between the inclined section and the periphery of the test through-silicon via.

4. The through-silicon via (TSV) testing structure according to claim 1, characterized in that, The conductive structure includes a first metal plate and a second metal plate; The first metal plate and the second metal plate are symmetrically arranged about the test through-silicon via along a first direction, wherein the first metal plate is disposed on one side of the test through-silicon via along the first direction, and the second metal plate is disposed on the other side of the test through-silicon via along the first direction. The first metal plate and the second metal plate respectively form a capacitor with the test through-silicon via under the isolation of the dielectric layer.

5. The through-silicon via (TSV) testing structure according to claim 4, characterized in that, The first metal plate and the second metal plate are electrically connected to their respective test pads.

6. The through-silicon via (TSV) testing structure according to claim 4, characterized in that, The conductive structure includes a third metal plate and a fourth metal plate; The third metal plate and the fourth metal plate are symmetrically arranged about the test through-silicon via along the second direction, wherein the third metal plate is disposed on one side of the test through-silicon via along the second direction, and the fourth metal plate is disposed on the other side of the test through-silicon via along the second direction, the second direction being perpendicular to the first direction, and the third metal plate and the fourth metal plate respectively form a capacitor with the test through-silicon via under the isolation of the dielectric layer.

7. The through-silicon via (TSV) testing structure according to claim 6, characterized in that, The third metal plate and the fourth metal plate are electrically connected to their corresponding test pads.

8. The through-silicon via (TSV) testing structure according to claim 1, characterized in that, The wafer also includes a first metal structure disposed on the semiconductor substrate; The first metal structure includes a plurality of first metal layers and a top conductive layer stacked along the thickness direction of the semiconductor substrate; The test silicon via is electrically connected to the top conductive layer; The adjacent first metal layers are electrically connected through metal vias; wherein the first metal layer and the metal vias are disposed in the same layer as at least a portion of the metal plate.

9. The through-silicon via (TSV) testing structure according to claim 1, characterized in that, The wafer also includes a second metal structure disposed on the semiconductor substrate; The second metal structure includes a bottom conductive layer stacked on the semiconductor substrate and a second metal layer disposed on the bottom conductive layer; The test silicon via is electrically connected to the underlying conductive layer; The second metal layer is disposed in the same layer as at least a portion of the metal plate in the conductive structure.

10. The through-silicon via (TSV) testing structure according to claim 9, characterized in that, The second metal layer includes a gate sublayer; The gate sublayer is disposed in the same layer as at least a portion of the metal plate in the conductive structure.

11. The through-silicon via (TSV) testing structure according to claim 10, characterized in that, The second metal layer includes a metal interconnect sublayer; The metal interconnect sublayer is disposed in the same layer as at least a portion of the metal plate in the conductive structure.

12. A wafer, characterized in that, Includes the through-silicon via (TSV) test structure as described in any one of claims 1 to 11.

13. A method for testing the offset of a through-silicon via (TSV), characterized in that, The test method uses a through-silicon via (TSV) test structure located in the dicing area of ​​the wafer for testing. The TSV test structure includes at least one test TSV and a conductive structure spaced apart from the test TSV on a plane. The test TSV and the conductive structure are separated by a dielectric layer to form a capacitor. The conductive structure includes: four metal plates arranged symmetrically around and relative to the test through-silicon via (TSV), each forming a capacitor with respect to the opposite sides of the TSV under the isolation of the dielectric layer; each metal plate includes a straight section extending along its length and two inclined sections, the two inclined sections being respectively located at both ends of the straight section and connected to the straight section, the inclined sections gradually approaching the TSV from the ends of the straight section; wherein, the two inclined sections arranged adjacent to each other along the circumference of the TSV and connected to different metal plates are arranged face-to-face; The testing method includes: The capacitance values ​​formed between the four metal plates and the test silicon vias were measured respectively. Based on the difference in capacitance values ​​between the two metal plates symmetrically arranged with respect to the test through-silicon via, the offset of the test through-silicon via along the arrangement direction of the two metal plates is determined.

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