A test structure, a bonded wafer structure, a method of detecting wafer bonding misalignment based on a test structure, and a detection apparatus

Abstract

The application provides a test structure, a bonded wafer structure, a wafer bonding offset detection method based on the test structure, and a detection device. The test structure comprises at least one test subunit arranged in a cutting area. The test subunit comprises a first electrode plate and a second electrode plate. The first electrode plate is formed on a first wafer, and the second electrode plate is formed on a second wafer. The first electrode plate and the second electrode plate are arranged at intervals to form a capacitor. When the first wafer and the second wafer are in a preset alignment state, in a projection plane along a bonding direction of the first wafer and the second wafer, the orthographic projection of the first electrode plate is at least partially located in the coverage range of the orthographic projection of the second electrode plate, and at least one side boundary of the orthographic projection of the first electrode plate is aligned with the corresponding side boundary of the orthographic projection of the second electrode plate. The test structure can determine the bonding offset between the first wafer and the second wafer.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a test structure, a bonding wafer structure, a wafer bonding offset detection method based on the test structure, and a detection device. Background Technology

[0002] In related technologies, with the development of 3D integration and advanced packaging technologies, wafer bonding technology is widely used to connect two wafers in the thickness direction to achieve electrical connections or structural integration between different wafers. Through wafer bonding, different wafers can be fabricated using appropriate processes, and then bonded together to form an integral structure, thereby improving chip integration and enhancing signal transmission efficiency and system integration performance.

[0003] However, during wafer bonding, a high degree of alignment accuracy must be maintained between the two wafers. If an overlap misalignment occurs between the two wafers, the effective contact area between the bonding structures, interconnect structures, or conductive structures on the upper and lower wafers may deviate from the design specifications, leading to problems such as increased contact resistance, open circuits, short circuits, or decreased yield. Since the alignment relationship between the upper and lower wafers after wafer bonding is difficult to directly observe or measure, how to detect the bonding misalignment between the two wafers after bonding becomes a problem that needs to be solved. Summary of the Invention

[0004] To overcome the problems existing in related technologies, this specification provides a test structure, a bonding wafer structure, a wafer bonding offset detection method based on the test structure, and a detection device to determine the bonding offset between a first wafer and a second wafer.

[0005] According to a first aspect of the embodiments of this specification, a test structure is provided for bonding process testing of a first wafer and a second wafer, both the first wafer and the second wafer including a chip region and a dicing region located between adjacent chip regions; the test structure includes at least one test sub-unit disposed in the dicing region; the test sub-unit includes a first electrode plate and a second electrode plate, the first electrode plate being formed on the first wafer and the second electrode plate being formed on the second wafer, the first electrode plate and the second electrode plate being spaced apart to form a capacitor; wherein, when the first wafer and the second wafer are in a preset alignment state, on a projection surface along the bonding direction of the first wafer and the second wafer, the orthographic projection of the first electrode plate is at least partially located within the coverage area of ​​the orthographic projection of the second electrode plate, and at least one side boundary of the orthographic projection of the first electrode plate is aligned with the corresponding side boundary of the orthographic projection of the second electrode plate.

[0006] In some embodiments of this disclosure, the at least one test subunit includes a first subunit and a second subunit; and / or a third subunit and a fourth subunit; wherein the first subunit and the second subunit are used to jointly characterize the overlap offset of the first wafer and the second wafer in a first direction; the third subunit and the fourth subunit are used to jointly characterize the overlap offset of the first wafer and the second wafer in a second direction; both the first direction and the second direction are perpendicular to the bonding direction, and the first direction intersects the second direction.

[0007] In some embodiments of this disclosure, the at least one test subunit includes a first subunit and a second subunit; the first subunit forms a first capacitor, and the second subunit forms a second capacitor; the capacitance difference between the first capacitor and the second capacitor is used to characterize the stacking offset of the first wafer and the second wafer in a first direction.

[0008] In some embodiments of this disclosure, the at least one test subunit further includes a third subunit and a fourth subunit; the third subunit is used to form a third capacitor, the fourth subunit is used to form a fourth capacitor, and the capacitance difference between the third capacitor and the fourth capacitor is used to characterize the stacking offset of the first wafer and the second wafer in a second direction.

[0009] In some embodiments of this disclosure, in the first sub-unit, the first electrode plate has a first side and a second side disposed along a first direction; the second electrode plate has a third side and a fourth side disposed along the first direction; wherein, when the first wafer and the second wafer are in a preset alignment state, the orthographic projection of the first side is aligned with the orthographic projection of the third side, and the orthographic projection of the second side is located between the orthographic projection of the third side and the orthographic projection of the fourth side.

[0010] In some embodiments of this disclosure, in the second sub-unit, the first electrode plate has a fifth side and a sixth side disposed opposite to each other along the first direction; the second electrode plate has a seventh side and an eighth side disposed opposite to each other along the first direction; wherein, when the first wafer and the second wafer are in a preset alignment state, on the projection surface along the bonding direction, the orthographic projection of the sixth side is aligned with the orthographic projection of the eighth side, and the orthographic projection of the fifth side is located between the orthographic projection of the seventh side and the orthographic projection of the eighth side.

[0011] In some embodiments of this disclosure, in the third sub-unit, the first electrode plate has a ninth side and a tenth side disposed opposite to each other along a second direction; the second electrode plate has an eleventh side and a twelfth side disposed opposite to each other along the second direction; wherein, when the first wafer and the second wafer are in a preset alignment state, on the projection surface along the bonding direction, the orthographic projection of the ninth side is aligned with the orthographic projection of the eleventh side, and the orthographic projection of the tenth side is located between the orthographic projection of the eleventh side and the orthographic projection of the twelfth side.

[0012] In some embodiments of this disclosure, in the fourth sub-unit, the first electrode plate has a thirteenth side and a fourteenth side disposed opposite to each other along the second direction; the second electrode plate has a fifteenth side and a sixteenth side disposed opposite to each other along the second direction; wherein, when the first wafer and the second wafer are in a preset alignment state, on the projection surface along the bonding direction, the orthographic projection of the fourteenth side is aligned with the orthographic projection of the sixteenth side, and the orthographic projection of the thirteenth side is located between the orthographic projections of the fifteenth side and the sixteenth side.

[0013] In some embodiments of this disclosure, the first wafer includes a first substrate and a bonding layer disposed on one side of the first substrate; the second wafer includes a second substrate, a metal conductive layer disposed on one side of the second substrate, and an interlayer dielectric layer formed in the second wafer; wherein the first electrode plate is disposed in the same layer as the bonding layer, the second electrode plate is disposed in the same layer as the metal conductive layer, and the interlayer dielectric layer is located between the first electrode plate and the second electrode plate when the first wafer and the second wafer are bonded together.

[0014] In some embodiments of this disclosure, the first wafer includes a first substrate, a first metal interconnect layer disposed on one side of the first substrate, and a first dielectric layer formed in the first wafer; the second wafer includes a second substrate, a second metal interconnect layer disposed on one side of the second substrate, and a second dielectric layer formed in the second wafer; wherein, the first electrode plate and the first metal interconnect layer are disposed in the same layer, and the second electrode plate and the second metal interconnect layer are disposed in the same layer; when the first wafer and the second wafer are bonded together, the first dielectric layer and / or the second dielectric layer are located between the first electrode plate and the second electrode plate.

[0015] In some embodiments of this disclosure, the first wafer includes a first substrate, a metal interconnect layer disposed on one side of the first substrate, and an interlayer dielectric layer formed in the first wafer; the second wafer includes a second substrate and a bonding layer disposed on one side of the second substrate; wherein the first electrode plate is disposed in the same layer as the metal interconnect layer, and the second electrode plate is disposed in the same layer as the bonding layer; when the first wafer and the second wafer are bonded together, the interlayer dielectric layer is located between the first electrode plate and the second electrode plate.

[0016] According to a second aspect of the embodiments of this specification, a bonding wafer structure is provided, including a first wafer, a second wafer, and the aforementioned test structure; the first wafer and the second wafer are bonded together, and both the first wafer and the second wafer include a chip region and a dicing region located between adjacent chip regions; the test structure is disposed in the dicing region of the first wafer and the second wafer.

[0017] According to a third aspect of the embodiments of this specification, a wafer bonding offset detection method based on a test structure is provided. The test structure is disposed in a dicing region of a first wafer and a second wafer. The test structure includes at least one test sub-unit disposed in the dicing region. The test sub-unit includes a first electrode plate and a second electrode plate. The first electrode plate is formed on the first wafer, and the second electrode plate is formed on the second wafer. The first electrode plate and the second electrode plate are spaced apart to form a capacitor. On a projection plane along the bonding direction of the first wafer and the second wafer, the orthographic projection of the first electrode plate is at least partially located within the coverage area of ​​the orthographic projection of the second electrode plate, and at least one side boundary of the orthographic projection of the first electrode plate is aligned with the corresponding side boundary of the orthographic projection of the second electrode plate. The detection method includes: acquiring a capacitance value between the first electrode plate and the second electrode plate; and determining a bonding offset result between the first wafer and the second wafer based on the capacitance value and a preset correspondence.

[0018] In some embodiments of this disclosure, the at least one test subunit includes a first subunit and a second subunit; and / or a third subunit and a fourth subunit; wherein the first subunit and the second subunit are used to jointly characterize the stacking offset of the first wafer and the second wafer in a first direction; the third subunit and the fourth subunit are used to jointly characterize the stacking offset of the first wafer and the second wafer in a second direction; both the first direction and the second direction are perpendicular to the bonding direction of the first wafer and the second wafer, and the first direction intersects the second direction; obtaining the capacitance value between the first electrode plate and the second electrode plate includes: obtaining a first capacitance value formed by the first subunit and a second capacitance value formed by the second subunit; and / or, obtaining a third capacitance value formed by the third subunit and a fourth capacitance value formed by the fourth subunit.

[0019] In some embodiments of this disclosure, determining the bonding offset result between the first wafer and the second wafer based on the capacitance value and a preset correspondence includes at least one of the following: determining the bonding offset of the first wafer and the second wafer in the first direction based on the capacitance difference between the first capacitance value and the second capacitance value and a first preset correspondence; determining the bonding offset of the first wafer and the second wafer in the second direction based on the capacitance difference between the third capacitance value and the fourth capacitance value and a second preset correspondence.

[0020] According to a fourth aspect of the embodiments of this specification, a testing device is provided for testing a test structure disposed on a first wafer and a second wafer, comprising: a sampling module configured to acquire capacitance values ​​formed by test sub-units in the test structure; a comparison module connected to the sampling module, the comparison module being configured to acquire capacitance differences between at least two capacitance values ​​formed by the test sub-units; and an offset determination module connected to the comparison module, the offset determination module being configured to determine a bonding offset result between the first wafer and the second wafer based on the capacitance difference and a preset correspondence.

[0021] In the embodiments of this specification, after the first wafer and the second wafer are bonded, the capacitance value between the first electrode plate and the second electrode plate can be obtained. Since the first electrode plate is formed on the first wafer and the second electrode plate is formed on the second wafer, when a bond misalignment occurs between the first wafer and the second wafer, the overlap relationship between the first electrode plate and the second electrode plate in the projection direction changes, causing a change in the effective overlap area between them and resulting in a change in the capacitance value. Therefore, the bond misalignment between the first wafer and the second wafer can be determined based on this capacitance value. Compared with related technologies where the alignment relationship between the upper and lower wafers after wafer bonding is difficult to observe directly, leading to difficulties in bond misalignment detection, this application transforms the bond misalignment into a capacitance change between the first electrode plate and the second electrode plate, making it easier to detect the bond misalignment through electrical testing. At the same time, by aligning at least one side boundary of the first electrode plate with the corresponding side boundary of the second electrode plate, the sensitivity of the capacitance value to the corresponding directional misalignment can be improved; furthermore, the test subunit is located in the dicing area, which reduces the occupation of the functional structure of the chip area and facilitates detection before wafer dicing.

[0022] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this specification. Attached Figure Description

[0023] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this specification and, together with the description, serve to explain the principles of this specification.

[0024] Figure 1 This is a schematic diagram of the test structure in the first embodiment of this disclosure.

[0025] Figure 2 This is a schematic diagram of the test structure in the second embodiment of this disclosure.

[0026] Figure 3 This is a schematic diagram of the test structure in the third embodiment of this disclosure.

[0027] Figure 4 This is a schematic diagram of the first electrode plate and the second electrode plate in the first subunit of this disclosure embodiment.

[0028] Figure 5 This is a schematic diagram of the first electrode plate and the second electrode plate in the second subunit of this disclosure embodiment.

[0029] Figure 6 This is a schematic diagram of the first electrode plate and the second electrode plate in the third subunit of this disclosure embodiment.

[0030] Figure 7This is a schematic diagram of the first electrode plate and the second electrode plate in the fourth subunit of this disclosure embodiment.

[0031] Explanation of reference numerals in the attached figures: 1. Test Structure; 11. Test Subunit; 111. First Subunit; 1111. First Side; 1112. Second Side; 1113. Third Side; 1114. Fourth Side; 112. Second Subunit; 1121. Fifth Side; 1122. Sixth Side; 1123. Seventh Side; 1124. Eighth Side; 113. Third Subunit; 1131. Ninth Side; 1132. Tenth Side; 1133. Eleventh Side; 1134. Twelfth Side; 114. Fourth Subunit; 1141. Thirteenth Side 1142, Fourteenth side edge; 1143, Fifteenth side edge; 1144, Sixteenth side edge; 12, First electrode plate; 13, Second electrode plate; 2, First wafer; 21, First substrate; 22, Bonding layer; 23, First metal interconnect layer; 24, First dielectric layer; 25, Metal connection layer; 26, Interlayer dielectric layer; 3, Second wafer; 31, Second substrate; 32, Metal conductive layer; 33, Interlayer dielectric layer; 34, Second metal interconnect layer; 35, Second dielectric layer; 36, Bonding layer; X, First direction; Y, Second direction. Detailed Implementation

[0032] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this specification. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this specification as detailed in the appended claims.

[0033] The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to be limiting of this specification. The singular forms “a,” “the,” and “the” as used in this specification and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.

[0034] It should be understood that although the terms first, second, third, etc., may be used in this specification to describe various information, this information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this specification, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0035] In related technologies, the alignment of two wafers during the bonding process is quite difficult, and the stack offset after bonding is difficult to measure directly. Poor control of the stack offset can easily lead to problems such as increased contact resistance, open circuit or short circuit.

[0036] Based on this, see Figures 1 to 7 This application provides a test structure 1 for bonding process testing of a first wafer 2 and a second wafer 3. Both the first wafer 2 and the second wafer 3 include a chip region and a dicing region located between adjacent chip regions. The test structure 1 includes at least one test sub-unit 11 disposed in the dicing region. The test sub-unit 11 includes a first electrode plate 12 and a second electrode plate 13. The first electrode plate 12 is formed on the first wafer 2, and the second electrode plate 13 is formed on the second wafer 3. After the first wafer 2 and the second wafer 3 are bonded, the first electrode plate 12 and the second electrode plate 13 are spaced apart and opposite each other, forming a capacitor between them. Wherein, when the first wafer 2 and the second wafer 3 are in a preset alignment state, on the projection surface along the bonding direction of the first wafer 2 and the second wafer 3, the orthographic projection of the first electrode plate 12 is at least partially located within the coverage area of ​​the orthographic projection of the second electrode plate 13, and at least one side boundary of the orthographic projection of the first electrode plate 12 is aligned with the corresponding side boundary of the orthographic projection of the second electrode plate 13. By obtaining the capacitance value of the capacitor, the change in the effective overlap area between the first electrode plate 12 and the second electrode plate 13 can be reflected.

[0037] Compared to related technologies where the bonding offset of two wafers after bonding is difficult to measure directly, leading to problems such as increased contact resistance, open circuits, or short circuits due to poor offset control, this embodiment transforms the bonding offset between the first wafer 2 and the second wafer 3 into a capacitance change between the first electrode plate 12 and the second electrode plate 13, allowing the bonding offset to be characterized through electrical testing. This reduces the difficulty of bonding offset detection and facilitates monitoring of bonding quality after wafer bonding and before dicing.

[0038] It is understood that the dicing area is the region located between adjacent chip areas, such as a dicing track, dicing track, or test key area. This area is usually not used as the functional device area of ​​the final chip and can be removed during wafer dicing. Therefore, setting the test sub-unit 11 in the dicing area can reduce the occupation of the functional circuit or effective device area of ​​the chip area, while facilitating the arrangement of test pads, test lead structures, or other test support structures during the wafer-level testing stage.

[0039] The statement that "when the first wafer 2 and the second wafer 3 are in a preset alignment state, on the projection surface along the bonding direction of the first wafer 2 and the second wafer 3, the orthographic projection of the first electrode plate 12 is at least partially located within the coverage area of ​​the orthographic projection of the second electrode plate 13, and at least one side boundary of the orthographic projection of the first electrode plate 12 is aligned with the corresponding side boundary of the orthographic projection of the second electrode plate 13" can be understood as follows: when viewed along the stacking direction of the first wafer 2 and the second wafer 3, the first electrode plate 12 and the second electrode plate 13 have an overlapping area, and they form a boundary flush relationship on at least one side. Thus, when the first wafer 2 and the second wafer 3 experience bonding offset along the direction corresponding to this flush boundary, the effective overlap area between the first electrode plate 12 and the second electrode plate 13 changes, thereby causing a change in capacitance value, which facilitates the determination of bonding offset in the corresponding direction through capacitance value. In some embodiments of this disclosure, the test subunit 11 includes a first subunit 111 and a second subunit 112. The first subunit 111 is used to form a first capacitor, and the second subunit 112 is used to form a second capacitor. The capacitance difference between the first capacitor and the second capacitor is used to characterize the stacking offset of the first wafer 2 and the second wafer 3 in the first direction X. Here, the first direction X is perpendicular to the bonding direction, that is, the first direction X can be understood as an offset detection direction located in the wafer plane.

[0040] In this embodiment, compared to judging the stacking offset by relying solely on a single capacitance value, this embodiment forms a first capacitor and a second capacitor by using a first subunit 111 and a second subunit 112 respectively, and uses the capacitance difference between the first capacitor and the second capacitor to characterize the stacking offset in the first direction X. This helps to reduce the impact of electrode plate size error, dielectric thickness fluctuation, or dielectric constant fluctuation on the detection results, thereby improving the reliability of the stacking offset detection in the first direction X.

[0041] It is understandable that the first subunit 111 and the second subunit 112 can correspond to opposite offset directions in the first direction X. Since one side boundary of the first electrode plate 12 in each test subunit 11 is aligned with the corresponding side boundary of the second electrode plate 13, and the remaining part of the first electrode plate 12 is located within the coverage area of ​​the second electrode plate 13, within the stacking offset range allowed by normal process, when the first wafer 2 and the second wafer 3 are offset towards the alignment boundary direction, the effective overlap area between the first electrode plate 12 and the second electrode plate 13 in the corresponding test subunit 11 decreases, resulting in a decrease in the corresponding capacitance value; when the first wafer 2 and the second wafer 3 are offset towards the coverage area, the first electrode plate 12 is still located within the coverage area of ​​the second electrode plate 13, making it difficult for the effective overlap area to decrease significantly. Therefore, the larger capacitance value of the first capacitance and the second capacitance can be used as the reference capacitance value, and the offset direction in the first direction X can be determined according to the test subunit 11 corresponding to the smaller capacitance value, and the stacking offset amount in the first direction X can be determined according to the capacitance difference between the first capacitance and the second capacitance.

[0042] Specifically, in the first sub-unit 111, the first electrode plate 12 has opposing first side 1111 and second side 1112 along the first direction X, and the second electrode plate 13 has opposing third side 1113 and fourth side 1114 along the first direction X. When the first wafer 2 and the second wafer 3 are in a preset alignment state, on the projection plane along the bonding direction, the orthographic projection of the first side 1111 is aligned with the orthographic projection of the third side 1113, and the orthographic projection of the second side 1112 is located between the orthographic projections of the third side 1113 and the fourth side 1114. That is, one side of the first electrode plate 12 in the first direction X is flush with one side of the second electrode plate 13, and the other side of the first electrode plate 12 in the first direction X does not exceed the coverage area of ​​the second electrode plate 13. Thus, the first sub-unit 111 forms an offset-sensitive structure on one side of the first direction X; when the first wafer 2 and the second wafer 3 are offset along the side corresponding to the first side 1111 and the third side 1113, the effective overlap area between the first electrode plate 12 and the second electrode plate 13 decreases, and the first capacitance decreases accordingly.

[0043] In the second subunit 112, the first electrode plate 12 has a fifth side 1121 and a sixth side 1122 opposite to each other along the first direction X, and the second electrode plate 13 has a seventh side 1123 and an eighth side 1124 opposite to each other along the first direction X. When the first wafer 2 and the second wafer 3 are in a preset alignment state, on the projection plane along the bonding direction, the orthographic projection of the sixth side 1122 is aligned with the orthographic projection of the eighth side 1124, and the orthographic projection of the fifth side 1121 is located between the orthographic projections of the seventh side 1123 and the eighth side 1124. In other words, the second sub-unit 112 and the first sub-unit 111 have opposite boundary alignment directions in the first direction X, so that the second sub-unit 112 forms an offset-sensitive structure on the other side of the first direction X; when the first wafer 2 and the second wafer 3 are offset along the side corresponding to the sixth side 1122 and the eighth side 1124, the effective overlap area between the first electrode plate 12 and the second electrode plate 13 is reduced, and the second capacitance is reduced accordingly.

[0044] Therefore, the first subunit 111 and the second subunit 112 can respectively correspond to opposite offset directions in the first direction X. By comparing the sizes of the first capacitor and the second capacitor, the offset sides of the first wafer 2 and the second wafer 3 in the first direction X can be determined; the capacitance difference between the first capacitor and the second capacitor can characterize the stacking offset in the first direction X.

[0045] In some embodiments, the test subunit 11 further includes a third subunit 113 and a fourth subunit 114. The third subunit 113 is used to form a third capacitor, and the fourth subunit 114 is used to form a fourth capacitor. The capacitance difference between the third capacitor and the fourth capacitor is used to characterize the stacking offset of the first wafer 2 and the second wafer 3 in the second direction Y. The second direction Y intersects the first direction X and is perpendicular to the bonding direction; that is, the second direction Y can be understood as another offset detection direction located within the wafer plane and distinct from the first direction X.

[0046] In this embodiment, a third capacitor and a fourth capacitor are formed by a third subunit 113 and a fourth subunit 114, respectively, and the capacitance difference between the third capacitor and the fourth capacitor is used to characterize the stacking offset in the second direction Y. This enables the test structure 1 to detect the stacking offset of the first wafer 2 and the second wafer 3 in different directions, thereby improving the integrity and reliability of the bonding offset detection.

[0047] It is understandable that the third subunit 113 and the fourth subunit 114 can correspond to opposite offset directions in the second direction Y, respectively. Since one side boundary of the first electrode plate 12 in each test subunit 11 is aligned with the corresponding side boundary of the second electrode plate 13, and the remaining portion of the first electrode plate 12 is within the coverage area of ​​the second electrode plate 13, within the allowable stacking offset range of the normal process, when the first wafer 2 and the second wafer 3 offset towards the aligned boundary direction, the effective overlap area between the first electrode plate 12 and the second electrode plate 13 in the corresponding test subunit 11 decreases, resulting in a decrease in the corresponding capacitance value. When the first wafer 2 and the second wafer 3 offset towards the coverage area, the first electrode plate 12 remains within the coverage area of ​​the second electrode plate 13, making it less likely for the effective overlap area to decrease significantly. Therefore, the larger capacitance value between the third and fourth capacitors can be used as the reference capacitance value, and the offset direction in the second direction Y can be determined based on the test subunit 11 corresponding to the smaller capacitance value. The stacking offset amount in the second direction Y can be determined based on the capacitance difference between the third and fourth capacitors.

[0048] Specifically, in the third sub-unit 113, the first electrode plate 12 has opposing ninth side 1131 and tenth side 1132 along the second direction Y, and the second electrode plate 13 has opposing eleventh side 1133 and twelfth side 1134 along the second direction Y. When the first wafer 2 and the second wafer 3 are in a preset alignment state, on the projection plane along the bonding direction, the orthographic projection of the ninth side 1131 is aligned with the orthographic projection of the eleventh side 1133, and the orthographic projection of the tenth side 1132 is located between the orthographic projection of the eleventh side 1133 and the orthographic projection of the twelfth side 1134. That is, one side of the first electrode plate 12 in the second direction Y is flush with one side of the second electrode plate 13, and the other side of the first electrode plate 12 in the second direction Y does not exceed the coverage area of ​​the second electrode plate 13. Thus, the third subunit 113 forms an offset-sensitive structure on one side of the second direction Y; when the first wafer 2 and the second wafer 3 are offset along the side corresponding to the ninth side 1131 and the eleventh side 1133, the effective overlap area between the first electrode plate 12 and the second electrode plate 13 decreases, and the third capacitance decreases accordingly.

[0049] In the fourth sub-unit 114, the first electrode plate 12 has a thirteenth side 1141 and a fourteenth side 1142 along the second direction Y, and the second electrode plate 13 has a fifteenth side 1143 and a sixteenth side 1144 along the second direction Y. When the first wafer 2 and the second wafer 3 are in a preset alignment state, on the projection plane along the bonding direction, the orthographic projection of the fourteenth side 1142 is aligned with the orthographic projection of the sixteenth side 1144, and the orthographic projection of the thirteenth side 1141 is located between the orthographic projections of the fifteenth side 1143 and the sixteenth side 1144. In other words, the fourth subunit 114 and the third subunit 113 have opposite boundary alignment directions in the second direction Y, so that the fourth subunit 114 forms an offset-sensitive structure on the other side of the second direction Y; when the first wafer 2 and the second wafer 3 are offset along the fourteenth side 1142 and the sixteenth side 1144 respectively, the effective overlap area between the first electrode plate 12 and the second electrode plate 13 is reduced, and the fourth capacitor is reduced accordingly.

[0050] Therefore, the third subunit 113 and the fourth subunit 114 can respectively correspond to opposite offset directions in the second direction Y. By comparing the values ​​of the third capacitor and the fourth capacitor, the offset sides of the first wafer 2 and the second wafer 3 in the second direction Y can be determined; the capacitance difference between the third capacitor and the fourth capacitor can characterize the stacking offset in the second direction Y.

[0051] In some embodiments, test structure 1 may include only a first sub-unit 111 and a second sub-unit 112 to characterize the stacking offset of the first wafer 2 and the second wafer 3 in the first direction X by the capacitance difference between the first capacitor and the second capacitor; or, test structure 1 may include only a third sub-unit 113 and a fourth sub-unit 114 to characterize the stacking offset of the first wafer 2 and the second wafer 3 in the second direction Y by the capacitance difference between the third capacitor and the fourth capacitor. In this way, stacking offset in a single direction can be selected for detection according to actual testing requirements, which helps to simplify test structure 1 and reduce the space occupied by test structure 1 in the cutting area.

[0052] In other embodiments, the test structure 1 may simultaneously include a first sub-unit 111, a second sub-unit 112, a third sub-unit 113, and a fourth sub-unit 114, so as to characterize the stacking offset in the first direction X by the capacitance difference between the first capacitor and the second capacitor, and to characterize the stacking offset in the second direction Y by the capacitance difference between the third capacitor and the fourth capacitor, thereby obtaining the stacking offset of the first wafer 2 and the second wafer 3 in different directions and improving the integrity of the bonding offset detection.

[0053] It is understood that the preset alignment state is the reference state when the first wafer 2 and the second wafer 3 are arranged relative to each other according to the designed stacking position, used to characterize the designed projection relationship of the first electrode plate 12 and the second electrode plate 13 in the test subunit 11 when no bonding offset occurs; this state does not limit the first wafer 2 and the second wafer 3 to necessarily not having an stacking offset after actual bonding. When the first wafer 2 and the second wafer 3 have an stacking offset relative to the preset alignment state after actual bonding, the effective overlap area of ​​the first electrode plate 12 and the second electrode plate 13 on the projection plane of the bonding direction changes, thereby causing a change in the capacitance value formed between them. In some embodiments of this disclosure, the first wafer 2 includes a first substrate 21 and a bonding layer 22 disposed on one side of the first substrate 21, and the second wafer 3 includes a second substrate 31, a metal conductive layer 32 disposed on one side of the second substrate 31, and an interlayer dielectric layer 33 formed in the second wafer 3. The first electrode plate 12 is disposed in the same layer as the bonding layer 22, and the second electrode plate 13 is disposed in the same layer as the metal conductive layer 32. When the first wafer 2 and the second wafer 3 are bonded together, the first electrode plate 12 and the second electrode plate 13 are arranged opposite each other along the bonding direction, and the interlayer dielectric layer 33 in the second wafer 3 is located between the first electrode plate 12 and the second electrode plate 13, so that a capacitor can be formed between the first electrode plate 12 and the second electrode plate 13.

[0054] This configuration allows one electrode plate to be formed using the bonding layer 22 of the first wafer 2, and the other electrode plate to be formed using the metal conductive layer 32 of the second wafer 3. The first electrode plate 12 and the second electrode plate 13 are isolated by the interlayer dielectric layer 33 in the second wafer 3, thus preventing direct conductivity between them and facilitating the formation of a capacitor structure for stack-off detection. This method combines the existing bonding layer 22 and metal conductive layer 32 to complete the fabrication of the test structure 1, reducing the need for additional electrode layers.

[0055] In other embodiments of this disclosure, the first wafer 2 includes a first substrate 21, a first metal interconnect layer 23 disposed on one side of the first substrate 21, and a first dielectric layer 24 formed in the first wafer 2. The second wafer 3 includes a second substrate 31, a second metal interconnect layer 34 disposed on one side of the second substrate 31, and a second dielectric layer 35 formed in the second wafer 3. The first electrode plate 12 is disposed on the same layer as the first metal interconnect layer 23, and the second electrode plate 13 is disposed on the same layer as the second metal interconnect layer 34. When the first wafer 2 and the second wafer 3 are bonded together, the first electrode plate 12 and the second electrode plate 13 are disposed opposite to each other, and the first dielectric layer 24 and / or the second dielectric layer 35 are located between the first electrode plate 12 and the second electrode plate 13, thereby forming a capacitor between the first electrode plate 12 and the second electrode plate 13.

[0056] With this configuration, both the first electrode plate 12 and the second electrode plate 13 can be formed through the metal interconnect layers in the corresponding wafers, allowing the test structure 1 to avoid occupying the conductive structure in the bonding layer 22, which helps to reduce the impact of the test structure 1 on the metal layout of the bonding interface. At the same time, the first dielectric layer 24 and / or the second dielectric layer 35 can provide an insulating gap between the first electrode plate 12 and the second electrode plate 13, allowing the test structure 1 to characterize the stacking offset between the first wafer 2 and the second wafer 3 through changes in capacitance value.

[0057] In other embodiments of this disclosure, the first wafer 2 includes a first substrate 21, a metal interconnect layer 25 disposed on one side of the first substrate 21, and an interlayer dielectric layer 26 formed in the first wafer 2. The second wafer 3 includes a second substrate 31 and a bonding layer 36 disposed on one side of the second substrate 31. The first electrode plate 12 is disposed in the same layer as the metal interconnect layer 25 of the first wafer 2, and the second electrode plate 13 is disposed in the same layer as the bonding layer 36 of the second wafer 3. When the first wafer 2 and the second wafer 3 are bonded together, the interlayer dielectric layer 26 in the first wafer 2 is located between the first electrode plate 12 and the second electrode plate 13, thereby forming a capacitor between the first electrode plate 12 and the second electrode plate 13.

[0058] With this configuration, the second electrode plate 13 can be formed using the bonding layer 36 of the second wafer 3, and the first electrode plate 12 can be formed using the metal interconnect layer 25 of the first wafer 2, so that the dielectric of the capacitor structure is mainly provided by the interlayer dielectric layer 26 in the first wafer 2. This method provides another option for the layer arrangement of the first electrode plate 12 and the second electrode plate 13, making it easier to flexibly set the test structure 1 according to the metal layer layout, bonding layer 36 layout and test sensitivity requirements of different wafers.

[0059] In the above embodiment, the test structure 1 can be fabricated simultaneously with the functional structures in the chip region. That is, the first electrode plate 12 and the second electrode plate 13 can be formed using the existing conductive layer patterning process in the corresponding wafer, without requiring additional metal deposition, photolithography, or etching processes for the test structure 1. This arrangement facilitates bonding misalignment detection without significantly increasing process complexity. Simultaneously, the test structure 1 is located in the dicing area, not occupying the effective device area of ​​the chip region, making wafer-level testing convenient after wafer bonding and before dicing.

[0060] This application also provides a bonded wafer structure. The bonded wafer structure can be understood as a wafer-level bonding structure after the first wafer 2 and the second wafer 3 have been bonded together but before dicing. The first wafer 2 and the second wafer 3 are bonded together, and both the first wafer 2 and the second wafer 3 include multiple chip regions and dicing regions located between adjacent chip regions; wherein the chip regions of the first wafer 2 can correspond to the chip regions of the second wafer 3, and the dicing regions of the first wafer 2 can correspond to the dicing regions of the second wafer 3. A test structure 1 is located in the corresponding dicing regions of the first wafer 2 and the second wafer 3, and can be used to perform wafer-level bond offset detection before dicing the bonded wafer structure.

[0061] With this setup, the bonding offset between the first wafer 2 and the second wafer 3 can be obtained through the test structure 1 before dicing, which facilitates the monitoring of bonding quality at the wafer level. At the same time, since the test structure 1 is located in the dicing area, it can be removed or at least partially removed during the subsequent dicing process, thereby reducing the impact on the functional structure of the single chip after dicing.

[0062] This application also provides a wafer bonding misalignment detection method based on test structure 1. Test structure 1 is disposed in the dicing area of ​​a first wafer 2 and a second wafer 3; test structure 1 includes at least one test sub-unit 11 disposed in the dicing area; test sub-unit 11 includes a first electrode plate 12 and a second electrode plate 13; the first electrode plate 12 is formed on the first wafer 2, the second electrode plate 13 is formed on the second wafer 3, and the first electrode plate 12 and the second electrode plate 13 are spaced apart to form a capacitor; wherein, on the projection surface along the bonding direction of the first wafer 2 and the second wafer 3, the orthographic projection of the first electrode plate 12 is at least partially located within the coverage area of ​​the orthographic projection of the second electrode plate 13, and at least one side boundary of the orthographic projection of the first electrode plate 12 is aligned with the corresponding side boundary of the orthographic projection of the second electrode plate 13; The detection methods include: S1: Obtain the capacitance value between the first electrode plate 12 and the second electrode plate 13.

[0063] S2: Based on the capacitance value and the preset correspondence, determine the bonding offset result between the first wafer 2 and the second wafer 3.

[0064] In some embodiments of this disclosure, at least one test subunit 11 may include a first subunit 111 and a second subunit 112; or, at least one test subunit 11 may include a third subunit 113 and a fourth subunit 114; or, at least one test subunit 11 may include a first subunit 111, a second subunit 112, a third subunit 113 and a fourth subunit 114.

[0065] Specifically, the first subunit 111 and the second subunit 112 are used to jointly characterize the stacking offset of the first wafer 2 and the second wafer 3 in the first direction X, and the third subunit 113 and the fourth subunit 114 are used to jointly characterize the stacking offset of the first wafer 2 and the second wafer 3 in the second direction Y. Both the first direction X and the second direction Y are perpendicular to the bonding direction of the first wafer 2 and the second wafer 3, and the first direction X intersects the second direction Y.

[0066] Obtaining the capacitance value between the first electrode plate 12 and the second electrode plate 13 may include: obtaining the first capacitance value formed by the first subunit 111 and the second capacitance value formed by the second subunit 112; and / or, obtaining the third capacitance value formed by the third subunit 113 and the fourth capacitance value formed by the fourth subunit 114.

[0067] It is understood that, in the first embodiment, at least one test subunit 11 includes a first subunit 111 and a second subunit 112. The first subunit 111 and the second subunit 112 correspond to opposite offset directions in the first direction X. By obtaining the first capacitance value formed by the first subunit 111 and the second capacitance value formed by the second subunit 112, the stacking offset of the first wafer 2 and the second wafer 3 in the first direction X can be determined based on the magnitude relationship or capacitance difference between the first capacitance value and the second capacitance value.

[0068] In the second embodiment, at least one test subunit 11 includes a third subunit 113 and a fourth subunit 114. The third subunit 113 and the fourth subunit 114 correspond to opposite offset directions in the second direction Y. By obtaining the third capacitance value formed by the third subunit 113 and the fourth capacitance value formed by the fourth subunit 114, the stacking offset of the first wafer 2 and the second wafer 3 in the second direction Y can be determined based on the magnitude relationship or capacitance difference between the third capacitance value and the fourth capacitance value.

[0069] In the third embodiment, at least one test subunit 11 includes a first subunit 111, a second subunit 112, a third subunit 113, and a fourth subunit 114. The first subunit 111 and the second subunit 112 are used to detect the stacking offset in the first direction X, and the third subunit 113 and the fourth subunit 114 are used to detect the stacking offset in the second direction Y. By acquiring the first capacitance value, the second capacitance value, the third capacitance value, and the fourth capacitance value respectively, the stacking offset of the first wafer 2 and the second wafer 3 in the first direction X and the second direction Y can be determined simultaneously.

[0070] In some embodiments of this disclosure, the bonding offset result between the first wafer 2 and the second wafer 3 is determined based on the capacitance value and a preset correspondence, including at least one of the following: determining the bonding offset of the first wafer 2 and the second wafer 3 in the first direction X based on the capacitance difference between the first capacitance value and the second capacitance value and the first preset correspondence; determining the bonding offset of the first wafer 2 and the second wafer 3 in the second direction Y based on the capacitance difference between the third capacitance value and the fourth capacitance value and the second preset correspondence.

[0071] Understandably, in one implementation, after obtaining the first capacitance value formed by the first sub-unit 111 and the second capacitance value formed by the second sub-unit 112, the capacitance difference between the first and second capacitance values ​​can be calculated, and the bonding offset between the first wafer 2 and the second wafer 3 in the first direction X can be determined based on the capacitance difference and a first preset correspondence. This method is suitable for scenarios where only the bonding offset in the first direction X needs to be monitored.

[0072] In another implementation, after obtaining the third capacitance value formed by the third subunit 113 and the fourth capacitance value formed by the fourth subunit 114, the capacitance difference between the third and fourth capacitance values ​​can be calculated. Based on this capacitance difference and a second preset correspondence, the bonding offset between the first wafer 2 and the second wafer 3 in the second direction Y can be determined. This method is suitable for scenarios where only the bonding offset in the second direction Y needs to be monitored.

[0073] In another embodiment, a first capacitance value, a second capacitance value, a third capacitance value, and a fourth capacitance value can be obtained simultaneously; the bonding offset in the first direction X is determined based on the capacitance difference between the first capacitance value and the second capacitance value, and the bonding offset in the second direction Y is determined based on the capacitance difference between the third capacitance value and the fourth capacitance value. Thus, the two-dimensional bonding offset between the first wafer 2 and the second wafer 3 in the wafer plane can be obtained.

[0074] Furthermore, the first preset correspondence is the correspondence between the capacitance difference between the first and second capacitance values ​​and the bonding offset in the first direction X; the second preset correspondence is the correspondence between the capacitance difference between the third and fourth capacitance values ​​and the bonding offset in the second direction Y. The first and second preset correspondences can be obtained through theoretical calculations, process simulations, or calibration tests, or can be represented as calibration curves, lookup tables, or calculation models.

[0075] In summary, the wafer bonding offset detection method based on test structure 1 provided in this application is described in detail below.

[0076] Taking the example of bonding misalignment occurring in both the first wafer 2 and the second wafer 3 in the first direction X and the second direction Y, the detection device can first acquire the capacitance values ​​corresponding to the first sub-unit 111, the second sub-unit 112, the third sub-unit 113, and the fourth sub-unit 114, respectively. Specifically, the first sub-unit 111 forms the first capacitance value, the second sub-unit 112 forms the second capacitance value, the third sub-unit 113 forms the third capacitance value, and the fourth sub-unit 114 forms the fourth capacitance value. Among them, the first sub-unit 111 and the second sub-unit 112 are used to detect the bonding misalignment in the first direction X, and the third sub-unit 113 and the fourth sub-unit 114 are used to detect the bonding misalignment in the second direction Y.

[0077] In the first direction X, the first sub-unit 111 and the second sub-unit 112 correspond to opposite offset directions in the first direction X. If the first capacitance value is less than the second capacitance value, it indicates that the effective overlap area between the first electrode plate 12 and the second electrode plate 13 in the first sub-unit 111 has decreased, and it can be determined that the first wafer 2 and the second wafer 3 have shifted towards the side corresponding to the first sub-unit 111; if the second capacitance value is less than the first capacitance value, it indicates that the effective overlap area between the first electrode plate 12 and the second electrode plate 13 in the second sub-unit 112 has decreased, and it can be determined that the first wafer 2 and the second wafer 3 have shifted towards the side corresponding to the second sub-unit 112. Further, the larger capacitance value of the first capacitance value and the second capacitance value can be used as the reference capacitance value in the first direction X, and the capacitance difference between the two can be used as the offset characterization quantity in the first direction X, and the bonding offset amount in the first direction X can be determined based on the first preset correspondence relationship.

[0078] In the second direction Y, the third subunit 113 and the fourth subunit 114 correspond to opposite offset directions in the second direction Y. If the third capacitance value is less than the fourth capacitance value, it indicates that the effective overlap area between the first electrode plate 12 and the second electrode plate 13 in the third subunit 113 is reduced, and it can be determined that the first wafer 2 and the second wafer 3 are offset towards the side corresponding to the third subunit 113; if the fourth capacitance value is less than the third capacitance value, it indicates that the effective overlap area between the first electrode plate 12 and the second electrode plate 13 in the fourth subunit 114 is reduced, and it can be determined that the first wafer 2 and the second wafer 3 are offset towards the side corresponding to the fourth subunit 114. Further, the larger capacitance value between the third and fourth capacitance values ​​can be used as the reference capacitance value in the second direction Y, and the capacitance difference between the two can be used as the offset characterization quantity in the second direction Y. The bonding offset amount in the second direction Y is determined based on the second preset correspondence.

[0079] For example, when the first wafer 2 and the second wafer 3 simultaneously shift towards the side corresponding to the first sub-unit 111 and the side corresponding to the third sub-unit 113, the first capacitance value and the third capacitance value will decrease respectively. At this time, the shift direction in the first direction X can be determined based on the fact that the first capacitance value is less than the second capacitance value; the shift direction in the second direction Y can be determined based on the fact that the third capacitance value is less than the fourth capacitance value. Further, the shift amount in the first direction X is determined based on the capacitance difference between the first and second capacitance values, and the shift amount in the second direction Y is determined based on the capacitance difference between the third and fourth capacitance values. Thus, the two-dimensional bonding shift result between the first wafer 2 and the second wafer 3 in the wafer plane can be obtained.

[0080] The first and second preset correspondences can be obtained through theoretical calculations, process simulations, or calibration tests. For example, in the first direction X, a correspondence can be pre-established between the capacitance difference between the first and second capacitance values ​​and the offset in the first direction X; in the second direction Y, a correspondence can be pre-established between the capacitance difference between the third and fourth capacitance values ​​and the offset in the second direction Y. During testing, the testing equipment substitutes the actually measured capacitance difference into the correspondence to obtain the bonding offset in the corresponding direction.

[0081] In the ideal parallel-plate capacitor model, the capacitance value is related to the effective overlap area between the first electrode plate 12 and the second electrode plate 13. When the first wafer 2 and the second wafer 3 are offset, the effective overlap area decreases, and the capacitance value decreases accordingly. Therefore, a larger capacitance difference usually indicates a greater change in the effective overlap area in the corresponding direction, and a larger corresponding bonding offset. In practical applications, calibration curves or lookup tables can be preferentially used as preset correspondences to reduce the influence of factors such as dielectric thickness, dielectric constant, edge electric field, and parasitic capacitance on the offset calculation.

[0082] This application also provides a testing device. The testing device is used to test a test structure 1 disposed on a first wafer 2 and a second wafer 3. The test structure 1 may include at least two test sub-units 11, each of which can form a corresponding capacitance. The testing device includes a sampling module, a comparison module, and an offset determination module. The sampling module is used to acquire the capacitance values ​​formed by the test sub-units 11 in the test structure 1, for example, acquiring the first capacitance value, second capacitance value, third capacitance value, and fourth capacitance value formed by different test sub-units 11 respectively. The comparison module is connected to the sampling module and is used to acquire the capacitance difference between the capacitance values ​​formed by at least two test sub-units 11. The offset determination module is connected to the comparison module and is used to determine the bonding offset result between the first wafer 2 and the second wafer 3 based on the capacitance difference and a preset correspondence.

[0083] Specifically, during the testing process, the sampling module first connects electrically to the test terminal of the test structure 1 and acquires the capacitance value formed by each test sub-unit 11 in the test structure 1. For example, the sampling module can acquire the first capacitance value formed by the first sub-unit 111, the second capacitance value formed by the second sub-unit 112, the third capacitance value formed by the third sub-unit 113, and the fourth capacitance value formed by the fourth sub-unit 114.

[0084] Then, the comparison module receives multiple capacitance values ​​acquired by the sampling module and compares the capacitance values ​​in corresponding directions. Specifically, the comparison module can acquire the capacitance difference between the first capacitance value and the second capacitance value to form an offset representation in the first direction X; it can also acquire the capacitance difference between the third capacitance value and the fourth capacitance value to form an offset representation in the second direction Y.

[0085] Subsequently, the offset determination module determines the bonding offset result between the first wafer 2 and the second wafer 3 based on the capacitance difference and a preset correspondence. For example, the offset determination module can determine the offset direction in the first direction X based on the magnitude relationship between the first capacitance value and the second capacitance value, and determine the offset amount in the first direction X based on the capacitance difference between the first capacitance value and the second capacitance value; the offset determination module can also determine the offset direction in the second direction Y based on the magnitude relationship between the third capacitance value and the fourth capacitance value, and determine the offset amount in the second direction Y based on the capacitance difference between the third capacitance value and the fourth capacitance value.

[0086] Therefore, the detection equipment can convert the capacitance change of the test structure 1 into the bonding offset result between the first wafer 2 and the second wafer 3, thereby obtaining the offset direction and offset amount in the first direction X and / or the second direction Y.

[0087] With this setup, the testing equipment can obtain the capacitance value of the test structure 1 through electrical testing, and use the capacitance difference to characterize the bonding offset in different directions, thereby obtaining the bonding offset result between the first wafer 2 and the second wafer 3, which facilitates the detection of bonding quality after wafer bonding.

[0088] Other embodiments of this specification will readily occur to those skilled in the art upon consideration of the specification and practice of the invention claimed herein. This specification is intended to cover any variations, uses, or adaptations that follow the general principles of this specification and include common knowledge or customary techniques in the art not claimed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this specification are indicated by the following claims.

[0089] It should be understood that this specification is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this specification is limited only by the appended claims.

[0090] The above description is merely a preferred embodiment of this specification and is not intended to limit this specification. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this specification should be included within the scope of protection of this specification.

Claims

1. A test structure for bonding process testing of a first wafer and a second wafer, wherein both the first wafer and the second wafer include a chip region and a dicing region located between adjacent chip regions; characterized in that: The test structure includes multiple test sub-units located in the cutting area, and the multiple test sub-units include at least a first sub-unit and a second sub-unit; Each test subunit includes a first electrode plate and a second electrode plate. The first electrode plate is formed on the first wafer, and the second electrode plate is formed on the second wafer. The first electrode plate and the second electrode plate are spaced apart to form a capacitor. When the first wafer and the second wafer are in a preset alignment state, on the projection surface along the bonding direction of the first wafer and the second wafer, the orthographic projection of the first electrode plate is entirely within the coverage area of ​​the orthographic projection of the second electrode plate, and one side boundary of the orthographic projection of the first electrode plate is aligned with the corresponding side boundary of the orthographic projection of the second electrode plate; the side boundaries of the orthographic projections in the first sub-unit that are aligned with each other and the boundary of the orthographic projections in the second sub-unit that overlap are set opposite to each other in the first direction. The first sub-unit forms a first capacitor, and the second sub-unit forms a second capacitor; the capacitance difference between the first capacitor and the second capacitor is used to characterize the stacking offset of the first wafer and the second wafer in a first direction.

2. The test structure according to claim 1, characterized in that: The plurality of test subunits also include a third subunit and a fourth subunit; The third sub-unit and the fourth sub-unit are used to jointly characterize the stacking offset of the first wafer and the second wafer in the second direction; Both the first direction and the second direction are perpendicular to the bonding direction, and the first direction intersects the second direction.

3. The test structure according to claim 2, characterized in that: The third sub-unit is used to form a third capacitor, and the fourth sub-unit is used to form a fourth capacitor. The capacitance difference between the third capacitor and the fourth capacitor is used to characterize the stacking offset of the first wafer and the second wafer in the second direction.

4. The test structure according to claim 1, characterized in that: In the first subunit, the first electrode plate has a first side and a second side disposed along a first direction; the second electrode plate has a third side and a fourth side disposed along the first direction. When the first wafer and the second wafer are in a preset alignment state, the orthographic projection of the first side is aligned with the orthographic projection of the third side, and the orthographic projection of the second side is located between the orthographic projection of the third side and the orthographic projection of the fourth side.

5. The test structure according to claim 1, characterized in that: In the second subunit, the first electrode plate has a fifth side and a sixth side that are disposed opposite to each other along the first direction; the second electrode plate has a seventh side and an eighth side that are disposed opposite to each other along the first direction; When the first wafer and the second wafer are in a preset alignment state, on the projection surface along the bonding direction, the orthographic projection of the sixth side is aligned with the orthographic projection of the eighth side, and the orthographic projection of the fifth side is located between the orthographic projection of the seventh side and the orthographic projection of the eighth side.

6. The test structure according to claim 3, characterized in that: In the third subunit, the first electrode plate has a ninth side and a tenth side that are disposed opposite to each other along the second direction; the second electrode plate has an eleventh side and a twelfth side that are disposed opposite to each other along the second direction. When the first wafer and the second wafer are in a preset alignment state, on the projection surface along the bonding direction, the orthographic projection of the ninth side is aligned with the orthographic projection of the eleventh side, and the orthographic projection of the tenth side is located between the orthographic projection of the eleventh side and the orthographic projection of the twelfth side.

7. The test structure according to claim 3, characterized in that: In the fourth subunit, the first electrode plate has a thirteenth side and a fourteenth side that are disposed opposite to each other along the second direction; the second electrode plate has a fifteenth side and a sixteenth side that are disposed opposite to each other along the second direction. Specifically, when the first wafer and the second wafer are in a preset alignment state, on the projection surface along the bonding direction, the orthographic projection of the fourteenth side is aligned with the orthographic projection of the sixteenth side, and the orthographic projection of the thirteenth side is located between the orthographic projection of the fifteenth side and the orthographic projection of the sixteenth side.

8. The test structure according to claim 1, characterized in that: The first wafer includes a first substrate and a bonding layer disposed on one side of the first substrate; The second wafer includes a second substrate, a metal conductive layer disposed on one side of the second substrate, and an interlayer dielectric layer formed in the second wafer; The first electrode plate is disposed in the same layer as the bonding layer, and the second electrode plate is disposed in the same layer as the metal conductive layer. When the first wafer and the second wafer are bonded together, the interlayer dielectric layer is located between the first electrode plate and the second electrode plate.

9. The test structure according to claim 1, characterized in that: The first wafer includes a first substrate, a first metal interconnect layer disposed on one side of the first substrate, and a first dielectric layer formed in the first wafer; The second wafer includes a second substrate, a second metal interconnect layer disposed on one side of the second substrate, and a second dielectric layer formed in the second wafer; Wherein, the first electrode plate is disposed in the same layer as the first metal interconnect layer, and the second electrode plate is disposed in the same layer as the second metal interconnect layer; when the first wafer and the second wafer are bonded together, the first dielectric layer and / or the second dielectric layer are located between the first electrode plate and the second electrode plate.

10. The test structure according to claim 1, characterized in that: The first wafer includes a first substrate, a metal interconnect layer disposed on one side of the first substrate, and an interlayer dielectric layer formed in the first wafer; The second wafer includes a second substrate and a bonding layer disposed on one side of the second substrate; The first electrode plate is disposed in the same layer as the metal interconnect layer, and the second electrode plate is disposed in the same layer as the bonding layer; when the first wafer and the second wafer are bonded together, the interlayer dielectric layer is located between the first electrode plate and the second electrode plate.

11. A bonding wafer structure, characterized in that, Includes a first wafer, a second wafer, and a test structure as described in any one of claims 1 to 10; The first wafer is bonded to the second wafer, and both the first wafer and the second wafer include a chip region and a dicing region located between adjacent chip regions; The test structure is located in the dicing area of ​​the first wafer and the second wafer.

12. A wafer bonding offset detection method based on a test structure, characterized in that, The test structure is located in the dicing area of ​​the first wafer and the second wafer; the test structure includes multiple test sub-units located in the dicing area, and the multiple test sub-units include at least a first sub-unit and a second sub-unit; each test sub-unit includes a first electrode plate and a second electrode plate; The first electrode plate is formed on the first wafer, and the second electrode plate is formed on the second wafer. The first electrode plate and the second electrode plate are spaced apart to form a capacitor. Wherein, when the first wafer and the second wafer are in a preset alignment state, on the projection surface along the bonding direction of the first wafer and the second wafer, the orthographic projection of the first electrode plate is entirely within the coverage area of ​​the orthographic projection of the second electrode plate, and at least one side boundary of the orthographic projection of the first electrode plate is aligned with the corresponding side boundary of the orthographic projection of the second electrode plate; the side boundaries of the orthographic projections in the first sub-unit that are aligned with each other and the boundary of the orthographic projections in the second sub-unit that overlap are arranged opposite to each other in the first direction; The detection method includes: Obtain the capacitance value between the first electrode plate and the second electrode plate of each test subunit; Based on the capacitance difference between the first capacitance value formed by the first sub-unit and the second capacitance value formed by the second sub-unit, and the first preset correspondence, the offset direction and bonding offset of the first wafer and the second wafer in the first direction are determined.

13. The wafer bonding offset detection method according to claim 12, characterized in that, The plurality of test subunits also include a third subunit and a fourth subunit; The third sub-unit and the fourth sub-unit are used to jointly characterize the stacking offset of the first wafer and the second wafer in the second direction; Both the first direction and the second direction are perpendicular to the bonding directions of the first wafer and the second wafer, and the first direction intersects the second direction; The step of obtaining the capacitance value between the first electrode plate and the second electrode plate of each test subunit further includes: Obtain the third capacitance value formed by the third subunit and the fourth capacitance value formed by the fourth subunit.

14. The wafer bonding offset detection method according to claim 13, characterized in that, The detection method further includes: Based on the capacitance difference between the third capacitance value and the fourth capacitance value and the second preset correspondence, the bonding offset between the first wafer and the second wafer in the second direction is determined.

15. A testing device for testing the bonded wafer structure as described in claim 11, characterized in that, include: The sampling module is configured to acquire the capacitance value formed by the test sub-unit in the test structure; A comparison module, connected to the sampling module, is configured to acquire the capacitance difference between at least two capacitance values ​​formed by the test subunits; An offset determination module is connected to the comparison module. The offset determination module is configured to determine the bonding offset result between the first wafer and the second wafer based on the capacitance difference and a preset correspondence.

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