Computing power center power supply adjustment method and device, equipment, medium and program product

Abstract

The application relates to the technical field of power supply planning, and provides a computing power center power supply adjustment method, device, equipment, medium and program product. Real-time junction temperature estimation values and loss distribution coefficients are estimated according to power supply data and internal temperature, optimal switching frequencies and optimal current distribution ratios are generated by performing energy efficiency optimization on the power supply data according to the real-time junction temperature estimation values, the loss distribution coefficients and a power reference instruction, target conduction duty cycles and target switching time sequences are generated by performing state correlation optimization on power switches according to the real-time junction temperature estimation values, the optimal switching frequencies and the optimal current distribution ratios, instruction correction values are obtained by performing load power disturbance estimation on the power reference instruction according to the target conduction duty cycles, the target switching time sequences and current voltage data, and power supply driving signals are generated according to the target conduction duty cycles, the target switching time sequences and the instruction correction values. The application realizes stable power supply of the computing power center through the cooperative control of thermoelectric coupling temperature estimation, energy efficiency optimization and voltage disturbance compensation.

Description

Technical Field

[0001] This application relates to the field of power supply planning technology, and in particular to a power supply regulation method, device, equipment, medium and program product for a computing center. Background Technology

[0002] Computing centers are typical application scenarios characterized by high power density and strong dynamic loads. Server clusters, GPUs / AI accelerator cards, storage, and network devices can experience significant power fluctuations within a short period. The power supply system must continuously output a stable DC voltage while minimizing energy conversion losses and controlling the temperature rise of power devices to prevent overheating-induced derating, protection shutdowns, or even lifespan reduction. Therefore, power supply regulation in computing centers must not only address the issue of "having enough power," but also the issues of "stable, economical, and long-lasting power supply." This is especially true in scenarios involving large model training, inference cluster expansion, and sudden load surges, where the real-time performance and reliability requirements for power supply regulation are even higher.

[0003] Current power supply methods for computing centers typically operate at a fixed frequency, using traditional voltage outer loop and current inner loop control. They maintain bus voltage through conventional PWM modulation and employ simple temperature protection or current limiting strategies to prevent device overheating. When multiple modules are connected in parallel, current is often shared equally or proportionally, with less emphasis on real-time losses, device junction temperatures, and bus power disturbances for coordinated adjustment. While these methods are simple to implement and easy to implement in engineering, meeting the voltage regulation and basic protection requirements under normal operating conditions, their control parameters are usually statically set, lacking adaptive optimization capabilities for different load stages, temperature rise states, and efficiency ranges. Summary of the Invention

[0004] This application provides a power supply regulation method, device, equipment, medium, and program product for computing centers to solve the problem of low power supply stability when the load fluctuates drastically.

[0005] In a first aspect, embodiments of this application provide a method for adjusting the power supply of a computing center, including: The power supply data and internal temperature of the power supply equipment in the computing center are obtained, and thermoelectric coupling analysis is performed on the power supply data and internal temperature to evaluate the real-time junction temperature estimate of each power switch and the corresponding loss distribution coefficient. Based on the real-time junction temperature estimate, the loss allocation coefficient, and the preset power reference command, the power supply data is subjected to energy efficiency optimization processing to generate the optimal switching frequency and the optimal current allocation ratio. Based on the real-time junction temperature estimate, the optimal switching frequency, and the optimal current allocation ratio, the power switches are state-predicted and correlated to generate target duty cycle and target switching timing for each power switch. Based on the target duty cycle, the target switching timing, and the detected current voltage data of the power supply bus, load power disturbance estimation is performed on the power reference command to obtain the command correction value; The signal is modulated according to the target duty cycle, the target switching timing, and the instruction correction value to generate a power supply drive signal.

[0006] In one optional implementation, the power supply data includes the three-phase voltage and three-phase current of each power switch. The step of acquiring the power supply data and internal temperature of the power supply equipment in the computing center, and performing thermoelectric coupling analysis on the power supply data and internal temperature to evaluate the real-time junction temperature estimate of each power switch and the corresponding loss distribution coefficient includes: The three-phase voltage and three-phase current of each power switch in the power supply equipment of the computing center are collected synchronously, and the fundamental positive sequence component of each phase is extracted. The instantaneous active power is calculated based on the fundamental positive sequence component to obtain the average active power. Based on preset loss parameters, the three-phase voltage and the three-phase current are averaged and separated by switching cycle to obtain the conduction loss and switching loss of each power switch. The internal temperature of the power supply equipment is obtained. Based on the average active power, the conduction loss, the switching loss, and the internal temperature, the thermal state of the power switches is recursively estimated to obtain the real-time junction temperature estimate of each power switch and the corresponding loss distribution coefficient.

[0007] In an optional implementation, the step of recursively estimating the thermal state of the power switches based on the average active power, the conduction loss, the switching loss, and the internal temperature to obtain the real-time junction temperature estimate and the corresponding loss allocation coefficient for each power switch includes: The total loss of each power switch is calculated based on the conduction loss and the switching loss, and an electrothermal equivalent analysis of the power switches is performed based on the total loss to obtain the state node of each power switch. Based on the preset set of thermal resistance coefficients, the total loss and the average active power, the heat transfer process between state nodes is recursively calculated to obtain the predicted temperature value corresponding to each state node. The predicted temperature value is corrected for error based on the internal temperature to obtain the real-time junction temperature estimate of each power switch; Based on the conduction loss and the proportional relationship between the switching loss and the total loss, the loss allocation coefficient corresponding to each power switch is determined.

[0008] In an optional implementation, the step of performing energy efficiency optimization processing on the power supply data based on the real-time junction temperature estimate, the loss allocation coefficient, and a preset power reference command to generate the optimal switching frequency and the optimal current allocation ratio includes: Based on the real-time junction temperature estimate, the power supply data, and the loss distribution coefficient, the total loss of the power supply equipment is analyzed to obtain total loss trend data. Based on the preset feasible range of switching frequency, the total loss trend data is optimized to minimize the total loss, thereby generating the optimal switching frequency of the power supply equipment. Based on the preset power reference command and the optimal switching frequency, the current is balanced and distributed among the power modules operating in parallel in the power supply equipment to generate the optimal current distribution ratio for each power module.

[0009] In an optional implementation, the step of performing state prediction and correlation optimization on the power switches based on the real-time junction temperature estimate, the optimal switching frequency, and the optimal current allocation ratio to generate the target duty cycle and target switching timing for each power switch includes: The sampling period is determined based on the optimal switching frequency, and the current state of the power switch is predicted based on the sampling period to obtain the predicted current value. The current deviation data is calculated based on the reference current value determined by the optimal current distribution ratio and the predicted current value, and the temperature over-limit deviation value is calculated based on the preset temperature threshold and the real-time junction temperature estimate. Based on the current deviation data and the temperature over-limit deviation value, the power switch is evaluated for state association, and a switch state combination and corresponding deviation cost are generated. The switch state combination corresponding to the minimum deviation cost is selected as the target state combination, and the target duty cycle and target switching timing corresponding to each power switch are generated based on the target state combination and the optimal switching frequency.

[0010] In an optional implementation, the step of estimating the load power disturbance of the power reference command based on the target duty cycle, the target switching timing, and the detected current voltage data of the power supply bus, to obtain the command correction value, includes: The power balance state of the power supply bus is constructed based on the target duty cycle and the target switching sequence, and the voltage deviation between the reference voltage value in the power reference command and the detected current voltage data of the power supply bus is calculated. Based on the current voltage data and the power balance state, load power disturbance is estimated to obtain the estimated load power value; The command correction value is obtained by calculating the voltage deviation value and the load power estimate based on the super-helical sliding mode control law.

[0011] Secondly, embodiments of this application provide a power supply adjustment device for a computing center, comprising: The loss assessment module is used to obtain the power supply data and internal temperature of the power supply equipment in the computing center, and to perform thermoelectric coupling analysis on the power supply data and internal temperature to evaluate the real-time junction temperature estimate of each power switch and the corresponding loss allocation coefficient. The energy efficiency optimization module is used to perform energy efficiency optimization processing on the power supply data based on the real-time junction temperature estimate, the loss allocation coefficient, and the preset power reference command, to generate the optimal switching frequency and the optimal current allocation ratio. The switching control module is used to perform state prediction and correlation optimization of the power switches based on the real-time junction temperature estimate, the optimal switching frequency, and the optimal current allocation ratio, and to generate the target duty cycle and target switching timing corresponding to each power switch. The disturbance compensation module is used to estimate the load power disturbance of the power reference command based on the target duty cycle, the target switching timing and the detected current voltage data of the power supply bus, and obtain the command correction value. The signal modulation module is used to modulate the signal according to the target duty cycle, the target switching timing and the instruction correction value to generate a power supply drive signal.

[0012] Thirdly, embodiments of this application provide a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the steps of the above-described computing center power supply regulation method.

[0013] Fourthly, embodiments of this application provide a readable storage medium storing a computer program that, when executed by a processor, implements the steps of the above-described power supply adjustment method for a computing center.

[0014] Fifthly, embodiments of this application provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps of the above-described computing center power supply regulation method.

[0015] In one solution provided by the aforementioned computing center power supply regulation method, device, equipment, medium, and program products, the actual heating state of the power switch is identified through the coupling relationship between power supply voltage, current, and temperature. Based on this, the operating frequency of the switch and the current shunting ratio of the module are adjusted to ensure that the power supply device operates at a point with lower losses and higher efficiency. Subsequently, more suitable switching actions are selected by combining current tracking results and temperature over-limit conditions to avoid additional losses and device stress caused by frequent switching or local overheating. Finally, disturbance estimation and compensation correction are performed for fluctuations in bus voltage caused by load changes to promptly offset the impact of voltage drops. This approach can balance high-efficiency operation and stable power output under dynamic operating conditions, thereby improving the overall energy efficiency and long-term reliability of the computing center power supply system. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the operating environment of the power supply adjustment method for the computing center in an embodiment of the present invention; Figure 2 This is a flowchart illustrating the power supply adjustment method for the computing center in an embodiment of the present invention; Figure 3 yes Figure 1 Functional module diagram of the power supply regulation device of the central computing center; Figure 4 This is a schematic diagram of the structure of the computer device in an embodiment of the present invention. Detailed Implementation

[0018] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0019] It should be understood that, when used in this specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or collections thereof. It should also be understood that, as used in this specification and the appended claims, the term "and / or" refers to any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0020] Furthermore, in the description of this invention and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0021] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of the invention include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0022] It should be understood that the sequence number of each step in the following embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0023] To illustrate the technical solution of the present invention, specific embodiments are described below.

[0024] Computing centers are typical application scenarios characterized by high power density and strong dynamic loads. Server clusters, GPUs / AI accelerator cards, storage, and network devices can experience significant power fluctuations within a short period. The power supply system must continuously output a stable DC voltage while minimizing energy conversion losses and controlling the temperature rise of power devices to prevent overheating-induced derating, protection shutdowns, or even lifespan reduction. Therefore, power supply regulation in computing centers must not only address the issue of "having enough power," but also the issues of "stable, economical, and long-lasting power supply." This is especially true in scenarios involving large model training, inference cluster expansion, and sudden load surges, where the real-time performance and reliability requirements for power supply regulation are even higher.

[0025] Current power supply methods for computing centers typically operate at a fixed frequency, using traditional voltage outer loop and current inner loop control. They maintain bus voltage through conventional PWM modulation and employ simple temperature protection or current limiting strategies to prevent device overheating. When multiple modules are connected in parallel, current is often shared equally or proportionally, with less emphasis on real-time losses, device junction temperatures, and bus power disturbances for coordinated adjustment. While these methods are simple to implement and easy to implement in engineering, meeting the voltage regulation and basic protection requirements under normal operating conditions, their control parameters are usually statically set, lacking adaptive optimization capabilities for different load stages, temperature rise states, and efficiency ranges.

[0026] Existing methods typically focus only on output voltage stability, without integrating and addressing device losses, junction temperature evolution, switching frequency selection, and current distribution optimization. Consequently, they are prone to efficiency degradation, excessive device temperature rise, or short-term bus voltage drops under drastic load fluctuations. Especially in high power density scenarios, fixed frequency and fixed shunt strategies often only address some objectives, making it difficult to simultaneously achieve high efficiency, low temperature rise, and high dynamic response. This results in power supply systems that are either too conservative, wasting energy, or too aggressive, increasing device thermal stress and instability risks, leading to power supply instability.

[0027] To address the aforementioned issues, this application proposes a power supply regulation method, apparatus, device, medium, and program product for computing centers. It identifies the actual heating state of the power switch by analyzing the coupling relationship between power supply voltage, current, and temperature. Based on this, it adjusts the switch operating frequency and module shunt ratio to ensure the power supply device operates at a point with lower losses and higher efficiency. Subsequently, it combines current tracking results with temperature exceedance scenarios to select more suitable switching actions, avoiding additional losses and device stress caused by frequent switching or localized overheating. Finally, it estimates and compensates for fluctuations in bus voltage caused by load changes, promptly offsetting the impact of voltage drops. This approach balances high-efficiency operation and stable power output under dynamic conditions, thereby improving the overall energy efficiency and long-term reliability of the computing center power supply system.

[0028] The power supply adjustment method for computing centers provided in this embodiment of the invention can be applied to, for example... Figure 1In the operating environment shown, the power supply regulation method for the computing center runs on a server that integrates a power supply regulation device for the computing center. This server is connected to the power supply equipment of the computing center via a high-speed data bus. The power supply equipment includes at least a three-phase Vienna rectifier, multiple parallel power modules (each power module integrates a SiC MOSFET power switch, gate drive circuit, DC bus capacitor bank, input filter inductor, and heat sink), and each power module is equipped with a Hall voltage sensor for acquiring three-phase voltage, a closed-loop Hall current sensor for acquiring three-phase current, a thermistor for monitoring the temperature of the heat sink near the power switch, and a resistor divider sampling circuit for monitoring the DC bus voltage. The server integrates a field-programmable gate array (FPGA). The system comprises a Programmable Gate Array (FPGA) and a multi-core ARM processor. The FPGA is responsible for synchronously triggering all sensors to perform analog-to-digital conversion and read sampled data at a fixed sampling period (e.g., 20kHz). The ARM processor executes the various steps of the power supply regulation method for the computing center. The server's analog signal input port is connected to the output terminals of each voltage sensor, current sensor, and temperature sensor via shielded cables. The server's PWM output port is connected to the gate of each power switch via an optocoupler isolation drive circuit. The server's communication interface (such as PMBus or CAN bus) is connected to the management unit of the power supply equipment to receive preset power reference commands and report the operating status. During operation, the server executes the power supply regulation method for the computing center provided in this application.

[0029] In one embodiment, such as Figure 2 As shown, a power supply adjustment method for a computing center is provided, which is applied to... Figure 1 Taking the runtime environment of [the system] as an example, the following steps are included: S1: Obtain the power supply data and internal temperature of the power supply equipment in the computing center, and perform thermoelectric coupling analysis on the power supply data and internal temperature to evaluate the real-time junction temperature estimate of each power switch and the corresponding loss distribution coefficient.

[0030] In the server used to implement the power supply regulation method for the computing center, it is first necessary to acquire the power supply data and internal temperature of the computing center's power supply equipment. The power supply data includes at least the real-time phase voltage and phase current of each power switch's three-phase bridge arm. This data is synchronously acquired by Hall voltage sensors and closed-loop Hall current sensors installed on the input side of the Vienna rectifier at a fixed sampling period (e.g., 20kHz) and sent to the server's FPGA for preprocessing. The internal temperature specifically refers to the temperature value measured by a negative temperature coefficient thermistor installed on the heat sink substrate near the power switches; this value reflects the current thermal state of the heat sink. The server first performs fundamental positive sequence component extraction on the synchronously acquired three-phase voltage and three-phase current. Because the grid voltage may contain harmonics, negative sequence components, or DC offset, directly using the raw sampled values ​​to calculate power would introduce periodic fluctuation errors, leading to unstable subsequent junction temperature estimation. This application employs a second-order generalized integrator to extract the fundamental positive-sequence component. It generates the fundamental component and its orthogonal signal for each phase voltage and current, then separates the positive-sequence component using Clarke transform and the symmetrical component method. The final obtained fundamental positive-sequence component includes the fundamental positive-sequence voltage and current of each phase. Based on the extracted fundamental positive-sequence voltage and current, the instantaneous active power is calculated. Specifically, the fundamental positive-sequence voltage and current in the αβ coordinate system are multiplied and summed to obtain the instantaneous power. To obtain a slow time-varying signal suitable for thermal dynamic analysis, the instantaneous power is filtered by a moving average over one power frequency cycle (20 milliseconds) to obtain the average active power. The average active power represents the actual active energy absorbed by the power supply equipment from the grid.

[0031] While obtaining the average active power, the original three-phase voltage and three-phase current are averaged and separated by switching cycle. This embodiment of the application performs switching cycle averaging based on the physical mechanism of power switch losses: conduction loss is positively correlated with the square of the effective current value and the on-resistance of the device, while switching loss is related to the switching frequency, bus voltage, instantaneous current, and junction temperature. By extracting the waveform characteristics of voltage and current in each switching cycle, such as using the effective and average current values, and the current values ​​at the voltage rising and falling edges, combined with preset loss parameters (including the threshold voltage of IGBT or SiC MOSFET, the temperature coefficient of on-resistance, and the fitting coefficients of turn-on and turn-off energy changes with current and junction temperature), the conduction loss and switching loss are calculated respectively. The conduction loss corresponds to the Joule heating generated when current passes through the device channel or diode; the switching loss corresponds to the energy dissipation generated during parasitic capacitance charging and discharging and Miller plateaus in each switching action. Adding the conduction loss and switching loss yields the total loss of a single power switch in one switching cycle. The total loss is the heat source item in the electrothermal equivalent analysis.

[0032] Next, an electrothermal equivalent analysis is performed on the power switches, i.e., a multi-node thermal network model is established from the chip junction to the environment. Each power switch is abstracted as a series of series and parallel thermal state nodes, typically including junction nodes, package nodes, heat sink nodes, and environment nodes. The junction node represents the heat-generating core inside the chip, the package node represents the temperature of the device's package casing, and the heat sink node represents the temperature at which the heat sink is mounted. The heat transfer behavior between these nodes is described by thermal resistance and thermal capacity, forming a lumped-parameter RC network. Based on the total losses and average active power (the average active power provides the overall thermal background; for example, very little of the input electrical power is not converted into heat, and the vast majority is ultimately converted into heat), combined with a preset set of thermal resistance coefficients (derived from the junction-to-case thermal resistance, case-to-heat sink thermal resistance, and heat sink-to-environment thermal resistance in the device datasheet, as well as the coupling thermal resistance calibrated experimentally), the heat transfer process between each state node is recursively calculated. In this embodiment, the recursive calculation is based on discretized ordinary differential equations: for each node, the heat stored at the current moment is equal to the heat source minus the heat flowing to adjacent nodes through thermal resistance, while the temperature change rate is caused by heat capacity. Through numerical integration (e.g., the first-order Euler method), starting from the known initial temperature, the predicted temperature value of each node at each moment is calculated sequentially. These predicted temperature values ​​include theoretical estimates of junction temperature, estimated case temperature, and estimated radiator temperature. However, since the nominal values ​​of thermal resistance and heat capacity deviate from their actual values ​​after aging, and heat dissipation conditions (such as fan speed and thermal grease condition) also change over time, the predicted temperature values ​​obtained solely through model recursion will accumulate errors.

[0033] Therefore, the previously obtained internal temperature of the power supply equipment (i.e., the measured temperature of the thermistor on the heat sink substrate) is used as an observation value to correct the error of the predicted temperature value. In this embodiment, an extended Kalman filter or a similar state observer is used for correction: the difference between the model-predicted heat sink temperature and the measured heat sink temperature is used as information, and the temperature estimates of the junction and shell nodes are corrected inversely through the Kalman gain. The resulting derivation is the real-time junction temperature estimate for each power switch. The real-time junction temperature estimate reflects the current true thermal state inside the chip, and its accuracy directly affects subsequent energy efficiency optimization and over-temperature protection. Finally, based on the previously separated proportional relationship between conduction loss, switching loss, and total loss, the loss allocation coefficient is defined as the proportion of the conduction loss and switching loss of the switch to the total loss.

[0034] S2: Based on the real-time junction temperature estimate, the loss allocation coefficient, and the preset power reference command, perform energy efficiency optimization processing on the power supply data to generate the optimal switching frequency and the optimal current allocation ratio.

[0035] After obtaining the real-time junction temperature estimates and corresponding loss allocation coefficients for each power switch, this embodiment of the application enters the energy efficiency optimization processing stage. This stage is based on the real-time junction temperature estimates and loss allocation coefficients obtained from the above operations, a preset power reference command obtained from the power supply equipment management unit, and pre-processed power supply data (including three-phase voltage, three-phase current, DC bus voltage, and average active power). First, the total loss of the power supply equipment is analyzed based on these inputs. The total loss analysis operation expresses all energy dissipation components within the power supply equipment using explicit functions. These dissipation components include the conduction loss of the power switches, the switching loss of the power switches, the core loss of magnetic components (input inductors and transformers), and the winding copper loss. The conduction loss is positively correlated with the square of the effective current value and the on-resistance of the device, and the on-resistance itself increases linearly with the real-time junction temperature estimate. The loss allocation coefficient is used here to distinguish the contribution share of different switching transistors or different bridge arms to the total conduction loss. Switching losses are closely related to the switching frequency, DC bus voltage, instantaneous peak current, and real-time junction temperature estimate. The loss allocation coefficient is also used to weight the switching loss contribution of each device. Core losses are described using the Steinmetz equation, and their value is proportional to the α power of the switching frequency and the β power of the peak flux density. The peak flux density depends on the current voltage-second product and is directly coupled to the DC bus voltage and switching frequency. Copper losses are only related to the square of the effective current value and are independent of the switching frequency. By superimposing the above loss expressions according to physical relationships, and using the switching frequency and normalized current as independent variables, and the real-time junction temperature estimate and DC bus voltage as parameters, a total loss analytical model is constructed. This model performs local sampling calculations near the current operating point to obtain a series of discrete loss values. The sequence of these discrete values ​​changing with the switching frequency is called the total loss trend data. For example, with a DC bus voltage of 800 volts, an output power of 50 kW, and a real-time junction temperature of 85 degrees Celsius, the total loss is calculated at switching frequencies of 18 kHz, 25 kHz, 32 kHz, 40 kHz, 50 kHz, 65 kHz, 80 kHz, and 100 kHz, respectively. A U-shaped curve is obtained, which first decreases and then increases with frequency; this curve represents the total loss trend data. Through the above operations, internal physical processes that cannot be directly measured (such as chip switching energy dissipation and core eddy current losses) are transformed into quantifiable mathematical relationships.

[0036] After obtaining the total loss trend data, the data is optimized to minimize the total loss within a preset feasible switching frequency range. This feasible switching frequency range is determined by both physical constraints and engineering experience: the lower limit frequency is limited by audio noise (below 18kHz will produce an audible whistling sound) and inductor current ripple (too low a frequency leads to excessive ripple current, potentially causing core saturation); the upper limit frequency is limited by switching transistor losses (too high a frequency will cause switching losses to dominate, leading to a sharp increase in total loss) and the maximum operating frequency of the gate drive circuit (e.g., 100kHz). Within this range, the total loss trend data exhibits a single-peak characteristic—that is, there exists a unique frequency point that minimizes the total loss. To quickly and accurately find this minimum point, this embodiment employs a golden section search algorithm: first, two interior points are selected within the range according to the golden ratio, and the total loss values ​​corresponding to these two points are calculated (in real-time using a total loss analytical model). Then, the magnitudes of the two loss values ​​are compared, discarding the range with the larger loss and retaining the sub-range containing the minimum value. This process is repeated within the narrowed new range until the range width is less than a preset threshold (e.g., 100Hz). For example, the initial range is 18kHz to 100kHz, with the golden ratio points approximately 46.2kHz and 71.8kHz. If the total loss at 46.2kHz is less than that at 71.8kHz, the new range shrinks to 18kHz to 71.8kHz, and the iteration continues. After approximately 20 function evaluations, the range converges to near its minimum, and the midpoint of the range is taken as the optimal switching frequency. This optimal switching frequency achieves the best balance between conduction and switching losses under the current load, voltage, and junction temperature conditions, thus approaching a peak efficiency of 99%. This operation changes the traditional fixed switching frequency control mode, enabling dynamic frequency adjustment based on operating conditions, avoiding excessive switching losses under light loads or uncontrolled conduction losses under heavy loads.

[0037] After generating the optimal switching frequency, the current is further balanced across the power modules operating in parallel within the power supply equipment based on the preset power reference command and the optimal switching frequency. In 100-kilowatt-level power supply equipment, to improve power capacity and redundancy reliability, multiple identical power modules (each containing a complete rectifier bridge, inductor, and control circuit) are typically connected in parallel on the DC side. Due to differences in device manufacturing tolerances, aging levels, and heat dissipation conditions, the efficiency characteristics of each module are not the same: some modules are more efficient in light load areas, while others are more efficient in heavy load areas. Simply distributing the total current equally according to the number of modules will cause some modules to operate in inefficient areas, resulting in a decrease in overall efficiency. The goal of current balancing is to balance the total output current... Equals power reference command divided by DC bus voltage Under the constraints, the current share of each module is adjusted to minimize the total input power of all modules (i.e., the sum of the total output power divided by the efficiency of each module). The mathematical essence of this problem is convex optimization, and this application uses the Lagrange multiplier method to solve it. Specifically, firstly, using the already obtained optimal switching frequency (this frequency is uniformly set for all parallel modules to avoid frequency beat interference between different modules), an efficiency function η is independently established for each module. This function, obtained through offline testing or online learning, describes the module's output current I. i The relationship with efficiency. The efficiency function typically peaks around 40% to 60% of the rated current and then gradually decreases towards both ends. Then, the Lagrangian function L = Σ is constructed. The first term is the sum of the input power of each module (i.e., the objective to be minimized), and the second term is the total current constraint. Taking the partial derivative of the current Ii of each module and setting it to zero yields the optimal current distribution condition: This means that the marginal power (derivative of current) of each module is equal. In actual execution, the total output current is first considered. A set of initial current values ​​is established based on the rated capacity of each module. Then, the marginal power of each module is calculated. Modules with higher marginal power have their current allocation increased (because the increase in input power per unit current is smaller), while modules with lower marginal power have their current allocation decreased. This adjustment is iterated until the marginal power of all modules is equal and the total current meets the constraints. The final current value of each module divided by the total current is the optimal current allocation ratio for each power module. For example, with two parallel modules at a total current of 200 amps, module A has a marginal power of 1.02 at 100 amps, and module B has a marginal power of 1.05 at 100 amps. Therefore, the current for module A should be increased to 110 amps, and the current for module B should be decreased to 90 amps to equalize their marginal power. This process converts physical parameters into optimal control parameters, ensuring that the power supply equipment always operates at its most energy-efficient point across the entire load range.

[0038] S3: Based on the estimated real-time junction temperature, the optimal switching frequency, and the optimal current allocation ratio, perform state prediction and correlation optimization on the power switches to generate the target duty cycle and target switching timing for each power switch.

[0039] After obtaining the optimal switching frequency and the optimal current allocation ratio for each power module, this application enters the power switch state prediction and correlation optimization stage. The data used in this stage includes real-time junction temperature estimates, the optimal switching frequency, the optimal current allocation ratio, and instantaneous values ​​of DC bus voltage and three-phase current from the power supply data. First, the sampling period is determined based on the optimal switching frequency, and the current state prediction of the power switch is performed using this sampling period to obtain the predicted current value. The optimal switching frequency has been determined after energy efficiency optimization, for example, 65kHz, with a corresponding switching period of approximately 15.38 microseconds. To enable model predictive control to make decisions within each switching period, the sampling period is set to be the same as the switching period, i.e., current state prediction is performed every 15.38 microseconds. The current state prediction uses a discrete-time state-space model, which is established in the αβ stationary coordinate system, using the filter inductor current as the state variable. Specifically, the α-axis current i is obtained by Clarke transformation of the three-phase current collected at the current sampling moment. α (k) and β-axis current i β (k), and the grid voltage v at the current moment. α (k), v β (k) and rectifier AC side voltage v cα (k), v cβ (k) Using the discretized equations of inductance L and equivalent resistance R, the predicted current value i at the next sampling time is calculated. α (k+1) and i β (k+1). This prediction formula originates from the forward Euler discretization of the circuit differential equations, which considers that the rate of change of inductor current is proportional to the voltage difference. Since the switching action of the power switch can only change the AC side voltage of the rectifier at discrete moments, by predicting the current at future moments, the effects of different switching states can be evaluated before the switching action occurs, thereby selecting the optimal switching combination and avoiding current distortion or overshoot caused by trial and error. For example, when the AI ​​computing load suddenly increases from idle to full load, the current command will change instantaneously. Without predictive capabilities, the controller can only start adjusting after the current deviation occurs, resulting in response delay and overshoot; however, through current state prediction, the controller can calculate the voltage vector that needs to be applied in advance, so that the current accurately reaches the target value in the next switching cycle.

[0040] After obtaining the predicted current value, the current deviation data is calculated based on the reference current value determined by the optimal current allocation ratio and the predicted current value. Simultaneously, the temperature exceedance deviation value is calculated based on the preset temperature threshold and the real-time junction temperature estimate. The optimal current allocation ratio gives the current share that each power module should bear. Multiplying this share by the total current command yields the reference current value for each module. For a three-phase rectifier, the reference current value is typically represented as a sinusoidal signal in the αβ coordinate system. Its amplitude is determined by both the power reference command and the DC bus voltage, and its phase is synchronized with the positive sequence component of the grid voltage. The current deviation data is defined as the difference between the reference current value and the predicted current value. The α-axis and β-axis components are calculated separately, and the square root of their sum of squares is taken, or the sum of squares is directly used as the scalar deviation. This deviation data reflects the difference between the actual current and the expected current at the next moment if operation continues according to the currently predicted current. On the other hand, the preset temperature threshold refers to the warning line for the safe operating junction temperature of the power switch. For example, 90% of the highest junction temperature of the device (150 degrees Celsius), i.e., 135 degrees Celsius, is taken as the temperature threshold. The real-time junction temperature estimate comes from step S1. If the estimate is lower than the temperature threshold, the temperature deviation is zero; if the estimate exceeds the threshold, the deviation is defined as the square of the excess. For example, if the estimated junction temperature is 140 degrees Celsius and the threshold is 135 degrees Celsius, the deviation is 25 (5 squared). Quantifying the temperature safety constraint into a numerical cost allows subsequent state selection to proactively avoid switching states that could lead to overheating damage while ensuring current tracking accuracy, thus achieving synergistic optimization of thermal management and electrical performance.

[0041] After obtaining the current deviation data and temperature over-limit deviation value, a state correlation evaluation of the power switch is further performed based on these two deviation data. For a three-phase Vienna rectifier or a two-level three-phase inverter, each arm has 2 or 3 switching states, resulting in 8 or 27 possible switching state combinations for the three phases. Each combination corresponds to a set of rectifier AC side voltages ( For each candidate switching state combination, the predicted current at the next moment under that switching state is first calculated using a discrete-time state-space model, thus calculating the current deviation value corresponding to that switching state. Simultaneously, this switching state also affects the instantaneous losses and temperature change rate of the power switch. However, for simplicity, within a very short control cycle, the temperature exceedance deviation value can use the result calculated in the previous step (because temperature changes slowly). The current deviation value and the temperature exceedance deviation value are weighted and summed according to preset weighting coefficients to obtain the deviation cost value for that switching state combination. The principle for setting the weights is: within the normal temperature range, current tracking has a dominant weight; when the temperature approaches or exceeds the threshold, the weight of the temperature exceedance deviation increases significantly. For example, if the current deviation weight is set to 1 and the temperature exceedance deviation weight is set to 10, then even if the current deviation is small, as long as the temperature exceeds the limit, the total cost will be large, thus forcing the controller to choose a state that can reduce the temperature (e.g., switching to zero voltage vector to reduce output power). The above calculation is repeated for each switching state combination to obtain a set of deviation cost values, each cost value associated with a specific switching state combination. The above operations transform the multi-objective optimization problem (which simultaneously requires accurate current tracking and temperature safety) into a single-objective cost comparison problem, enabling the controller to select the optimal solution from a finite number of discrete options within microseconds, thus avoiding the complex iterations of continuous optimization algorithms.

[0042] After evaluating the cost of all candidate switching state combinations, the switching state combination with the smallest deviation cost is selected as the target state combination. Based on this target state combination and the optimal switching frequency, the target duty cycle and target switching timing for each power switch are generated. Specifically, among all enumerated switching state combinations, the one with the smallest deviation cost is found. This combination directly specifies whether each power switch should be on or off in the next switching cycle. For example, for a three-phase rectifier, the target state combination might be represented as binary code such as (upper switch on, lower switch off, upper switch on, lower switch off, upper switch off, lower switch on). To generate a usable PWM signal, this discrete switching state needs to be converted into a continuous duty cycle instruction. Since model predictive control directly selects discrete states, the output is a constant duty cycle (either 0 or 1), but this method generates significant current ripple during the switching cycle. To smooth the current waveform, space vector modulation or symmetrical PWM modulation is typically used to extend the selected discrete states into a duty cycle form: based on the reference voltage vector corresponding to the target state combination, the duty cycle on each bridge arm is calculated such that the average output voltage during the switching cycle equals the reference voltage. The duty cycle calculation formula depends on the DC bus voltage and the reference voltage value; for example, for phase A, the duty cycle d... Simultaneously, the period value of the PWM counter is determined based on the optimal switching frequency. For example, 65kHz corresponds to a counting period of 15.38 microseconds. The duty cycle is multiplied by the period value to obtain the conduction time length. Finally, using the PWM module in the server, complementary PWM pulse pairs are generated according to the target switching timing (i.e., the phase relationship between each phase, usually using center alignment). A dead time dynamically adjusted by the real-time junction temperature estimate in step S1 is inserted to obtain the final gate signal driving each power switch. The optimization decision is translated into hardware-executable instructions, enabling the power switches to operate according to the predetermined timing, achieving the dual goals of current tracking and temperature protection. For example, when the real-time junction temperature estimate reaches 140 degrees Celsius, the target state combination will tend to select the zero voltage vector, corresponding to a reduced target conduction duty cycle, thereby reducing output power and heat generation. After the temperature drops, the normal duty cycle is restored. Through the above operations, the parameters obtained from energy efficiency optimization are fused with the physical state parameters to generate specific drive instructions for each power switch.

[0043] S4: Based on the target duty cycle, the target switching timing, and the detected current voltage data of the power supply bus, perform load power disturbance estimation on the power reference command to obtain the command correction value.

[0044] After obtaining the target duty cycle and target switching timing for each power switch, the process enters the load power disturbance estimation and correction stage for the power reference command. The input data for this stage includes the target duty cycle and target switching timing, the current voltage data detected in real-time by the voltage divider sampling circuit across the DC capacitor of the power supply bus (i.e., the instantaneous value of the DC bus voltage), and the power reference command preset by the upper-level management unit (this command is expressed in voltage form, for example, requiring the DC bus voltage to be stable at 800 volts). First, the power balance state of the power supply bus is constructed based on the target duty cycle and target switching timing, and the voltage deviation between the reference voltage value in the power reference command and the detected current voltage data of the power supply bus is calculated. The power balance state of the power supply bus refers to the energy flow relationship on the DC bus capacitor: the power flowing into the bus comes from the rectifier front end (i.e., the DC power rectified from the grid via the power switch), and the power flowing out of the bus flows to the load (i.e., the power consumed by GPUs, memory, fans, etc. in the AI ​​computing center). Bus capacitors themselves do not consume power, but they store energy. The rate of change of this stored energy is equal to the difference between the incoming power and the outgoing power. Using the target duty cycle and target switching sequence, the average power injected into the bus by the rectifier over one switching cycle can be calculated. Specifically, for a three-phase rectifier, based on the combination of switching states of each phase determined by the target switching sequence, combined with the current instantaneous values ​​of the three-phase current, the instantaneous power output from the rectifier to the bus is calculated. This is then averaged over one switching cycle to obtain the average incoming power. Due to load power Unable to be directly measured, the dynamic changes in bus voltage reflect... and Imbalance: When When the bus voltage rises; when At this time, the bus voltage drops. Therefore, the power balance state can be expressed as... ,in This is the bus capacitance value. This refers to the bus voltage. The significance of establishing this equilibrium state lies in linking the unobservable load power with the measurable (bus voltage, input power), providing a physical relationship for subsequent disturbance estimation. Simultaneously, the difference between the reference voltage value in the power reference command (e.g., 800 volts) and the currently measured bus voltage is calculated to obtain the voltage deviation value. This deviation value reflects the degree of deviation between the current output voltage of the power supply equipment and the target value, and is the main input signal for subsequent sliding mode control laws.

[0045] After obtaining the voltage deviation and power balance state, the load power disturbance is estimated based on the current voltage data and power balance state to obtain the estimated load power value. The core of load power disturbance estimation is to use a sliding mode observer to infer the unknown load power from the measurable bus voltage. The sliding mode observer is designed based on the aforementioned power balance equation, treating the load power as an unknown disturbance state. The state equation for constructing the observer is: for the square of the bus voltage... Its derivative satisfies The estimator of the observer is defined as follows: and ,in It is an estimate of the square of the bus voltage. This is the load power estimate, and the observer drives the convergence of the estimation error through a sign function. The specific recursive process is as follows: In each control cycle, the estimation error is first calculated. ,in It is obtained from the square of the measured bus voltage. Then it is updated according to the sliding mode observer structure. and : , ,in and For a positive observer gain, This is the sign function. After discretization, the current sampling time is used. (Calculated from the target conduction duty cycle and current) and the previous estimate, the current value is recursively derived. The convergence of this observer is guaranteed by sliding mode theory: once the estimation error enters the sliding surface ( ),but This will approach the expected value. Load power (i.e., the power consumed by the AI ​​computing cluster in real time) can change drastically at millisecond speeds. For example, when a GPU suddenly switches from an idle state to full-load training, the load power can jump from 10kW to 100kW within milliseconds. If the change in load power cannot be detected in time, the voltage controller can only start compensating after the bus voltage drops, leading to large voltage fluctuations or even triggering discharge protection. A sliding mode observer, however, can quickly track changes in load power without adding extra sensors, using only the measured bus voltage and known input power, providing crucial information for feedforward compensation. For example, when the load power increases by a step, the bus voltage begins to drop, and the observer will rapidly increase based on the abnormal rate of voltage change. The estimated value allows the subsequent control law to increase the input power in advance to counteract the disturbance.

[0046] After obtaining the load power estimate, the command correction value is obtained by calculating based on the voltage deviation and the load power estimate using a super-helical sliding mode control law. The super-helical sliding mode control law is a second-order sliding mode algorithm that retains the advantages of traditional sliding mode control, such as insensitivity to disturbances and parameters, while eliminating high-frequency chattering in the control quantity caused by the sign function. This control law calculates the voltage deviation value... As input, output a correction value. This correction will be superimposed on the original power reference command. The expression for the super-helical sliding mode control law consists of two terms: the first term is related to the square root of the voltage deviation multiplied by the sign function, and the second term is the integral of the sign function. The specific calculation process is as follows: first, calculate the square root of the absolute value of the voltage deviation and multiply it by the sign function, i.e. Then multiply by the scaling factor. We obtain the first term. The second term is a relation to the sign function. The integral multiplied by the integral coefficient Add the two values ​​together, then subtract the estimated load power. (To offset the effects of disturbances), the final command correction value is obtained. The command correction value specifies how much power needs to be added (if positive) or subtracted (if negative) from the input power command of the front-end rectifier in order to bring the bus voltage back to the reference value as quickly as possible. Because... Load changes have been tracked in real time, feedforward section It can compensate for most disturbances, while the remaining voltage deviation is gradually eliminated by the sliding mode term. The super-helical sliding mode control law can ensure that the voltage error and its derivative converge to zero simultaneously within a finite time, and the output is continuous and jitter-free, avoiding the impact of high-frequency switching signals on the power switch in traditional sliding mode. For example, when the load power suddenly increases by 100kW, causing the bus voltage to drop from 800V to 780V, the voltage deviation is -20V. The super-helical sliding mode control law calculates a positive correction value (e.g., +105kW). This correction value, when superimposed with the original power reference command, causes the rectifier to output more power, rapidly raising the bus voltage. At the same time, the estimated load power... It was also updated to approximately 100kW, bringing the steady-state correction value back to zero. Through the above operations, the rapid estimation of external load disturbances and the error-free tracking of the voltage loop ensure that the power supply bus voltage remains highly stable even when the AI ​​computing power load fluctuates drastically, providing an accurate power command reference for subsequent drive signal modulation.

[0047] S5: Modulate the signal according to the target duty cycle, the target switching timing and the instruction correction value to generate a power supply drive signal.

[0048] After obtaining the instruction correction value, the final signal modulation and drive generation stage begins. This stage first compensates and adjusts the target duty cycle based on the instruction correction value to obtain the compensated duty cycle. Then, based on the compensated duty cycle and the target switching timing, combined with the real-time junction temperature estimate, the dead time is dynamically adjusted to generate the original PWM pulse pair. Finally, the PWM pulse pair is converted by the gate drive circuit into a gate voltage waveform capable of driving the SiC MOSFET switch, i.e., the power supply drive signal.

[0049] First, the target duty cycle is compensated and adjusted. The command correction value is essentially an adjustment to the power reference command, reflecting the additional or reduced output power required by the rectifier to eliminate bus voltage deviation. Since there is a direct relationship between the rectifier's output power and the duty cycle—under constant DC bus voltage, the output power is proportional to the effective value of the input current, and the effective value of the input current is modulated by the duty cycle—it is necessary to convert the power correction value into a duty cycle correction value. The specific conversion method is based on the rectifier's modulation principle: for a three-phase Vienna rectifier, under unity power factor control, the amplitude of the AC side current is proportional to the duty cycle modulation depth. The relationship between the power correction value ΔP and the duty cycle correction value Δd is as follows: V m I represents the voltage amplitude of the power grid. mThe value represents the current amplitude. During actual execution, the ARM processor in the server calculates a proportional gain based on the measured grid voltage and current amplitudes. Then, it divides the instruction correction value by this gain to obtain the duty cycle increment Δd. This duty cycle increment is then added to the target duty cycle to obtain the compensated duty cycle. For example, when the instruction correction value is +5kW, the calculated duty cycle increment is +0.02. If the original target duty cycle is 0.45, the compensated value becomes 0.47. This compensation operation directly applies the voltage loop disturbance suppression result to the power switch's on-time, enabling the rectifier to respond to load changes in real time and maintain stable bus voltage. If this compensation is skipped and only the target duty cycle based on current prediction is used, only current tracking of the instruction can be guaranteed, but voltage deviations caused by sudden changes in load power cannot be compensated, resulting in steady-state error in voltage control.

[0050] After obtaining the compensated duty cycle, the dead time is dynamically adjusted based on the compensated duty cycle and the target switching timing, combined with the real-time junction temperature estimate, to generate the original PWM pulse pair. The target switching timing specifies the switching order and phase relationship of the power switches on each bridge arm. For example, the PWM carriers of a three-phase bridge arm typically use a center-aligned method with a phase difference of 120 degrees. The compensated duty cycle determines the conduction time of the upper transistor in each switching cycle: conduction time = duty cycle × switching cycle. Taking a switching cycle of 15.38 microseconds (corresponding to 65kHz) and a compensated duty cycle of 0.47 as an example, the conduction time of the upper transistor is 7.23 microseconds, and the conduction time of the lower transistor is 8.15 microseconds. However, since the power switches have turn-on and turn-off delays, and these delays increase with the junction temperature, directly outputting complementary PWM according to the duty cycle time would lead to a short-circuit risk of simultaneous conduction (i.e., shoot-through) of the upper and lower transistors. Therefore, a dead time must be inserted: after the upper transistor is turned off, wait for a dead time before turning on the lower transistor; after the lower transistor is turned off, wait for a dead time before turning on the upper transistor. The length of the dead time needs to be dynamically adjusted based on the real-time junction temperature estimate, because the higher the junction temperature, the longer the turn-off delay. The specific adjustment rule is: obtain the curve of turn-off delay versus junction temperature from the device datasheet, and fit a function... Dead time set to Safety margin. For example, if the turn-off delay is 150 nanoseconds at a junction temperature of 25 degrees Celsius and 250 nanoseconds at the same junction temperature, the dynamic dead time is linearly increased from 180 nanoseconds to 300 nanoseconds. The FPGA in the server integrates a high-precision PWM generator. Each PWM channel is configured with a rising edge comparator register and a falling edge comparator register. Based on the compensated duty cycle and dynamic dead time, the comparison value is calculated, and then two complementary PWM signals are generated. These two PWM signals are spaced apart according to the set dead time, avoiding shoot-through risk. The significance of this dynamic dead time adjustment is: using a smaller dead time at low junction temperatures reduces the additional losses caused by the freewheeling diode conducting during the dead time, thereby improving light-load efficiency; increasing the dead time at high junction temperatures ensures that shoot-through will not occur even under the worst temperature conditions, protecting the power switch from damage. While using a fixed maximum dead time is safer, it sacrifices efficiency, while dynamic adjustment achieves a balance between safety and efficiency.

[0051] After obtaining the original PWM pulse pair, the PWM pulse pair is converted into a gate voltage waveform capable of driving the SiC MOSFET switch, i.e., the power supply drive signal, through the gate drive circuit. The PWM logic level output by the server (typically 0 to 3.3 volts or 0 to 5 volts) cannot directly drive the gate of the power switch because the SiC MOSFET requires a positive voltage of +20 volts to fully conduct and a negative voltage of -5 volts to reliably turn off. Therefore, the PWM signal is first sent to the gate drive chip (such as IXDD630 or a dedicated SiC driver chip), which internally contains an isolation transformer or capacitor isolation circuit and a push-pull output stage. When the PWM input is high, the driver chip outputs a +20 volt gate voltage, turning on the SiC MOSFET; when the PWM input is low, the driver chip outputs a -5 volt gate voltage, quickly turning off the SiC MOSFET. Simultaneously, the driver chip also integrates Miller clamping and undervoltage lockout protection: automatically shutting off the output when the gate voltage is detected to be below a set threshold to prevent the switch from overheating and burning out due to operating in the linear region. The gate voltage waveform, amplified by the driver chip, is connected to the gate and source terminals of the SiC MOSFET via a gate resistor. The value of the gate resistor needs to be optimized based on the switching frequency and switching losses, typically ranging from 5 to 10 Ω, to balance switching speed and electromagnetic interference. The final output power drive signal is a multi-channel synchronous square wave pulse sequence with an amplitude of +20V / -5V, with each drive signal corresponding to the gate of a power switch. In the power supply equipment of a computing center, a three-phase Vienna rectifier typically contains six or more power switches, thus generating six or more power drive signals. These signals sequentially drive the switches of each bridge arm according to the target switching timing, achieving AC-DC conversion of electrical energy.

[0052] When the load power suddenly increases, the output command correction value becomes positive. This positive value increases the compensated duty cycle, thereby increasing the duration of the PWM high level. The drive signal makes the switching transistor conduct for a longer time, allowing the rectifier to inject more power into the bus and suppress voltage drops. Conversely, when the load decreases, the command correction value becomes negative, the duty cycle decreases, and the injected power decreases to prevent bus overvoltage. Simultaneously, the dynamic dead time is adjusted in real-time based on the estimated junction temperature, ensuring safety and reliability even at high temperatures. Through the above signal modulation operations, the final power supply drive signal is sent to the power switch gate of the power supply equipment, completing the full conversion from digital control algorithm to physical power transformation. The optimization decisions (optimal switching frequency for energy efficiency, optimal duty cycle for current tracking, voltage compensation correction value, and temperature adaptive dead time) are ultimately implemented as specific electrical signals controlling the power semiconductor devices, enabling the power supply equipment of the computing center to operate under high power density, high efficiency, and high stability conditions, meeting the stringent requirements of AI computing clusters for power supply systems.

[0053] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0054] In one embodiment, a computing center power supply adjustment device 2 is provided, which corresponds one-to-one with the computing center power supply adjustment method described in the above embodiments. For example... Figure 3 As shown, the power supply regulation device 2 of the computing center may include: a loss assessment module 21, an energy efficiency optimization module 22, a switch control module 23, a disturbance compensation module 24, and a signal modulation module 25. Detailed descriptions of each functional module are as follows: The loss assessment module 21 is used to obtain the power supply data and internal temperature of the power supply equipment in the computing center, and to perform thermoelectric coupling analysis on the power supply data and internal temperature to evaluate the real-time junction temperature estimate of each power switch and the corresponding loss allocation coefficient. The energy efficiency optimization module 22 is used to perform energy efficiency optimization processing on the power supply data based on the real-time junction temperature estimate, the loss allocation coefficient and the preset power reference command, to generate the optimal switching frequency and the optimal current allocation ratio. The switch control module 23 is used to perform state prediction and correlation optimization on the power switches based on the real-time junction temperature estimate, the optimal switching frequency and the optimal current distribution ratio, and generate the target duty cycle and target switching timing corresponding to each power switch. The disturbance compensation module 24 is used to estimate the load power disturbance of the power reference command based on the target duty cycle, the target switching timing and the detected current voltage data of the power supply bus, and obtain the command correction value. The signal modulation module 25 is used to modulate the signal according to the target duty cycle, the target switching timing and the instruction correction value to generate a power supply drive signal.

[0055] It should be noted that the information interaction and execution process between the above-mentioned devices / units are based on the same concept as the method embodiments of this application. For details on their specific functions and technical effects, please refer to the method embodiments section, and they will not be repeated here.

[0056] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0057] This application also provides a computer device, such as... Figure 4 As shown, the computer device includes: at least one processor 32, a memory 31, and a computer program stored in the memory 31 and executable on the at least one processor 32. When the processor 32 executes the computer program, it implements the steps in any of the above method embodiments, or when the processor 32 executes the computer program, it implements the functions of each module / unit in the above device embodiments.

[0058] For example, the computer program may be divided into one or more modules / units, which are stored in the memory 31 and executed by the processor 32 to complete this application. The one or more modules / units may be a series of computer program instruction segments capable of performing a specific function, which describe the execution process of the computer program in the computer device.

[0059] Those skilled in the art will understand that Figure 4The computer device described is merely an example and does not constitute a limitation on the computer device. It may include more or fewer components than shown, or combine certain components, or different components. For example, the computer device may also include input / output devices, network access devices, buses, etc.

[0060] The processor 32 mentioned above can be a Central Processing Unit (CPU), or it can be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), or field-programmable gate arrays (FPGAs). Programmable Gate Array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor 32 can be a microprocessor or any conventional processor, etc.

[0061] The memory 31 can be an internal storage unit of the computer device, such as a hard drive or memory. The memory 31 can also be an external storage device of the computer device, such as a plug-in hard drive, Smart Media Card (SMC), Secure Digital (SD) card, or Flash Card. Furthermore, the memory 31 can include both internal and external storage units of the computer device.

[0062] This application also provides a readable storage medium storing a computer program that, when executed by a processor, implements the steps described in the various method embodiments above.

[0063] This application provides a computer program product that, when run on an electronic device, enables the electronic device to perform the steps described in the various method embodiments above.

[0064] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments of this application can be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include at least: any entity or device capable of carrying computer program code to a photographing device / terminal device, a recording medium, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electrical carrier signal, a telecommunication signal, and a software distribution medium. Examples include USB flash drives, portable hard drives, magnetic disks, or optical disks. In some jurisdictions, according to legislation and patent practice, computer-readable media cannot be electrical carrier signals or telecommunication signals.

[0065] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0066] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0067] In the embodiments provided in this application, it should be understood that the disclosed apparatus / devices and methods can be implemented in other ways. For example, the apparatus / device embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0068] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0069] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A power supply regulation method for a computing center, characterized in that, The method includes: The power supply data and internal temperature of the power supply equipment in the computing center are obtained, and thermoelectric coupling analysis is performed on the power supply data and internal temperature to evaluate the real-time junction temperature estimate of each power switch and the corresponding loss distribution coefficient. Based on the real-time junction temperature estimate, the loss allocation coefficient, and the preset power reference command, the power supply data is subjected to energy efficiency optimization processing to generate the optimal switching frequency and the optimal current allocation ratio. Based on the real-time junction temperature estimate, the optimal switching frequency, and the optimal current allocation ratio, the power switches are state-predicted and correlated to generate target duty cycle and target switching timing for each power switch. Based on the target duty cycle, the target switching timing, and the detected current voltage data of the power supply bus, load power disturbance estimation is performed on the power reference command to obtain the command correction value; The signal is modulated according to the target duty cycle, the target switching timing, and the instruction correction value to generate a power supply drive signal.

2. The power supply adjustment method for a computing center as described in claim 1, characterized in that, The power supply data includes the three-phase voltage and three-phase current of each power switch. The process of acquiring the power supply data and internal temperature of the power supply equipment in the computing center, and performing thermoelectric coupling analysis on the power supply data and internal temperature to evaluate the real-time junction temperature estimate of each power switch and the corresponding loss distribution coefficient includes: The three-phase voltage and three-phase current of each power switch in the power supply equipment of the computing center are collected synchronously, and the fundamental positive sequence component of each phase is extracted. The instantaneous active power is calculated based on the fundamental positive sequence component to obtain the average active power. Based on preset loss parameters, the three-phase voltage and the three-phase current are averaged and separated by switching cycle to obtain the conduction loss and switching loss of each power switch. The internal temperature of the power supply equipment is obtained. Based on the average active power, the conduction loss, the switching loss, and the internal temperature, the thermal state of the power switches is recursively estimated to obtain the real-time junction temperature estimate of each power switch and the corresponding loss distribution coefficient.

3. The power supply adjustment method for a computing center as described in claim 2, characterized in that, The step of recursively estimating the thermal state of the power switches based on the average active power, the conduction loss, the switching loss, and the internal temperature to obtain the real-time junction temperature estimate and corresponding loss distribution coefficient for each power switch includes: The total loss of each power switch is calculated based on the conduction loss and the switching loss, and an electrothermal equivalent analysis of the power switches is performed based on the total loss to obtain the state node of each power switch. Based on the preset set of thermal resistance coefficients, the total loss and the average active power, the heat transfer process between state nodes is recursively calculated to obtain the predicted temperature value corresponding to each state node. The predicted temperature value is corrected for error based on the internal temperature to obtain the real-time junction temperature estimate of each power switch; Based on the conduction loss and the proportional relationship between the switching loss and the total loss, the loss allocation coefficient corresponding to each power switch is determined.

4. The power supply adjustment method for a computing center as described in claim 1, characterized in that, The step of performing energy efficiency optimization processing on the power supply data based on the real-time junction temperature estimate, the loss allocation coefficient, and the preset power reference command to generate the optimal switching frequency and the optimal current allocation ratio includes: Based on the real-time junction temperature estimate, the power supply data, and the loss distribution coefficient, the total loss of the power supply equipment is analyzed to obtain total loss trend data. Based on the preset feasible range of switching frequency, the total loss trend data is optimized to minimize the total loss, thereby generating the optimal switching frequency of the power supply equipment. Based on the preset power reference command and the optimal switching frequency, the current is balanced and distributed among the power modules operating in parallel in the power supply equipment to generate the optimal current distribution ratio for each power module.

5. The power supply adjustment method for a computing center as described in claim 1, characterized in that, The step of performing state prediction and correlation optimization on the power switches based on the real-time junction temperature estimate, the optimal switching frequency, and the optimal current allocation ratio to generate the target duty cycle and target switching timing for each power switch includes: The sampling period is determined based on the optimal switching frequency, and the current state of the power switch is predicted based on the sampling period to obtain the predicted current value. The current deviation data is calculated based on the reference current value determined by the optimal current distribution ratio and the predicted current value, and the temperature over-limit deviation value is calculated based on the preset temperature threshold and the real-time junction temperature estimate. Based on the current deviation data and the temperature over-limit deviation value, the power switch is evaluated for state association, and a switch state combination and corresponding deviation cost are generated. The switch state combination corresponding to the minimum deviation cost is selected as the target state combination, and the target duty cycle and target switching timing corresponding to each power switch are generated based on the target state combination and the optimal switching frequency.

6. The power supply adjustment method for a computing center as described in claim 1, characterized in that, The step of estimating the load power disturbance of the power reference command based on the target duty cycle, the target switching timing, and the detected current voltage data of the power supply bus, and obtaining the command correction value, includes: The power balance state of the power supply bus is constructed based on the target duty cycle and the target switching sequence, and the voltage deviation between the reference voltage value in the power reference command and the detected current voltage data of the power supply bus is calculated. Based on the current voltage data and the power balance state, load power disturbance is estimated to obtain the estimated load power value; The command correction value is obtained by calculating the voltage deviation value and the load power estimate based on the super-helical sliding mode control law.

7. A power supply adjustment device for a computing center, applied to the power supply adjustment method for a computing center as described in claim 1, characterized in that, The device includes: The loss assessment module is used to obtain the power supply data and internal temperature of the power supply equipment in the computing center, and to perform thermoelectric coupling analysis on the power supply data and internal temperature to evaluate the real-time junction temperature estimate of each power switch and the corresponding loss allocation coefficient. The energy efficiency optimization module is used to perform energy efficiency optimization processing on the power supply data based on the real-time junction temperature estimate, the loss allocation coefficient, and the preset power reference command, to generate the optimal switching frequency and the optimal current allocation ratio. The switching control module is used to perform state prediction and correlation optimization of the power switches based on the real-time junction temperature estimate, the optimal switching frequency, and the optimal current allocation ratio, and to generate the target duty cycle and target switching timing corresponding to each power switch. The disturbance compensation module is used to estimate the load power disturbance of the power reference command based on the target duty cycle, the target switching timing and the detected current voltage data of the power supply bus, and obtain the command correction value. The signal modulation module is used to modulate the signal according to the target duty cycle, the target switching timing and the instruction correction value to generate a power supply drive signal.

8. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the power supply adjustment method for the computing center as described in any one of claims 1 to 6.

9. A readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements the steps of the power supply adjustment method for the computing center as described in any one of claims 1 to 6.

10. A computer program product, characterized in that, The computer program product includes a computer program that, when executed by a processor, implements the steps of the power supply regulation method for the computing center as described in any one of claims 1 to 6.

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