Upper plate sampling mode offset calibration circuit and method

Abstract

The application discloses a top plate sampling type offset calibration circuit and method, and relates to the technical field of analog-to-digital converter calibration. The circuit comprises: a plurality of parallel sub-analog-to-digital converters, a top plate type gain modulation module is arranged at the sampling front end of the sub-analog-to-digital converter, and the sub-analog-to-digital converter is further provided with a clock module and a quantizer; a plurality of parallel digital calibration engines, each digital calibration engine is connected with a corresponding sub-analog-to-digital converter; a pseudo-random sequence generator connected with the sub-analog-to-digital converter and the digital calibration engine, the pseudo-random sequence generator is used for generating a pseudo-random sequence; and the digital calibration engine is used for performing offset detection, offset calibration and gain demodulation on a quantized signal output by the sub-analog-to-digital converter according to the pseudo-random sequence, and outputting a digital signal. The circuit can realize accurate calibration of the analog-to-digital converter.

Description

Technical Field

[0001] This application relates to, but is not limited to, the field of analog-to-digital converter calibration technology, and particularly to an upper plate sampling offset calibration circuit and method. Background Technology

[0002] With the increasing demands on ADC sampling rate and dynamic range from high-speed communication, radar detection, and broadband data acquisition systems, time-interleaved analog-to-digital converters (TI ADCs) have become a crucial architecture for overcoming the speed limitations of single-core ADCs. TI ADCs achieve high-speed conversion through alternating sampling by multiple sub-ADC channels. The sampling front-end of each sub-ADC directly impacts the system's input bandwidth, sampling accuracy, and dynamic performance. For TI ADCs using capacitor-sampling ADCs as sub-channels, the sampling network typically consists of a capacitor array and a switching network, often employing an upper-plate sampling structure. In this structure, the upper plates of multiple sampling capacitors are connected to a common sampling node to receive the input signal, while the lower plates are connected to different reference or control nodes according to the sampling and conversion timing. The upper-plate sampling structure offers high timing efficiency, improves sampling consistency, and allows the capacitor array to simultaneously handle input sampling, holding, and charge redistribution functions, thereby reducing additional buffering, area, and power consumption overhead.

[0003] While TI's ADCs achieve high-speed conversion by alternating sampling of sub-ADC channels, they also introduce new problems. Due to process variations and circuit non-ideals, mismatch errors such as offset, gain, and sampling time inevitably exist between sub-channels. Among these, the offset mismatch between channels can create fixed-pattern noise or interleaved spurious signals in the output spectrum, reducing SFDR and SNDR.

[0004] To eliminate offset mismatch, existing techniques typically employ foreground calibration or statistically based background calibration: Front-end calibration: This typically involves shorting the inputs to common-mode level when the system is idle and measuring the output offset of each sub-ADC channel. While simple to implement, this method requires interrupting the normal sampling process and cannot meet the needs of continuously operating systems such as high-speed communication and real-time monitoring.

[0005] Background calibration: Offset is typically estimated by averaging the output data of each sub-ADC over a long period. This method relies on the assumption that the statistical mean of the input signals of each sub-channel is consistent or that the long-term mean of the input signals is zero. When the input signal contains DC components, low-frequency components, or is correlated with the interleaving frequency, the calibration logic may misinterpret these components as offset errors, leading to inaccurate calibration results or even filtering out useful signals.

[0006] Therefore, traditional front-end calibration and statistical back-end calibration have significant limitations in high-speed TI ADC applications with continuous operation, unknown input signals, or complex input spectra. Summary of the Invention

[0007] This application provides an upper plate sampling offset calibration circuit and method that can achieve offset calibration independent of the input signal.

[0008] In a first aspect, embodiments of this application provide an upper electrode sampling offset calibration circuit, including: Multiple parallel sub-analog-to-digital converters (ADCs) are provided. The sampling front end of each ADC is equipped with an upper plate gain modulation module. Each ADC is also equipped with a clock module and a quantizer. The upper plate gain modulation module is used to sample the input signal. The quantizer is used to quantize the sampled input signal. The clock module is used to provide a clock signal for the sampling and quantization process of the ADC. Multiple parallel digital calibration engines, each digital calibration engine corresponding to a sub-analog-to-digital converter, with each digital calibration engine connected to its corresponding sub-analog-to-digital converter; A pseudo-random sequence generator is connected to the sub-analog-to-digital converter and the digital calibration engine, respectively. The pseudo-random sequence generator is used to generate a pseudo-random sequence and send the pseudo-random sequence to the sub-analog-to-digital converter and the digital calibration engine, so that the upper plate gain modulation module adjusts the sampling gain of the sub-analog-to-digital converter according to the pseudo-random sequence. The digital calibration engine is used to perform offset detection, offset calibration, and gain demodulation on the quantized signal output by the sub-analog-to-digital converter based on the pseudo-random sequence, and output a digital signal.

[0009] In some embodiments, the upper electrode type gain modulation module includes: A sampling capacitor, wherein the upper plate of the sampling capacitor is connected to the input signal via a sampling switch; A switching network is connected to the lower plate of the sampling capacitor. The switching network is used to switch the connection of the lower plate of the sampling capacitor to a reference level, a common-mode level, or ground. A first modulation capacitor, the upper plate of which is connected to the input signal via the sampling switch, and the lower plate of which is grounded via a switching switch, wherein the switching switch is turned on and off by the pseudo-random sequence. The second modulation capacitor has its upper plate connected to the lower plate of the first modulation capacitor, and its lower plate is grounded.

[0010] In some embodiments, the switch network includes: A first switch, one end of which is connected to the lower plate of the sampling capacitor, and the other end of which is connected to the reference level; A second switch, one end of which is connected to the lower plate of the sampling capacitor, and the other end of which is connected to the common-mode level; The third switch has one end connected to the lower plate of the sampling capacitor and the other end grounded.

[0011] In some embodiments, the digital calibration engine includes an offset detection module, an offset calibration module, and a gain demodulation module. The offset detection module is used to detect the offset error of the quantization signal of the sub-analog-to-digital converter. The offset calibration module is used to perform offset calibration on the quantization signal of the sub-analog-to-digital converter according to the offset error. The gain demodulation module is used to perform gain demodulation on the offset-calibrated quantization signal and output the digital signal.

[0012] In some embodiments, the offset detection module includes a first shunt component and a second shunt component connected in parallel. The first shunt component includes a first multiplier, a first accumulator, and a first averager connected in sequence. The second shunt component includes a second multiplier, a second accumulator, a second averager, and a third multiplier connected in sequence. The input terminals of the first multiplier are respectively connected to the quantized signal and the pseudo-random sequence. The input terminals of the second multiplier are respectively connected to the quantized signal and the inverted signal of the pseudo-random sequence. The input terminal of the third multiplier is respectively connected to the output terminal of the second averager and a preset modulation gain ratio. The offset detection module further includes a first subtractor and a fourth multiplier. The input terminals of the first subtractor are respectively connected to the output terminals of the first averager and the third multiplier. The input terminal of the fourth multiplier is respectively connected to the output terminal of the first subtractor and a preset scaling factor. The output terminal of the fourth multiplier is used to output the offset error.

[0013] In some embodiments, the offset calibration module includes a second subtractor, the input of which is connected to the quantized signal and the offset error, respectively. The second subtractor is used to subtract the quantized signal and the offset error to obtain an offset calibration result. The gain demodulation module includes a multiplexer and a fifth multiplier. The multiplexer is used to select a corresponding gain recovery coefficient according to the pseudo-random sequence. The input of the fifth multiplier is connected to the output of the second subtractor and the multiplexer, respectively. The fifth multiplier is used to multiply the offset calibration result by the gain recovery coefficient to obtain the digital signal.

[0014] Secondly, embodiments of this application also provide an upper electrode plate sampling offset calibration method, based on the upper electrode plate sampling offset calibration circuit as described in the first aspect embodiment, the method comprising: A pseudo-random sequence is generated by the pseudo-random sequence generator, and the pseudo-random sequence is sent to the sub-analog-to-digital converter and the digital calibration engine; The sampling gain is adjusted according to the pseudo-random sequence so that the upper plate gain modulation module samples the input signal according to the adjusted sampling gain; The sampled input signal is quantized by the quantizer, and the quantized signal is output to the digital calibration engine. The digital calibration engine performs offset detection, offset calibration, and gain demodulation on the quantized signal based on the pseudo-random sequence, and outputs a digital signal.

[0015] In some embodiments of this application, the upper plate gain modulation module includes a sampling capacitor, a switching network, a first modulation capacitor, and a second modulation capacitor. The upper plate of the sampling capacitor is connected to the input signal via a sampling switch. The switching network is connected to the lower plate of the sampling capacitor and is used to switch the connection of the lower plate of the sampling capacitor to a reference level, a common-mode level, or ground. The upper plate of the first modulation capacitor is connected to the input signal via the sampling switch, and the lower plate of the first modulation capacitor is grounded via a switching switch. The switching switch is controlled by a pseudo-random sequence. The upper plate of the second modulation capacitor is connected to the lower plate of the first modulation capacitor, and the lower plate of the second modulation capacitor is grounded. The pseudo-random sequence includes 0 and 1. The step of adjusting the sampling gain according to the pseudo-random sequence so that the upper plate gain modulation module samples the input signal according to the adjusted sampling gain includes: During the sampling phase, the sampling switch is closed, and the lower plate of the sampling capacitor is connected to the common-mode level through the switch switching network. When the pseudo-random sequence is 1, the switching switch is turned on, so that the lower plate of the first modulation capacitor is grounded. When the pseudo-random sequence is 0, the switching switch is turned off, so that the first modulation capacitor and the second modulation capacitor are connected in series. During the holding phase, the sampling switch is disconnected, and the lower plate of the sampling capacitor is connected to the common-mode level via the switch switching network. When the pseudo-random sequence is 1, the switching switch is turned on, so that the lower plate of the first modulation capacitor is grounded. When the pseudo-random sequence is 0, the switching switch is turned off, so that the first modulation capacitor and the second modulation capacitor are connected in series. During the quantization phase, the sampling switch is disconnected, and the lower plate of the sampling capacitor is connected to the reference level or ground via the switch switching network. When the pseudo-random sequence is 1, the switching switch is turned on, so that the lower plate of the first modulation capacitor is grounded. When the pseudo-random sequence is 0, the switching switch is turned off, so that the first modulation capacitor and the second modulation capacitor are connected in series.

[0016] In some embodiments of this application, the digital calibration engine includes an offset detection module, an offset calibration module, and a gain demodulation module. The offset detection module includes a first shunt component and a second shunt component connected in parallel. The first shunt component includes a first multiplier, a first accumulator, and a first averager connected in sequence. The second shunt component includes a second multiplier, a second accumulator, a second averager, and a third multiplier connected in sequence. The offset detection module also includes a first subtractor and a fourth multiplier. Offset detection of the quantized signal includes: The quantized signal is input to the first shunt component and the second shunt component respectively; The first multiplier multiplies the quantized signal with the pseudo-random sequence to obtain a first multiplication result; The first accumulation result is obtained by accumulating all the first multiplication results using the first accumulator. The first average result is obtained by averaging the first accumulated result using the first averager. The second multiplier multiplies the quantized signal with the inverted signal of the pseudo-random sequence to obtain a second multiplication result. The second accumulator is used to accumulate all the second multiplication results to obtain the second accumulated result; The second average result is obtained by averaging the second accumulated result using the second averager. A preset modulation gain ratio is obtained, and the second average result is multiplied by the modulation gain ratio using the third multiplier to obtain the third multiplication result; The difference result is obtained by subtracting the first average result from the third multiplication result using the first subtractor. The offset error is obtained by multiplying the difference result with the scaling factor using the fourth multiplier.

[0017] In some embodiments of this application, the offset calibration module includes a second subtractor, which is used to subtract the quantized signal and the offset error to obtain an offset calibration result; the gain demodulation module includes a multiplexer and a fifth multiplier, and the gain demodulation includes: The multiplexer selects the corresponding gain recovery coefficient based on the pseudo-random sequence. The digital signal is obtained by multiplying the offset calibration result with the gain recovery coefficient using the fifth multiplier.

[0018] The upper plate sampling offset calibration circuit and method according to the embodiments of this application have at least the following beneficial effects: a pseudo-random sequence is generated by a pseudo-random sequence generator, and the pseudo-random sequence is sent to the upper plate gain modulation module in each sub-analog-to-digital converter (ADC) to adjust the sampling gain of the sub-ADC. Simultaneously, the pseudo-random sequence is also sent to the subsequent digital calibration engine for offset detection, offset calibration, and gain demodulation. By changing the sampling gain using the pseudo-random sequence, and by performing offset detection, offset calibration, and gain demodulation based on the pseudo-random sequence using the digital calibration engine, offset calibration of the ADC independent of the input signal can be achieved.

[0019] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the upper plate sampling offset calibration circuit provided in one embodiment of this application; Figure 2 This is a circuit schematic diagram of an upper plate type gain modulation module provided in one embodiment of this application; Figure 3 This is a schematic diagram of the working principle of an upper plate type gain modulation module provided in one embodiment of this application; Figure 4 This is a circuit schematic diagram of a digital calibration engine provided in one embodiment of this application; Figure 5 This is a flowchart of the steps of an upper electrode sampling offset calibration method provided in one embodiment of this application; Figure 6 This is a schematic diagram of the controller provided in one embodiment of this application. Detailed Implementation

[0021] The embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application. The step numbers in the following embodiments are only set for ease of explanation, and there is no limitation on the order between the steps. The execution order of each step in the embodiments can be adaptively adjusted according to the understanding of those skilled in the art.

[0022] In the description of this invention, it should be understood that the orientation descriptions, such as up, down, front, back, left, right, etc., are based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0023] The terms "first," "second," "third," and "fourth," etc., used in the specification, claims, and accompanying drawings of this invention are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.

[0024] In this invention, the reference to "embodiment" means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a mutually exclusive, independent, or alternative embodiment. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0025] To reduce the dependence of offset calibration on the statistical characteristics of the input signal, this application achieves decoupling between the input signal and the offset error by dynamically adjusting the input signal gain. The basic idea of ​​this method is that the input signal components change proportionally with the front-end gain, while the offset component, which is additive in the digital output, does not change synchronously with this gain.

[0026] Specifically, the principle behind dynamically adjusting the gain to calculate the offset is as follows: A variable gain controlled by a pseudo-random sequence (PN) is introduced at the sampling front end of the sub-ADC channel. At this time, the output of the ADC channel... It can be represented as: ; Where X is the input signal and OS is the offset error, which refers to the offset component that is additively expressed in the channel's digital output during sampling and quantization and does not change synchronously with the equivalent sampling gain modulation. Its sources include, but are not limited to, sampling switch charge injection mismatch, clock feedthrough mismatch, additive errors related to the reference level or digital-to-analog conversion, and the drift of the aforementioned errors with temperature and time. This equation reveals a key characteristic: when the front-end gain is changed... At that time, the input signal It will be magnified or reduced proportionally, while the offset error OS, as an additive component in the digital output, does not change with the switching of the gain state G.

[0027] Based on this characteristic, the system can control the gain in two known states (e.g., using a PN sequence). and Randomly switch between ) When PN = 1, the gain is The channel output is: ; When PN = 0, the gain is The channel output is: ; In the digital backend, the data calibration engine groups and statistically analyzes the output data based on the PN status. Because... and These are known different constants; the calibration logic only needs to be... and By performing simple scaling and subtraction operations on the statistical mean, the input signal can be included. The terms completely cancel each other out (decouple), ultimately leaving only the terms related to The expression is given. Through this dynamic gain adjustment method, the system perfectly eliminates interference from the input signal, achieving true calibration independent of the input signal.

[0028] Since dynamically adjusting the gain can achieve calibration independent of the input signal, the key question becomes how to physically implement this gain modulation within the chip. Currently, the feasible methods for achieving gain adjustment mainly include the following: 1. Adjusting the gain of the input buffer: This method generally switches the gain by changing the load resistance or bias current inside the buffer.

[0029] 2. Use a variable gain amplifier (VGA): This method typically involves cascading a first-order VGA circuit at the front end of the ADC and controlling its gain level through digital logic.

[0030] 3. Set up a programmable amplifier (PGA) feedback network: This method generally changes the closed-loop gain by switching the feedback capacitor or resistor array of the closed-loop amplifier.

[0031] However, in high-speed, high-precision ADCs (such as those at the GS / s level), the above method of directly manipulating analog input buffers and amplification devices to adjust the gain has a serious performance bottleneck: 1. Disruption of front-end linearity and impedance matching: The input / output impedance and nonlinear characteristics of buffers and amplifiers change under different gain states. This not only alters the signal amplitude but also introduces state-dependent harmonic distortion, disrupting the aforementioned linearity and impedance matching. The ideal linear equation.

[0032] 2. Introducing transient settling error: High-speed ADCs have extremely short sampling windows. Buffers and amplifiers are prone to transient responses after switching gain states. If they cannot stabilize completely within the extremely short sampling window, it will directly lead to serious sampling errors.

[0033] 3. Increased analog power consumption and area: Introducing VGA or complex buffer feedback networks will significantly increase the power consumption and layout area of ​​the high-speed front end, increasing the burden on the front end driver.

[0034] In summary, existing physical implementations of gain adjustment severely degrade the dynamic performance of the high-speed ADC front-end. Therefore, there is an urgent need for a novel, low-distortion gain modulation circuit structure that can retain the perfect algorithmic characteristic of "calculating offset by adjusting gain" while avoiding dynamic gain switching of the high-speed analog front-end.

[0035] To address this, this application proposes an upper plate sampling offset calibration circuit and method for offset calibration of time-interleaved analog-to-digital converters. When the ADC adopts an upper plate sampling structure, modulation is not achieved by dynamically changing the input buffer or front-end amplifier gain, nor is an additional control switch introduced at the common upper plate sampling node. Instead, the equivalent sampling capacitance value is changed by altering the connection state of the modulation capacitor within the sampling network, thereby achieving equivalent random gain modulation of the input signal and providing stable, low-distortion modulation conditions for subsequent offset calibration algorithms.

[0036] The embodiments of this application will be further described below with reference to the accompanying drawings.

[0037] Firstly, embodiments of this application propose an upper plate sampling offset calibration circuit, such as... Figure 1 As shown, the circuit includes multiple parallel sub-analog-to-digital converters 200. Multiple parallel digital calibration engines 300 and pseudo-random sequence generators 400 are included. Each sub-analog-to-digital converter 200 (sub-ADC_1 to sub-ADC_M, where M is a positive integer) has an upper-plate gain modulation module 210 at its sampling front end. Each sub-ADC 200 also includes a clock module 220 and a quantizer 230. The upper-plate gain modulation module 210 samples the input signal Vin, the quantizer 230 quantizes the sampled input signal, and the clock module 220 provides a clock signal for the sampling and quantization processes of the sub-ADC 200. Each digital calibration engine 300 corresponds one-to-one with a sub-ADC 200. Each digital calibration engine 300 is connected to its corresponding sub-analog-to-digital converter 200; a pseudo-random sequence generator 400 is connected to both the sub-analog-to-digital converter 200 and the digital calibration engine 300. The pseudo-random sequence generator 400 generates a pseudo-random sequence (PN) and sends it to both the sub-analog-to-digital converter 200 and the digital calibration engine 300, so that the upper plate gain modulation module 210 adjusts the sampling gain of the sub-analog-to-digital converter 200 according to the pseudo-random sequence; the digital calibration engine 300 performs offset detection, offset calibration, and gain demodulation on the quantized signal output by the sub-analog-to-digital converter according to the pseudo-random sequence, and outputs a digital signal. Figure 1 In this context, Dout_raw refers to the quantized signal output by sub-analog-to-digital converter 200, Dout1_raw refers to the quantized signal output by sub-ADC_1, and DoutM_raw is the quantized signal output by sub-ADC_M. Dout1_cal through DoutM_cal are the digital signals output by each digital calibration engine 300, respectively.

[0038] Specifically, the pseudo-random sequence generator 400 generates a pseudo-random sequence PN, which can be implemented by a linear feedback shift register, a pseudo-random code generator, a random number generator, or other digital sequence generation circuits. The PN sequence is fed into the upper plate gain modulation module 210 in each sub-ADC channel to adjust the sampling gain of the sub-analog-to-digital converter 200. Simultaneously, the PN sequence is also fed into the subsequent digital calibration engine 300 for offset detection, offset calibration, and gain demodulation. For each sub-analog-to-digital converter 200, each includes an upper plate gain modulation module 210, a clock module 220, and a quantizer 230. The PN sequence and the sampling clock jointly control the state of the upper plate gain modulation module 210, causing the input signal to correspond to different equivalent sampling gains under different PN states. In this embodiment, the structure of the quantizer 230 is not particularly limited. The quantizer 230 can adopt a successive approximation quantization structure, a pipelined quantization structure, a hybrid pipelined successive approximation quantization structure, a flash quantization structure, a folded interpolation quantization structure, or other quantization structures with a switched-capacitor sampling scheme at the sampling front end. The upper plate gain modulation module 210 of this application is mainly disposed at the sampling front end of the sub-analog-to-digital converter 200, and its function occurs during the input signal sampling stage. Therefore, this application does not depend on the specific working mode of the subsequent quantizer, nor does it require changing the quantization process of the sub-analog-to-digital converter 200. As long as the input front end of the sub-analog-to-digital converter 200 includes a switched-capacitor sampling network, equivalent sampling gain modulation controlled by the PN sequence can be achieved by controlling whether some of the sampling capacitors participate in the input signal sampling.

[0039] It should be noted that, as Figure 1 As shown, the upper plate sampling offset calibration circuit may also include an input buffer 100. The input buffer 100 is used to receive the input signal Vin, buffer the input signal Vin, and then send the buffered input signal Vin to the sub-analog-to-digital converter 200. Of course, the upper plate sampling offset calibration circuit may also exclude the input buffer 100, depending on the actual needs.

[0040] In some embodiments of this application, such as Figure 2As shown, the upper plate type gain modulation module 210 includes: a sampling capacitor Cs, a switching network, a first modulation capacitor Ca1, and a second modulation capacitor Ca2; the upper plate of the sampling capacitor Cs is connected to the input signal Vin through a sampling switch S5; the switching network is connected to the lower plate of the sampling capacitor Cs, and the switching network is used to switch the connection of the lower plate of the sampling capacitor Cs to the reference level Vref, the common-mode level Vcm, or ground; the upper plate of the first modulation capacitor Ca1 is connected to the input signal Vin through the sampling switch S5, and the lower plate of the first modulation capacitor Ca1 is grounded through a switching switch S4, and the conduction and disconnection of the switching switch S4 are controlled by a pseudo-random sequence; the upper plate of the second modulation capacitor Ca2 is connected to the lower plate of the first modulation capacitor Ca1, and the lower plate of the second modulation capacitor Ca2 is grounded.

[0041] It should be noted that the sampling capacitor Cs can exist as a single, complete sampling capacitor, or it can be divided into a main sampling capacitor array composed of multiple unit capacitors, such as a binary weighted capacitor array, a segmented capacitor array, or a redundant capacitor array. The upper plates of the sampling capacitor Cs and the first modulation capacitor Ca1 can be connected to the sample-and-hold node, comparator input node, residual signal node, or quantizer input node of the sub-analog-to-digital converter 200. This node is used to provide the sampled analog voltage or charge to the subsequent quantizer 230. The lower plate of the sampling capacitor Cs is selectively connected to the reference level Vref, the common-mode level Vcm, or ground through a switching network. During the sampling phase, the sampling clock provided by the clock module 220 controls the lower plate of the sampling capacitor Cs to be connected to the common-mode level Vcm; during the quantization phase, the lower plate of the sampling capacitor Cs is switched to be connected to the reference level Vref or ground according to the comparison result of the quantizer 230, i.e., controlled by the decision of the quantizer 230.

[0042] In some embodiments of this application, such as Figure 2 As shown, the switching network includes a first switch S1, a second switch S2, and a third switch S3. One end of the first switch S1 is connected to the lower plate of the sampling capacitor Cs, and the other end of the first switch S1 is connected to the reference level Vref. One end of the second switch S2 is connected to the lower plate of the sampling capacitor Cs, and the other end of the second switch S2 is connected to the common-mode level Vcm. One end of the third switch S3 is connected to the lower plate of the sampling capacitor Cs, and the other end of the third switch S3 is grounded.

[0043] It should be noted that the PN control logic generates a capacitor selection signal based on the current pseudo-random sequence state, which is used to control the switching state of the switching switch S4 in each sampling period. Figure 3 This diagram illustrates the working state of the PN-controlled upper plate gain modulation module 210 provided in this embodiment of the application. Its workflow includes three stages: In the first stage (sampling stage), sampling switch S5 is closed (the switching state of sampling switch S5 is controlled by the sampling clock provided by clock module 220), the lower plate of sampling capacitor Cs is connected to the common-mode voltage Vcm, and the upper plate is connected to the input signal Vin. The connection state of the first modulation capacitor Ca1 and the second modulation capacitor Ca2 is as follows: If PN is 1, then the lower plate of Ca1 is directly grounded through the switching switch S4, and at the same time, both the upper and lower plates of Ca2 are grounded. If PN is 0, then the lower plate of Ca1 is connected to the upper plate of Ca2, and the lower plate of Ca2 is grounded, thus realizing that Ca1 and Ca2 are connected in series on the lower plate side and then grounded.

[0044] Therefore, the total capacitance of the upper plate to ground varies depending on the PN value: when PN is 1, the equivalent capacitance involved in modulation is Ca1; when PN is 0, the equivalent capacitance involved in modulation is the series value of Ca1 and Ca2, i.e. .

[0045] In the second stage (holding stage), sampling switch S5 is opened, the upper plates of sampling capacitor Cs and first modulation capacitor Ca1 are disconnected from Vin, and quantizer 230 starts comparison.

[0046] In the third stage (quantization stage), sampling switch S5 is opened, and the lower plates of the first modulation capacitors Ca1 and Ca2 maintain the same connection state as in the sampling stage (i.e., maintaining the grounded or series-grounded state under PN control). Simultaneously, the lower plate of the sampling capacitor Cs switches to the reference voltage Vref or ground based on the comparison result. The following derivation uses the common-mode level Vcm as the voltage reference zero point, and all voltage quantities are differences relative to Vcm (i.e., Vin' = Vin). Vcm, Vout' = Vout Therefore, Vcm does not appear explicitly in the derivation process. For simplicity, Vin and Vout will still be used to represent Vin' and Vout' below. According to the law of conservation of charge, the voltage on the upper plate of the sampling capacitor Cs at this time can be expressed as: Vout=Vin-V DAC ; Among them, V DAC The equivalent analog feedback voltage generated by charge redistribution (with Vcm as the reference zero, which has been incorporated into the reference base and is not explicitly shown) is affected by the equivalent capacitance to ground controlled by the PN state and varies between the following two states: If PN is 1, then V DAC It can be represented as: ; If PN is 0, then It can be represented as: ; in, This is the normalized DAC digital output code.

[0047] At the end of the quantization process of the sub-analog-to-digital converter 200, the residual voltage Vout of the upper plate of the sampling capacitor Cs approaches the common-mode level Vcm (approaching 0 in a coordinate system with Vcm as the reference zero), that is... By reorganizing the above formulas, we can obtain the final output numeric code. The relationship with the input signal Vin is as follows: ; in, This represents the equivalent value of the modulation capacitor in the PN state. Therefore, it can be seen that changing the value of PN changes... The magnitude of this effectively alters the conversion from the analog input signal Vin to the digital output code. The overall conversion gain. This perfectly achieves equivalent gain modulation controlled by the PN sequence without changing the physical gain of the input buffer and front-end amplifier, satisfying the theoretical requirements of the subsequent input signal-independent offset calibration algorithm. When PN is 1, the equivalent capacitance involved in modulation is When PN is 0, the equivalent capacitance involved in modulation is the series value of Ca1 and Ca2, that is... .

[0048] The upper plate gain modulation module 210 proposed in this application can group, accumulate, and average the original digital output according to the PN state with the subsequent digital calibration engine 300 to obtain the output average value under different PN states, thereby extracting the offset error of the sub-ADC and completing the offset calibration.

[0049] It should be noted that, for ease of explanation and logical derivation, the accompanying drawings and embodiments of this application are mainly shown with a single-ended circuit structure. In actual high-speed, high-precision analog-to-digital converter chip design, the upper plate gain modulation module 210 proposed in this application is also, and more preferably, applicable to a fully differential architecture.

[0050] In the fully differential embodiment, it is only necessary to arrange the above-mentioned single-ended sampling capacitor array and switching network symmetrically and connect them to the non-inverting input terminal of the differential signal respectively. ) and negative input terminal ( Simultaneously, the switching networks at both ends are synchronously and symmetrically controlled by the same set of pseudo-random sequences (PN) and their control logic. In this way, not only can an equivalent gain modulation and charge redistribution mechanism completely consistent with the single-ended structure be achieved, but common-mode noise and even-order harmonic distortion can also be effectively suppressed.

[0051] In some embodiments of this application, such as Figure 4 As shown, the digital calibration engine 300 includes an offset detection module 310, an offset calibration module 320, and a gain demodulation module 330. The offset detection module 310 is used to detect the offset error (OS) of the quantization signal of the sub-analog-to-digital converter 200. The offset calibration module 320 is used to perform offset calibration on the quantization signal (Dout_raw) of the sub-analog-to-digital converter 200 according to the offset error. The gain demodulation module 330 is used to perform gain demodulation on the offset-calibrated quantization signal and output a digital signal (Dout_cal).

[0052] It should be noted that after the input signal Vin enters each sub-analog-to-digital converter 200, it first passes through the upper plate gain modulation module 210 driven by the PN sequence. The upper plate gain modulation module 210 randomly changes the overall gain of the sub-analog-to-digital converter 200 according to the current PN value, thereby achieving random modulation of the input signal. The modulated analog signal is quantized by the quantizer 230 in the sub-ADC, outputting a quantized signal (Dout_raw), which is then transmitted to the digital calibration engine 300. In the digital calibration engine 300, the offset detection module 310 uses the quantized signal and the corresponding PN sequence to perform operations (such as correlation detection) to accurately extract the offset error (OS) of that channel. Subsequently, the offset calibration module 320 performs a subtraction operation, subtracting the offset error OS from Dout_raw, completing the preliminary calibration of the offset mismatch. The signal after offset calibration enters the gain demodulation module 330, which performs inverse demodulation on the signal according to the corresponding PN value to eliminate the influence of the previously introduced random gain changes on the signal linearity and modulation noise, finally obtaining the calibrated high-precision digital signal (Dout_cal).

[0053] like Figure 4 As shown, in some embodiments of this application, the offset detection module 310 includes a first shunt component and a second shunt component connected in parallel. The first shunt component includes a first multiplier 311, a first accumulator 312, and a first averager 313 connected in sequence. The second shunt component includes a second multiplier 314, a second accumulator 315, a second averager 316, and a third multiplier 317 connected in sequence. The input of the first multiplier 311 is connected to a quantized signal (Dout_raw) and a pseudo-random sequence (PN), respectively. The input of the second multiplier 314 is connected to the quantized signal (Dout_raw) and the inverted signal of the pseudo-random sequence (PN), respectively. The third multiplier 317 is connected to the output of the second averager 316 and a preset modulation gain ratio (α). The offset detection module 310 also includes a first subtractor 318 and a fourth multiplier 319. The input of the first subtractor 318 is connected to the output of the first averager 313 and the third multiplier 317, respectively. The input of the fourth multiplier 319 is connected to the output of the first subtractor 318 and a preset scaling factor (α). / (1-α)), the output of the fourth multiplier 319 is used to output the offset error (OS).

[0054] Specifically, in the upper plate type gain modulation module 210, α is the ratio of the conversion gain in the two states of PN=1 and PN=0, that is, α is the gain when PN=1. With PN=0 The ratio, as shown above, indicates that when PN is 1, the equivalent capacitance involved in modulation is... When PN is 0, the equivalent capacitance involved in modulation is Ca1 and The concatenation value, i.e. Therefore, the value of α is (Cs+Ca1) / (Cs+Ca1·Ca2 / (Ca1+Ca2)). The quantized signal (Dout_raw) output from the sub-analog-to-digital converter 200 enters the digital calibration engine and is then split according to the corresponding PN value. When PN=1, =0. At this time, the quantized signal entering the second shunt component becomes 0 after passing through the second multiplier 314 and is discarded. The quantized signal entering the first shunt component passes through the first multiplier 311 and then enters the first accumulator 312 for accumulation. The average value of these accumulated quantized signals is calculated by the first averager 313. When PN=0, =1. At this time, the quantized signal entering the first splitter component becomes 0 after passing through the first multiplier 311 and is discarded. The quantized signal entering the second splitter component passes through the second multiplier 314 and then enters the second accumulator 315 for accumulation. The average value of these accumulated quantized signals is calculated by the second averager 316. Since the signal component in the output code in the PN=1 state is α times that in the PN=0 state, in order to facilitate the subsequent subtraction of the quantized signals of PN=1 and PN=0, the average value calculated by the second averager 316 is multiplied by α by the third multiplier 317. Finally, the average value obtained by the first averager 313 is subtracted from the output result of the third multiplier 317 by the first subtractor 318, and the difference is then multiplied by the scaling factor by the fourth multiplier 319. The offset error (OS) can be calculated by multiplying the average value of the pseudo-random sequence (PN) and the input signal (Vin) by (1-α). In this process, the influence of Vin on the average value obtained by the two averagers is eliminated by utilizing the statistically uncorrelated property of the pseudo-random sequence (PN) and the input signal (Vin). At the same time, the system performs calculations on the average values ​​of the two channels to extract the offset error: the cumulative average value of Dout_raw (PN=0) is multiplied by the coefficient α, and then the difference operation (i.e., subtraction) is performed with the cumulative average value of Dout_raw (PN=1). The difference result is further multiplied by the scaling factor 1 / (1-α) to calculate the accurate offset error (OS) of the channel.

[0055] like Figure 4 As shown, in some embodiments of this application, the offset calibration module 320 includes a second subtractor. The input of the second subtractor is connected to the quantization signal (Dout_raw) and the offset error (OS), respectively. The second subtractor is used to subtract the quantization signal and the offset error to obtain the offset calibration result. By subtracting the calculated offset error OS from the quantization signal by the offset calibration module 320, the offset mismatch caused by the offset error in the channel can be eliminated.

[0056] The gain demodulation module 330 includes a multiplexer 331 and a fifth multiplier 332. The multiplexer 331 selects the corresponding gain recovery coefficient (1 or 1 / α) based on the pseudo-random sequence (PN). The input of the fifth multiplier 332 is connected to the output of the second subtractor and the multiplexer 331, respectively. The fifth multiplier 332 multiplies the offset calibration result with the gain recovery coefficient to obtain the digital signal. Specifically, in the gain demodulation module 330, the multiplexer selects the corresponding gain recovery coefficient based on the current PN value: when PN=1, the gain recovery coefficient is 1 / α; when PN=0, the gain recovery coefficient is 1. By multiplying the offset calibration result with the gain recovery coefficient, inverse gain demodulation is completed. Through the digital calibration engine 300, the final output digital signal is free from the effects of offset error and gain modulation, resulting in a high-precision digital signal (Dout_cal).

[0057] Compared with existing schemes that achieve random gain modulation by changing the input buffer or front-end amplifier gain, the upper plate sampling offset calibration circuit according to the embodiments of this application has the following advantages: 1. Avoiding dynamic gain switching of the input buffer: This application achieves equivalent sampling gain modulation by controlling the equivalent capacitance to ground of the upper plate during each sampling process, without dynamically changing the gain state of the input buffer or front-end amplifier. Therefore, this application can avoid the input impedance changes, output impedance changes, and output swing changes caused by the switching of the input buffer between different gain states, reducing the design difficulty of high-speed analog front-end.

[0058] 2. Reduce transient settling error: Input buffer or front-end amplifier gain switching can generate transient responses, requiring time to re-establish a stable output. In high-speed ADCs, the sampling period is extremely short, and incomplete transient settling introduces sampling errors. The gain modulation in this application occurs at the sampling capacitor array level, primarily achieved by switching different numbers of unit capacitors to participate in input sampling, without needing to change the operating state of the input buffer. Therefore, it can reduce the transient settling error caused by dynamic gain switching of the front-end amplifier.

[0059] 3. Maintaining Input Signal-Independent Offset Calibration Capability: The equivalent sampling gain modulation implemented in this application satisfies the fundamental condition that the offset error (i.e., the offset component expressed in additive form in the digital output) of the input signal does not change with the PN state. Therefore, this application can be used in conjunction with input signal-independent offset calibration algorithms. Even if the input signal contains DC components, low-frequency components, silent signals, or periodic signals related to the interleaving frequency, the subsequent digital calibration logic can still extract the offset error using the output data under different modulation states.

[0060] 4. Low analog overhead and user-friendly digital control: This application mainly utilizes existing sampling capacitor arrays and switching networks to achieve gain modulation. Especially in ADC structures that include capacitor sampling, the original capacitor array can be reused, resulting in minimal additional analog hardware overhead. Furthermore, the modulation state in this application is determined by the PN sequence and digital control logic, making it easy to implement in advanced CMOS processes, aligning with the development trend of digital-aided analog design in high-speed ADCs.

[0061] 5. Compatible with upper plate sampling, possessing the advantages of upper plate sampling: The gain modulation method proposed in this application is perfectly compatible with the upper plate sampling architecture. By switching on the lower plate side of the modulation capacitor, the introduction of an additional control switch at the upper plate (common sampling node), which serves as the charge convergence node, is avoided, thereby ensuring the stability of the sensitive node.

[0062] Therefore, this invention, while achieving random gain modulation, fully retains the inherent advantages of the upper plate sampling architecture in ultra-high-speed time-interleaved analog-to-digital converters (TI ADCs): Maintaining extremely high timing efficiency: After sampling, there is no need to consume additional clock phase to switch the capacitor base plate. The comparator can directly make the decision on the most significant bit (MSB) with "zero delay", which greatly shortens the quantization cycle.

[0063] Maintaining lower input parasitic capacitance: Avoiding the parasitic capacitance caused by the large lower plate wiring network, significantly reducing the capacitive load and drive burden of the front-end buffer.

[0064] Ensuring ultra-wideband input bandwidth: The number of series switches in the signal path is small, and the signal routing is direct, which meets the stringent requirements of ultra-high-speed ADCs for extremely high analog bandwidth.

[0065] Ensures better interleaved routing symmetry: It is easier to achieve high symmetry in multi-channel clock distribution and signal network layout, effectively suppressing timing mismatch between TI ADC channels.

[0066] This enables the present invention to achieve input signal-independent background offset calibration without sacrificing the dynamic performance and timing efficiency of the ultra-high-speed ADC front end.

[0067] In summary, this application implements a low-distortion, low-overhead, and easily digitally controllable random gain modulation method. This method can provide stable and reliable front-end modulation conditions for input signal-independent offset calibration of time-interleaved analog-to-digital converters, significantly improving the performance stability of high-speed ADC systems under complex input scenarios and long-term operating conditions.

[0068] Secondly, based on the upper plate sampling offset calibration circuit described in the first aspect embodiment, this application also proposes an upper plate sampling offset calibration method, such as... Figure 5 As shown, the method includes the following steps: Step S100: Generate a pseudo-random sequence through the pseudo-random sequence generator 400, and send the pseudo-random sequence to the sub-analog-to-digital converter 200 and the digital calibration engine 300; Step S200: Adjust the sampling gain according to the pseudo-random sequence so that the upper plate gain modulation module 210 samples the input signal according to the adjusted sampling gain; Step S300: The sampled input signal is quantized by quantizer 230 and the quantized signal is output to digital calibration engine 300; Step S400: The digital calibration engine 300 performs offset detection, offset calibration, and gain demodulation on the quantized signal based on the pseudo-random sequence, and outputs a digital signal.

[0069] Specifically, the pseudo-random sequence generator 400 generates a pseudo-random sequence PN, which can be implemented by a linear feedback shift register, a pseudo-random code generator, a random number generator, or other digital sequence generation circuits. The PN sequence is fed into the upper plate gain modulation module 210 in each sub-ADC channel to adjust the sampling gain of the sub-analog-to-digital converter 200. Simultaneously, the PN sequence is also fed into the subsequent digital calibration engine 300 for offset detection, offset calibration, and gain demodulation. For each sub-analog-to-digital converter 200, each includes an upper plate gain modulation module 210, a clock module 220, and a quantizer 230. The PN sequence and the sampling clock jointly control the state of the upper plate gain modulation module 210, causing the input signal to correspond to different equivalent sampling gains under different PN states.

[0070] In some embodiments of this application, such as Figure 2 As shown, the upper plate type gain modulation module 210 includes: a sampling capacitor Cs, a switching network, a first modulation capacitor Ca1, and a second modulation capacitor Ca2; the upper plate of the sampling capacitor Cs is connected to the input signal Vin through a sampling switch S5; the switching network is connected to the lower plate of the sampling capacitor Cs, and the switching network is used to switch the connection of the lower plate of the sampling capacitor Cs to the reference level Vref, the common-mode level Vcm, or ground; the upper plate of the first modulation capacitor Ca1 is connected to the input signal Vin through the sampling switch S5, and the lower plate of the first modulation capacitor Ca1 is grounded through a switching switch S4, and the conduction and disconnection of the switching switch S4 are controlled by a pseudo-random sequence; the upper plate of the second modulation capacitor Ca2 is connected to the lower plate of the first modulation capacitor Ca1, and the lower plate of the second modulation capacitor Ca2 is grounded.

[0071] It should be noted that the sampling capacitor Cs can exist as a single, complete sampling capacitor, or it can be divided into a main sampling capacitor array composed of multiple unit capacitors, such as a binary weighted capacitor array, a segmented capacitor array, or a redundant capacitor array. The upper plates of the sampling capacitor Cs and the first modulation capacitor Ca1 can be connected to the sample-and-hold node, comparator input node, residual signal node, or quantizer input node of the sub-analog-to-digital converter 200. This node is used to provide the sampled analog voltage or charge to the subsequent quantizer 230. The lower plate of the sampling capacitor Cs is selectively connected to the reference level Vref, the common-mode level Vcm, or ground through a switching network. During the sampling phase, the sampling clock provided by the clock module 220 controls the lower plate of the sampling capacitor Cs to be connected to the common-mode level Vcm; during the quantization phase, the lower plate of the sampling capacitor Cs is switched to be connected to the reference level Vref or ground according to the comparison result of the quantizer 230, i.e., controlled by the decision of the quantizer 230.

[0072] In some embodiments of this application, step S200 above, which adjusts the sampling gain according to the pseudo-random sequence so that the upper plate gain modulation module 210 samples the input signal according to the adjusted sampling gain, includes the following steps: Step S210: During the sampling phase, close the sampling switch S5 and control the lower plate of the sampling capacitor Cs to connect to the common-mode level Vcm through the switch switching network; Step S220: When the pseudo-random sequence is 1, control switch S4 is turned on, so that the lower plate of the first modulation capacitor Ca1 is grounded; Step S230: When the pseudo-random sequence is 0, the control switch S4 is turned off, so that the first modulation capacitor Ca1 and the second modulation capacitor Ca2 are connected in series. Step S240: During the holding phase, disconnect the sampling switch S5 and control the lower plate of the sampling capacitor Cs to connect to the common-mode level Vcm through the switch switching network; Step S250: When the pseudo-random sequence is 1, control switch S4 is turned on, so that the lower plate of the first modulation capacitor Ca1 is grounded. Step S260: When the pseudo-random sequence is 0, the control switch S4 is turned off, so that the first modulation capacitor Ca1 and the second modulation capacitor Ca2 are connected in series. Step S270: During the quantization stage, disconnect the sampling switch S5 and control the lower plate of the sampling capacitor Cs to connect to the reference level Vref or ground through the switch switching network; Step S280: When the pseudo-random sequence is 1, control switch S4 is turned on, so that the lower plate of the first modulation capacitor Ca1 is grounded. Step S290: When the pseudo-random sequence is 0, the control switch S4 is turned off, so that the first modulation capacitor Ca1 and the second modulation capacitor Ca2 are connected in series.

[0073] Specifically, such as Figure 2 As shown, the switching network includes a first switch S1, a second switch S2, and a third switch S3. One end of the first switch S1 is connected to the lower plate of the sampling capacitor Cs, and the other end of the first switch S1 is connected to the reference level Vref. One end of the second switch S2 is connected to the lower plate of the sampling capacitor Cs, and the other end of the second switch S2 is connected to the common-mode level Vcm. One end of the third switch S3 is connected to the lower plate of the sampling capacitor Cs, and the other end of the third switch S3 is grounded.

[0074] It should be noted that the PN control logic generates a capacitor selection signal based on the current pseudo-random sequence state, which is used to control the switching state of the switching switch S4 in each sampling period. Figure 3 This diagram illustrates the working state of the PN-controlled upper plate gain modulation module 210 provided in this embodiment of the application. Its workflow includes three stages: In the first stage (sampling stage), sampling switch S5 is closed (the switching state of sampling switch S5 is controlled by the sampling clock provided by clock module 220), the lower plate of sampling capacitor Cs is connected to the common-mode voltage Vcm, and the upper plate is connected to the input signal Vin. The connection state of the first modulation capacitor Ca1 and the second modulation capacitor Ca2 is as follows: If PN is 1, then the lower plate of Ca1 is directly grounded through the switching switch S4, and at the same time, both the upper and lower plates of Ca2 are grounded. If PN is 0, then the lower plate of Ca1 is connected to the upper plate of Ca2, and the lower plate of Ca2 is grounded, thus realizing that Ca1 and Ca2 are connected in series on the lower plate side and then grounded.

[0075] Therefore, the total capacitance of the upper plate to ground varies depending on the PN value: when PN is 1, the equivalent capacitance involved in modulation is Ca1; when PN is 0, the equivalent capacitance involved in modulation is the series value of Ca1 and Ca2, i.e. .

[0076] In the second stage (holding stage), sampling switch S5 is opened, the upper plates of sampling capacitor Cs and first modulation capacitor Ca1 are disconnected from Vin, and quantizer 230 starts comparison.

[0077] In the third stage (quantization stage), sampling switch S5 is opened, and the lower plates of the first modulation capacitors Ca1 and Ca2 maintain the same connection state as in the sampling stage (i.e., maintaining the grounded or series-grounded state under PN control). Simultaneously, the lower plate of the sampling capacitor Cs switches to the reference voltage Vref or ground based on the comparison result. The following derivation uses the common-mode level Vcm as the voltage reference zero point, and all voltage quantities are differences relative to Vcm (i.e., Vin' = Vin). Vcm, Vout' = Vout Therefore, Vcm does not appear explicitly in the derivation process. For simplicity, Vin and Vout will still be used to represent Vin' and Vout' below. According to the law of conservation of charge, the voltage on the upper plate of the sampling capacitor Cs at this time can be expressed as: Vout=Vin-V DAC ; Among them, V DAC The equivalent analog feedback voltage generated by charge redistribution (with Vcm as the reference zero, which has been incorporated into the reference base and is not explicitly shown) is affected by the equivalent capacitance to ground controlled by the PN state and varies between the following two states: If PN is 1, then V DAC It can be represented as: ; If PN is 0, then It can be represented as: ; in, This is the normalized DAC digital output code.

[0078] At the end of the quantization process of the sub-analog-to-digital converter 200, the residual voltage Vout of the upper plate of the sampling capacitor Cs approaches the common-mode level Vcm (approaching 0 in a coordinate system with Vcm as the reference zero), that is... By reorganizing the above formulas, we can obtain the final output numeric code. With input signal The relationship is: ; in, This represents the equivalent value of the modulation capacitor in the PN state. Therefore, it can be seen that changing the value of PN changes... The magnitude of this effectively alters the conversion from the analog input signal Vin to the digital output code. The overall conversion gain. This perfectly achieves equivalent gain modulation controlled by the PN sequence without changing the physical gain of the input buffer and front-end amplifier, satisfying the theoretical requirements of the subsequent input signal-independent offset calibration algorithm. When PN is 1, the equivalent capacitance involved in modulation is When PN is 0, the equivalent capacitance involved in modulation is the series value of Ca1 and Ca2, that is... .

[0079] The upper plate gain modulation module 210 proposed in this application can group, accumulate, and average the original digital output according to the PN state with the subsequent digital calibration engine 300 to obtain the output average value under different PN states, thereby extracting the offset error of the sub-ADC and completing the offset calibration.

[0080] It should be noted that, for ease of explanation and logical derivation, the accompanying drawings and embodiments of this application are mainly shown with a single-ended circuit structure. In actual high-speed, high-precision analog-to-digital converter chip design, the upper plate gain modulation module 210 proposed in this application is also, and more preferably, applicable to a fully differential architecture.

[0081] In the fully differential embodiment, it is only necessary to arrange the above-mentioned single-ended sampling capacitor array and switching network symmetrically and connect them to the non-inverting input terminal of the differential signal respectively. ) and negative input terminal ( Simultaneously, the switching networks at both ends are synchronously and symmetrically controlled by the same set of pseudo-random sequences (PN) and their control logic. In this way, not only can an equivalent gain modulation and charge redistribution mechanism completely consistent with the single-ended structure be achieved, but common-mode noise and even-order harmonic distortion can also be effectively suppressed.

[0082] In some embodiments of this application, offset detection of the quantized signal includes the following steps: Step S410: Input the quantized signal into the first shunt component and the second shunt component respectively; Step S420: Multiply the quantized signal and the pseudo-random sequence using the first multiplier 311 to obtain the first multiplication result; Step S430: Accumulate all the first multiplication results using the first accumulator 312 to obtain the first accumulated result; Step S440: The first average result is obtained by averaging the first accumulated result using the first averager 313; Step S450: Multiply the quantized signal and the inverted signal of the pseudo-random sequence by the second multiplier 314 to obtain the second multiplication result; Step S460: Accumulate all the second multiplication results using the second accumulator 315 to obtain the second accumulated result; Step S470: The second average result is obtained by averaging the second accumulated result using the second averager 316; Step S480: Obtain the preset modulation gain ratio, and multiply the second average result with the modulation gain ratio through the third multiplier 317 to obtain the third multiplication result; Step S490: Subtract the first average result from the third multiplication result using the first subtractor 318 to obtain the difference result; Step S4100: Multiply the difference result by the scaling factor using the fourth multiplier 319 to obtain the offset error.

[0083] Specifically, such as Figure 4 As shown, in some embodiments of this application, the offset detection module 310 includes a first shunt component and a second shunt component connected in parallel. The first shunt component includes a first multiplier 311, a first accumulator 312, and a first averager 313 connected in sequence. The second shunt component includes a second multiplier 314, a second accumulator 315, a second averager 316, and a third multiplier 317 connected in sequence. The input of the first multiplier 311 is connected to a quantized signal (Dout_raw) and a pseudo-random sequence (PN), respectively. The input of the second multiplier 314 is connected to the quantized signal (Dout_raw) and the inverted signal of the pseudo-random sequence (PN), respectively. The input of the third multiplier 317 is connected to the output of the second averager 316 and a preset modulation gain ratio (denoted as α). The offset detection module 310 also includes a first subtractor 318 and a fourth multiplier 319. The input of the first subtractor 318 is connected to the output of the first averager 313 and the third multiplier 317, respectively. The input of the fourth multiplier 319 is connected to the output of the first subtractor 318 and a preset scaling factor (α). / (1-α)), the output of the fourth multiplier 319 is used to output the offset error (OS).

[0084] Specifically, in the upper plate type gain modulation module 210, α is the ratio of the conversion gain in the two states of PN=1 and PN=0, that is, α is the gain when PN=1. With PN=0 The ratio, as shown above, indicates that when PN is 1, the equivalent capacitance involved in modulation is... When PN is 0, the equivalent capacitance involved in modulation is Ca1 and The concatenation value, i.e. Therefore, the value of α is (Cs+Ca1) / (Cs+Ca1·Ca2 / (Ca1+Ca2)). The quantized signal (Dout_raw) output from the sub-analog-to-digital converter 200 enters the digital calibration engine and is then split according to the corresponding PN value. When PN=1, =0. At this time, the quantized signal entering the second shunt component becomes 0 after passing through the second multiplier 314 and is discarded. The quantized signal entering the first shunt component passes through the first multiplier 311 and then enters the first accumulator 312 for accumulation. The average value of these accumulated quantized signals is calculated by the first averager 313. When PN=0, =1. At this time, the quantized signal entering the first splitter component becomes 0 after passing through the first multiplier 311 and is discarded. The quantized signal entering the second splitter component passes through the second multiplier 314 and then enters the second accumulator 315 for accumulation. The average value of these accumulated quantized signals is calculated by the second averager 316. Since the signal component in the output code in the PN=1 state is α times that in the PN=0 state, in order to facilitate the subsequent subtraction of the quantized signals of PN=1 and PN=0, the average value calculated by the second averager 316 is multiplied by α by the third multiplier 317. Finally, the average value obtained by the first averager 313 is subtracted from the output result of the third multiplier 317 by the first subtractor 318, and the difference is then multiplied by the scaling factor by the fourth multiplier 319. The offset error (OS) can be calculated by multiplying the average value of the pseudo-random sequence (PN) and the input signal (Vin) by (1-α). In this process, the influence of Vin on the average value obtained by the two averagers is eliminated by utilizing the statistically uncorrelated property of the pseudo-random sequence (PN) and the input signal (Vin). At the same time, the system performs calculations on the average values ​​of the two channels to extract the offset error: the cumulative average value of Dout_raw (PN=0) is multiplied by the coefficient α, and then the difference operation (i.e., subtraction) is performed with the cumulative average value of Dout_raw (PN=1). The difference result is further multiplied by the scaling factor 1 / (1-α) to calculate the accurate offset error (OS) of the channel.

[0085] like Figure 4 As shown, in some embodiments of this application, the offset calibration module 320 includes a second subtractor. The input of the second subtractor is connected to the quantization signal (Dout_raw) and the offset error (OS), respectively. The second subtractor is used to subtract the quantization signal and the offset error to obtain the offset calibration result. By subtracting the calculated offset error OS from the quantization signal by the offset calibration module 320, the offset mismatch caused by the offset error in the channel can be eliminated.

[0086] The gain demodulation module 330 includes a multiplexer 331 and a fifth multiplier 332. The multiplexer 331 is used to select the corresponding gain recovery coefficient (1 or 1 / α) according to the pseudo-random sequence (PN). The input of the fifth multiplier 332 is connected to the output of the second subtractor and the multiplexer 331, respectively. The fifth multiplier 332 is used to multiply the offset calibration result with the gain recovery coefficient to obtain a digital signal.

[0087] In some embodiments of this application, the following two steps are included when performing gain demodulation on the quantized signal: Step S4110: Select the corresponding gain recovery coefficient according to the pseudo-random sequence using multiplexer 331; Step S4120: Multiply the offset calibration result and the gain recovery coefficient by the fifth multiplier 332 to obtain the digital signal.

[0088] Specifically, in the gain demodulation module 330, the multiplexer selects the corresponding gain recovery coefficient based on the current PN value: when PN=1, the gain recovery coefficient is 1 / α; when PN=0, the gain recovery coefficient is 1. Inverse gain demodulation is completed by multiplying the offset calibration result by the gain recovery coefficient. Through the digital calibration engine 300, the final output digital signal is free from the effects of offset error and gain modulation, resulting in a high-precision digital signal (Dout_cal).

[0089] The upper plate sampling offset calibration method according to the embodiments of this application has the following advantages compared with the existing schemes that achieve random gain modulation by changing the input buffer or front-end amplifier gain: 1. Avoiding dynamic gain switching of the input buffer: This application achieves equivalent sampling gain modulation by controlling the equivalent capacitance to ground of the upper plate during each sampling process, without dynamically changing the gain state of the input buffer or front-end amplifier. Therefore, this application can avoid the input impedance changes, output impedance changes, and output swing changes caused by the switching of the input buffer between different gain states, reducing the design difficulty of high-speed analog front-end.

[0090] 2. Reduce transient settling error: Input buffer or front-end amplifier gain switching can generate transient responses, requiring time to re-establish a stable output. In high-speed ADCs, the sampling period is extremely short, and incomplete transient settling introduces sampling errors. The gain modulation in this application occurs at the sampling capacitor array level, primarily achieved by switching different numbers of unit capacitors to participate in input sampling, without needing to change the operating state of the input buffer. Therefore, it can reduce the transient settling error caused by dynamic gain switching of the front-end amplifier.

[0091] 3. Maintaining Input Signal-Independent Offset Calibration Capability: The equivalent sampling gain modulation implemented in this application satisfies the fundamental condition that the offset error (i.e., the offset component expressed in additive form in the digital output) of the input signal does not change with the PN state. Therefore, this application can be used in conjunction with input signal-independent offset calibration algorithms. Even if the input signal contains DC components, low-frequency components, silent signals, or periodic signals related to the interleaving frequency, the subsequent digital calibration logic can still extract the offset error using the output data under different modulation states.

[0092] 4. Low analog overhead and user-friendly digital control: This application mainly utilizes existing sampling capacitor arrays and switching networks to achieve gain modulation. Especially in ADC structures that include capacitor sampling, the original capacitor array can be reused, resulting in minimal additional analog hardware overhead. Furthermore, the modulation state in this application is determined by the PN sequence and digital control logic, making it easy to implement in advanced CMOS processes, aligning with the development trend of digital-aided analog design in high-speed ADCs.

[0093] 5. Compatible with upper plate sampling, possessing the advantages of upper plate sampling: The gain modulation method proposed in this application is perfectly compatible with the upper plate sampling architecture. By switching on the lower plate side of the modulation capacitor, the introduction of an additional control switch at the upper plate (common sampling node), which serves as the charge convergence node, is avoided, thereby ensuring the stability of the sensitive node.

[0094] Therefore, this invention, while achieving random gain modulation, fully retains the inherent advantages of the upper plate sampling architecture in ultra-high-speed time-interleaved analog-to-digital converters (TI ADCs): Maintaining extremely high timing efficiency: After sampling, there is no need to consume additional clock phase to switch the capacitor base plate. The comparator can directly make the decision on the most significant bit (MSB) with "zero delay", which greatly shortens the quantization cycle.

[0095] Maintaining lower input parasitic capacitance: Avoiding the parasitic capacitance caused by the large lower plate wiring network, significantly reducing the capacitive load and drive burden of the front-end buffer.

[0096] Ensuring ultra-wideband input bandwidth: The number of series switches in the signal path is small, and the signal routing is direct, which meets the stringent requirements of ultra-high-speed ADCs for extremely high analog bandwidth.

[0097] Ensures better interleaved routing symmetry: It is easier to achieve high symmetry in multi-channel clock distribution and signal network layout, effectively suppressing timing mismatch between TI ADC channels.

[0098] This enables the present invention to achieve input signal-independent background offset calibration without sacrificing the dynamic performance and timing efficiency of the ultra-high-speed ADC front end.

[0099] In summary, this application implements a low-distortion, low-overhead, and easily digitally controllable random gain modulation method. This method can provide stable and reliable front-end modulation conditions for input signal-independent offset calibration of time-interleaved analog-to-digital converters, significantly improving the performance stability of high-speed ADC systems under complex input scenarios and long-term operating conditions.

[0100] Thirdly, such as Figure 6 As shown, the present invention also provides a controller, comprising: The processor 101 can be implemented using a general-purpose central processing unit (CPU), microprocessor, application specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of this application. The memory 102 can be implemented as a read-only memory (ROM), static storage device, dynamic storage device, or random access memory (RAM). The memory 102 can store the operating system and other applications. When the technical solutions provided in the embodiments of this specification are implemented through software or firmware, the relevant program code is stored in the memory 102 and called by the processor 101 to execute the upper electrode sampling offset calibration method of the embodiments of this application. Input / output interface 103 is used to implement information input and output; The communication interface 104 is used to enable communication and interaction between this device and other devices. Communication can be achieved through wired means (such as USB, network cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.). Bus 105 transmits information between various components of the device (e.g., processor 101, memory 102, input / output interface 103, and communication interface 104); The processor 101, memory 102, input / output interface 103 and communication interface 104 are connected to each other within the device via bus 105.

[0101] Fourthly, embodiments of this application also provide a storage medium, which is a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described upper plate sampling offset calibration method.

[0102] Memory, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs and non-transitory computer-executable programs. Furthermore, memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, memory may optionally include memory remotely located relative to the processor, and these remote memories can be connected to the processor via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof. The device embodiments described above are merely illustrative, and the units described as separate components may or may not be physically separate, and may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0103] It will be understood by those skilled in the art that all or some of the steps and systems in the methods disclosed above can be implemented as software, firmware, hardware, and suitable combinations thereof. Some or all of the physical components can be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on a computer-readable medium, which can include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and is accessible to a computer. Furthermore, as is known to those skilled in the art, communication media typically include computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0104] The above provides a detailed description of the preferred embodiments of the present invention. However, the present invention is not limited to the above embodiments. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present invention. All such equivalent modifications or substitutions are included within the scope defined by the claims of the present invention.

Claims

1. A sampling offset calibration circuit for upper electrode plates, characterized in that, include: Multiple parallel sub-analog-to-digital converters (ADCs) are provided. The sampling front end of each ADC is equipped with an upper plate gain modulation module. Each ADC is also equipped with a clock module and a quantizer. The upper plate gain modulation module is used to sample the input signal. The quantizer is used to quantize the sampled input signal. The clock module is used to provide a clock signal for the sampling and quantization process of the ADC. Multiple parallel digital calibration engines, each corresponding to a sub-analog-to-digital converter, with each digital calibration engine connected to its corresponding sub-analog-to-digital converter. A pseudo-random sequence generator is connected to the sub-analog-to-digital converter and the digital calibration engine, respectively. The pseudo-random sequence generator is used to generate a pseudo-random sequence and send the pseudo-random sequence to the sub-analog-to-digital converter and the digital calibration engine, so that the upper plate gain modulation module adjusts the sampling gain of the sub-analog-to-digital converter according to the pseudo-random sequence. The digital calibration engine is used to perform offset detection, offset calibration, and gain demodulation on the quantized signal output by the sub-analog-to-digital converter according to the pseudo-random sequence, and output a digital signal. The digital calibration engine includes an offset detection module, an offset calibration module, and a gain demodulation module. The offset detection module is used to detect the offset error of the quantization signal of the sub-analog-to-digital converter. The offset calibration module is used to perform offset calibration on the quantization signal of the sub-analog-to-digital converter according to the offset error. The gain demodulation module is used to perform gain demodulation on the offset-calibrated quantization signal and output the digital signal.

2. The upper plate sampling offset calibration circuit according to claim 1, characterized in that, The upper electrode type gain modulation module includes: A sampling capacitor, wherein the upper plate of the sampling capacitor is connected to the input signal via a sampling switch; A switching network is connected to the lower plate of the sampling capacitor. The switching network is used to switch the connection of the lower plate of the sampling capacitor to a reference level, a common-mode level, or ground. A first modulation capacitor, the upper plate of which is connected to the input signal via the sampling switch, and the lower plate of which is grounded via a switching switch, wherein the switching switch is turned on and off by the pseudo-random sequence. The second modulation capacitor has its upper plate connected to the lower plate of the first modulation capacitor, and its lower plate is grounded.

3. The upper plate sampling offset calibration circuit according to claim 2, characterized in that, The switching network includes: A first switch, one end of which is connected to the lower plate of the sampling capacitor, and the other end of which is connected to the reference level; A second switch, one end of which is connected to the lower plate of the sampling capacitor, and the other end of which is connected to the common-mode level; The third switch has one end connected to the lower plate of the sampling capacitor and the other end grounded.

4. The upper plate sampling offset calibration circuit according to claim 3, characterized in that, The offset detection module includes a first shunt component and a second shunt component connected in parallel. The first shunt component includes a first multiplier, a first accumulator, and a first averager connected in sequence. The second shunt component includes a second multiplier, a second accumulator, a second averager, and a third multiplier connected in sequence. The input terminals of the first multiplier are respectively connected to the quantized signal and the pseudo-random sequence. The input terminals of the second multiplier are respectively connected to the inverted signals of the quantized signal and the pseudo-random sequence. The input terminal of the third multiplier is respectively connected to the output terminal of the second averager and a preset modulation gain ratio. The offset detection module also includes a first subtractor and a fourth multiplier. The input terminals of the first subtractor are respectively connected to the output terminals of the first averager and the third multiplier. The input terminal of the fourth multiplier is respectively connected to the output terminal of the first subtractor and a preset scaling factor. The output terminal of the fourth multiplier is used to output the offset error.

5. The upper plate sampling offset calibration circuit according to claim 4, characterized in that, The offset calibration module includes a second subtractor, the input of which is connected to the quantized signal and the offset error, respectively. The second subtractor is used to subtract the quantized signal and the offset error to obtain the offset calibration result. The gain demodulation module includes a multiplexer and a fifth multiplier. The multiplexer is used to select the corresponding gain recovery coefficient according to the pseudo-random sequence. The input of the fifth multiplier is connected to the output of the second subtractor and the multiplexer, respectively. The fifth multiplier is used to multiply the offset calibration result by the gain recovery coefficient to obtain the digital signal.

6. A method for upper electrode sampling-based offset calibration, characterized in that, Based on the upper plate sampling offset calibration circuit as described in any one of claims 1-5, the method includes: A pseudo-random sequence is generated by the pseudo-random sequence generator, and the pseudo-random sequence is sent to the sub-analog-to-digital converter and the digital calibration engine; The sampling gain is adjusted according to the pseudo-random sequence so that the upper plate gain modulation module samples the input signal according to the adjusted sampling gain; The sampled input signal is quantized by the quantizer, and the quantized signal is output to the digital calibration engine. The digital calibration engine performs offset detection, offset calibration, and gain demodulation on the quantized signal based on the pseudo-random sequence, and outputs a digital signal.

7. The upper plate sampling offset calibration method according to claim 6, characterized in that, The upper plate type gain modulation module includes a sampling capacitor, a switching network, a first modulation capacitor, and a second modulation capacitor. The upper plate of the sampling capacitor is connected to the input signal through a sampling switch. The switching network is connected to the lower plate of the sampling capacitor. The switching network is used to switch the connection of the lower plate of the sampling capacitor to a reference level, a common-mode level, or ground. The upper plate of the first modulation capacitor is connected to the input signal through the sampling switch. The lower plate of the first modulation capacitor is grounded through a switching switch. The switching on and off is controlled by the pseudo-random sequence. The upper plate of the second modulation capacitor is connected to the lower plate of the first modulation capacitor, and the lower plate of the second modulation capacitor is grounded; the pseudo-random sequence includes 0 and 1; The step of adjusting the sampling gain according to the pseudo-random sequence so that the upper plate gain modulation module samples the input signal according to the adjusted sampling gain includes: During the sampling phase, the sampling switch is closed, and the lower plate of the sampling capacitor is connected to the common-mode level through the switch switching network. When the pseudo-random sequence is 1, the switching switch is turned on, so that the lower plate of the first modulation capacitor is grounded. When the pseudo-random sequence is 0, the switching switch is turned off, so that the first modulation capacitor and the second modulation capacitor are connected in series. During the holding phase, the sampling switch is disconnected, and the lower plate of the sampling capacitor is connected to the common-mode level via the switch switching network. When the pseudo-random sequence is 1, the switching switch is turned on, so that the lower plate of the first modulation capacitor is grounded. When the pseudo-random sequence is 0, the switching switch is turned off, so that the first modulation capacitor and the second modulation capacitor are connected in series. During the quantization phase, the sampling switch is disconnected, and the lower plate of the sampling capacitor is connected to the reference level or ground via the switch switching network. When the pseudo-random sequence is 1, the switching switch is turned on, so that the lower plate of the first modulation capacitor is grounded. When the pseudo-random sequence is 0, the switching switch is turned off, so that the first modulation capacitor and the second modulation capacitor are connected in series.

8. The upper plate sampling offset calibration method according to claim 7, characterized in that, The digital calibration engine includes an offset detection module, an offset calibration module, and a gain demodulation module. The offset detection module includes a first shunt component and a second shunt component connected in parallel. The first shunt component includes a first multiplier, a first accumulator, and a first averager connected in sequence. The second shunt component includes a second multiplier, a second accumulator, a second averager, and a third multiplier connected in sequence. The offset detection module also includes a first subtractor and a fourth multiplier. Offset detection of the quantized signal includes: The quantized signal is input to the first shunt component and the second shunt component respectively; The first multiplier multiplies the quantized signal with the pseudo-random sequence to obtain a first multiplication result; The first accumulation result is obtained by accumulating all the first multiplication results using the first accumulator. The first average result is obtained by averaging the first accumulated result using the first averager. The second multiplier multiplies the quantized signal with the inverted signal of the pseudo-random sequence to obtain a second multiplication result. The second accumulator is used to accumulate all the second multiplication results to obtain the second accumulated result; The second average result is obtained by averaging the second accumulated result using the second averager. A preset modulation gain ratio is obtained, and the second average result is multiplied by the modulation gain ratio using the third multiplier to obtain the third multiplication result; The difference result is obtained by subtracting the first average result from the third multiplication result using the first subtractor. The offset error is obtained by multiplying the difference result with the scaling factor using the fourth multiplier.

9. The upper plate sampling offset calibration method according to claim 8, characterized in that, The offset calibration module includes a second subtractor, which is used to subtract the quantized signal and the offset error to obtain the offset calibration result; the gain demodulation module includes a multiplexer and a fifth multiplier, and the gain demodulation includes: The multiplexer selects the corresponding gain recovery coefficient based on the pseudo-random sequence. The offset calibration result is multiplied by the gain recovery coefficient using the fifth multiplier to obtain the digital signal.

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