Gallium oxide-based photoelectric synaptic arrays, their fabrication methods, and imaging methods.

Abstract

This invention provides a gallium oxide-based opto-synaptic array, its fabrication method, and its imaging method. The opto-synaptic array includes an electrode interconnect structure and multiple basic synaptic devices arranged in an array. Each basic synaptic device includes: a gallium oxide substrate; a light-absorbing layer disposed on the surface of the gallium oxide substrate; an interdigitated electrode structure including Schottky contact electrodes and ohmic contact electrodes disposed in different regions on the side of the light-absorbing layer away from the gallium oxide substrate, wherein the Schottky contact electrodes and ohmic contact electrodes form a Schottky junction on the surface of the light-absorbing layer; wherein the fingers of the Schottky contact electrodes and the fingers of the ohmic contact electrodes are arranged alternately, and the distance L between adjacent fingers is the interdigitated spacing, which is determined based on the oxygen vacancy concentration on the surface of the gallium oxide substrate; and an encapsulation layer covering the exposed areas on the light-absorbing layer and the sides of the Schottky contact electrodes and ohmic contact electrodes away from the light-absorbing layer.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and in particular to a gallium oxide-based photoelectric synapse array and its fabrication and imaging methods. Background Technology

[0002] Photosynaptic arrays, based on their unique photoelectric signal conversion and synaptic plasticity simulation capabilities, can simultaneously achieve optical signal detection, information storage, and neuromorphic computation in a single device. They maintain high-efficiency signal processing performance in low-power, high-parallelism intelligent sensing scenarios, and are therefore widely used in intelligent imaging, pattern recognition, and robot vision. However, ambient light in the atmosphere can interfere with imaging; using solar-blind ultraviolet light as a light source can effectively reduce this interference and improve imaging accuracy.

[0003] Gallium oxide (GaO), as an ultra-wide bandgap semiconductor material (4.2-4.9 eV), can precisely respond to ultraviolet light signals, possesses inherent photo-controlled synaptic plasticity, and exhibits excellent thermal stability and carrier mobility adaptability. Furthermore, the oxygen vacancies on GaO possess dynamic modulation characteristics, enabling the simulation of long-term potentiation / inhibition (LTP / LTD) plasticity behaviors in biological synapses, thus achieving brain-like learning functions. Therefore, GaO is an ideal substrate material for constructing opto-synaptic arrays.

[0004] However, existing gallium oxide-based optosynaptic arrays suffer from low oxygen vacancy concentrations on their gallium oxide substrates. This limits the number of oxygen vacancies available to mimic the long-term duration enhancement / inhibition (LTP / LTD) and other plastic behaviors of biological synapses, thus restricting the brain-like learning capabilities of these arrays. Furthermore, existing gallium oxide-based optosynaptic arrays struggle to efficiently erase written signals, hindering the realization of reconfigurable optosynaptic operations. Summary of the Invention

[0005] In view of this, the present invention provides a gallium oxide-based photoelectric synapse array, its fabrication method, and its imaging method.

[0006] One embodiment of the present invention provides a photoelectric synapse array, including an electrode interconnect structure and a plurality of basic synaptic devices arranged in an array. The electrode interconnect structure is electrically connected to each basic synaptic device. Each basic synaptic device includes: a gallium oxide substrate; a light absorption layer disposed on the surface of the gallium oxide substrate; and an interdigitated electrode structure including Schottky contact electrodes and ohmic contact electrodes disposed in different regions on the side of the light absorption layer away from the gallium oxide substrate. The Schottky contact electrodes and the ohmic contact electrodes form a Schottky junction on the surface of the light absorption layer; wherein the fingers of the Schottky contact electrodes are in contact with the ohmic contact electrodes. The fingers of the electrodes are arranged in an interlaced pattern, and the distance L between adjacent fingers is the interdigital spacing. The interdigital spacing is determined according to the oxygen vacancy concentration on the surface of the gallium oxide substrate. When a reverse bias voltage is applied to the interdigital electrode structure, the interdigital electrode structure generates a local electric field with an intensity corresponding to the oxygen vacancy concentration on the surface of the gallium oxide substrate. This ensures that the charge carriers are quickly desorbed from the oxygen vacancy on the surface of the gallium oxide substrate under the action of the local electric field, thereby achieving rapid erasure of the imaging pattern. The encapsulation layer covers the exposed area on the light absorption layer and the Schottky contact electrode and the Ohmic contact electrode on the side away from the light absorption layer, respectively.

[0007] According to an embodiment of the present invention, the gallium oxide substrate is a β-phase gallium oxide single crystal substrate, and the oxygen vacancy concentration on the surface of the gallium oxide substrate is 30%~40%.

[0008] According to an embodiment of the present invention, the Schottky contact electrode is made of Pt or Ni, and the ohmic contact electrode is made of Ti.

[0009] According to an embodiment of the present invention, an isolation layer is provided between adjacent basic synaptic devices in a plurality of basic synaptic devices to prevent signal interference between adjacent basic synaptic devices; the isolation layer covers the side of the gallium oxide substrate and the light absorption layer, the side of the gallium oxide substrate and the light absorption layer covered by the isolation layer is perpendicular to the contact surface of the gallium oxide substrate and the light absorption layer, and the Schottky contact electrode and the Ohmic contact electrode each contact the isolation layer on the side of the light absorption layer closest to the light absorption layer.

[0010] According to an embodiment of the present invention, the electrode interconnect structure includes a plurality of row leads arranged along a first direction and a plurality of column leads arranged along a second direction perpendicular to the first direction. The plurality of row leads are located in a first plane, and the plurality of column leads are located in a second plane that is parallel to and does not coincide with the first plane. Each row lead is electrically connected to a Schottky contact electrode close to itself, and each column lead is electrically connected to an ohmic contact electrode close to itself.

[0011] According to an embodiment of the present invention, a protective layer is provided between the first plane and the second plane to separate multiple row leads and multiple column leads, thereby avoiding electrical crosstalk between the leads.

[0012] According to an embodiment of the present invention, each basic synaptic device has multiple connection holes on its encapsulation layer to expose the electrode interconnect structure.

[0013] Another aspect of this invention provides a method for fabricating a photoelectric synapse array according to any of the above embodiments, comprising:

[0014] S1: Provide a gallium oxide substrate and perform heat treatment on the gallium oxide substrate;

[0015] S2: Multiple photosensitive units distributed in an array are etched on a gallium oxide substrate to form a light absorption layer;

[0016] S3: Facile interdigital electrode structures are fabricated on each photosensitive unit;

[0017] S4: An isolation layer is deposited between adjacent photosensitive units in a plurality of photosensitive units;

[0018] S5: Electrode interconnect structure is fabricated on the isolation layer;

[0019] S6: An encapsulation layer is deposited on the exposed area of ​​the light-absorbing layer and on the side of the interdigitated electrode structure away from the light-absorbing layer.

[0020] Another aspect of the present invention provides an imaging method for a photoelectric synaptic array according to any of the above embodiments, comprising:

[0021] S11: Provides a readout circuit for an external terminal, electrically connecting the electrode interconnection structure in the photosynapse array to the readout circuit;

[0022] S12: Ultraviolet light signals are received through the light absorption layer in the photoelectric synapse array. Oxygen vacancies on the surface of the gallium oxide substrate in the photoelectric synapse array capture charge carriers and convert the light signals into electrical signals.

[0023] S13: The readout circuit outputs an electrical signal to the external terminal, and the external terminal generates an imaging pattern based on the electrical signal.

[0024] According to an embodiment of the present invention, after S13, a reverse bias voltage is applied to the interdigital electrode structure in the photosynaptic array to erase the imaging pattern.

[0025] The photoelectric synaptic array, its fabrication method, and imaging method according to embodiments of the present invention have at least the following beneficial effects:

[0026] (1) By using high-temperature vacuum annealing bulk phase modulation process and low-power oxygen plasma process, more oxygen vacancy defects are introduced on the surface of gallium oxide substrate, so that the oxygen vacancy concentration on the surface of gallium oxide substrate is high, and the brain-like learning function of photoelectric synapse array is not limited due to insufficient oxygen vacancy on the surface of gallium oxide substrate.

[0027] (2) The writing of optical signals and the dynamic control of synaptic weights are achieved through oxygen vacancies on the surface of the gallium oxide substrate. By applying a reverse bias voltage to the interdigital electrode structure, the written optical signals can be quickly erased, ensuring that the device can perform cyclic imaging. The combination of these two methods makes the opto-synaptic array a promising candidate for applications in multiple fields such as next-generation neuromorphic computing, intelligent ultraviolet detection, and efficient human-computer interaction. Attached Figure Description

[0028] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0029] Figure 1 The schematic diagram illustrates a structural schematic of a photoelectric synapse array provided in an embodiment of the present invention;

[0030] Figure 2 The schematic diagram shows a top view of a basic synaptic device in an opto-synaptic array provided by an embodiment of the present invention;

[0031] Figure 3 The illustration schematically shows a side view of a basic synaptic device in an opto-synaptic array according to an embodiment of the present invention;

[0032] Figure 4 The flowchart illustrating a method for fabricating a photoelectric synapse array according to an embodiment of the present invention is shown in the schematic diagram.

[0033] Figure 5 The flowchart illustrates an imaging method for a photoelectric synaptic array provided by an embodiment of the present invention.

[0034] Explanation of reference numerals in the attached figures:

[0035] 1. Basic synaptic device; 11. Gallium oxide substrate; 12. Light absorption layer; 13. Interdigitated electrode structure; 131. Schottky contact electrode; 132. Ohmic contact electrode; 14. Encapsulation layer; 15. Connecting hole; 2. Electrode interconnect structure; 21. Row lead; 22. Column lead; 3. Isolation layer. Detailed Implementation

[0036] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0037] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. The terms “comprising,” “including,” etc., as used herein indicate the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0038] All terms used herein, including technical and scientific terms, have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0039] When using expressions such as "at least one of A, B, and C," the meaning should generally be interpreted according to the understanding of someone skilled in the art. For example, "a system having at least one of A, B, and C" should include, but is not limited to, systems having A alone, having B alone, having C alone, having A and B, having A and C, having B and C, and / or having A, B, and C. Similarly, when using expressions such as "at least one of A, B, or C," the meaning should generally be interpreted according to the understanding of someone skilled in the art. For example, "a system having at least one of A, B, or C" should include, but is not limited to, systems having A alone, having B alone, having C alone, having A and B, having A and C, having B and C, and / or having A, B, and C.

[0040] It should also be noted that the directional terms mentioned in the embodiments, such as "up," "down," "front," "back," "left," and "right," are only for reference to the directions in the accompanying drawings and are not intended to limit the scope of protection of the present invention. Throughout the accompanying drawings, the same elements are represented by the same or similar reference numerals. Conventional structures or constructions will be omitted where they may cause confusion in understanding the present invention.

[0041] like Figures 1-3As shown, this embodiment of the invention provides a photoelectric synapse array, including an electrode interconnect structure 2 and a plurality of basic synaptic devices 1 arranged in an array. The electrode interconnect structure 2 is electrically connected to each basic synaptic device 1. Each basic synaptic device 1 includes: a gallium oxide substrate 11; a light absorption layer 12 disposed on the surface of the gallium oxide substrate 11; and an interdigitated electrode structure 13, including a Schottky contact electrode 131 and an ohmic contact electrode 132 disposed in different regions on the side of the light absorption layer 12 away from the gallium oxide substrate 11. The Schottky contact electrode 131 and the ohmic contact electrode 132 form a Schottky junction on the surface of the light absorption layer 12. In this design, the fingers of the Schottky contact electrode 131 and the fingers of the ohmic contact electrode 132 are arranged alternately, with the spacing L between adjacent fingers being the interdigital spacing. This interdigital spacing is determined based on the oxygen vacancy concentration on the surface of the gallium oxide substrate 11. When a reverse bias voltage is applied to the interdigital electrode structure 13, it generates a local electric field with an intensity corresponding to the oxygen vacancy concentration on the surface of the gallium oxide substrate 11. This ensures that charge carriers are rapidly removed from the oxygen vacancies on the surface of the gallium oxide substrate 11 under the influence of the local electric field, thereby achieving rapid erasure of the imaging pattern. The encapsulation layer 14 covers the exposed area on the light-absorbing layer 12 and the sides of the Schottky contact electrode 131 and the ohmic contact electrode 132 that are away from the light-absorbing layer 12.

[0042] In this embodiment, a large number of oxygen vacancy defects can be formed on the surface of the gallium oxide substrate 11 through a high-temperature vacuum annealing phase modulation process or a low-power oxygen plasma process. These oxygen vacancies can serve as efficient carrier storage and release centers, providing core support for the synaptic function of the device. A light absorption layer 12 is etched on the surface of the gallium oxide substrate 11. When ultraviolet light signals irradiate the light absorption layer 12 of the device, they will be excited to generate electron-hole pairs. At this time, the oxygen vacancies will capture the corresponding carriers and form non-volatile defect states, causing the output current of the device to show a slow decay trend, eventually stabilizing at a specific value (corresponding to the "memory" state of the synaptic weight). This serves as the basis for simulating the plastic behavior of biological synapses, such as long-term potentiation / inhibition (LTP / LTD), enabling the opto-synaptic array to achieve brain-like learning functions.

[0043] The Schottky contact electrode 131 and the Ohmic contact electrode 132 of the interdigitated electrode structure 13 form a Schottky junction on the light absorption layer 12. On the one hand, when the ultraviolet light signal irradiates the light absorption layer 12, the light signal is converted into an electrical signal, and then the interdigitated electrode structure 13 can transmit the converted electrical signal. On the other hand, when it is necessary to erase the memory imaging pattern, a reverse bias voltage is applied to the interdigitated electrode structure 13, which can generate a local electric field on the surface of the gallium oxide substrate 11. This causes the carriers trapped by oxygen vacancies on the surface of the gallium oxide substrate 11 to quickly de-enter, recombine and drift, blocking the continuous photoconductivity effect, thereby realizing the rapid erasure of the imaging pattern and ensuring that the device can perform cyclic imaging.

[0044] It should be noted that the vacancy concentration on the surface of the gallium oxide substrate 11 of this invention is higher than that of conventional substrates. When erasing the imaging pattern remembered by the photosynaptic array, in order to ensure that the carriers trapped in the large number of oxygen vacancies on the surface of the gallium oxide substrate 11 can be quickly removed, it is necessary to ensure that the interdigitated electrode structure 13 can provide a sufficiently strong local electric field. The strength of the local electric field generated by the interdigitated electrode structure 13 is affected by the interdigital spacing; the smaller the interdigital spacing, the stronger the local electric field. Therefore, the interdigital spacing of the interdigitated electrode structure 13 needs to be determined according to the oxygen vacancy concentration on the surface of the gallium oxide substrate 11 to ensure that the local electric field is strong enough. This strong local electric field accelerates the removal of carriers from the large number of oxygen vacancies, achieving rapid image erasure.

[0045] In this embodiment, an isolation layer 3 is provided between adjacent basic synaptic devices 1. The isolation layer 3 covers the sides of the gallium oxide substrate 11 and the light absorption layer 12. The sides of the gallium oxide substrate 11 and the light absorption layer 12 covered by the isolation layer 3 are perpendicular to the contact surface between the gallium oxide substrate 11 and the light absorption layer 12. The Schottky contact electrode 131 and the ohmic contact electrode 132 each have their sides closest to the light absorption layer 12 in contact with the isolation layer 3. The sides of the gallium oxide substrate 11 and the light absorption layer 12 of each basic synaptic device 1 are covered by the isolation layer 3 and isolated from adjacent basic synaptic devices 1, thereby preventing signal interference between adjacent basic synaptic devices 1.

[0046] In this embodiment, the electrode interconnect structure 2 includes a plurality of row leads 21 arranged along a first direction and a plurality of column leads 22 arranged along a second direction perpendicular to the first direction. The plurality of row leads 21 are located in a first plane, and the plurality of column leads 22 are located in a second plane that is parallel to the first plane and does not coincide with it. Each row lead 21 is electrically connected to a Schottky contact electrode 131 adjacent to it, and each column lead 22 is electrically connected to an ohmic contact electrode 132 adjacent to it.

[0047] like Figure 1 As shown, each row lead 21 is in close contact with each adjacent basic synaptic device 1 along a first direction, and the Schottky contact electrodes 131 of these basic synaptic devices 1 make contact with the adjacent row lead 21 to achieve electrical connection. Each column lead 22 is in close contact with each adjacent basic synaptic device 1 along a second direction, and the ohmic contact electrodes 132 of these basic synaptic devices 1 make contact with the adjacent column lead 22 to achieve electrical connection. The row leads 21 and column leads 22 are arranged in a crisscross pattern in the gaps between the basic synaptic devices 1, thereby constructing a regular two-dimensional signal transmission array.

[0048] In this embodiment, a protective layer is provided between the first plane and the second plane to separate multiple row leads 21 and multiple column leads 22, thereby avoiding electrical crosstalk between the leads.

[0049] Specifically, there is a certain gap between the first plane where the row leads 21 are located and the second plane where the column leads 22 are located, so that the row leads 21 and column leads 22 are arranged alternately in space. The protective layer forms an isolation between the first plane and the second plane, so that the row leads 21 and column leads 22 will not come into contact at the positions where they intersect, thereby avoiding short circuits between the row leads 21 and column leads 22 and electrical interference.

[0050] In this embodiment, each basic synaptic device 1 has multiple connection holes 15 on its encapsulation layer 14 to expose the electrode interconnect structure 2.

[0051] In practical use, the photoelectric synapse array of the present invention is equipped with a matching external terminal. The electrode interconnection structure 2 exposed through the connection hole 15 can be electrically connected to the readout circuit of the external terminal, so that the electrical signal converted by the light absorption layer 12 can be transmitted to the external terminal through the electrode interconnection structure 2 and the readout circuit.

[0052] In this embodiment, the gallium oxide substrate 11 is a β-phase gallium oxide single-crystal substrate with an oxygen vacancy concentration of 30%~40% on its surface. Gallium oxide can be grown into large-size single-crystal substrates using a melt method, and large-area array devices can be fabricated using semiconductor micro-nano fabrication processes. The chemical bonds of β-phase gallium oxide have high bond energy and stability, allowing it to maintain stable photoelectric synaptic characteristics in complex environments. The dynamic regulation characteristics of its internal oxygen vacancies can simulate the long-term potentiation / inhibition (LTP / LTD) plasticity of biological synapses, enabling brain-like learning functions. Therefore, using a β-phase gallium oxide single-crystal substrate can both meet the fabrication requirements of large-area array devices and enable the photoelectric synaptic array to possess brain-like learning functions.

[0053] It should be noted that oxygen vacancy defects are a necessary condition for the gallium oxide substrate 11 to realize brain-like learning functions. However, in the practical application of photosynaptic arrays, a sufficient amount of oxygen vacancies is required to ensure the stable operation of brain-like learning functions. Therefore, this invention sets the oxygen vacancy concentration on the surface of the gallium oxide substrate 11 to a high concentration range of 30% to 40%, which can effectively ensure the stable operation of the photosynaptic array's brain-like learning functions.

[0054] In this embodiment, the Schottky contact electrode 131 is made of Pt or Ni, and the ohmic contact electrode 132 is made of Ti. Pt or Ni, with their high work function, readily form Schottky contacts with gallium oxide, thereby creating a high potential barrier and enhancing photoresponse and synaptic weight plasticity. Ti, with its low work function, readily forms ohmic contacts with gallium oxide, thereby creating a low potential barrier, reducing contact resistance, and ensuring linear photocurrent output.

[0055] Based on the photoelectric synaptic array of the above embodiments, the present invention also provides an imaging method for the photoelectric synaptic array. Figure 5 The flowchart illustrates an imaging method for a photoelectric synaptic array provided by an embodiment of the present invention.

[0056] like Figure 5 As shown, the imaging method of the photoelectric synaptic array may include the following steps.

[0057] In step S11, a readout circuit for an external terminal is provided, and the electrode interconnection structure 2 in the photosynapse array is electrically connected to the readout circuit.

[0058] In some embodiments, the external terminal can be a computer paired with a data acquisition card, or a field-programmable gate array (FPGA) development board paired with a display screen. The computer-based data acquisition card solution is easy to debug, offers good flexibility, and allows direct image reconstruction and recognition using Python / MATLAB. The FPGA development board-based display screen solution enables real-time imaging and is suitable for on-site demonstrations.

[0059] In step S12, ultraviolet light signals are received through the light absorption layer 12 in the photoelectric synapse array. Oxygen vacancies on the surface of the gallium oxide substrate 11 in the photoelectric synapse array capture charge carriers and convert the light signals into electrical signals.

[0060] Specifically, when ultraviolet light irradiates the light-absorbing layer 12, it excites the generation of electron-hole pairs. The excited electrons and holes do not recombine immediately; one type of charge carrier (the hole in the synapse) is captured by oxygen vacancies on the surface of the gallium oxide substrate 11, forming a non-volatile defect state. The captured hole acts like a "memory cell" storing positive charge, creating an internal electric field on the surface of the gallium oxide substrate 11, corresponding to the formation of the "memory" of the photosynaptic array.

[0061] During this process, all the holes captured by the oxygen vacancies on the surface of the gallium oxide substrate 11 together form an internal electric field. The electrons that are not captured move directionally under the action of this internal electric field to form a current, thereby realizing the conversion of optical signals into electrical signals.

[0062] In step S13, an electrical signal is output to an external terminal through the readout circuit, and the external terminal generates an imaging pattern based on the electrical signal.

[0063] Specifically, after the readout circuit obtains the current signal at each location, it performs an analog-to-digital signal conversion. The digital signal can then be mapped to grayscale values ​​to obtain the grayscale value of each point. Finally, the external terminal stitches together the grayscale values ​​of each location to generate an imaging pattern.

[0064] The imaging method for the photoelectric synaptic array provided in this embodiment of the invention allows each basic synaptic device 1 in the array to both sense light and convert optical signals into electrical signals, exhibiting highly efficient signal processing performance. Simultaneously, the photoelectric synaptic array can utilize oxygen vacancy defects on the surface of the gallium oxide substrate 11 to form a memory of the optical signals, enabling dynamic adjustment of synaptic weights.

[0065] In this embodiment, after step S13, a reverse bias voltage is applied to the interdigital electrode structure 13 in the photosynaptic array to erase the imaging pattern.

[0066] Specifically, when a reverse bias voltage is applied to the interdigital electrode structure 13 in the photoelectric synapse array, a local electric field can be generated on the surface of the gallium oxide substrate 11, which causes the carriers trapped by oxygen vacancies on the surface of the gallium oxide substrate 11 to quickly de-enter, recombine and drift, blocking the continuous photoconductive effect, thereby realizing the rapid erasure of the imaging pattern and ensuring that the device can perform cyclic imaging.

[0067] In some embodiments, key parameters such as the intensity and irradiation area of ​​the input ultraviolet light source are precisely modulated so that the ultraviolet light signal emitted by the input ultraviolet light source has a corresponding target imaging pattern. Then, the photoelectric synapse array is irradiated with the ultraviolet light signal generated by the modulated input ultraviolet light source to generate an imaging pattern. The imaging pattern is then compared with the target imaging pattern to test and analyze the imaging accuracy of the photoelectric synapse array.

[0068] Based on the photoelectric synapse array of the above embodiments, the present invention also provides a method for fabricating a photoelectric synapse array. Figure 4 The flowchart illustrating a method for fabricating a photoelectric synapse array according to an embodiment of the present invention is shown.

[0069] like Figure 4 As shown, the fabrication method of the photoelectric synapse array may include the following steps.

[0070] In step S1, a gallium oxide substrate 11 is provided, and the gallium oxide substrate 11 is subjected to heat treatment.

[0071] In some embodiments, a high-temperature vacuum annealing bulk phase modulation process is used to heat-treat the gallium oxide substrate 11. Specifically, the gallium oxide substrate 11 is vacuum-held at 700-800°C for 30-60 minutes, thereby introducing a large number of oxygen vacancy defects on the surface of the gallium oxide substrate 11 and increasing the oxygen vacancy concentration on the surface of the gallium oxide substrate 11.

[0072] In some embodiments, for gallium oxide substrates that have undergone high-temperature vacuum annealing phase modulation processes, if it is necessary to further enrich the oxygen vacancies on their surface, a low-power oxygen plasma process can be used as an auxiliary method. Specifically, treating the gallium oxide substrate 11 at a power of 10-50W for 5-15 minutes can precisely optimize the oxygen vacancy defects on the surface of the gallium oxide substrate 11, thereby further enriching the oxygen vacancies on the surface of the gallium oxide substrate 11.

[0073] In step S2, multiple photosensitive units distributed in an array are etched on the gallium oxide substrate 11 to form a light absorption layer 12.

[0074] In some embodiments, the gallium oxide substrate 11 is etched using an inductively coupled plasma (ICP) process, and then the surface of the light absorption layer 12 formed by the etching can be repaired using chemical reagents to reduce etching damage to the surface of the light absorption layer 12.

[0075] In step S3, an interdigitated electrode structure 13 is fabricated on each photosensitive unit.

[0076] In some embodiments, an electron beam evaporation process is used to fabricate a Schottky contact electrode 131 on each photosensitive unit using Pt or Ni as the material, and an ohmic contact electrode 132 on each photosensitive unit using Ti as the material, thereby forming a corresponding interdigitated electrode structure 13 on each photosensitive unit.

[0077] In step S4, an isolation layer 3 is deposited between adjacent photosensitive units in the plurality of photosensitive units.

[0078] In some embodiments, silicon oxide is used as the deposition material to deposit an isolation layer 3 between adjacent photosensitive units in a plurality of photosensitive units, which can avoid signal interference between adjacent photosensitive units.

[0079] In step S5, an electrode interconnect structure 2 is fabricated on the isolation layer 3.

[0080] In some embodiments, a combination of ultraviolet lithography and metal deposition is first used to fabricate a plurality of row leads 21 arranged along a first direction on the isolation layer 3, so that each row lead 21 contacts the Schottky contact electrode 131 of the interdigital electrode structure 13 closest to it to achieve electrical connection. Then, silicon oxide is deposited on each row lead 21 to form a protective layer to separate the row leads 21 and column leads 22 and prevent short circuits between the row leads 21 and column leads 22 from causing electrical interference. Finally, a combination of ultraviolet lithography and metal deposition is used to fabricate a plurality of column leads 22 arranged along a second direction perpendicular to the first direction on the isolation layer 3, so that each column lead 22 contacts the ohmic contact electrode 132 of the interdigital electrode structure 13 closest to it to achieve electrical connection, thus completing the fabrication of the electrode interconnect structure 2.

[0081] It should be noted that when fabricating multiple row leads 21 arranged along the first direction on the isolation layer 3, the photolithography depth of the isolation layer 3 is relatively deep. When fabricating multiple column leads 22 arranged along a second direction perpendicular to the first direction on the isolation layer 3, the photolithography depth of the isolation layer 3 is relatively shallow. This photolithography method ensures that the row leads 21 and column leads 22 are located on two different planes, thereby ensuring that the row leads 21 and column leads 22 can be arranged in a crisscross pattern.

[0082] In step S6, an encapsulation layer 14 is deposited on the exposed area of ​​the light-absorbing layer 12 and on the side of the interdigitated electrode structure 13 away from the light-absorbing layer 12.

[0083] In some embodiments, silicon oxide is used as the deposition material, wherein an encapsulation layer 14 is deposited on the exposed areas of the light absorption layer 12 not covered by the Schottky contact electrode 131 and the ohmic contact electrode 132, and on the side of the Schottky contact electrode 131 and the ohmic contact electrode 132 away from the light absorption layer 12, thereby achieving physical protection and environmental isolation for the entire opto-synaptic array.

[0084] It should be noted that the encapsulation layer 14 should have connection holes 15 to expose the electrode interconnect structure 2 so that the electrode interconnect structure 2 can be electrically connected to the readout circuit.

[0085] The method for fabricating photoelectric synapse arrays provided in this invention uses semiconductor micro-nano technology to integrate processes such as high-temperature vacuum annealing for bulk phase modulation and modification, ICP etching for array formation, and electron beam evaporation for electrode fabrication. The entire process chain is simple and controllable, which greatly reduces the fabrication difficulty and helps to achieve mass production of large-scale devices.

[0086] The embodiments of the present invention have been described above. However, these embodiments are merely illustrative and not intended to limit the scope of the invention. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. The scope of the invention is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of the invention, and all such substitutions and modifications should fall within the scope of the invention.

Claims

1. A photoelectric synapse array, characterized in that, The device includes an electrode interconnection structure (2) and a plurality of basic synaptic devices (1) arranged in an array. The electrode interconnection structure (2) is electrically connected to each of the basic synaptic devices (1). Each basic synaptic device (1) includes: Gallium oxide substrate (11); A light-absorbing layer (12) is disposed on the surface of the gallium oxide substrate (11); The interdigitated electrode structure (13) includes a Schottky contact electrode (131) and an ohmic contact electrode (132) disposed in different regions on the side of the light absorption layer (12) away from the gallium oxide substrate (11), wherein the Schottky contact electrode (131) and the ohmic contact electrode (132) form a Schottky junction on the surface of the light absorption layer (12); The fingers of the Schottky contact electrode (131) and the fingers of the Ohmic contact electrode (132) are arranged alternately, and the distance L between adjacent fingers is the interdigitated distance. The interdigitated distance is determined according to the oxygen vacancy concentration on the surface of the gallium oxide substrate (11). When a reverse bias voltage is applied to the interdigitated electrode structure (13), the interdigitated electrode structure (13) generates a local electric field with an intensity corresponding to the oxygen vacancy concentration on the surface of the gallium oxide substrate (11), ensuring that the charge carriers are quickly removed from the oxygen vacancy on the surface of the gallium oxide substrate (11) under the action of the local electric field, thereby realizing the rapid erasure of the imaging pattern. An encapsulation layer (14) covers the exposed area on the light-absorbing layer (12) and the Schottky contact electrode (131) and the ohmic contact electrode (132) on the side away from the light-absorbing layer (12).

2. The photoelectric synapse array according to claim 1, characterized in that, The gallium oxide substrate (11) is a β-phase gallium oxide single crystal substrate, and the oxygen vacancy concentration on the surface of the gallium oxide substrate (11) is 30%~40%.

3. The photosynaptic array according to claim 1, characterized in that, The Schottky contact electrode (131) is made of Pt or Ni, and the ohmic contact electrode (132) is made of Ti.

4. The photoelectric synapse array according to claim 1, characterized in that, An isolation layer (3) is provided between adjacent basic synaptic devices (1) to prevent signal interference between adjacent basic synaptic devices; The isolation layer (3) covers the side of the gallium oxide substrate (11) and the light absorption layer (12). The side of the gallium oxide substrate (11) and the light absorption layer (12) covered by the isolation layer (3) is perpendicular to the contact surface of the gallium oxide substrate (11) and the light absorption layer (12). The Schottky contact electrode (131) and the Ohmic contact electrode (132) are respectively in contact with the isolation layer (3) on the side of the light absorption layer (12) close to the light absorption layer (12).

5. The photoelectric synapse array according to claim 1, characterized in that, The electrode interconnect structure (2) includes a plurality of row leads (21) arranged along a first direction and a plurality of column leads (22) arranged along a second direction perpendicular to the first direction. The plurality of row leads (21) are located in a first plane, and the plurality of column leads (22) are located in a second plane that is parallel to and does not coincide with the first plane. Each of the row leads (21) is electrically connected to each of the Schottky contact electrodes (131) adjacent to itself, and each of the column leads (22) is electrically connected to each of the ohmic contact electrodes (132) adjacent to itself.

6. The photoelectric synapse array according to claim 5, characterized in that, A protective layer is provided between the first plane and the second plane to separate the plurality of row leads (21) and the plurality of column leads (22), thereby avoiding electrical crosstalk between the leads.

7. The photosynaptic array according to claim 1, characterized in that, Each of the basic synaptic devices (1) has a plurality of connection holes (15) on its encapsulation layer (14) for exposing the electrode interconnect structure (2).

8. A method for fabricating a photoelectric synapse array, characterized in that, include: S1: Provide a gallium oxide substrate (11) and perform heat treatment on the gallium oxide substrate (11); S2: Multiple photosensitive units distributed in an array are etched on the gallium oxide substrate (11) to form a light absorption layer (12). S3: An interdigitated electrode structure (13) is fabricated on each of the photosensitive units; S4: An isolation layer (3) is deposited between adjacent photosensitive units in the plurality of photosensitive units; S5: An electrode interconnect structure (2) is fabricated on the isolation layer (3); S6: An encapsulation layer is deposited on the exposed area of ​​the light-absorbing layer (12) and on the side of the interdigitated electrode structure (13) away from the light-absorbing layer (12).

9. An imaging method using the photoelectric synaptic array according to any one of claims 1-7, characterized in that, include: S11: Provide a readout circuit for an external terminal, electrically connecting the electrode interconnection structure (2) in the photoelectric synapse array to the readout circuit; S12: Ultraviolet light signal is received through the light absorption layer (12) in the photoelectric synapse array. Oxygen vacancies on the surface of the gallium oxide substrate (11) in the photoelectric synapse array capture charge carriers and convert the light signal into an electrical signal. S13: The electrical signal is output to the external terminal through the readout circuit, and the external terminal generates an imaging pattern based on the electrical signal.

10. The imaging method for a photoelectric synaptic array according to claim 9, characterized in that, The imaging method further includes: After S13, a reverse bias voltage is applied to the interdigital electrode structure (13) in the photosynaptic array to erase the imaging pattern.

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