Power management chip dynamic timing control method and system based on multi-circuit integration

Abstract

The application provides a power management chip dynamic timing control method and system based on multi-circuit integration, and relates to the technical field of power management. The application collects core voltage change signals, load current change rates and historical recovery times, uses a load prediction model to predict a load change time and determine a pre-charging time window, controls a power switch device to enter a switching transition stage within the time window, injects a pre-charging current into an output capacitor to form a reserved voltage, adjusts a buck circuit switching duty cycle in combination with the prediction time, the reserved voltage and the load current change rate, and dynamically compensates the switching duty cycle and updates the load prediction model according to a core voltage error sequence after the load actually changes, so that pre-charging and duty cycle adjustment before load change and voltage deviation correction after load change can be realized, and the load response capability and core voltage output stability are improved.

Description

Technical Field

[0001] This application relates to the field of power management technology, and in particular to a dynamic timing control method and system for a power management chip based on multi-circuit integration. Background Technology

[0002] Power management chips are core components of electronic devices. Dynamic timing control methods directly affect their power supply stability and energy efficiency, and they have broad application prospects in fields such as smartphones, servers, and industrial control. As electronic devices develop towards higher performance and miniaturization, the requirements for the dynamic response speed and voltage stability of power management chips are constantly increasing.

[0003] Currently, existing dynamic timing control methods for power management chips based on multi-circuit integration mostly employ the approach of monitoring load changes and then adjusting circuit parameters. This involves regulating the switch duty cycle or current output through feedback loops to adapt to load fluctuations. Some solutions introduce simple load prediction logic, but these primarily rely on single current or voltage signals and lack comprehensive analysis of multi-dimensional characteristics.

[0004] However, these existing methods generally suffer from response lag, making it difficult to predict sudden load changes in advance, leading to voltage drops or overshoots in the core voltage and affecting equipment operational stability. Furthermore, the predictive models lack dynamic update mechanisms, resulting in decreased prediction accuracy over long-term use and an inability to adapt to complex and variable load scenarios. Therefore, existing technologies suffer from insufficient adaptability of power management chips to load changes and poor voltage output stability. Summary of the Invention

[0005] This application provides a dynamic timing control method and system for power management chips based on multi-circuit integration, in order to solve the problems of insufficient adaptability and poor voltage output stability in the prior art.

[0006] In a first aspect, this application provides a dynamic timing control method for a power management chip based on multi-circuit integration, comprising: The core voltage is continuously monitored to generate voltage change signals, and the rate of change of load current is collected; based on the most recent completed load change process, the historical recovery time of the load current from deviating from the steady state to returning to the steady state is determined to generate current change signals. Based on the current change signal, the historical recovery time, and the voltage change signal, a load prediction model trained on historical load events is used to generate the predicted load change time. Based on the predicted load change time, a pre-charging time window is determined; Within the pre-charge time window, the power switching device is controlled to enter the switching transition stage by generating and applying a gate drive voltage, and the current source is controlled to inject pre-charge current into the output capacitor of the power stage circuit, so that the voltage of the output capacitor is increased within the allowable fluctuation range of the core voltage to form a reserved voltage. Based on the predicted load change time, the reserved voltage, and the rate of change of the load current, adjust the switching duty cycle of the buck circuit; When the core voltage deviates from the target regulated value after the actual load change, the voltage error sequence of the core voltage is collected and the switch duty cycle is dynamically compensated; using the actual load change time as a label, the compensated switch duty cycle and the voltage error sequence are fed back to the load prediction model to update the model parameters of the load prediction model.

[0007] Optionally, controlling the power switching device to enter the switching transition phase and injecting pre-charging current into the output capacitor during the pre-charging time window includes: During the pre-charge time window, the gate drive of the power switching device is controlled to enable the power switching device to enter the switching transition phase. At the beginning of the switching transition phase, the absolute value of the gate drive voltage change rate is monitored. When the absolute value is lower than a first threshold, the corresponding moment is marked as the injection start point. Starting from the injection initiation point, the control current source injects pre-charge current into the output capacitor of the power stage circuit; when the absolute value of the voltage drop slope between the drain and source is less than the second threshold, the absolute value of the drain current change rate is less than the third threshold, and the voltage of the output capacitor reaches the pre-charge target value, the injection of the pre-charge current stops to form the reserved voltage.

[0008] Optionally, controlling the current source to inject pre-charge current into the output capacitor of the power stage circuit from the injection start point includes: Starting from the injection start point, the control current source injects the pre-charge current into the output capacitor of the power stage circuit; Using a sampling frequency determined according to the switching cycle of the power switching device, the voltage value between the drain and source, the drain current value, and the voltage value of the output capacitor are synchronously collected. Based on the voltage and current values ​​obtained from two consecutive samplings, the absolute value of the voltage drop slope and the absolute value of the drain current change rate are determined respectively. The absolute value of the voltage drop slope, the absolute value of the drain current change rate, and the voltage value of the output capacitor are compared with the corresponding threshold or pre-charge target value, respectively. When the absolute value of the voltage drop slope is less than the second threshold, the absolute value of the drain current change rate is less than the third threshold, and the voltage of the output capacitor reaches the pre-charge target value, the current source is controlled to stop injecting the pre-charge current, so that the voltage of the output capacitor increases within the allowable fluctuation range of the core voltage, and the increased voltage forms the reserved voltage.

[0009] Optionally, based on the current change signal, the historical recovery time, and the voltage change signal, a load prediction model trained on historical load events is used to generate the predicted load change time, including: The current change signal is divided into multiple time window segments according to the time series, and the voltage change signal of the core voltage monitored in each time window segment is extracted as the time change feature. The length of the historical recovery time is converted into a time decay coefficient, and combined with the voltage change signal to generate a deviation weighting factor; The time variation feature, the time decay coefficient, and the deviation weighting factor are concatenated to form a fused feature vector; The fused feature vector is input into the load prediction model to generate a probability distribution sequence of load changes; In the probability distribution sequence, the time point corresponding to the probability peak is identified as the initial trigger time of the load change; Load events with the same probability peak rising edge slope and the same time window segment length are selected from historical labeled samples. The time increment is determined based on the average duration from the initial triggering of the selected load event to the completion of the load change. The initial triggering time is added to the time increment to generate the predicted load change time.

[0010] Optionally, based on the predicted load change time, a pre-charging time window is determined, including: The pre-charge duration required to form the reserved voltage is determined based on the output capacitor value of the power stage circuit, the amplitude of the pre-charge current, and the reserved voltage. The end time of the pre-charge time window is determined by subtracting the time margin determined based on the controller command delay and the switching delay of the power switching device from the predicted load change time. The start time of the precharge time window is determined by subtracting the precharge duration from the end time. The pre-charging time window is defined as the time period from the start time to the end time.

[0011] Optionally, adjusting the switching duty cycle of the buck circuit based on the predicted load change time, the reserved voltage, and the rate of change of the load current includes: The expected load current increment is calculated based on the rate of change of the load current at the time when the predicted load change is generated. The available voltage margin of the core voltage is determined based on the reserved voltage, and the duty cycle adjustment amount used to compensate for the load current increment is determined based on the expected load current increment, the available voltage margin, and the output impedance characteristics of the buck circuit. The duty cycle adjustment amount is added to the current switch duty cycle to generate a target switch duty cycle; At the predicted load change time, the switching duty cycle of the buck circuit is set to the target switching duty cycle.

[0012] Optionally, when a voltage change signal is detected in the core voltage after an actual change in load, the switch duty cycle is dynamically compensated, including: When the core voltage is detected to deviate from the corresponding target regulated voltage value and exceed the allowable fluctuation range, dynamic compensation is triggered, and the voltage error sequence of the core voltage relative to the target regulated voltage value is recorded according to the sampling time sequence. The voltage error sequence is input into the proportional-integral-derivative compensation algorithm, and the compensation duty cycle is determined based on the voltage error at each sampling time, the cumulative voltage error, and the voltage error change at adjacent sampling times. The compensated duty cycle is superimposed with the current switching duty cycle to generate a compensated switching duty cycle, thereby restoring the core voltage to the target regulated value.

[0013] Secondly, this application provides a dynamic timing control system based on a multi-circuit integrated power management chip, comprising: The acquisition module is used to continuously monitor the core voltage to generate voltage change signals and acquire the rate of change of load current; it determines the historical recovery time based on the most recent completed load change process to generate current change signals. The prediction module is used to generate predicted load change times based on the current change signal, the historical recovery time, and the voltage change signal, using a load prediction model trained on historical load events. The determination module is used to determine a pre-charging time window based on the predicted load change time. The injection module is used to control the power switching device to enter the switching transition stage within the pre-charging time window, and to control the current source to inject pre-charging current into the output capacitor of the power stage circuit, so that the voltage of the output capacitor is increased within the allowable fluctuation range of the core voltage to form a reserved voltage. An adjustment module is used to adjust the switching duty cycle of the buck circuit based on the predicted load change time, the reserved voltage, and the rate of change of the load current. The feedback module is used to dynamically compensate the switch duty cycle based on the voltage error sequence of the core voltage after the actual load change, and to feed back the compensated switch duty cycle and the voltage error sequence to the load prediction model with the actual load change time as a label, so as to update the model parameters.

[0014] Thirdly, this application provides a computing device, including a processing component and a storage component; the storage component stores one or more computer instructions; the one or more computer instructions are invoked and executed by the processing component to implement a dynamic timing control method for a power management chip based on multi-circuit integration as described in the first aspect above.

[0015] Fourthly, this application provides a computer storage medium storing a computer program, which, when executed by a computer, implements a dynamic timing control method for a power management chip based on multi-circuit integration as described in the first aspect.

[0016] This application collects core voltage change signals, load current change rate, and historical recovery time. The load current change rate reflects the current trend of load change, the core voltage change signal reflects the degree to which the supply voltage is affected by load changes, and the historical recovery time reflects the circuit's recovery characteristics after a load change has occurred. Predicting the timing of load changes based on this information reduces judgment errors caused by controlling solely based on a single current or voltage signal, and advances voltage regulation actions before the actual load change.

[0017] A pre-charging time window is determined before the predicted load change, and within this window, the power switching devices are controlled to enter the switching transition phase. Simultaneously, a pre-charging current is injected into the output capacitor, increasing its voltage within the allowable core voltage fluctuation range. This increases the energy stored in the output capacitor before the load increases, enabling it to provide some transient current when the load increases, thus reducing the initial drop in core voltage during load changes.

[0018] Furthermore, the switching duty cycle of the buck converter is adjusted based on the predicted load change time, reserved voltage, and load current change rate. After the actual load change, the switching duty cycle is dynamically compensated based on the core voltage error sequence. By feeding back the actual load change time and compensation results to the load prediction model, the model parameters can be updated based on the actual control results, reducing the deviation between subsequent prediction times and actual load change times. This shortens the duration of core voltage deviation from the target regulated value, improving the power management chip's response to load changes and the stability of the core voltage output. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 A flowchart of a dynamic timing control method for a power management chip based on multi-circuit integration, provided in this application, is shown. Figure 2 A flowchart illustrating a specific implementation of the dynamic timing control method for a power management chip based on multi-circuit integration provided in this application is shown. Figure 3 A schematic diagram of the structure of a dynamic timing control system based on a multi-circuit integrated power management chip provided in this application is shown. Figure 4 A schematic diagram of the structure of a computing device provided in this application is shown. Detailed Implementation

[0021] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings.

[0022] In some of the processes described in the specification, claims, and accompanying drawings of this application, multiple operations appearing in a specific order are included. However, it should be clearly understood that these operations may not be executed in the order they appear herein, or may be executed in parallel. The operation numbers, such as 101, 102, etc., are merely used to distinguish different operations and do not themselves represent any execution order. Furthermore, these processes may include more or fewer operations, and these operations may be executed sequentially or in parallel. It should be noted that the descriptions such as "first," "second," etc., in this document are used to distinguish different messages, devices, modules, etc., and do not represent a chronological order, nor do they limit "first" and "second" to different types.

[0023] In highly dynamic scenarios such as sudden load changes, existing feedback control schemes typically adjust the output only after detecting load changes. This response delay can cause the core voltage to deviate from the target regulated value. Therefore, it is necessary to determine the timing of regulation before load changes occur and to compensate for voltage errors after the actual load change.

[0024] To address the aforementioned issues, this application proposes a dynamic timing control method for power management chips based on multi-circuit integration. This method uses current voltage and current change information and the historical recovery time of the most recent completed load event to predict the timing of load changes, and controls the power switching devices and current sources to perform pre-charging before this timing. After the actual load change, the duty cycle is adjusted based on continuously collected core voltage errors, and the prediction model is updated with the actual load change timing, thereby reducing the core voltage deviation caused by load changes.

[0025] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0026] Figure 1 This application provides a flowchart of a dynamic timing control method for a power management chip based on multi-circuit integration, as shown in the following embodiment. Figure 1 As shown, this method is executed by the power management chip; The method includes: 101. Continuously monitor the core voltage to generate voltage change signals and collect the rate of change of load current; determine the historical recovery time based on the most recent completed load change process to generate current change signals; The historical recovery time is the duration during which the load current deviates from a steady state and recovers to a steady state during the most recent completed load change process. The current change signal is generated by the rate of change of the current load current and the historical recovery time, and is used to characterize the current change trend and the recovery characteristics of the most recent load event.

[0027] In one specific implementation, the core voltage is acquired by a voltage monitoring module and a voltage change signal is generated. The rate of change of the current load current is acquired by a current detection element. The most recent historical recovery time is read from the record of completed load events and combined with the rate of change of the current load current to generate a current change signal.

[0028] 102. Based on the current change signal, the historical recovery time, and the voltage change signal, generate the predicted load change time using a load prediction model trained on historical load events; Optionally, step 102 may specifically include the following steps: 1021. Divide the current change signal into multiple time window segments according to the time series, and extract the voltage change signal of the core voltage monitored in each time window segment as the time change feature; In this context, a time window segment refers to a series of continuous, non-overlapping or partially overlapping time intervals obtained by truncating a continuous time series signal according to a fixed, preset time length. Temporal variation characteristics refer to the information extracted from these time windows that represents the signal variation patterns within that time interval.

[0029] In one specific implementation, step 1021 is first performed, dividing the current change signal into multiple time window segments according to the time series. Then, the voltage change signal of the core voltage monitored within each time window segment is extracted and used as the time change feature.

[0030] For example, setting the time window length to 10 milliseconds, starting from the beginning of the current change signal, 10-millisecond signal segments are sequentially extracted to obtain multiple consecutive time window segments. For each time window segment, the changes in the core voltage within the corresponding time period are extracted. For example, if the voltage drops from 1.2V to 1.15V and then rises back to 1.18V within a certain 10-millisecond window, these voltage change data are the time change characteristics of that window. The above example is only one example of this application. In practical applications, it can be set according to requirements, and this application does not limit it.

[0031] 1022. Convert the length of the historical recovery time into a time decay coefficient, and combine it with the voltage change signal to generate a deviation weighting factor; The time decay coefficient is used to represent the impact of historical recovery time on the current prediction. The longer the historical recovery time, the smaller the impact. The deviation weighting factor is determined based on the time decay coefficient and the magnitude of the core voltage deviation from the target regulated value within the same time window.

[0032] Next, step 1022 is executed. The current historical recovery time is normalized based on the distribution of recovery times in historical samples to obtain a time decay coefficient. Then, the time decay coefficient is weighted according to the magnitude of voltage deviation from the target regulated value to obtain a deviation weighting factor. The normalization range of the time decay coefficient and the deviation weighting factor is consistent with the feature range used during the training of the load prediction model.

[0033] 1023. The time variation feature, the time decay coefficient, and the deviation weighting factor are concatenated to form a fused feature vector; Among them, the fusion feature vector is a multidimensional data set formed by combining multiple different types of feature information in a certain order.

[0034] Then, the time variation features, time decay coefficient, and deviation weight factor are concatenated according to the feature order used during the training of the load prediction model to form a fused feature vector.

[0035] 1024. Input the fused feature vector into the load prediction model to generate a probability distribution sequence of load changes; The probability distribution sequence is a set of probability values ​​output by the model, arranged in chronological order. Each probability value represents the likelihood of a load change occurring at the corresponding time point. A load prediction model is a pre-trained mathematical model or algorithm used to predict the specific time points at which significant load changes will occur based on input feature data.

[0036] Subsequently, the fused feature vectors are input into the pre-trained load prediction model. After analyzing and calculating the feature vectors, the model generates a probability distribution sequence of load changes.

[0037] The load forecasting model employs a time-series forecasting network capable of outputting the probability of load changes at each time point. Training samples include historical current change signals, historical recovery times, voltage change signals, and the corresponding actual load change times. The output time point containing the actual load change is used as a label, enabling the model to establish a correspondence between the fused feature vector and the load change time. The model outputs a probability distribution sequence corresponding to multiple consecutive future time points, where each probability value represents the probability of a load change occurring at the corresponding time point.

[0038] 1025. In the probability distribution sequence, the time point corresponding to the probability peak is identified as the initial trigger time of the load change; Perform step 1025. In the probability distribution sequence output by step 1024, find the point with the highest probability value, i.e., the probability peak. The corresponding time point is the initial trigger time of the load change. For example, in the probability distribution sequence [0.01, 0.02, 0.05, 0.85, 0.04, 0.02, 0.01], 0.85 is the maximum value, and the corresponding time point is 4ms in the future. Therefore, 4ms in the future is the initial trigger time of the load change.

[0039] 1026. Based on the rising slope of the probability peak and the length of the time window segment, calculate the time increment from the initial triggering time to the completion of the load change, and add the initial triggering time to the time increment to generate the predicted load change time.

[0040] The rising slope refers to the inclination of the curve in the probability distribution sequence from the point where the probability begins to rise significantly until it reaches its peak. The time increment refers to the estimated time required from the start of a load change to the completion of the load change.

[0041] Finally, step 1026 is executed to select load events from the historical labeled samples that have the same probability peak rising edge slope interval and the same time window segment length. The average duration of these load events from initial triggering to completion of load change is taken as the time increment. The initial triggering time is then added to this time increment to obtain the predicted load change time.

[0042] This application achieves early prediction of load changes through multi-dimensional feature fusion and model prediction, providing a reliable basis for the chip to adjust its operating strategy in advance, effectively improving the chip's timeliness and adaptability in response to load fluctuations, and ensuring the stability of chip operation.

[0043] 103. Based on the predicted load change time, determine a pre-charging time window; Optionally, step 103 may specifically include the following steps: 1031. Determine the pre-charging duration required to form the reserved voltage based on the output capacitor value of the power stage circuit, the amplitude of the pre-charging current, and the reserved voltage; The reserved voltage is the amount by which the output capacitor voltage increases relative to its pre-charge value within the allowable fluctuation range of the core voltage. The pre-charge target value is the sum of the output capacitor voltage before pre-charge and the reserved voltage. The pre-charge duration is the time required for the current source to charge the output capacitor with the pre-charge current, causing the output capacitor voltage to reach the pre-charge target value.

[0044] In one specific implementation, step 1031 is first performed to determine the pre-charging duration based on the output capacitor value, the pre-charging current amplitude, and the reserved voltage. The larger the reserved voltage or the larger the output capacitor value, the longer the required duration; the larger the pre-charging current, the shorter the required duration.

[0045] 1032. Subtract the time margin determined based on the controller instruction delay and the power switching device switching delay from the predicted load change time to determine the end time of the pre-charging time window; The pre-charge time window refers to a specific period of time during which the relevant circuits are charged in advance to cope with upcoming load changes. The time margin refers to the extra time allowed to ensure that the pre-charge process can be fully completed before the load change occurs. The end time of the pre-charge time window is the expected completion time of the pre-charge process.

[0046] Next, step 1032 is executed to subtract the time margin from the predicted load change time to obtain the end time of the pre-charging time window. The time margin is determined based on the controller command delay and the switching delay calibration results of the power switching devices.

[0047] 1033. Subtract the pre-charge duration from the end time to determine the start time of the pre-charge time window.

[0048] The pre-charging time window is defined as the time period from the start time to the end time.

[0049] Finally, step 1033 is executed, subtracting the pre-charge duration calculated in step 1031 from the end time of the pre-charge time window determined in step 1032, thus obtaining the start time of the pre-charge time window. Pre-charging will begin at the start time and complete at the end time.

[0050] This application accurately calculates the pre-charging time and combines it with the predicted load change time to rationally determine the start and end times of pre-charging, forming a pre-charging time window that adapts to load change requirements. This design ensures that the output capacitor of the power stage circuit can be charged to the required reserved voltage before the load change occurs, effectively suppressing voltage drops or fluctuations during sudden load changes and improving the stability and reliability of the system power supply.

[0051] 104. During the pre-charge time window, the power switching device is controlled to enter the switching transition stage by generating and applying a gate drive voltage, and the current source is controlled to inject pre-charge current into the output capacitor of the power stage circuit, so that the voltage of the output capacitor is increased within the allowable fluctuation range of the core voltage to form a reserved voltage. In this step, the state of the power switching device is regulated by the gate drive voltage. The switching transition phase is the stage in which the power switching device transitions between the on and off states; during this phase, the current source injects pre-charge current into the output capacitor, and the gate drive and the current source are timed by the power management chip according to the same pre-charge time window.

[0052] The pre-charge current is output from the current source to the output capacitor of the power stage circuit. The reserved voltage is the amount of voltage increase of the output capacitor voltage within the allowable fluctuation range of the core voltage, used to provide voltage margin for subsequent load changes.

[0053] Optionally, such as Figure 2 As shown, step 104 may specifically include the following steps: 1041. During the pre-charge time window, control the gate drive of the power switching device to enable the power switching device to enter the switching transition phase; In one specific implementation, step 1041 is first performed, in which a gate drive voltage is generated and applied to the gate of the power switching device within the pre-charge time window determined in step 103. By adjusting the timing of the voltage application, the power switching device is controlled to enter the switching transition phase.

[0054] 1042. At the beginning of the switching transition phase, monitor the absolute value of the gate drive voltage change rate. When the absolute value is lower than a first threshold, mark the corresponding moment as the injection start point. The monitored object is the absolute value of the rate of change of the gate drive voltage. The first threshold is configured according to the driving characteristics of the power switching device and the upper limit of the sampling noise, and is used to determine that the gate drive has entered the stage of slowing down the change; the moment when this condition is met is taken as the injection start point.

[0055] 1043. Starting from the injection start point, control the current source to inject pre-charge current into the output capacitor of the power stage circuit; when the absolute value of the voltage drop slope between the drain and source is less than the second threshold, the absolute value of the drain current change rate is less than the third threshold, and the voltage of the output capacitor reaches the pre-charge target value, stop injecting the pre-charge current to form the reserved voltage.

[0056] Specifically, step 1043 may include: starting from the injection start point, controlling the current source to inject pre-charge current into the output capacitor; synchronously acquiring the voltage value between the drain and source, the drain current value, and the output capacitor voltage value at a sampling frequency determined according to the switching cycle of the power switching device; stopping the injection when the absolute value of the drain-source voltage drop slope is less than the second threshold, the absolute value of the drain current change rate is less than the third threshold, and the output capacitor voltage reaches the pre-charge target value.

[0057] The second and third thresholds are configured according to the switching characteristics and sampling noise upper limit shown in the datasheet of the power switching device, and are used to determine whether the drain-source voltage and drain current have entered a state of slowing change; at the same time, the condition for charging completion is that the output capacitor voltage reaches the pre-charge target value.

[0058] This application achieves stable formation of the reserved voltage by applying a gate drive voltage to regulate the power switching device within the pre-charge time window, accurately injecting pre-charge current during the switching transition phase, and monitoring voltage and current parameters. This scheme can replenish the output capacitor energy in advance before load changes, effectively resisting voltage surges caused by sudden load changes, reducing voltage fluctuations, ensuring stable core voltage output, and improving the dynamic response performance and reliability of the power conversion system.

[0059] 105. Based on the predicted load change time, the reserved voltage, and the rate of change of the load current, adjust the switching duty cycle of the step-down circuit.

[0060] A buck converter is a power conversion circuit that transforms the input voltage into a lower target output voltage (such as the core voltage). It regulates the output voltage by controlling the ratio of the on-time to off-time of the power switching devices. The switching duty cycle, the ratio of the on-time of the power switching device within one switching cycle to the entire cycle, is a core parameter for controlling the output voltage and current of the buck converter.

[0061] Optionally, step 105 may specifically include the following steps: 1051. Based on the rate of change of the load current at the moment when the predicted load change is generated, the expected load current increment is calculated. The expected load current increment is determined based on the current load current change rate and the time interval between the current moment and the predicted load change moment, and is limited to the rated load range of the buck circuit.

[0062] In one specific implementation, step 1051 is first performed to extract the rate of change data of the load current at the predicted load change time. The expected load current increment is calculated by combining the current value of the load current with the time interval between the predicted load change time and the current time.

[0063] When determining the expected load current increment, the same time unit as the load current change rate is used, and the increment is limited to the rated load range when it exceeds the rated load range of the buck circuit.

[0064] 1052. Determine the available voltage margin of the core voltage based on the reserved voltage, and determine the duty cycle adjustment amount to compensate for the load current increment based on the expected load current increment, the available voltage margin, and the output impedance characteristics of the buck circuit. The output impedance characteristic of the buck circuit refers to the way the output impedance of the buck circuit changes with parameters such as frequency and current, which determines the degree of fluctuation in the output voltage when the load current changes. The duty cycle adjustment amount refers to the value required to adjust the current switch duty cycle to compensate for the impact of the load current increment on the output voltage.

[0065] Next, step 1052 is executed. Based on the expected load current increment and the output impedance characteristics of the buck circuit, the expected voltage change is determined, and the available voltage margin is determined from the core voltage allowable fluctuation range and the reserved voltage. The buck circuit controller converts the expected voltage change that exceeds the available voltage margin into a duty cycle adjustment amount based on the calibration relationship between its input voltage, target regulated voltage value and duty cycle.

[0066] The calibration relationship is determined by the duty cycle response data of the buck circuit controller under different input voltage and load conditions, and the duty cycle adjustment is set within the limit of the controller's allowable range.

[0067] 1053. Add the duty cycle adjustment amount to the current switch duty cycle to generate a target switch duty cycle; The target switching duty cycle refers to the switching duty cycle value that the buck circuit needs to switch to at the predicted load change time in order to cope with the upcoming load change.

[0068] Then, step 1053 is executed, adding the duty cycle adjustment amount to the current switch duty cycle, and limiting the result to the duty cycle range allowed by the buck circuit controller to generate the target switch duty cycle.

[0069] 1054. At the predicted load change time, the switching duty cycle of the step-down circuit is set to the target switching duty cycle.

[0070] Finally, step 1054 is executed to continuously track the current time; when the current time reaches the predicted load change time, the switching duty cycle of the buck circuit is switched to the target switching duty cycle.

[0071] This application achieves early compensation for load changes by accurately calculating the duty cycle adjustment corresponding to the load current increment and synchronously switching to the target switch duty cycle when load changes occur. This solution effectively offsets the impact of load current changes on the output voltage, reduces voltage drop or overshoot, further improves the stability and dynamic response speed of the buck circuit output voltage, and ensures the reliable operation of core components under load fluctuation scenarios.

[0072] 106. When the core voltage deviates from the target regulated value after the actual load change, the voltage error sequence of the core voltage is collected and the switch duty cycle is dynamically compensated; the compensated switch duty cycle and the voltage error sequence are fed back to the load prediction model with the actual load change time as the label, so as to update the model parameters of the load prediction model.

[0073] Dynamic compensation involves adjusting the switching duty cycle based on continuously collected voltage errors when actual load changes cause the core voltage to deviate from the target regulated value. Model parameter updates use the actual load change time as a label, and the voltage error sequence and the corresponding compensated switching duty cycle as feedback features to correct subsequent predictions.

[0074] Optionally, the dynamic compensation in step 106 may specifically include the following steps: 1061. When the core voltage is detected to deviate from the corresponding target regulated voltage value and exceed the allowable fluctuation range, dynamic compensation is triggered, and the voltage error sequence of the core voltage relative to the target regulated voltage value is recorded according to the sampling time sequence. The allowable fluctuation range of the core voltage is determined according to the power supply specifications of the powered chip. The voltage error sequence records the difference between the actual core voltage value and the target regulated voltage value according to the controller's sampling period.

[0075] 1062. Input the voltage error sequence into the proportional-integral-derivative compensation algorithm, and determine the compensation duty cycle based on the voltage error at each sampling time, the cumulative voltage error, and the voltage error change at adjacent sampling times; The proportional-integral-derivative (PID) compensation algorithm processes the voltage error sequence according to the sampling order, determines the compensation duty cycle by using the current voltage error, the cumulative voltage error, and the voltage error changes at adjacent sampling times, and limits the output to the duty cycle range allowed by the buck circuit controller.

[0076] 1063. The compensated duty cycle is superimposed with the current switching duty cycle to generate a compensated switching duty cycle, and the core voltage is restored to the target regulated value.

[0077] The compensated switching duty cycle refers to the final control parameter resulting from the superposition of the current switching duty cycle and the compensated duty cycle. It is used to accurately correct voltage deviations and bring the core voltage back to the target regulated value.

[0078] Finally, step 1063 is executed, which superimposes the compensation duty cycle with the current switching duty cycle of the buck circuit, limits it within the range allowed by the controller, and sends it to the buck circuit to correct the core voltage deviation.

[0079] After dynamic compensation is completed, the actual load change time detected is used as a label, and the error sequence of the compensated switch duty cycle and the voltage after the actual load change is fed back to the load prediction model; the model updates the internal weight parameters according to the error between the prediction time and the actual load change time.

[0080] This application can not only quickly eliminate core voltage deviations caused by sudden load changes and ensure the stability of voltage output, but also continuously optimize the accuracy of the load prediction model through feedback data, improve the system's ability to predict and respond to subsequent load changes, and achieve a synergistic improvement in dynamic response performance and prediction accuracy.

[0081] Figure 3 This application provides a schematic diagram of the structure of a dynamic timing control system based on a multi-circuit integrated power management chip, as shown in the embodiment of the present application. Figure 3 As shown, the system includes: The acquisition module 31 is used to continuously monitor the core voltage to generate a voltage change signal and acquire the rate of change of the load current; it determines the historical recovery time based on the most recent completed load change process to generate a current change signal. Prediction module 32 is used to generate predicted load change times based on the current change signal, the historical recovery time, and the voltage change signal using a load prediction model trained on historical load events. The determination module 33 is used to determine a pre-charging time window based on the predicted load change time. The injection module 34 is used to control the power switching device to enter the switching transition stage within the pre-charging time window, and to control the current source to inject pre-charging current into the output capacitor of the power stage circuit, so that the voltage of the output capacitor is increased within the allowable fluctuation range of the core voltage to form a reserved voltage. The adjustment module 35 is used to adjust the switching duty cycle of the step-down circuit based on the predicted load change time, the reserved voltage, and the rate of change of the load current. Feedback module 36 is used to dynamically compensate the switch duty cycle based on the voltage error sequence of the core voltage after the actual load change, and to feed back the compensated switch duty cycle and the voltage error sequence to the load prediction model with the actual load change time as a label, so as to update the model parameters.

[0082] Figure 3 The aforementioned dynamic timing control system based on a multi-circuit integrated power management chip can execute... Figure 1 The implementation principle and technical effects of the dynamic timing control method for power management chips based on multi-circuit integration described in the illustrated embodiment will not be repeated here. The specific methods by which each module and unit of the dynamic timing control system for power management chips based on multi-circuit integration in the above embodiments are described in detail in the embodiments related to this method, and will not be elaborated upon here.

[0083] In one possible design, Figure 3 The illustrated embodiment of a dynamic timing control system based on a multi-circuit integrated power management chip can be implemented as a computing device, such as... Figure 4 As shown, the computing device may include a storage component 41 and a processing component 42; The storage component 41 stores one or more computer instructions, wherein the one or more computer instructions are invoked and executed by the processing component 42.

[0084] The processing component 42 is used for the above Figure 1 The embodiment describes a dynamic timing control method for power management chips based on multi-circuit integration.

[0085] The processing component 42 may include one or more processors to execute computer instructions to complete all or part of the steps in the above-described method. Alternatively, the processing component may be implemented as one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to perform the above-described method.

[0086] Storage component 41 is configured to store various types of data to support operations at the terminal. The storage component can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0087] Of course, computing devices may also include other components, such as input / output interfaces, display components, communication components, etc.

[0088] Input / output interfaces provide interfaces between processing components and peripheral interface modules, which can be output devices, input devices, etc.

[0089] The communication components are configured to facilitate wired or wireless communication between computing devices and other devices.

[0090] The computing device can be a physical device or an elastic computing host provided by a cloud computing platform. In this case, the computing device can refer to a cloud server, and the aforementioned processing components, storage components, etc., can be basic server resources rented or purchased from the cloud computing platform.

[0091] This application also provides a computer storage medium storing a computer program, which, when executed by a computer, can perform the above-described functions. Figure 1 The embodiment shown illustrates a dynamic timing control method for a power management chip based on multi-circuit integration.

[0092] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A dynamic timing control method for a power management chip based on multi-circuit integration, characterized in that, include: Continuously monitor the core voltage to generate voltage change signals and acquire the rate of change of load current; Based on the most recent completed load change process, determine the historical recovery time of the load current from deviating from the steady state to returning to the steady state, in order to generate a current change signal; Based on the current change signal, the historical recovery time, and the voltage change signal, a load prediction model trained on historical load events is used to generate the predicted load change time. Based on the predicted load change time, a pre-charging time window is determined; Within the pre-charge time window, the power switching device is controlled to enter the switching transition stage by generating and applying a gate drive voltage, and the current source is controlled to inject pre-charge current into the output capacitor of the power stage circuit, so that the voltage of the output capacitor is increased within the allowable fluctuation range of the core voltage to form a reserved voltage. Based on the predicted load change time, the reserved voltage, and the rate of change of the load current, adjust the switching duty cycle of the buck circuit; When the core voltage deviates from the target regulated value after the actual load change, the voltage error sequence of the core voltage is collected and the switch duty cycle is dynamically compensated. Using the actual load change time as a label, the compensated switch duty cycle and the voltage error sequence are fed back to the load prediction model to update the model parameters of the load prediction model.

2. The method according to claim 1, characterized in that, Controlling the power switching device to enter the switching transition phase and injecting pre-charging current into the output capacitor within the pre-charging time window includes: During the pre-charge time window, the gate drive of the power switching device is controlled to enable the power switching device to enter the switching transition phase. At the beginning of the switching transition phase, the absolute value of the gate drive voltage change rate is monitored. When the absolute value is lower than a first threshold, the corresponding moment is marked as the injection start point. Starting from the injection initiation point, the control current source injects pre-charge current into the output capacitor of the power stage circuit; when the absolute value of the voltage drop slope between the drain and source is less than the second threshold, the absolute value of the drain current change rate is less than the third threshold, and the voltage of the output capacitor reaches the pre-charge target value, the injection of the pre-charge current stops to form the reserved voltage.

3. The method according to claim 2, characterized in that, Starting from the injection initiation point, controlling the current source to inject pre-charge current into the output capacitor of the power stage circuit includes: Starting from the injection start point, the control current source injects the pre-charge current into the output capacitor of the power stage circuit; Using a sampling frequency determined according to the switching cycle of the power switching device, the voltage value between the drain and source, the drain current value, and the voltage value of the output capacitor are synchronously collected. Based on the voltage and current values ​​obtained from two consecutive samplings, the absolute value of the voltage drop slope and the absolute value of the drain current change rate are determined respectively. The absolute value of the voltage drop slope, the absolute value of the drain current change rate, and the voltage value of the output capacitor are compared with the corresponding threshold or pre-charge target value, respectively. When the absolute value of the voltage drop slope is less than the second threshold, the absolute value of the drain current change rate is less than the third threshold, and the voltage of the output capacitor reaches the pre-charge target value, the current source is controlled to stop injecting the pre-charge current, so that the voltage of the output capacitor increases within the allowable fluctuation range of the core voltage, and the increased voltage forms the reserved voltage.

4. The method according to claim 1, characterized in that, Based on the current change signal, the historical recovery time, and the voltage change signal, a load prediction model trained on historical load events is used to generate the predicted load change time, including: The current change signal is divided into multiple time window segments according to the time series, and the voltage change signal of the core voltage monitored in each time window segment is extracted as the time change feature. The length of the historical recovery time is converted into a time decay coefficient, and combined with the voltage change signal to generate a deviation weighting factor; The time variation feature, the time decay coefficient, and the deviation weighting factor are concatenated to form a fused feature vector; The fused feature vector is input into the load prediction model to generate a probability distribution sequence of load changes; In the probability distribution sequence, the time point corresponding to the probability peak is identified as the initial trigger time of the load change; Load events with the same probability peak rising edge slope and the same time window segment length are selected from historical labeled samples. The time increment is determined based on the average duration from the initial triggering of the selected load event to the completion of the load change. The initial triggering time is added to the time increment to generate the predicted load change time.

5. The method according to claim 1, characterized in that, Based on the predicted load change time, a pre-charging time window is determined, including: The pre-charge duration required to form the reserved voltage is determined based on the output capacitor value of the power stage circuit, the amplitude of the pre-charge current, and the reserved voltage. The end time of the pre-charge time window is determined by subtracting the time margin determined based on the controller command delay and the switching delay of the power switching device from the predicted load change time. The start time of the precharge time window is determined by subtracting the precharge duration from the end time. The pre-charging time window is defined as the time period from the start time to the end time.

6. The method according to claim 1, characterized in that, Adjusting the switching duty cycle of the buck circuit based on the predicted load change time, the reserved voltage, and the rate of change of the load current includes: The expected load current increment is calculated based on the rate of change of the load current at the time when the predicted load change is generated. The available voltage margin of the core voltage is determined based on the reserved voltage, and the duty cycle adjustment amount used to compensate for the load current increment is determined based on the expected load current increment, the available voltage margin, and the output impedance characteristics of the buck circuit. The duty cycle adjustment amount is added to the current switch duty cycle to generate a target switch duty cycle; At the predicted load change time, the switching duty cycle of the buck circuit is set to the target switching duty cycle.

7. The method according to claim 1, characterized in that, When the core voltage deviates from the target regulated value after an actual change in load, the switch duty cycle is dynamically compensated, including: When the core voltage is detected to deviate from the corresponding target regulated voltage value and exceed the allowable fluctuation range, dynamic compensation is triggered, and the voltage error sequence of the core voltage relative to the target regulated voltage value is recorded according to the sampling time sequence. The voltage error sequence is input into the proportional-integral-derivative compensation algorithm, and the compensation duty cycle is determined based on the voltage error at each sampling time, the cumulative voltage error, and the voltage error change at adjacent sampling times. The compensated duty cycle is superimposed with the current switching duty cycle to generate a compensated switching duty cycle, thereby restoring the core voltage to the target regulated value.

8. A dynamic timing control system based on a multi-circuit integrated power management chip, characterized in that, include: The acquisition module is used to continuously monitor the core voltage to generate voltage change signals and acquire the rate of change of load current; Historical recovery time is determined based on the most recent completed load change process to generate current change signals; The prediction module is used to generate predicted load change times based on the current change signal, the historical recovery time, and the voltage change signal, using a load prediction model trained on historical load events. The determination module is used to determine a pre-charging time window based on the predicted load change time. The injection module is used to control the power switching device to enter the switching transition stage within the pre-charging time window, and to control the current source to inject pre-charging current into the output capacitor of the power stage circuit, so that the voltage of the output capacitor is increased within the allowable fluctuation range of the core voltage to form a reserved voltage. An adjustment module is used to adjust the switching duty cycle of the buck circuit based on the predicted load change time, the reserved voltage, and the rate of change of the load current. The feedback module is used to dynamically compensate the switch duty cycle based on the voltage error sequence of the core voltage after the actual load change, and to feed back the compensated switch duty cycle and the voltage error sequence to the load prediction model with the actual load change time as a label, so as to update the model parameters.

9. A computing device, characterized in that, It includes a processing component and a storage component; the storage component stores one or more computer instructions; the one or more computer instructions are invoked and executed by the processing component to implement the dynamic timing control method for a power management chip based on multi-circuit integration as described in any one of claims 1 to 7.

10. A computer storage medium, characterized in that, The device stores a computer program, which, when executed by a computer, implements a dynamic timing control method for a power management chip based on multi-circuit integration as described in any one of claims 1 to 7.

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