Analog switch multiplexing type driving system for thermal-optic phase shifter array and control method thereof

Abstract

The application discloses a kind of analog switch multiplexing type drive system and control method for thermo-optic phase shifter array, belong to integrated optoelectronic chip drive and control field.System includes digital-analog conversion unit, analog switch array, sample-and-hold circuit array, output buffer drive array, timing control logic unit and channel self-calibration unit.The application realizes the time-sharing multiplexing of small number of digital-analog conversion unit by analog switch array, maintains voltage stable during switch-off by sample-and-hold circuit, and makes intermittent refresh equivalent to continuous driving by the thermal time constant of thermo-optic phase shifter;While introducing dynamic priority scheduling and two-point self-calibration mechanism, significantly reduce hardware size, reduce power consumption and improve consistency without sacrificing accuracy.Can be used for computing reconstruction type spectrometer, optical phased array and other integrated photonics equipment.

Description

Technical Field

[0001] This invention relates to the field of driving and control circuits for integrated optoelectronic chips, and particularly to an analog switch multiplexing driving system and its control method for thermo-optical phase shifter arrays. Background Technology

[0002] Thermo-optic phase shifters are core control components in silicon-based photonic integrated chips. They are achieved by fabricating a metal heating resistor above or around a silicon waveguide. When a driving current flows through the resistor, it generates Joule heating, changing the waveguide temperature. This utilizes the thermo-optic effect of silicon (the refractive index changes with temperature) to control the phase of the optical signal. Due to their advantages such as good process compatibility, wide tuning range, and low insertion loss, thermo-optic phase shifters are widely used in integrated photonic systems such as optical phased arrays, Mach-Zehnder interferometer arrays, optical switch arrays, and computational reconstruction spectrometers.

[0003] As integrated photonics technology advances towards large-scale and high-density applications, the number of thermo-optical phase shifters integrated on a single optical chip is increasing dramatically. For example, optical phased arrays often contain dozens or even hundreds of array element channels, and the on-chip spectral analysis module of computational reconstruction spectrometers also requires large-scale thermo-optical phase shifter arrays to achieve diverse spectral encoding states. Each thermo-optical phase shifter requires an independent analog driving voltage to precisely control its phase shift, which places extremely high demands on the channel density, accuracy, and power consumption of the driving circuit.

[0004] Currently, existing technologies for driving thermo-optical phase shifter arrays can be mainly categorized as follows: Category 1: Independent DAC Parallel Drive Scheme for Each Channel. This scheme configures an independent DAC channel and output buffer for each thermo-optical phase shifter, resulting in simple control logic and independence between channels. However, when the number of channels reaches dozens or even hundreds, multiple DAC chips and a large number of peripheral circuits need to be cascaded, causing the drive circuit size to expand dramatically, far exceeding the size of the optical chip itself. Furthermore, inherent differences in gain error, offset error, and temperature drift between different DAC chips and different channels of the same chip make it difficult to guarantee consistency between channels.

[0005] The second category is voltage regulation schemes based on digital potentiometers. This scheme has a simple structure and low cost, but its resolution is limited, and its output noise and temperature drift performance are not as good as those of precision DACs, making it difficult to meet the requirements of high-precision optical phase control.

[0006] The third type: PWM plus low-pass filter scheme. This scheme requires almost no additional hardware resources, but it has inherent ripple. The residual AC component in the output voltage will cause optical phase jitter. At the same time, the equivalent resolution is limited by the number of bits of the timer, making it difficult to achieve high precision requirements.

[0007] In summary, existing thermo-optical phase shifter array driving solutions generally suffer from problems such as large hardware scale, poor channel consistency, high static power consumption, and lack of optimization design for the thermal inertia characteristics of thermo-optical phase shifters in large-scale application scenarios. How to significantly simplify the hardware architecture, reduce power consumption, and improve channel consistency while ensuring driving accuracy is a technical challenge that urgently needs to be solved in this field. Summary of the Invention

[0008] To address the aforementioned technical problems, this invention provides an analog switch multiplexing drive system and its control method for thermo-optical phase shifter arrays, achieving the goal of driving a large-scale thermo-optical phase shifter array with a small number of high-precision DACs, while ensuring drive accuracy, and realizing miniaturization, low power consumption, and high consistency of the drive circuit.

[0009] To achieve the above objectives, the technical solution of the present invention is as follows: An analog switch-multiplexed drive system for thermo-optical phase shifter arrays includes: The digital-to-analog converter unit is used to receive digital voltage setpoints and output corresponding analog voltage signals. An analog switch array, whose input is connected to the output of the digital-to-analog converter, is used to transmit the analog voltage signal to the corresponding output path in a time-division multiplexing manner under the control of a timing control signal. The sample-and-hold circuit array includes multiple sample-and-hold units that correspond one-to-one with the output paths of the analog switch array. The input terminal of each sample-and-hold unit is connected to the corresponding output path, which is used to store the analog voltage signal during the sampling phase and maintain the output voltage during the holding phase. The output buffer drive array includes multiple output buffers that are connected one-to-one with the output terminals of the multiple sample-and-hold units. The output terminal of each output buffer is used to connect to the corresponding thermo-optical phase shifter load to provide drive current. The timing control logic unit is connected to the digital-to-analog converter unit and the analog switch array, respectively. It is used to generate control signals to control the selection state of the analog switch array and dynamically determine the refresh priority of each channel according to the voltage change of each channel and the time interval since the last refresh.

[0010] The above solution also includes the following: The channel self-calibration unit includes an analog-to-digital converter and a calibration multiplexer. The input of the calibration multiplexer is connected to the output of each of the output buffers, and its output is connected to the input of the analog-to-digital converter. The output of the analog-to-digital converter is connected to the digital-to-analog conversion unit. The channel self-calibration unit is used to sample and measure the actual output voltage of each drive channel during system initialization or idle periods to generate calibration parameters for each channel.

[0011] In the above scheme, the sample-and-hold unit includes: A holding capacitor is provided, one end of which is connected to the output of the analog switch array; A buffer amplifier, the input of which is connected to one end of the holding capacitor, and the output of which serves as the output of the sample-and-hold unit; A discharge reset switch is connected in parallel across the holding capacitor to discharge the holding capacitor under the control of a reset control signal.

[0012] In the above scheme, the timing control logic unit includes: The refresh scheduling state machine is used to maintain the refresh request flags and refresh timers for each channel; The channel priority calculation module is used to calculate the refresh priority of each channel based on the voltage change of each channel and the time interval since the last refresh. The DAC instruction queue is used to cache the voltage setting values ​​to be written to the digital-to-analog converter unit.

[0013] A control method for an analog switch-multiplexed drive system for a thermo-optical phase shifter array, based on the system implementation described above, includes the following steps: S1: The timing control logic unit dynamically determines the refresh priority of each channel based on the voltage change of each channel and the time interval since the last refresh. S2: Allocate time slot resources of digital-to-analog conversion units to the corresponding channels in descending order of refresh priority; S3: During the time slice allocated to the target channel, control the analog switch array to connect the output terminal of the digital-to-analog converter unit to the sample-and-hold unit of the target channel, and charge the holding capacitor in the sample-and-hold unit; S4: After charging is complete, control the analog switch array to disconnect the target channel, so that the sample-and-hold unit enters the holding phase, and the sample-and-hold unit maintains the output voltage until the next refresh.

[0014] In the above scheme, the specific method for dynamically determining the refresh priority of each channel in step S1 is as follows: The channel priority calculation module scans the refresh request flags of all channels. For channels with refresh requests, the urgency of refreshing is comprehensively evaluated based on the following principles: The greater the voltage change, the higher the refresh urgency of the channel; When the voltage changes are similar, the channel with a longer time interval since the last refresh has a higher refresh urgency. The timing control logic unit prioritizes allocating the time slot resources of the digital-to-analog conversion unit to channels with high refresh urgency.

[0015] In the above scheme, the charging time of the capacitor in step S3 satisfies the following condition: ; in, The duration of a single charge of the holding capacitor. The on-resistance of the corresponding switch in the analog switch array is given. The capacitance value of the holding capacitor.

[0016] In the above scheme, the duration of a complete refresh cycle is set to be less than the minimum value of the thermal time constant of each of the thermo-optical phase shifters, so that the phase change caused by voltage fluctuations in the thermo-optical phase shifter during the two refresh intervals is smoothly absorbed by its thermal inertia.

[0017] The above scheme also includes a channel self-calibration step: T1: During system initialization or idle time, control the analog switch array to sequentially connect the output terminals of each channel to the analog-to-digital converter of the channel self-calibration unit; T2: Control the digital-to-analog converter unit to sequentially output the first known voltage value. Second known voltage value The actual output voltage of the corresponding channel is measured using the analog-to-digital converter. and ; T3: Calculate the gain error coefficient of this channel according to the following formula. and offset error coefficient : ; T4: Store the gain error coefficient and offset error coefficient of each channel as calibration parameters in non-volatile memory; T5: During normal operation, the input target voltage value is adjusted according to the calibration parameters. Perform pre-compensation and calculate the pre-compensation setpoint. ,Will The data is written into the digital-to-analog converter to make the actual output voltage approximate the target voltage value.

[0018] In the above scheme, when the system is in an idle state or the target voltage of all channels does not change within a preset time, the timing control logic unit controls the digital-to-analog converter to enter a low-power standby mode and maintains the static bias of the sample-and-hold circuit array and the output buffer drive array.

[0019] Through the above technical solution, the analog switch multiplexing drive system and its control method for thermo-optical phase shifter arrays provided by the present invention have the following beneficial effects: (1) The hardware architecture is greatly simplified, and the driving circuit is miniaturized. This invention achieves time-division multiplexing of a small number of high-precision DACs using an analog switch array, reducing the required number of DAC channels from the same number as the phase shifter channels to just a few. Combined with a sample-and-hold circuit, it maintains voltage stability during DAC switching intervals. The drive circuit board area is reduced by more than an order of magnitude compared to the traditional "independent DAC per channel" solution, allowing the drive module size to match the optical chip, thus laying the hardware foundation for the integration of portable spectrometers and other devices.

[0020] (2) The system power consumption is significantly reduced. In this invention, the DAC only operates at full speed during the refresh period and can enter a low-power standby mode during non-refresh periods. The total power consumption of the system is significantly reduced compared to traditional solutions, thus significantly extending the battery life of battery-powered devices.

[0021] (3) The consistency between channels has been substantially improved. All driving voltages in this invention originate from the same DAC core and the same reference source, fundamentally eliminating the inherent mismatch between multiple chips; furthermore, by combining a channel self-calibration mechanism, the analog link error is automatically measured and digitally compensated, and the actual output voltage accuracy of each channel converges to the DAC's own accuracy level, providing a reliable voltage reference for high-precision spectral coding.

[0022] (4) Fully utilize the thermal inertia characteristics of the thermo-optical phase shifter to achieve electro-optical synergistic optimization. This invention designs the driving refresh cycle to match the thermal time constant of the thermo-optical phase shifter. By utilizing the thermal inertia of the temperature change of the thermo-optical phase shifter, the actual impact of the small voltage drop between two refresh intervals on the optical phase can be ignored after thermal capacitance smoothing. The driving effect is equivalent to continuous driving, and efficient reuse of DAC resources is achieved while ensuring phase stability.

[0023] (5) Dynamic refresh scheduling improves resource utilization efficiency This invention dynamically determines the refresh priority based on the voltage change of each channel and the time interval since the last refresh, prioritizing the allocation of DAC resources to channels with larger voltage changes, so that the effective DAC bandwidth is concentrated on the channels that actually need voltage updates, further reducing system power consumption and digital switching noise.

[0024] (6) Channel self-calibration eliminates analog multiplexing link errors This invention employs a two-point method to automatically measure and digitally pre-compensate the gain error and offset error of each driving channel, effectively eliminating inconsistencies between channels introduced by factors such as analog switch on-resistance and sampling-hold op-amp offset voltage. It exhibits good long-term stability and requires no frequent manual calibration.

[0025] (7) High scalability and flexibility This invention, through the modular design of logic configuration and analog switch array, can adapt to optical chip arrays of different sizes through software configuration without changing the main hardware, thus significantly shortening the development cycle of new systems. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below.

[0027] Figure 1 This is a schematic diagram of an analog switch multiplexing drive system for thermo-optical phase shifter arrays disclosed in an embodiment of the present invention. Detailed Implementation

[0028] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0029] This invention provides an analog switch-multiplexed drive system and its control method for thermo-optical phase shifter arrays, with specific embodiments as follows: I. System Overall Structure like Figure 1 As shown in the figure, this embodiment provides an analog switch multiplexing drive system for thermo-optical phase shifter arrays, which includes six functional modules: digital-to-analog conversion unit, analog switch array, sample-and-hold circuit array, output buffer drive array, timing control logic unit, and channel self-calibration unit.

[0030] (a) Digital-to-analog conversion unit The digital-to-analog converter (DAC) unit employs a single high-precision multi-channel DAC chip. Its input is connected to the digital bus of the central control module to receive digital voltage setpoints and convert them into one or more high-precision analog voltage signals for output. The DAC chip's resolution is preferably 12-bit to 16-bit, and the specific resolution can be determined based on the phase control accuracy requirements of the thermo-optical phase shifter. The DAC output is connected to the input of the analog switch array.

[0031] (ii) Analog switch array The analog switch array is constructed using multiple CMOS analog switches, forming a cross-switch matrix with M inputs and N outputs. The inputs of the analog switch array are connected to the output channels of the digital-to-analog converter unit, and the outputs are connected to the inputs of the subsequent sample-and-hold circuit array. To meet the accuracy requirements of the thermo-optical phase shifter driver, the analog switches are preferably precision devices with low on-resistance (e.g., on-resistance less than 10Ω), low charge injection, and low leakage current (e.g., leakage current less than 1nA). The selection state of the analog switches is determined by the digital control signal output by the timing control logic unit.

[0032] (III) Sample and Hold Circuit Array The sample-and-hold circuit array corresponds to N drive output channels, with each channel containing one sample-and-hold unit. Each sample-and-hold unit consists of a holding capacitor, a high input impedance buffer amplifier, and a discharge reset switch.

[0033] One end of the holding capacitor is connected to the output of the analog switch array, and the other end is grounded; the input of the buffer amplifier is connected to one end of the holding capacitor, and the output is used as the output of the sample-and-hold unit. The buffer amplifier is configured as a voltage follower; the discharge reset switch is connected in parallel across the holding capacitor to rapidly discharge the holding capacitor under the control of the reset control signal.

[0034] When the corresponding analog switch is closed, the DAC output voltage charges the holding capacitor through the analog switch; when the analog switch is open, the voltage on the holding capacitor is maintained by the buffer amplifier. The holding capacitor is selected with low leakage current (e.g., leakage current less than 1pA) and low dielectric absorption; the buffer amplifier is selected with a precision CMOS operational amplifier with low input bias current (e.g., input bias current less than 1pA) to ensure that the voltage drop is minimal during the refresh interval.

[0035] The working process of the sample-and-hold unit is divided into a sampling phase and a holding phase: Sampling Phase: The analog switch closes, and the DAC output voltage charges the holding capacitor through the analog switch. By appropriately selecting the holding capacitor value and the analog switch's on-resistance, the charging time constant can be kept on the order of microseconds, ensuring that the capacitor voltage closely approximates the DAC output value within the allocated time slice.

[0036] Hold Phase: The analog switch is open, isolating the hold capacitor from the DAC. During this phase, the charge on the hold capacitor is discharged only through the input bias current of the buffer amplifier and the capacitor's own leakage current, resulting in an extremely low voltage sag rate. Within a typical refresh interval, the voltage sag can be controlled to the microvolt level, which is negligible.

[0037] (iv) Output buffer drive array The output buffer drive array, located after the sample-and-hold circuit array, contains multiple output buffers connected one-to-one with the outputs of multiple sample-and-hold units. The output of each output buffer is connected to the corresponding thermo-optical phase shifter load to provide drive current. The thermo-optical phase shifter is electrically equivalent to a resistive load and requires a certain drive current to generate Joule heat. The output buffers employ unity-gain stable power operational amplifiers, capable of providing the required output current (e.g., greater than 50mA), and feature short-circuit protection and thermal shutdown functions.

[0038] (v) Timing control logic unit The timing control logic unit, connected to both the digital-to-analog converter (DAC) and the analog switch array, serves as the system's control hub. It is responsible for generating the gating control signals for the analog switch array, the timing of the DAC's digital interface, and managing refresh scheduling. The timing control logic unit can be implemented using an FPGA, CPLD, or microcontroller.

[0039] The timing control logic unit contains the following three core modules: Refresh scheduling state machine: used to maintain refresh request flags and refresh timers for each channel.

[0040] Channel priority calculation module: used to calculate the refresh priority of each channel based on the voltage change of each channel and the time interval since the last refresh.

[0041] DAC instruction queue: used to buffer the voltage setting values ​​to be written to the digital-to-analog converter unit.

[0042] (vi) Channel self-calibration unit The channel self-calibration unit includes an analog-to-digital converter (ADC) and a calibration multiplexer. The inputs of the calibration multiplexer are connected to the outputs of each output buffer, and its output is connected to the input of the ADC. The digital data output of the ADC is connected to the digital-to-analog converter unit via a data bus (such as an SPI interface). The channel self-calibration unit is used to sample and measure the actual output voltage of each drive channel during system initialization or idle periods to generate calibration parameters for each channel.

[0043] II. System Working Principle This invention achieves the goal of driving a large-scale thermo-optical phase shifter array with a small number of DACs by combining analog switch time-division multiplexing with sample-and-hold technology. Its core principle lies in: By using an analog switch array, the output voltage of a small number of high-precision DACs is distributed to each sample-and-hold circuit in a time-division manner. The sample-and-hold circuit maintains the stability of the drive voltage during DAC switching intervals. At the same time, the thermal time constant characteristics of the thermo-optical phase shifter are used to make the intermittent voltage refresh equivalent to continuous drive in terms of optical phase response. On this basis, a dynamic priority scheduling mechanism is introduced to allocate the limited DAC time slot resources to the channels that urgently need to be updated. A channel self-calibration mechanism is introduced to eliminate the inter-channel errors introduced by the analog multiplexing link.

[0044] For details on the specific implementation steps of the above mechanism, please refer to Sections 3 to 5.

[0045] III. Dynamic Refresh Scheduling Control Method The timing control logic unit performs dynamic refresh scheduling control on all N drive channels according to the following steps: S1: Determine refresh priority. The channel priority calculation module in the timing control logic unit scans the refresh request flags and refresh timers of all channels. For channels with refresh requests, the refresh urgency is comprehensively evaluated based on the following principles: the greater the voltage change, the higher the refresh urgency; when voltage changes are similar, the longer the time interval since the last refresh, the higher the refresh urgency. For channels with no voltage change for several consecutive cycles, the timing control logic unit can appropriately extend its refresh interval, only needing to meet the minimum refresh cycle constraint (to prevent voltage drops due to leakage current).

[0046] S2: Allocate time slot resources. Following the refresh priority from highest to lowest, the timing control logic unit allocates time slot resources for the corresponding digital-to-analog converter (DAC) to the corresponding channels. Within each time slice, the M DACs are connected to the M highest-priority outputs among the N outputs, completing the charging and updating of the holding capacitors for those M outputs. After several time slices, all N outputs with refresh requests complete one refresh cycle.

[0047] S3: Sampling and Charging. During the time slice allocated to the target channel, the timing control logic unit controls the analog switch array to connect the output of the digital-to-analog converter (DAC) to the sample-and-hold unit of the target channel. Simultaneously, it controls the sampling switch of that channel to close, and the DAC output voltage charges the holding capacitor through the analog switch. The single charging time of the holding capacitor... satisfy: ; in, The on-resistance of the corresponding switch in the analog switch array is given. The capacitance value of the holding capacitor. This condition ensures that the voltage across the holding capacitor is charged to more than 99.3% of the DAC output voltage.

[0048] After charging is complete, the timing control logic unit controls the analog switch array to disconnect the target channel (sampling switch disconnects), causing the sample-and-hold unit to enter the hold phase. At this time, the hold capacitor is isolated from the DAC, and the voltage on the capacitor is maintained by the buffer amplifier until the next refresh cycle arrives.

[0049] S4: Refresh cycle setting. Duration of one complete refresh cycle. The value is set to be less than the minimum thermal time constant of each thermo-optical phase shifter (e.g., set to 1 / 10 of the minimum thermal time constant) so that the phase change caused by voltage fluctuations in the thermo-optical phase shifter during the two refresh intervals is smoothly absorbed by its thermal inertia, and the driving effect is equivalent to continuous driving.

[0050] IV. Channel Self-Calibration Method The initialization and self-calibration process after system power-on is as follows: Step 1: After the system is powered on, the timing control logic unit first controls all analog switches to open, the DAC outputs an initial level, and at the same time controls all discharge reset switches to close, discharging all holding capacitors to ensure that the system starts from a known state.

[0051] Step 2: The timing control logic unit sequentially connects the output of each sample-and-hold channel to the input of the analog-to-digital converter (ADC) via a calibration multiplexer. For the i-th channel, the control ADC sequentially outputs the first known voltage value. Second known voltage value (For example , The actual output voltage of each channel was measured using an analog-to-digital converter. and .

[0052] Step 3: Calculate the gain error coefficient of this channel based on the two-point measurement results. and offset error coefficient : ; ; If the gain error coefficient If the value is zero or close to zero, a hardware fault is determined in that channel, the calibration process is terminated, and an error signal is output; if... If everything is normal, proceed to step four.

[0053] Step 4: Store the gain error coefficient and offset error coefficient of each channel as calibration parameters in the non-volatile memory inside the timing control logic unit to generate a calibration parameter table for each channel.

[0054] Step 5: During normal operation, when the central control unit requests a target voltage value from a certain channel output... At this time, the timing control logic unit first performs pre-compensation based on the calibration parameter and calculates the pre-compensation setpoint: ; Then The voltage is written into the digital-to-analog converter unit, and after passing through the analog link, the actual output voltage approximates the target voltage value.

[0055] The calibration process can be executed automatically every time the system is powered on, or it can be started at any time under user command to compensate for error drift caused by factors such as temperature changes and device aging.

[0056] V. Low Power Management Mode When the system is in an idle state (i.e., no new voltage update command is received for more than a preset time threshold), the timing control logic unit automatically enters a low-power mode. In low-power mode, the timing control logic unit controls the digital-to-analog converter to enter a standby or shutdown state, and shuts down the DAC's internal reference source and output amplifier to reduce the DAC's static power consumption (typically reducing the DAC power consumption from several milliwatts to the microwatt level).

[0057] Meanwhile, the sample-and-hold circuit array and the output buffer drive array maintain static bias, continuing to provide a stable drive voltage for the thermo-optical phase shifter. Because the leakage current of the holding capacitor is extremely low and the input bias current of the buffer op-amp is minimal, the voltage across the holding capacitor can remain stable for a relatively long period without frequent refreshes.

[0058] When the system receives a new voltage update command, the timing control logic unit immediately wakes up the digital-to-analog converter unit and waits for the DAC to re-establish a stable output (the establishment time is usually less than 100μs) before resuming normal refresh scheduling.

[0059] In addition, when it is necessary to reset all channels to zero, the timing control logic unit controls the discharge reset switch of each channel to close, which will keep the capacitor discharging rapidly to the initial level.

[0060] VI. Specific Application Examples The invention will be further described in detail below with specific examples. Taking the application of this system in a computational reconstruction spectrometer with a 64-channel thermo-optical phase shifter array as an example: Step 1: System hardware configuration.

[0061] A 4-channel 16-bit high-precision DAC chip is selected, with some channels used for drive output and a few reserved for self-calibration reference generation. The analog switch array uses eight cascaded 8-to-1 analog switch chips to form a 64-to-1 cross matrix. The typical on-resistance of the analog switches is 4Ω, and the typical leakage current is 0.5nA. The sample-and-hold circuit array contains 64 independent channels, each with a 10nF C0G ceramic capacitor for holding, and a precision CMOS operational amplifier (typical input bias current 1pA) for the buffer. The timing control logic unit is implemented using an FPGA, internally including a refresh scheduling state machine, a channel priority calculation module, and a DAC instruction queue.

[0062] Step 2: System initialization and self-calibration.

[0063] The timing parameters are designed as follows: charging time constant A time constant of 5 times is 200 ns, which is much smaller than the length of a single time slice (set as 10 μs). A complete refresh cycle... The value is set to 50 μs, which is much smaller than the thermal time constant of the thermo-optical phase shifter, which is 500 μs (1 / 10 of it).

[0064] After the system is powered on, the timing control logic unit first controls all analog switches to disconnect and performs a global discharge reset. Then, it starts the self-calibration process and outputs sequentially using the two-point method. and The actual output voltage of each channel is measured, the gain error coefficient and offset error coefficient are calculated, and a calibration parameter table is generated and stored in non-volatile memory.

[0065] Step 3: Dynamically refresh the scheduling process.

[0066] The timing control logic unit maintains a refresh timer (recording the time interval since the last refresh) and a voltage change flag for each channel. During normal operation, the channel priority calculation module scans the refresh request flags of all channels and calculates the refresh priority based on the voltage change and the time interval since the last refresh for each channel. For channels with refresh requests, the channel with the larger voltage change has a higher refresh urgency; when the voltage changes are similar, the channel with the longer time interval since the last refresh has a higher refresh urgency. DAC time slot resources are allocated to each channel sequentially according to priority from high to low.

[0067] Step 4: Single-channel refresh operation process.

[0068] The central control processing module sends a voltage update command to the FPGA via the bus. The command includes the channel number and the target voltage value. The FPGA sets the refresh request flag for the corresponding channel and stores the target voltage value. At the start of the next time slice, the channel priority calculation module scans all channels to be refreshed, selects the four channels with the highest priority (equal to the number of DAC channels M), and performs the following operations sequentially: Calculate the DAC pre-compensation setting value based on the calibration parameter table. → Write the value to the corresponding DAC channel via the SPI interface → Wait for the DAC to complete setup (typical setup time is 5μs) → Select the corresponding analog switch → Close the sampling switch → Wait for the capacitor to complete charging (10μs, much greater than 5 times the time constant 200ns) → Disconnect the sampling switch and the analog switch.

[0069] Step 5: Voltage maintenance and thermal drive.

[0070] After the sampling switch is turned off, the voltage across the holding capacitor drives the heating resistor of the thermo-optical phase shifter via the buffer operational amplifier. During the 50μs refresh cycle, due to the buffer operational amplifier's input bias current being only 1pA, the voltage drop rate across the 10nF capacitor is approximately... The voltage drop within 50μs is only The temperature of the thermo-optical phase shifter stabilizes near the target value under the smoothing effect of a 500μs thermal time constant, and the driving effect is equivalent to continuous driving, providing precise phase control for optical chips.

[0071] Step 6: Exception handling and power consumption management.

[0072] When the system is idle, the FPGA puts the DAC in low-power standby mode, maintaining only the static bias of the sample-and-hold circuit array and the output buffer drive array. When all thermo-optical phase shifters need to be reset to zero, the FPGA controls the discharge reset switches of each channel to close, rapidly discharging the holding capacitors to their initial levels.

[0073] Actual testing showed that the board area for the 64-channel driver circuit is approximately 15cm². 2 The traditional 64-channel independent DAC solution has a board area of ​​approximately 120cm². 2 The area is reduced to 1 / 8 of the original; the total power consumption of the system is about 80mW, while the power consumption of the traditional solution is about 450mW, which is a power consumption reduction of about 82%; after self-calibration, the output voltage deviation between channels is less than ±0.5mV (relative to the full scale of 2.5V), which is far better than the ±5mV deviation level of the traditional multi-chip solution.

[0074] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An analog switch-multiplexed drive system for thermo-optical phase shifter arrays, characterized in that, include: The digital-to-analog converter unit is used to receive digital voltage setpoints and output corresponding analog voltage signals. An analog switch array, whose input is connected to the output of the digital-to-analog converter, is used to transmit the analog voltage signal to the corresponding output path in a time-division multiplexing manner under the control of a timing control signal. The sample-and-hold circuit array includes multiple sample-and-hold units that correspond one-to-one with the output paths of the analog switch array. The input terminal of each sample-and-hold unit is connected to the corresponding output path, which is used to store the analog voltage signal during the sampling phase and maintain the output voltage during the holding phase. The output buffer drive array includes multiple output buffers that are connected one-to-one with the output terminals of the multiple sample-and-hold units. The output terminal of each output buffer is used to connect to the corresponding thermo-optical phase shifter load to provide drive current. The timing control logic unit is connected to the digital-to-analog converter unit and the analog switch array, respectively. It is used to generate control signals to control the selection state of the analog switch array and dynamically determine the refresh priority of each channel according to the voltage change of each channel and the time interval since the last refresh.

2. The analog switch multiplexing drive system for thermo-optical phase shifter arrays according to claim 1, characterized in that, Also includes: The channel self-calibration unit includes an analog-to-digital converter and a calibration multiplexer. The input of the calibration multiplexer is connected to the output of each of the output buffers, and its output is connected to the input of the analog-to-digital converter. The output of the analog-to-digital converter is connected to the digital-to-analog conversion unit. The channel self-calibration unit is used to sample and measure the actual output voltage of each drive channel during system initialization or idle periods to generate calibration parameters for each channel.

3. The analog switch multiplexing drive system for thermo-optical phase shifter arrays according to claim 1, characterized in that, The sample-and-hold unit includes: A holding capacitor is provided, one end of which is connected to the output of the analog switch array; A buffer amplifier, the input of which is connected to one end of the holding capacitor, and the output of which serves as the output of the sample-and-hold unit; A discharge reset switch is connected in parallel across the holding capacitor to discharge the holding capacitor under the control of a reset control signal.

4. The analog switch multiplexing drive system for thermo-optical phase shifter arrays according to claim 1, characterized in that, The timing control logic unit includes: The refresh scheduling state machine is used to maintain the refresh request flags and refresh timers for each channel; The channel priority calculation module is used to calculate the refresh priority of each channel based on the voltage change of each channel and the time interval since the last refresh. The DAC instruction queue is used to cache the voltage setting values ​​to be written to the digital-to-analog converter unit.

5. A control method for an analog switch-multiplexed drive system for a thermo-optical phase shifter array, implemented based on the system described in any one of claims 1 to 4, characterized in that, Includes the following steps: S1: The timing control logic unit dynamically determines the refresh priority of each channel based on the voltage change of each channel and the time interval since the last refresh. S2: Allocate time slot resources of digital-to-analog conversion units to the corresponding channels in descending order of refresh priority; S3: During the time slice allocated to the target channel, control the analog switch array to connect the output terminal of the digital-to-analog converter unit to the sample-and-hold unit of the target channel, and charge the holding capacitor in the sample-and-hold unit; S4: After charging is complete, control the analog switch array to disconnect the target channel, so that the sample-and-hold unit enters the holding phase, and the sample-and-hold unit maintains the output voltage until the next refresh.

6. The control method according to claim 5, characterized in that, The specific method for dynamically determining the refresh priority of each channel in step S1 is as follows: The channel priority calculation module scans the refresh request flags of all channels. For channels with refresh requests, the urgency of refreshing is comprehensively evaluated based on the following principles: The greater the voltage change, the higher the refresh urgency of the channel; When the voltage changes are similar, the channel with a longer time interval since the last refresh has a higher refresh urgency. The timing control logic unit prioritizes allocating the time slot resources of the digital-to-analog conversion unit to channels with high refresh urgency.

7. The control method according to claim 5, characterized in that, In step S3, the charging time of the capacitor is maintained to meet the following conditions: ； in, The duration of a single charge of the holding capacitor. The on-resistance of the corresponding switch in the analog switch array is given. The capacitance value of the holding capacitor.

8. The control method according to claim 5, characterized in that, The duration of a complete refresh cycle is set to be less than the minimum value of the thermal time constant of each of the thermo-optical phase shifters, so that the phase change caused by voltage fluctuations in the thermo-optical phase shifter during the interval between two refreshes is smoothly absorbed by its thermal inertia.

9. The control method according to claim 5, characterized in that, It also includes a channel self-calibration step: T1: During system initialization or idle time, control the analog switch array to sequentially connect the output terminals of each channel to the analog-to-digital converter of the channel self-calibration unit; T2: Control the digital-to-analog converter unit to sequentially output the first known voltage value. Second known voltage value The actual output voltage of the corresponding channel is measured using the analog-to-digital converter. and ; T3: Calculate the gain error coefficient of this channel according to the following formula. and offset error coefficient : ； T4: Store the gain error coefficient and offset error coefficient of each channel as calibration parameters in non-volatile memory; T5: During normal operation, the input target voltage value is adjusted according to the calibration parameters. Perform pre-compensation and calculate the pre-compensation setpoint. ,Will The data is written into the digital-to-analog converter to make the actual output voltage approximate the target voltage value.

10. The control method according to claim 5, characterized in that, When the system is in an idle state or the target voltage of all channels does not change within a preset time, the timing control logic unit controls the digital-to-analog converter to enter a low-power standby mode and maintains the static bias of the sample-and-hold circuit array and the output buffer drive array.

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