System for testing wafers and method for performing wafer acceptance testing on first circuit

Abstract

Embodiments of the present disclosure provide a system for testing a wafer and a method for performing a wafer acceptance test on a first circuit. A system includes a first circuit, a test circuit, and a test system. The first circuit is to generate a first signal having a first oscillation frequency. The test circuit is coupled to the first circuit to generate a second signal in response to the first signal and to generate a third signal representing a value of a first capacitance of a first capacitor in the test circuit. The second signal represents a value of the first oscillation frequency. The second signal has a second oscillation frequency that is lower than the first oscillation frequency. The test system is coupled to the test circuit to receive the second signal and the third signal and to perform a wafer acceptance test (WAT) on the first circuit to determine an inductance of the first circuit in response to the second signal and the third signal.

Description

Technical Field

[0001] The embodiments of the present invention generally relate to the semiconductor field, and more specifically, to a system for testing wafers and a method for performing wafer acceptance tests on a first circuit. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has produced a variety of digital devices to solve problems in many different fields. Some of these digital devices (such as memory macros) are configured as storage for data. As ICs become smaller and more complex, the resistance of the conductive wiring within these digital devices also changes, affecting the operating voltage of these digital devices and the overall IC performance. Summary of the Invention

[0003] An embodiment of the present invention provides a system for testing a wafer, comprising: a first circuit for generating a first signal having a first oscillation frequency; a test circuit coupled to the first circuit for generating a second signal in response to the first signal, the second signal representing a value of the first oscillation frequency, and for generating a third signal representing a value of a first capacitance of a first capacitor in the test circuit, the second signal having a second oscillation frequency less than the first oscillation frequency; and a test system coupled to the test circuit for receiving the second signal and the third signal, and for performing a wafer acceptance test on the first circuit, thereby determining the inductance of the first circuit in response to the second signal and the third signal.

[0004] Another embodiment of the present invention provides a method for performing wafer acceptance testing on a first circuit, the method comprising: determining a first oscillation frequency of the first circuit of a first inductor-capacitor (LC) resonant oscillator by means of a test system, the first inductor-capacitor resonant oscillator including the first circuit and a test circuit; determining a first capacitance of a first capacitor of the first circuit by means of the test system; and determining the inductance of the first circuit by means of the test system based on the first oscillation frequency and the first capacitance of the first capacitor.

[0005] Another embodiment of the present invention provides a system for testing a wafer, comprising: a first circuit for generating a first signal having a first oscillation frequency; a test circuit coupled to the first circuit for generating a second signal in response to the first signal, the second signal representing a value of the first oscillation frequency, and for generating a third signal representing a value of a first capacitance of a first capacitor in the test circuit, the second signal having a second oscillation frequency less than the first oscillation frequency; and a test system coupled to the test circuit for performing a wafer acceptance test on the first circuit to determine the inductance of the first circuit in response to the second signal and the third signal, wherein the test system comprises: a probe coupled to the test circuit for receiving the second signal and the third signal from the test circuit; a probe card coupled to the probe for receiving the second signal and the third signal from the probe; and a test device coupled to the probe card for receiving the second signal and the third signal from the probe card and for determining the inductance of the first circuit. Attached Figure Description

[0006] The various aspects of the invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0007] Figure 1 This is a block diagram of a system according to some embodiments.

[0008] Figure 2 It is a block diagram of a circuit according to some embodiments.

[0009] Figure 3 It is a block diagram of a circuit according to some embodiments.

[0010] Figure 4 This is a block diagram of an integrated circuit according to some embodiments.

[0011] Figure 5 It is a block diagram of a circuit according to some embodiments.

[0012] Figure 6 It is a block diagram of a circuit according to some embodiments.

[0013] Figure 7 This is a circuit diagram of a frequency divider circuit according to some embodiments.

[0014] Figures 8A to 8BThis is a flowchart of a method for performing wafer acceptance testing on a circuit according to some embodiments.

[0015] Figure 9A This is a flowchart of a corresponding method for performing wafer acceptance testing on a circuit according to some embodiments.

[0016] Figure 9B This is a flowchart of a corresponding method for performing wafer acceptance testing on a circuit according to some embodiments.

[0017] Figure 10 The figure is a schematic diagram of a system according to some embodiments. Detailed Implementation

[0018] This invention provides numerous different embodiments or examples for implementing various features of this disclosure. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are formed in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the invention. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0019] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower," "above," and "upper" may be used herein to describe the relationship between one element or component and another (or other elements or components) as shown in the figure. In addition to the orientations shown in the figure, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0020] During the semiconductor manufacturing process, the performance of various interconnects and devices on a semiconductor wafer is evaluated by wafer acceptance testing (WAT) after the manufacturing process. Furthermore, after the semiconductor wafer has undergone semiconductor processing, testing is performed in a stage known as wafer acceptance testing.

[0021] In wafer acceptance testing, probes can be placed on pads coupled to various devices and interconnect structures within an IC, which is formed on a semiconductor wafer, allowing for certain measurements. If the performance measured in wafer acceptance testing is unacceptable, the semiconductor wafer (which has undergone numerous processing steps), the material used to perform the semiconductor manufacturing process, may be wasted. Defect diagnosis can be implemented as part of the semiconductor manufacturing process in wafer acceptance testing to detect defects in the interconnects and devices on the semiconductor wafer.

[0022] Furthermore, wafer acceptance testing can be performed to deduce product yield. Prior to wafer acceptance testing, test circuit structures (i.e., test keys and test pads) electrically connected to the wafer die or non-product areas can be formed within scribe lines. One or more test circuit structures are electrically connected to external circuitry or probes on a probe card via test pads to check the quality of various processes during wafer acceptance testing. Wafer acceptance testing can be used to confirm the stability of semiconductor processes and improve IC yield. Therefore, by utilizing wafer acceptance testing, the quality and stability of semiconductor wafers can be ensured.

[0023] According to some embodiments, the system includes a first circuit for generating a first signal. In some embodiments, the first signal has a first oscillation frequency.

[0024] In some embodiments, the system further includes a test circuit coupled to the first circuit.

[0025] In some embodiments, the test circuit generates a second signal in response to the first signal. In some embodiments, the second signal represents a value of the first oscillation frequency.

[0026] In some embodiments, the test circuit is further configured to generate a third signal, which represents the value of the first capacitance of the first capacitor in the test circuit. In some embodiments, the second signal has a second oscillation frequency lower than the first oscillation frequency.

[0027] In some embodiments, the system further includes a test system coupled to the test circuitry.

[0028] In some embodiments, the test system is used to receive a second signal and a third signal.

[0029] In some embodiments, the test system is further used to perform a wafer acceptance test (WAT) on the first circuit, thereby determining the inductance of the first circuit in response to a second signal and a third signal.

[0030] In some embodiments, by performing a WAT ​​on the first circuit using a test system, the inductance of the first circuit can be determined simultaneously with the WAT, thereby reducing the time required to measure the inductance compared to other methods.

[0031] Figure 1 This is a block diagram of system 100 according to some embodiments.

[0032] Figure 1 Simplified for illustrative purposes. In some embodiments, system 100 includes, except... Figure 1 Various elements other than those described herein, or arranged in other ways to perform the operations discussed below.

[0033] In some embodiments, the system 100 is used to perform wafer acceptance testing (WAT) on the semiconductor wafer 101.

[0034] System 100 includes semiconductor wafer 101 (also referred to as “wafer 101”), circuit 102, a set of test circuits 104 and test system 112.

[0035] In some embodiments, system 100 is used to perform wafer acceptance testing on circuit 102. In some embodiments, test system 112 is used to perform wafer acceptance testing on circuit 102.

[0036] In some embodiments, semiconductor wafer 101 uses various interconnect structures to interconnect circuit systems on the IC. In some embodiments, the interconnect structure includes multiple metal layers separated by one or more interlayer dielectrics.

[0037] In some embodiments, circuit 102 is formed in wafer 101. In some embodiments, circuit 102 includes one or more circuits formed in wafer 101. In some embodiments, circuit 102 is used to generate signal FO1. In some embodiments, signal FO1 is a radio frequency (RF) signal. In some embodiments, signal FO1 is an oscillation signal. In some embodiments, signal FO1 has an oscillation frequency F1.

[0038] In some embodiments, the oscillation frequency F1 of signal FO1 is greater than 2 MHz. In some embodiments, the oscillation frequency F1 includes frequencies ranging from about 50 MHz to about 500 MHz. Other values ​​or ranges for the oscillation frequency F1 are within the scope of one embodiment of this disclosure.

[0039] In some embodiments, one or more circuits that are part of circuit 102 include one or more inductors. In some embodiments, one or more circuits that are part of circuit 102 include... Figures 2 to 5 One or more of the inductors L1a, L1b, L2a, or L2b. Other types of circuitry used in circuit 102 are within the scope of one embodiment of this disclosure.

[0040] In some embodiments, this group of test circuits 104 includes one or more test circuits (collectively referred to as "test circuit group 104").

[0041] This set of test circuits 104 is coupled to circuit 102. In some embodiments, this set of test circuits 104 is on wafer 101. In some embodiments, this set of test circuits 104 is used to receive signal FO1. In some embodiments, this set of test circuits 104 is used to generate signal FOUT in response to signal FO1. In some embodiments, signal FOUT represents the value of oscillation frequency F1.

[0042] In some embodiments, this set of test circuits 104 is further used to generate a signal CM. In some embodiments, the signal CM represents the capacitance value of at least one of the capacitors C1a or C3 in this set of test circuits 104. In some embodiments, the signal FOUT has an oscillation frequency F2. In some embodiments, the oscillation frequency F2 is less than the oscillation frequency F1.

[0043] In some embodiments, the oscillation frequency F2 signal FOUT is a low frequency. In some embodiments, the low frequency of this disclosure includes frequencies ranging from about 0 Hz to about 2 MHz. Other values ​​or ranges used for the low frequency range are within the scope of one embodiment of this disclosure.

[0044] In some embodiments, this set of test circuits 104 includes circuits 104a and 104b.

[0045] In some embodiments, circuit 104a is used to receive signal FO1. In some embodiments, this set of test circuits 104 is used to generate signal FOUT in response to signal FO1. In some embodiments, circuit 104a includes at least capacitor C1a or C1b, or NMOS transistors N1 and N2 (in Figures 2 to 5 (See diagram in Chinese).

[0046] In some embodiments, circuit 104b is configured to generate a signal CM during impedance / capacitance measurements of circuit 104b. In some embodiments, signal CM represents the capacitance value of circuit 104b. In some embodiments, circuit 104b includes at least capacitor C3 (in... Figures 2 to 5 (See diagram in Chinese).

[0047] In some embodiments, one or more test circuit structures in this set of test circuits 104 are formed on a semiconductor wafer 101. In some embodiments, one or more test circuit structures in this set of test circuits 104 are formed in scribe lines (not shown) between a plurality of dies (not shown) of the semiconductor wafer 101. In some embodiments, one or more test circuit structures in this set of test circuits 104 are formed in a test region at the edge of the semiconductor wafer 101. In some embodiments, one or more test circuit structures in this set of test circuits 104 are formed in circuit 102, so at least a portion of this set of test circuits 104 is a portion of circuit 102. In some embodiments, this set of test circuits 104 is used for testing or other functions, as discussed below. In some embodiments, each test circuit structure in this set of test circuits 104 includes a plurality of test pads, such as wafer acceptance test array pads (e.g., pad 110) and optical critical dimension (OCD) pads.

[0048] Test system 112 is coupled to this set of test circuits 104. In some embodiments, test system 112 is used to receive at least one of signal FOUT or signal CM. In some embodiments, test system 112 is used to perform wafer acceptance testing on circuit 102 through this set of test circuits 104.

[0049] In some embodiments, the test system 112 is used to perform a wafer acceptance test on the circuit 102 by measuring the signal FOUT, and the signal FOUT represents the oscillation frequency F1 of the signal F1, and the test system 112 can indirectly analyze the oscillation frequency F1 by measuring the signal FOUT or the oscillation frequency F2.

[0050] In some embodiments, the test system 112 is used to perform a wafer acceptance test on the circuit 102 by measuring a signal CM, and the signal CM represents the impedance or capacitance of at least one of capacitors C1a or C3, and the test system 112 is able to indirectly analyze the capacitance of at least one of capacitors C1a or C3 by measuring the signal CM.

[0051] In some embodiments, the test system 112 is used to determine the inductance of one or more inductors in the circuit 102 based on the signal FOUT and the signal CM. In some embodiments, the test system 112 is used to determine the inductance of one or more inductors in the circuit 102 based on the oscillation frequency F1 or F2 and the capacitance of at least one of the capacitors C1a or C3.

[0052] In some embodiments, the oscillation frequency F1 of circuit 102 and the capacitance of this set of test circuits 104 can be used to determine the inductance of one or more circuit elements in circuit 102 during wafer acceptance testing.

[0053] In some embodiments, circuit 102 and the set of test circuits 104 include one or more VCOs, and the oscillation frequency F1 of circuit 102 and the capacitance of the set of test circuits 104 can reflect the inductance changes of one or more inductors in circuit 102.

[0054] In some embodiments, by utilizing this set of test circuits 104 with circuit 102, the inductance of one or more circuit elements in circuit 102 can be measured / determined for wafer acceptance testing, thereby reducing the time required to measure inductance compared to other methods that may require up to 3 months to determine inductance.

[0055] In some embodiments, by utilizing this set of test circuits 104, the inductance changes of one or more circuit elements in circuit 102 can be monitored for process control as part of wafer acceptance testing, thereby reducing the time required to measure inductance changes compared to other methods that may require up to 3 months to determine the inductance.

[0056] In some embodiments, by utilizing this set of test circuits 104, the inductance changes of one or more circuit elements in circuit 102 can be monitored for process control, even if circuit 102 is used to operate under RF conditions. Compared with other methods that capture WAT data under DC conditions, wafer acceptance testing cannot accurately measure RF signals, and once the circuit under test is operating at RF frequencies, the WAT data is insufficient for RF performance.

[0057] The test system 112 includes a test device 120, a probe card 122, and a set of probes 130. For ease of explanation, Figure 1 The set of probes 130 in the figure illustrates a single probe; however, the set of probes 130 includes one or more probes.

[0058] This set of probes 130 is coupled to this set of test circuits 104. This set of probes 130 is used to receive at least one of the signals FOUT or CM from this set of test circuits 104. In some embodiments, this set of probes 130 is coupled to this set of test circuits 104 via pads 110. In some embodiments, pads 110 are part of this set of test circuits 104. In some embodiments, this set of probes 130 includes one or more different types of probes 130, such as electrical probe leads, optical probes, and / or magnetic probes.

[0059] Probe card 122 is coupled to this group of probes 130. Probe card 122 is used to receive at least one of the signals FOUT or CM from this group of probes 130. Probe card 122 is coupled between this group of probes 130 and the test equipment 120.

[0060] In some embodiments, probe card 122 is used to perform one or more wafer acceptance tests. In some embodiments, probe card 122 includes a plurality of probes (e.g., this set of probes 130).

[0061] In some embodiments, one or more probes in the group of probes 130 of probe card 122 are in direct contact with one or more test circuits in the group of test circuits 104, and the position of the test pads of one or more test circuits in the group of test circuits 104 is identified by probe card 122 or test device 120.

[0062] In some embodiments, after the probes 130 of the probe card 122 contact the test pads of one or more test circuits in the test circuit 104, the probe card 122 is used to sequentially and repeatedly apply one or more test signals to one or more test circuits in the test circuit 104 through the probes 130, and then the probe card 122 is used to receive one or more responses from one or more test circuits in the test circuit 104 through the probes 130.

[0063] Test equipment 120 is coupled to probe card 122. Test equipment 120 is used to receive at least one of the signals FOUT or CM from probe card 122. In some embodiments, test equipment 120 is used to measure at least one of the signals FOUT or CM, thereby performing wafer acceptance testing on one or more inductors in circuit 102 in response to at least one of the signals FOUT or CM.

[0064] In some embodiments, the test equipment 120 includes a test section 120a and a test section 120b.

[0065] In some embodiments, test section 120a is used to receive the signal FOUT from probe card 122. In some embodiments, test section 120a is used to measure the signal FOUT, thereby performing wafer acceptance testing on one or more inductors in circuit 102 in response to the signal FOUT.

[0066] In some embodiments, test section 120b is used to receive a signal CM from probe card 122. In some embodiments, test section 120b is used to measure the signal CM, thereby performing wafer acceptance testing on one or more inductors in circuit 102 in response to the signal CM. In some embodiments, test section 120b is an inductance, capacitance, and resistance (LCR) meter. In some embodiments, test section 120b is used to measure the impedance of at least one of capacitors C1a or C2, thereby performing wafer acceptance testing on one or more inductors in circuit 102 in response to the signal CM.

[0067] In some embodiments, the test equipment 120 is also referred to as a "tester". In some embodiments, the test equipment 120 is used to perform one or more test procedures and to record one or more corresponding test results of the semiconductor wafer 101 or circuit 102. In some embodiments, in back end of line (BEOL) testing, this set of test circuits 104 can provide process stability for various processing parameters.

[0068] In some embodiments, test results from test equipment 120 are used to modify processing parameters to improve IC yield. In some embodiments, upon completion of testing by test equipment 120, faulty dies are marked with ink and / or faulty process results are identified. The semiconductor wafer 101 is then diced along the scribing lines, thereby creating an integrated circuit device (chip).

[0069] In some embodiments, system 100 achieves one or more of the benefits described herein.

[0070] Other configurations of system 100 are within the scope of one embodiment of this disclosure.

[0071] Figure 2 This is a block diagram of circuit 200 according to some embodiments.

[0072] Circuit 200 is Figure 1 One embodiment of wafer 101 is described in detail below, therefore a similar detailed description is omitted.

[0073] Circuit 200 is Figure 1 This is one embodiment of circuit 102 and this set of test circuits 104, therefore a similar detailed description is omitted.

[0074] Circuit 200 includes step-down circuit 202 and circuit 204.

[0075] In some embodiments, the step-down circuit 202 is Figure 1 One embodiment of circuit 102 is described in detail below, therefore a similar detailed description is omitted.

[0076] In some embodiments, circuit 204 is Figure 1 This is one embodiment of the test circuit 104, therefore a similar detailed description is omitted. In some embodiments, circuit 204 is Figure 1 One embodiment of circuit 104a is described, therefore a similar detailed description is omitted.

[0077] The buck converter 202 is coupled to circuit 204 and voltage supply VDD1. In some embodiments, the buck converter 202 is used to convert a first direct current (DC) voltage to a second DC voltage. In some embodiments, the first DC voltage is less than the second DC voltage. In some embodiments, the first DC voltage is greater than the second DC voltage. In some embodiments, the buck converter 202 is also referred to as a "buck converter". In some embodiments, the buck converter 202 is part of an integrated voltage regulator (iVR).

[0078] The step-down circuit 202 includes inductors L1a, L1b, L2a, and L2b. In some embodiments, inductors L1a, L1b, L2a, and L2b are part of a transformer.

[0079] In some embodiments, at least one of inductors L2a or L2b is not in the buck circuit 202.

[0080] In some embodiments, at least one of inductors L1a, L1b, L2a, or L2b is identical to at least another of inductors L1a, L1b, L2a, or L2b.

[0081] In some embodiments, at least one of the corresponding inductors L1a, L1b, L2a, or L2b has an inductance value that is substantially the same as that of at least another of the corresponding inductors L1a, L1b, L2a, or L2b. In some embodiments, two elements are substantially the same if they differ from each other by + / -5%.

[0082] In some embodiments, at least one of inductors L1a, L1b, L2a, or L2b is a spiral inductor. In some embodiments, at least one of inductors L1a, L1b, L2a, or L2b is a toroidal inductor. In some embodiments, at least one of inductors L1a, L1b, L2a, or L2b is a multi-chip inductor. In some embodiments, at least one of inductors L1a, L1b, L2a, or L2b is a thin-film inductor.

[0083] In some embodiments, at least one of inductors L1a, L1b, L2a, or L2b is one or more of an iron-core, ferrite-core, air-core, or ceramic-core inductor.

[0084] Other inductor types for at least one of inductor L1a, inductor L1b, inductor L2a, or inductor L2b are within the scope of one embodiment of this disclosure.

[0085] In some embodiments, the self-inductance of inductor L1a can be measured by test system 112 using Equation 1 (described below) by setting inductors L2a and L2b to floating connection and by the capacitance of capacitor C1a based on oscillation frequency F1. In some embodiments, the self-inductance of inductor L2a or L2b can be measured by test system 112 using Equation 1 (described below) by setting inductors L1a and L1b to floating connection and by the capacitance of capacitor C1a based on oscillation frequency F1.

[0086] The first end of inductor L2a is coupled to a floating node (not shown), and the second end of inductor L2a is coupled to the first end of inductor L2b. The second end of inductor L2b is coupled to a floating node (not shown).

[0087] In some embodiments, during the wafer acceptance test of the buck circuit 202 Figure 1 The test system 112 can use circuit 204 to determine the oscillation frequency F1 of signal FO1 based on the oscillation frequency F2 of signal FOUT.

[0088] Circuit 204 includes capacitor C1a, capacitor C1b, N-type metal-oxide-semiconductor (NMOS) transistor N1, NMOS transistor N2, capacitor C2a, capacitor C2b, buffer circuit 206, buffer circuit 210, frequency divider circuit 208, and output pad 250.

[0089] Inductor L1a is coupled between nodes Nd1 and Nd2. Inductor L1a is coupled to the power supply VDD1 through node Nd1.

[0090] Inductor L1a includes a first terminal and a second terminal. The first terminal of inductor L1a is coupled to the voltage supply VDD1 and node Nd1. The second terminal of inductor L1a is coupled to at least node Nd2.

[0091] Other types, configurations, or numbers of inductors for inductor L1a are within the scope of one embodiment of this disclosure.

[0092] Inductor L1b is coupled between nodes Nd1 and Nd3. Inductor L1b is coupled to the voltage supply VDD1 through node Nd1.

[0093] Inductor L1b includes a first terminal and a second terminal. The first terminal of inductor L1b is coupled to the voltage supply VDD1, node Nd1, and the first terminal of inductor L1a. The second terminal of inductor L1b is coupled to at least node Nd3.

[0094] Other types, configurations, or numbers of inductors for inductor L1b are within the scope of one embodiment of this disclosure.

[0095] Capacitor C1a includes a first terminal and a second terminal. The first terminal of capacitor C1a, node Nd2, the second terminal of inductor L1a, the first terminal of capacitor C2a, the gate terminal of NMOS transistor N2, and the drain / source terminals of NMOS transistor N1 are all coupled together.

[0096] The second end of capacitor C1a is coupled to the second end of capacitor C1b. In some embodiments, the second end of capacitor C1a is coupled to an input node (not shown).

[0097] In some embodiments, at least one of capacitors C1a, C1b, C2a, or C2b is a metal oxide metal (MOM) capacitor.

[0098] Capacitor C1b includes a first terminal and a second terminal. The first terminal of capacitor C1b, node Nd3, the second terminal of inductor L1b, the first terminal of capacitor C2b, the gate terminal of NMOS transistor N1, and the drain / source terminals of NMOS transistor N2 are all coupled together.

[0099] In some embodiments, the second end of capacitor C1b is coupled to an input node (not shown). In some embodiments, capacitors C1a and C1b are coupled in parallel with inductors L1a and L1b.

[0100] In some embodiments, capacitor C1a and inductor L1a are configured as an LC resonant circuit and used to generate an oscillation signal FO1 with an oscillation frequency F1 at resonance.

[0101] In some embodiments, capacitor C1b and inductor L1b are configured as an LC resonant circuit and used to generate an oscillation signal FO1 with an oscillation frequency F1 at resonance.

[0102] Other types, configurations, or numbers of capacitors for capacitors C1a and / or C1b are within the scope of one embodiment of this disclosure.

[0103] NMOS transistors N1 and NMOS transistor N2 are cross-coupled to each other. In some embodiments, NMOS transistors N1 and NMOS transistor N2 are used to provide a negative resistance, which reduces some of the losses of the LC resonant circuit when it resonates at the resonant frequency (oscillation frequency F1), thereby giving the LC resonant circuit a gain greater than 1 and a phase shift of 0 degrees at the resonant frequency.

[0104] In some embodiments, each of the gate terminal of NMOS transistor N1, the drain / source terminal of NMOS transistor N2, the first terminal of capacitor C1b, node Nd3, and the second terminal of inductor L1b is coupled together and corresponds to the intermediate output terminal of circuit 200.

[0105] In some embodiments, each of the gate terminal of NMOS transistor N2, the drain / source terminal of NMOS transistor N1, the first terminal of capacitor C1a, node Nd2, and the second terminal of inductor L1a is coupled together and corresponds to another intermediate output terminal of circuit 200.

[0106] In some embodiments, the intermediate output terminal of circuit 200 is used to output signal FO1.

[0107] In some embodiments, each of the source / drain terminals of NMOS transistor N1 and the source / drain terminals of NMOS transistor N2 is coupled to a reference voltage supply VSS.

[0108] In some embodiments, at least one of the NMOS transistors N1 or N2 has a corresponding parasitic capacitance CN1a or CN1b. In some embodiments, when the capacitances of the corresponding capacitors C1a and C1b are much larger than the parasitic capacitances CN1a and CN1b, the parasitic capacitances CN1a and CN1b can be ignored during wafer acceptance testing. In some embodiments, when the parasitic capacitances CN1a and CN1b are less than 1% of the capacitances of the corresponding capacitors C1a and C1b, the capacitances of the corresponding capacitors C1a and C1b are much larger than the parasitic capacitances CN1a and CN1b.

[0109] Other transistor types are within the scope of one embodiment of this disclosure. In some embodiments, at least one of NMOS transistors N1 or N2 is a corresponding n-type transistor. In some embodiments, at least one of NMOS transistors N1 or N2 is a corresponding p-type transistor.

[0110] In some embodiments, at least one of the NMOS transistors N1 or N2 is a corresponding P-type metal-oxide-semiconductor (PMOS) transistor.

[0111] Other types, configurations, or numbers of transistors for at least one of NMOS transistors N1 or N2 are within the scope of one embodiment of this disclosure.

[0112] Capacitor C2b is coupled to at least the third node Nd3. Capacitor C2b is used to receive signal FO1 and output signal FO1'. Capacitor C2a is used to block the DC portion of signal FO1 and transmit the AC portion of signal FO1 (e.g., FO1'). In some embodiments, signal FO1' is the AC portion of signal FO1.

[0113] Capacitor C2b includes a first terminal and a second terminal. The second terminal of capacitor C2b is coupled to the input terminal of buffer circuit 206.

[0114] Capacitor C2a includes a first terminal and a second terminal. The second terminal of capacitor C2a is coupled to the input terminal of buffer circuit 210.

[0115] Other types, configurations, or numbers of capacitors for capacitors C2a and / or C2b are within the scope of one embodiment of this disclosure.

[0116] The buffer circuit 206 is coupled to the second terminal of capacitor C2b and the input terminal of frequency divider circuit 208. In some embodiments, the buffer circuit 206 is coupled to voltage supply VDD1 (not shown).

[0117] The input terminal of the buffer circuit 206 is used to receive the signal FO1', and the output terminal is used to output the oscillation signal FO2. In some embodiments, the oscillation signal FO2 has an oscillation frequency F1. In some embodiments, the buffer circuit 206 is used to output the oscillation signal FO2 in response to the AC portion (FO1') of the signal FO1.

[0118] The buffer circuit 206 is used to present a high input impedance to the capacitor C2b and the LC resonant oscillator. The buffer circuit 206 is also used to present a low input impedance to the frequency divider circuit 208.

[0119] In some embodiments, the buffer circuit 206 is also referred to as a "buffer amplifier circuit". In some embodiments, the buffer circuit 206 is used to electrically isolate the LC resonant oscillator from one or more circuits in the frequency divider circuit 208, thereby improving the performance of the LC resonant oscillator with frequency pulling and / or phase noise.

[0120] Other types, configurations, or numbers of circuit elements used for the buffer circuit 206 are within the scope of one embodiment of this disclosure.

[0121] The buffer circuit 210 is coupled to the second end of the capacitor C2a.

[0122] Buffer circuit 210 is configured as a pseudo-circuit. In some embodiments, the pseudo-circuit is a non-functional circuit. In some embodiments, buffer circuit 210 is similar to buffer circuit 206, and therefore a similar detailed description is omitted. In some embodiments, buffer circuit 210 is not configured as a pseudo-circuit.

[0123] Other types, configurations, or numbers of circuit elements used for the buffer circuit 210 are within the scope of one embodiment of this disclosure.

[0124] Frequency divider circuit 208 is coupled to buffer circuit and output pad 250. In some embodiments, frequency divider circuit 208 is coupled to voltage supply VDD1 (not shown).

[0125] The input terminal of the frequency divider circuit 208 is coupled to the output terminal of the buffer circuit 206. The output terminal of the frequency divider circuit 208 is coupled to the output pad 250.

[0126] In some embodiments, the frequency divider circuit 208 is used to receive the oscillation signal FO2 and generate an oscillation signal FOUT (also referred to as "signal FOUT") in response to the oscillation signal FO2. In some embodiments, the oscillation signal FOUT has an oscillation frequency F2. In some embodiments, the oscillation frequency F2 is less than the oscillation frequency F1.

[0127] In some embodiments, the oscillation frequency F2 of the oscillation signal FOUT is equal to the oscillation frequency F1 of the oscillation signal FO2 divided by a scaling factor N, where N is an integer. In some embodiments, the relationship between the oscillation frequency F2 and the oscillation frequency F1 is expressed as Equation 1:

[0128] F2 = F1 / N(1).

[0129] The oscillation frequency F2 is less than the oscillation frequency F1. In some embodiments, the oscillation frequency F2 is greater than or equal to the oscillation frequency F1.

[0130] In some embodiments, the frequency divider circuit 208 includes one or more D flip-flops, True Single-Phase Clocking (TSPC) flip-flops, or current-mode logic (CML) dividers.

[0131] Other types, configurations, or numbers of circuit elements used for the frequency divider circuit 208 are within the scope of one embodiment of this disclosure.

[0132] In some embodiments, during the wafer acceptance test of the buck circuit 202, the test system 112 may use the circuit 204 to determine the oscillation frequency F1 of the signal FO1 based on the oscillation frequency F2 of the signal FOUT.

[0133] In some embodiments, there is a relationship between the oscillation frequency F1 of signal FO1, the capacitance of capacitor C1a, and the self-inductance of inductor L1a, which is expressed by the following equation 2:

[0134] L1a =1 / (4×pi2×F12×C1a)(2).

[0135] The oscillation frequency F2 is less than the oscillation frequency F1. In some embodiments, the oscillation frequency F2 is greater than or equal to the oscillation frequency F1.

[0136] In some embodiments, during the wafer acceptance test of the buck circuit 202, the test system 112 is used to determine the oscillation frequency F1 of the signal FO1 based on the oscillation frequency F2 of the signal FOUT, and to determine the capacitance of the capacitor C1a. Then, the test system 112 is used to determine the self-inductance of the inductor L1a by using Equation 2 and the determined oscillation frequency F1 of the signal FO1 and the estimated capacitance C3a of the capacitor C1a (described below).

[0137] In some embodiments, by utilizing at least one of circuits 200, 300, or 500, the inductance of one or more circuit elements in the buck circuit 202 can be measured / determined during wafer acceptance testing, thereby reducing the time required to measure inductance compared to other methods.

[0138] In some embodiments, circuit 200 achieves one or more of the benefits described herein.

[0139] Other configurations, types, or numbers of circuit elements in circuit 200 are within the scope of one embodiment of this disclosure.

[0140] Figure 3 This is a circuit diagram of circuit 300 according to some embodiments.

[0141] Circuit 300 is Figure 2 A variant of circuit 200, therefore a similar detailed description is omitted. Figure 2 Compared to circuit 200, circuit 300 further includes circuits 320a and 320b (collectively referred to as "circuit 320"), therefore a similar detailed description is omitted.

[0142] Circuit 300 is Figure 1 One embodiment of wafer 101, therefore a similar detailed description is omitted.

[0143] Circuit 300 is Figure 1 This is one embodiment of circuit 102 and this set of test circuits 104, therefore a similar detailed description is omitted.

[0144] For simplicity, Figures 1 to 7One or more corresponding components in each drawing are designated by the same element symbol.

[0145] Circuit 300 includes step-down circuit 202 and circuit 304.

[0146] Circuit 304 is Figure 2 A variant of circuit 204, therefore a similar detailed description is omitted. Figure 2 Compared to circuit 204, circuit 304 further includes circuits 320a and 320b, therefore a similar detailed description is omitted.

[0147] In some embodiments, circuit 304 is Figure 1 This is one embodiment of the test circuit 104, therefore a similar detailed description is omitted. In some embodiments, circuit 304 is Figure 1 Circuit 104a and Figure 1 One embodiment of circuit 104b is described, therefore a similar detailed description is omitted.

[0148] In some embodiments, circuits 320a and 320b are Figure 1 One embodiment of circuit 104b is described, therefore a similar detailed description is omitted.

[0149] Test system 112 may use circuit 320a to determine the measured capacitance C3m of capacitor C3. Test system 112 may use circuit 320b to determine the estimated parasitic capacitance CP1 of capacitor C3. In some embodiments, the actual capacitance C3a of capacitor C3 is determined based on the measured capacitance C3m and the estimated parasitic capacitance CP1 of capacitor C3 according to Equation 3 (described below).

[0150] Circuit 320a includes capacitor C3, input pad I1a and output pad I1b.

[0151] Capacitor C3 includes a first terminal and a second terminal. The first terminal of capacitor C1a is coupled to the input pad I1a. The second terminal of capacitor C1a is coupled to the output pad I1b.

[0152] Circuit 320b includes input pad I2a, a set of nodes NO and output pad I2b.

[0153] This group of nodes NO is coupled between the input pad I2a and the output pad I2b. In some embodiments, this group of nodes NO is an open circuit. In some embodiments, this group of nodes NO is a short circuit.

[0154] Test system 112 can use circuit 320b to determine the estimated parasitic capacitance CP1 of capacitor C3. For example, in some embodiments, an LCR meter ( Figure 1The test section 120b (shown in the diagram) is coupled to the input pad I2a and the output pad I2b, and the parasitic capacitance CP2 of the circuit 320b is measured. In some embodiments, the circuit 320b includes one or more interconnects containing one or more wires, the size, shape, and arrangement of which are similar to one or more interconnects (containing one or more wires) of the circuit 320a. Therefore, the parasitic capacitance CP2 of the circuit 320b is estimated to be substantially equal to the parasitic capacitance CP1 of the circuit 320a.

[0155] The test system 112 can use circuit 320a to determine the measured capacitance C3m of capacitor C3.

[0156] In some embodiments, capacitor C3 is used to simulate capacitor C1a. In some embodiments, capacitor C3 is a MOM capacitor. In some embodiments, capacitor C3 is a capacitor of the same type as capacitor C1a or C1b. In some embodiments, capacitors C3, C1a, and C1b are identical in size, material, and area. Capacitor C3 is adjacent to capacitor C1a. In some embodiments, the two elements are adjacent to each other when no other similar elements exist between them. In some embodiments, capacitor C3 is adjacent to capacitor C1b.

[0157] In some embodiments, capacitor C3 is separated from capacitor C1a by a distance D1a ( Figure 4 (As shown). In some embodiments, distance D1a is based on the manufacturing process of circuit 300. In some embodiments, as distance D1a decreases, test system 112 can use capacitor C3 to estimate the capacitance of capacitor C1a. For example, in some embodiments, as distance D1a decreases, capacitor C3 exhibits similar characteristics to capacitor C1a, so test system 112 can use capacitor C3 to estimate the capacitance of capacitor C1a. In some embodiments, the capacitance and / or impedance of capacitor C3 are measured by an LCR meter in test system 112.

[0158] In some embodiments, the distance D1a ranges from about 1 micrometer (µm) to 1000 µm. In some embodiments, the distance D1a ranges from about 1 µm to 10000 µm. Other values ​​or ranges for the distance D1a are within the scope of one embodiment of this disclosure.

[0159] In some embodiments, capacitors C3 and C1a are housed in the same die. In some embodiments, capacitors C3 and C1a are housed in the same test lead.

[0160] In some embodiments, direct measurement of capacitor C1a would cause a change in the oscillation frequency F1, which would reduce the accuracy of determining the inductance of inductor L1a. Therefore, the capacitance of capacitor C1a is determined by measuring the adjacent capacitor C3 with an LCR meter, rather than by directly measuring capacitor C1a. In some embodiments, since capacitor C3 is electrically isolated from capacitor C1a, the oscillation frequency F1 of signal FO1 does not affect the accuracy of measuring the capacitance of capacitor C3.

[0161] In some embodiments, during capacitance and / or impedance measurement of capacitor C3, an LCR meter is coupled to input pad I1a and output pad I1b to send signal CM' to capacitor C3 and to receive signal CM in response to signal CM'.

[0162] In some embodiments, there is a relationship between the actual capacitance C3a of capacitor C3, the measured capacitance C3m of capacitor C3, and the parasitic capacitance CP2 of circuit 320b, which is represented by the following equation 3:

[0163] C3a = C3m – CP2(3).

[0164] In some embodiments, during the wafer acceptance test of the buck circuit 202, the test system 112 is used to determine the oscillation frequency F1 of the signal FO1 based on the oscillation frequency F2 of the signal FOUT, and to determine the capacitance of the capacitor C1a. Then, the test system 112 is used to determine the self-inductance of the inductor L1a by using Equation 2 and the determined oscillation frequency F1 of the signal FO1 and the estimated capacitance C3a of the capacitor C1a.

[0165] In some embodiments, during one or more chemical mechanical planarization (CMP) operations on at least one of capacitors C1a, C1b, or C3, the loading effect may cause uneven grinding of at least two of capacitors C1a, C1b, or C3, resulting in capacitance mismatch.

[0166] In some embodiments, the accuracy of LCR measurement decreases as the capacitance mismatch between capacitor C1a and capacitor C3 increases. In some embodiments, the accuracy of LCR measurement increases as the capacitance mismatch between capacitor C1a and capacitor C3 decreases.

[0167] In some embodiments, if the capacitance mismatch between capacitor C1a and capacitor C3 is less than or equal to 1% to 5%, then estimating the capacitance of capacitor C1a and capacitor C3 as substantially the same is sufficient to produce an accurate capacitance value for capacitor C1a (e.g., C3a).

[0168] In some embodiments, if the capacitance mismatch between capacitor C1a and capacitor C3 is greater than 1% to 5%, estimating the capacitance of capacitor C1a and capacitor C3 as substantially the same may result in a less accurate capacitance value for capacitor C1a (e.g., C3a).

[0169] In some embodiments, wafer acceptance testing cannot be used to determine the inductance of inductor L1a when the accuracy of the estimated capacitance C3a of capacitor C3 does not meet the ESR criterion. For example, in some embodiments, wafer acceptance testing cannot be used to determine the inductance of inductor L1a when the accuracy of the estimated capacitance C3a of capacitor C3 decreases.

[0170] In some embodiments, the parasitic capacitance CP2 of circuit 320b is less than 1% of the measured capacitance C3m of capacitor C3 (e.g., the ESR criterion described below). In some embodiments, as the parasitic capacitance CP2 of circuit 320b decreases to less than 1% of the measured capacitance C3m of capacitor C3, the accuracy of the estimated capacitance C3a of capacitor C3 increases during wafer acceptance testing. In some embodiments, as the parasitic capacitance CP2 of circuit 320b increases to greater than 1% of the measured capacitance C3m of capacitor C3, the accuracy of the estimated capacitance C3a of capacitor C3 decreases during wafer acceptance testing. Similarly, the same ESR criterion for the parasitic capacitance CP2 of circuit 320b, which is less than 1% of the measured capacitance C3m of capacitor C3, also applies to the impedance of capacitor C3, as expressed by Equation 4 below:

[0171] ESR < 0.01 × ABS(Zc)(4).

[0172] Where ABS(Zc) is the absolute value of impedance Zc, Zc is the impedance of capacitor C3, and ESR is the criterion for the maximum value of the impedance of parasitic capacitance CP2. In other words, according to some embodiments, the maximum value of the impedance of parasitic capacitance CP2 is less than 0.01 times ABS(Zc), where ABS(Zc) is the absolute value of impedance Zc, thereby ensuring that the estimated capacitance C3a of capacitor C3 is accurate and can be used as the capacitance of capacitor C1a.

[0173] In some embodiments, there is a relationship between the impedance Zc, the measured capacitance C3m of capacitor C3, and the oscillation frequency F1, which is represented by the following equation 5:

[0174] ABS(Zc) =1 / (2×pi×F1×C3m)(5).

[0175] For example, according to some embodiments, if the capacitance of capacitor C3 is 100 picofarads (pF) at an oscillation frequency of 1 MHz, then the impedance Zc is 1590 ohms, and 0.01 times 1590 ohms equals 15.90 ohms, and the ESR < 15.9 ohms. In these embodiments, if the parasitic impedance of parasitic capacitance CP2 is greater than 15.9 ohms, the ESR criterion is not met, and wafer acceptance testing cannot be used to accurately determine the inductance of inductor L1a. In these embodiments, if the parasitic impedance of parasitic capacitance CP2 is less than 15.9 ohms, the ESR criterion is met, and wafer acceptance testing can be used to accurately determine the inductance of inductor L1a.

[0176] Other types, configurations, or numbers of capacitors used for capacitor C3 are within the scope of one embodiment of this disclosure.

[0177] Other types, configurations, or numbers of capacitors used in circuit 320a are within the scope of one embodiment of this disclosure.

[0178] Other types, configurations, or numbers of capacitors used in circuit 320b are within the scope of one embodiment of this disclosure.

[0179] In some embodiments, circuit 300 achieves one or more of the benefits described herein.

[0180] Other configurations, types, or numbers of circuit elements in circuit 300 are within the scope of one embodiment of this disclosure.

[0181] Figure 4 This is a top-level schematic diagram of an integrated circuit 400 according to some embodiments.

[0182] Integrated Circuit 400 is Figure 1 One embodiment of wafer 101, therefore a similar detailed description is omitted.

[0183] Integrated Circuit 400 is Figure 2 Part of circuit 200 Figure 3 Part of circuit 300 or Figure 5 This is one embodiment of a portion of the circuit 500, therefore a similar detailed description is omitted.

[0184] Integrated Circuit 400 is Figure 1 This is one embodiment of circuit 102 and this set of test circuits 104, therefore a similar detailed description is omitted.

[0185] Integrated circuit 400 includes region 402, region 404 and region 406.

[0186] In some embodiments, region 402 is Figure 1 Circuit 102 or Figure 2One embodiment of the step-down circuit 202, and region 404 is Figure 1 This set of test circuits 104 or Figure 2 One embodiment of circuit 204 is described, therefore a similar detailed description is omitted.

[0187] In some embodiments, region 406 is Figure 1 Circuit 102 or Figure 2 One embodiment of the step-down circuit 202 is described, therefore a similar detailed description is omitted.

[0188] Area 402 includes inductors L1a, L1b, L2a, and L2b.

[0189] Inductors L2a and L2b are connected together.

[0190] In some embodiments, inductor L1a is magnetically coupled to inductor L2a. In some embodiments, inductor L1b is magnetically coupled to inductor L2b.

[0191] Region 404 includes capacitors C1a, C1b and C3.

[0192] Each of the inductors L1a, L1b, C1a, and C1b is coupled together.

[0193] like Figure 4 As shown, capacitor C1a and capacitor C3 are separated by a distance D1a in the Y direction.

[0194] In some embodiments, the first side of capacitor C1a is aligned with the corresponding first side of capacitor C3 in the Y direction. In some embodiments, the second side of capacitor C1a is aligned with the corresponding second side of capacitor C3 in the Y direction. In some embodiments, the second side of capacitor C1a is opposite to the first side of capacitor C1a. In some embodiments, the second side of capacitor C3 is opposite to the first side of capacitor C3.

[0195] In some embodiments, region 406 is similar to region 402, but region 406 is a buck converter circuit that can be used as part of an integrated voltage regulator (IVR) and is not electrically coupled to region 404, while region 402 is electrically coupled to region 404 and can be used in wafer acceptance testing, so a similar detailed description is omitted.

[0196] Region 406 includes inductors L1a, L1b, L2a, and L2b. In some embodiments, the inductors L1a, L1b, L2a, and L2b of region 406 are similar to the corresponding inductors L1a, L1b, L2a, and L2b of region 402, and therefore such detailed descriptions are omitted.

[0197] Other types, configurations, or numbers of circuit elements for one or more of regions 402, 404, or 406 are within the scope of one embodiment of this disclosure.

[0198] In some embodiments, integrated circuit 400 implements one or more of the benefits described herein.

[0199] Other configurations, types, or numbers of circuit elements in integrated circuit 400 are within the scope of one embodiment of this disclosure.

[0200] Figure 5 This is a circuit diagram of circuit 500 according to some embodiments.

[0201] Circuit 500 is Figure 3 A variant of circuit 300, therefore a similar detailed description is omitted. Figure 3 Compared to circuit 300, circuit 500 further includes bypass circuit 530 and buffer circuit 536, therefore a similar detailed description is omitted.

[0202] and Figure 3 Compared to circuit 300, frequency divider circuit 508 of circuit 500 replaces frequency divider circuit 208 of circuit 500, therefore a similar detailed description is omitted.

[0203] Circuit 500 is Figure 1 One embodiment of wafer 101, therefore a similar detailed description is omitted.

[0204] Circuit 500 is Figure 1 This is one embodiment of circuit 102 and this set of test circuits 104, therefore a similar detailed description is omitted.

[0205] Circuit 500 includes step-down circuit 202, circuit 320a, circuit 320b and circuit 504.

[0206] Circuit 504 is Figure 3 A variant of circuit 304, therefore a similar detailed description is omitted. Figure 3 Compared to circuit 304, circuit 504 further includes bypass circuit 530 and buffer circuit 536, therefore a similar detailed description is omitted.

[0207] and Figure 3Compared to circuit 304, circuit 504's frequency divider circuit 508 replaces circuit 304's frequency divider circuit 208, therefore a similar detailed description is omitted.

[0208] Frequency divider circuit 508 is coupled to voltage supply VDD2, buffer circuit 206, bypass circuit 530 and buffer circuit 536.

[0209] In some embodiments, the voltage supply VDD2 is the same as the voltage supply VDD1.

[0210] In some embodiments, the voltage supply VDD2 is different from the voltage supply VDD1.

[0211] In some embodiments, the voltage supply VDD2 may be adjusted to be different from the voltage supply VDD1. In some embodiments, when the voltage supply VDD1 increases to be greater than the voltage supply VDD2, the current flowing through inductor I1a will increase, thereby increasing the inductance of inductor L1a. In some embodiments, when the voltage supply VDD1 decreases to be less than the voltage supply VDD2, the current flowing through inductor I1a will decrease, thereby decreasing the inductance of inductor L1a.

[0212] In some embodiments, frequency divider circuit 508 is similar to frequency divider circuit 208, therefore a similar detailed description is omitted.

[0213] The frequency divider circuit 508 is used to receive the oscillation signal FO2 from the buffer circuit 206, the bypass signal BP from the bypass circuit 530, and the selection signal SEL. In some embodiments, the selection signal SEL is controlled by a controller (e.g., Figure 10 The system 1000 in the figure is generated. In some embodiments, at least one of the oscillation signal FO2 or the bypass signal BP is also referred to as the intermediate signal FI1. Figure 6 (As shown).

[0214] The frequency divider circuit 508 is used to generate an oscillation signal FO3 in response to one of the bypass signal BP, the selection signal SEL, and the oscillation signal FO2 or the bypass signal BP.

[0215] In some embodiments, the frequency divider circuit 508 generates an oscillation signal FO3 in response to a first logic state of the oscillation signal FO2 and the selection signal SEL. In some embodiments, the frequency divider circuit 508 generates an oscillation signal FO3 in response to a second logic state of the bypass signal BP and the selection signal SEL. In some embodiments, the second logic state of the selection signal is different from the first logic state of the selection signal.

[0216] In some embodiments, the oscillation signal FO3 has an oscillation frequency F2.

[0217] The output of the frequency divider circuit 508 is coupled to the input of the buffer circuit 536.

[0218] Other types, configurations, or numbers of frequency divider circuits 508 are within the scope of one embodiment of this disclosure.

[0219] The buffer circuit 536 is coupled to the voltage supply VDD2, the frequency divider circuit 508, and the output pad 250.

[0220] The output of the buffer circuit 536 is coupled to the output pad 250.

[0221] In some embodiments, buffer circuit 536 is similar to buffer circuit 206, therefore a similar detailed description is omitted.

[0222] The input terminal of the buffer circuit 536 is used to receive the oscillation signal FO3, and the output terminal of the buffer circuit 536 is used to output the signal FOUT. In some embodiments, the signal FOUT has an oscillation frequency F2. In some embodiments, the buffer circuit 536 is used to output the signal FOUT in response to the oscillation signal FO2.

[0223] In some embodiments, the buffer circuit 536 is also referred to as a "buffer amplifier circuit".

[0224] Other types, configurations, or numbers of circuit elements used for the buffer circuit 536 are within the scope of one embodiment of this disclosure.

[0225] The bypass circuit 530 is coupled to the frequency divider circuit 508. The bypass circuit 530 is used to generate the bypass signal BP.

[0226] In some embodiments, the bypass signal BP is similar to the oscillation signal FO2, therefore a similar detailed description is omitted. In some embodiments, the bypass signal BP has an oscillation frequency F1. In some embodiments, the bypass circuit 530 is... Figure 10 Part of system 1000 shown in the diagram.

[0227] Other types, configurations, or numbers of circuit elements for the bypass circuit 530 are within the scope of one embodiment of this disclosure.

[0228] In some embodiments, circuit 500 achieves one or more of the benefits described herein.

[0229] Other configurations, types, or numbers of circuit elements in circuit 500 are within the scope of one embodiment of this disclosure.

[0230] Figure 6 This is a circuit diagram of circuit 600 according to some embodiments.

[0231] Circuit 600 is Figure 5One embodiment of the frequency divider circuit 508 is described, therefore a similar detailed description is omitted.

[0232] Circuit 600 includes a multiplexer 602 and a frequency divider circuit 604.

[0233] Multiplexer 602 is coupled to voltage supply VDD2 and frequency divider circuit 604.

[0234] Multiplexer 602 is used to output an oscillation signal FO2 or a bypass signal BP as an intermediate signal FI1 in response to the selection signal SEL. In some embodiments, the intermediate signal FI1 is the oscillation signal FO2 or the bypass signal BP.

[0235] In some embodiments, multiplexer 602 outputs an oscillation signal FO2 as an intermediate signal FI1 in response to a first logic state of the selection signal SEL. In some embodiments, multiplexer 602 outputs a bypass signal BP as an intermediate signal FI1 in response to a second logic state of the selection signal SEL. In some embodiments, the second logic state of the selection signal is different from the first logic state of the selection signal.

[0236] Other configurations, types, or numbers of circuit elements in the multiplexer 602 are within the scope of one embodiment of this disclosure.

[0237] Frequency divider circuit 604 is coupled to multiplexer 602 and voltage supply VDD2. Frequency divider circuit 604 is used to receive intermediate signal FI1 and generate oscillation signal FO3 in response to intermediate signal FI1. In some embodiments, oscillation signal FO3 has oscillation frequency F2. In some embodiments, frequency divider circuit 604 is similar to frequency divider circuit 208, therefore a similar detailed description is omitted.

[0238] Other configurations, types, or numbers of circuit elements in the frequency divider circuit 604 are within the scope of one embodiment of this disclosure.

[0239] In some embodiments, circuit 600 achieves one or more of the benefits described herein.

[0240] Other configurations, types, or numbers of circuit elements in circuit 600 are within the scope of one embodiment of this disclosure.

[0241] Figure 7 This is a circuit diagram of a frequency divider circuit 700 according to some embodiments.

[0242] The frequency divider circuit 700 is... Figures 2 to 3 Frequency divider circuit 208 Figure 5 508 frequency divider circuit or Figure 6 One embodiment of the frequency divider circuit 604 is described, therefore a similar detailed description is omitted.

[0243] The frequency divider circuit 700 includes a flip-flop 702.

[0244] The 700 frequency divider circuit is a counter circuit that divides the frequency by 2.

[0245] Flip-flop 702 is a 1-bit flip-flop. Other numbers of bits or other corresponding numbers of flip-flops in the frequency divider circuit 700 are within the scope of one embodiment of this disclosure.

[0246] Trigger 702 is a DQ trigger. In some embodiments, trigger 702 comprises an SR trigger, a T trigger, a JK trigger, or the like. Other types of triggers or configurations for trigger 702 are within the scope of one embodiment of this disclosure.

[0247] The trigger 702 includes a clock input CLK, which receives the oscillation signal FOSC1. In some embodiments, the oscillation signal FOSC1 is an embodiment of the oscillation signal FO2, the signal FI1, or the bypass signal BP, and therefore a similar detailed description is omitted.

[0248] The trigger 702 further includes an output terminal Q1, which is used to output an oscillation signal FOSC2. In some embodiments, the oscillation signal FOSC2 is... Figures 5 to 6 The oscillation signal FO3 or Figures 2 to 3 One embodiment of the signal FOUT is given, therefore a similar detailed description is omitted.

[0249] The trigger 702 further includes an inverting output terminal Q1B and a data input terminal D. The inverting output terminal Q1B is coupled to the data input terminal D. In some embodiments, the inverting output terminal Q1B is used to output an inverted version of the oscillation signal FOSC2 to the data input terminal D. In some embodiments, the oscillation signal FOSC2B is an inverted version of the oscillation signal FOSC2. In some embodiments, the data input terminal D is used to receive an inverted version of the oscillation signal FOSC2 (e.g., FOSC2B).

[0250] Other types, configurations, or numbers of triggers are within the scope of one embodiment of this disclosure.

[0251] In some embodiments, the frequency divider circuit 700 achieves one or more of the benefits described herein.

[0252] Other configurations, types, or numbers of circuit elements in the frequency divider circuit 700 are within the scope of one embodiment of this disclosure.

[0253] Figures 8A to 8B This is a flowchart of a method 800 for performing wafer acceptance testing on a circuit according to some embodiments.

[0254] In some embodiments, Figures 8A to 8B This is a flowchart of a method 800 for performing wafer acceptance testing on circuits (such as wafer 101, circuit 200, circuit 300, integrated circuit 400, or circuit 500), and similar detailed descriptions are omitted for the sake of brevity.

[0255] In some embodiments, a wafer acceptance test is performed on one or more of wafer 101, circuit 200, circuit 300, integrated circuit 400, or circuit 500, resulting in one or more of the wafer acceptance tests being performed on the circuit (such as wafer 101, circuit 200, circuit 300, integrated circuit 400, circuit 500, circuit 600, frequency divider circuit 700, or system 1000), and similar detailed descriptions are omitted for brevity.

[0256] It should be understood that, Figures 8A to 8B Additional operations may be performed before, during, and / or after method 800 as described herein, and this document may only briefly describe some of these additional operations. It should be understood that method 800 utilizes... Figure 1 System 100 Figure 2 Circuit 200, Figure 3 Circuit 300 Figure 4 Integrated circuit 400, Figure 5 Circuit 500, Figure 6 Circuit 600, Figure 7 700 frequency divider circuit or Figure 10 The figure describes one or more features of at least one of the systems 1000 in the figure, and similar detailed descriptions are omitted for brevity.

[0257] In some embodiments, other orders of operation of method 800 are within the scope of one implementation of this disclosure. Method 800 includes exemplary operations, but the operations are not necessarily performed in the order illustrated. Operations may be appropriately added, substituted, ordered, and / or eliminated according to the spirit and scope of the disclosed embodiments. In some embodiments, one or more operations of method 800 are not performed.

[0258] In operation 802 of method 800, a first oscillation frequency of the first circuit of the first LC resonant oscillator is determined.

[0259] In some embodiments, the first LC resonant oscillator includes a first circuit and a test circuit.

[0260] In some embodiments, operation 802 is performed by at least one of test system 112, test section 120a, or system 1000.

[0261] In some embodiments, the first oscillation frequency of method 800 includes an oscillation frequency F1.

[0262] In some embodiments, the first circuit of method 800 includes at least one of circuit 102, step-down circuit 202, inductor L1a, inductor L1b, inductor L2a, or inductor L2b.

[0263] In some embodiments, the test circuit of method 800 includes at least one of test circuit 104, circuit 104a, circuit 104b, circuit 204, or circuit 504.

[0264] In some embodiments, operation 802 includes at least one of operation 804 or operation 806.

[0265] In operation 804 of method 800, a first signal is generated.

[0266] In some embodiments, the first signal is generated by at least one of the first circuit or capacitor C1a or C1b.

[0267] In some embodiments, the first signal has a first oscillation frequency.

[0268] In some embodiments, the first signal includes at least one or more of signals FO1.

[0269] In operation 806 of method 800, a second signal is generated in response to the first signal.

[0270] In some embodiments, the second signal represents the value of the first oscillation frequency.

[0271] In some embodiments, the second signal is generated by a test circuit.

[0272] In some embodiments, the second signal includes at least one or more of the signal FOUT or the oscillation signal FOSC2.

[0273] In operation 808 of method 800, the first capacitance of the first capacitor of the first circuit is determined.

[0274] In some embodiments, the first capacitance of the first capacitor of the first circuit is determined by at least one of the test system 112, the test section 120b, or the system 1000.

[0275] In some embodiments, the first capacitor of the first circuit includes at least one of capacitors C1a, C1b, or C3.

[0276] In some embodiments, operation 808 includes at least one of operation 810, operation 812, or operation 814.

[0277] In operation 810 of method 800, the impedance ZC3 or capacitance C3m of the second capacitor of the test circuit is measured.

[0278] In some embodiments, an LCR meter measures the impedance or capacitance of a second capacitor in the test circuit. In some embodiments, the LCR meter is test section 120b.

[0279] In some embodiments, the second capacitor of the test circuit includes at least one of capacitors C3.

[0280] In operation 812 of method 800, the second capacitance of the second capacitor of the test circuit is determined at least based on the impedance or capacitance of the second capacitor (C3) of the first circuit and the measurement frequency of the LCR meter (e.g., oscillation frequency F1).

[0281] In operation 814 of method 800, the first capacitance of the first capacitor of the first circuit is determined based on the second capacitance of the second capacitor of the first circuit.

[0282] In some embodiments, at least one of operations 810, 812, or 814 is performed by at least one of test system 112, test section 120b, or system 1000.

[0283] In some embodiments, at least one of operations 810, 812, or 814 is performed by using one or more of equations 1, 2, 3, 4, or 5.

[0284] In operation 816 of method 800, the inductance of the first circuit is determined based on the first oscillation frequency and the first capacitance of the first capacitor.

[0285] In some embodiments, the inductance of the first circuit is determined by at least one of test system 112 or system 1000.

[0286] In some embodiments, the inductance of the first circuit includes the inductance of at least one of inductors L1a, L1b, L2a, or L2b.

[0287] In some embodiments, operation 816 is performed using one or more of equations 1, 2, 3, 4, or 5.

[0288] In operation 818 of method 800, it is determined whether the frequency divider circuit or the first LC resonant oscillator has malfunctioned.

[0289] In some embodiments, when the signal FOUT does not contain an oscillating output signal, operation 818 of method 800 is performed.

[0290] In some embodiments, operation 818 includes at least one of operation 820 or operation 822.

[0291] In some embodiments, at least one of operations 818, 820, or 822 is performed by at least one of test system 112 or system 1000.

[0292] In operation 820 of method 800, it is determined that the frequency divider circuit has failed to respond to the second signal failing to contain an oscillation signal and has malfunctioned, and the selection signal has a first logic state; or it is determined that the frequency divider circuit has not failed to respond to the second signal containing an oscillation signal and has not malfunctioned, and the selection signal has a first logic state.

[0293] In some embodiments, the first logic state is logic 1 and the second logic state is logic 0. In some embodiments, the first logic state is logic 0 and the second logic state is logic 1.

[0294] In operation 822 of method 800, it is determined that the first LC resonant oscillator has failed to respond to the second signal by failing to contain an oscillation signal and that the selection signal has a second logic state different from the first logic state, or it is determined that the first LC resonant oscillator has not failed to respond to the second signal by containing an oscillation signal and that the selection signal has a second state.

[0295] In some embodiments, the first LC resonant oscillator includes an inductor L1a, L1b, L2a or L2b, a capacitor C1a or C1b, or at least one of an NMOS transistor N1 or N2.

[0296] In some embodiments, wafer acceptance testing is performed by test equipment 120.

[0297] Through operation method 800, Figure 1 The system 100, circuit 200, circuit 300, integrated circuit 400, circuit 500, circuit 600, frequency divider circuit 700, or system 1000 shall operate to achieve the benefits discussed herein.

[0298] In some embodiments, one or more of the operations of method 800 are not performed. Furthermore, Figures 2 to 3 The various PMOS or NMOS transistors illustrated in the figures have specific dopant types (e.g., N-type or P-type) and are used for illustrative purposes. One embodiment of this disclosure is not limited to a specific transistor type, and... Figures 2 to 3 and Figure 5 One or more of the PMOS or NMOS transistors illustrated in the diagram may be replaced by corresponding transistors of different transistor / dopant types. Similarly, the low or high logic values ​​of various signals used in the above description are also for illustrative purposes. An embodiment of this disclosure is not limited to specific logic values ​​when a signal is activated and / or deactivated. Different logic values ​​are chosen within the scope of various embodiments.

[0299] exist Figures 2 to 3 and Figure 5 Different numbers of transistors are selected within the scope of various embodiments. Figures 1 to 7Different numbers of individual elements are selected within the scope of various embodiments.

[0300] Figures 9A to 9B These are flowcharts of corresponding methods 900A to 900B for performing wafer acceptance tests on circuits according to some embodiments.

[0301] In some embodiments, methods 900A to 900B are Figures 8A to 8B The embodiment of operation 806 is described above, and similar detailed descriptions are omitted for the sake of brevity.

[0302] It should be understood that, Figures 9A to 9B Additional operations may be performed before, during, and / or after the methods 900A to 900B described herein, and only a few of these additional operations may be briefly described herein. It should be understood that methods 900A to 900B utilize... Figure 1 System 100 Figure 2 Circuit 200, Figure 3 Circuit 300 Figure 4 Integrated circuit 400, Figure 5 Circuit 500, Figure 6 Circuit 600, Figure 7 700 frequency divider circuit or Figure 10 The figure describes one or more features of at least one of the systems 1000 in the figure, and similar detailed descriptions are omitted for brevity.

[0303] In some embodiments, other orders of operations of methods 900A to 900B are within the scope of one embodiment of this disclosure. Methods 900A to 900B include exemplary operations, but the operations are not necessarily performed in the order illustrated. Operations may be appropriately added, substituted, ordered, and / or eliminated according to the spirit and scope of the disclosed embodiments. In some embodiments, one or more operations of methods 900A to 900B are not performed.

[0304] In some embodiments, method 900A includes one or more of operations 902, 904, or 906.

[0305] In some embodiments, method 900B includes one or more of operations 902, 904, 908, 910, or 912.

[0306] In operation 902 of methods 900A and 900B, the DC portion of the first signal is blocked, and the AC portion of the first signal is transmitted.

[0307] In some embodiments, the DC portion of the first signal is blocked by capacitor C2b, and the AC portion of the first signal is transmitted by a second capacitor.

[0308] In some embodiments, the second capacitor is coupled to the first circuit and the first capacitor.

[0309] In some embodiments, the second capacitor in methods 900A and 900B includes at least capacitor C2b.

[0310] In operation 904 of methods 900A and 900B, a first oscillation signal is output in response to the AC portion of the first signal.

[0311] In some embodiments, the first oscillation signal is output by the first buffer circuit.

[0312] In some embodiments, the first buffer circuit of methods 900A and 900B includes at least buffer circuit 206.

[0313] In some embodiments, the first oscillation signal of methods 900A and 900B includes at least an oscillation signal FO2.

[0314] In some embodiments, the first buffer circuit is coupled to the second capacitor.

[0315] In operation 906 of method 900A, a second oscillation signal is generated in response to the first oscillation signal.

[0316] In some embodiments, the second oscillation signal is generated by at least one of frequency divider circuits 208 or 700.

[0317] In some embodiments, the second oscillation signal of method 900A includes at least a signal FOUT. In some embodiments, the second oscillation signal of method 900A has a second oscillation frequency. In some embodiments, the second oscillation frequency of method 900A includes an oscillation frequency F2. In some embodiments, the second oscillation frequency is less than the first oscillation frequency.

[0318] In some embodiments, the frequency divider circuit is coupled to the first buffer circuit. In some embodiments, the second oscillation signal of method 900A is a second signal.

[0319] In some embodiments, method 900B includes one or more of operations 902, 904, 908, 910, or 912.

[0320] In operation 908 of method 900A, the first oscillation signal or bypass signal BP responds to the selection signal SEL and is output as the first intermediate signal.

[0321] In some embodiments, when the first intermediate signal is output by the multiplexer 602, a first oscillation signal or a bypass signal is output.

[0322] In some embodiments, the first intermediate signal includes either a first oscillation signal or a bypass signal.

[0323] In some embodiments, the first intermediate signal includes at least one of intermediate signal FI1 or signal FO2. In some embodiments, the multiplexer is coupled to the first buffer.

[0324] In operation 910 of method 900A, a second oscillation signal is generated in response to the first intermediate signal.

[0325] In some embodiments, the second oscillation signal is generated by the frequency divider circuit 508.

[0326] In some embodiments, the second oscillation signal of method 900B includes at least an oscillation signal FO3. In some embodiments, the second oscillation signal of method 900B has a second oscillation frequency. In some embodiments, the second oscillation frequency of method 900B includes an oscillation frequency F2. In some embodiments, the second oscillation frequency is less than the first oscillation frequency.

[0327] In some embodiments, the frequency divider circuit 508 is coupled to a multiplexer.

[0328] In operation 912 of method 900A, a third oscillation signal is output in response to the second oscillation signal.

[0329] In some embodiments, the third oscillation signal of method 900B includes at least the signal FOUT.

[0330] In some embodiments, the third oscillation signal is output by the second buffer circuit. In some embodiments, the second buffer circuit includes at least one of the buffer circuits 536.

[0331] In some embodiments, the second buffer circuit is coupled to the frequency divider circuit 508. In some embodiments, the third oscillation signal is the second signal (e.g., FOUT). In some embodiments, the multiplexer is coupled to the second buffer circuit.

[0332] By operating at least one of 900A or 900B Figure 1 The system 100, circuit 200, circuit 300, integrated circuit 400, circuit 500, circuit 600, frequency divider circuit 700, or system 1000 shall operate to achieve the benefits discussed herein.

[0333] Figure 10 The figure is a schematic diagram of a system 1000 according to some embodiments. In some embodiments, the system 1000 is Figure 1 An embodiment of at least one test device 120 is provided, therefore a similar detailed description is omitted.

[0334] In some embodiments, system 1000 is Figure 1 Test system 112 Figure 1 Test equipment 120 Figure 1 Test section 120a, Figure 1 An embodiment of at least one of the test section 120b or bypass circuit 530 is used, therefore a similar detailed description is omitted.

[0335] In some embodiments, system 1000 is used to control one or more of test equipment 120, test system 112, test section 120a, test section 120b, this set of test circuits 104, frequency divider circuit 508, or multiplexer 602, and therefore similar detailed descriptions are omitted.

[0336] In some embodiments, the system 1000 is used to generate one or more of the following: signal CM', selection signal SEL, or bypass signal BP.

[0337] In some embodiments, system 1000 is used to perform one or more operations described herein, including one or more operations of at least one of methods 800, 900A or 900B.

[0338] System 1000 includes a hardware processor 1002 and a non-transitory computer-readable memory 1004 (also referred to as "memory 1004" or "memory 1004"), which is encoded with (i.e. stored) computer program code 1006, i.e., an executable instruction set 1006.

[0339] The computer-readable memory 1004 is configured to interface with at least one or more of the test equipment 120, test system 112, test section 120a, test section 120b, this set of test circuits 104, frequency divider circuit 508, bypass circuit 530, and multiplexer 602, therefore similar detailed descriptions are omitted.

[0340] Processor 1002 is electrically coupled to computer-readable memory 1004 via bus 1008. Processor 1002 is also electrically coupled to I / O interface 1010 via bus 1008. Network interface 1012 is also electrically connected to processor 1002 via bus 1008. Network interface 1012 is connected to network 1014, enabling processor 1002 and computer-readable memory 1004 to be connected to external components via network 1014. Processor 1002 is used to execute computer program code 1006 (non-transitory instructions) encoded in computer-readable memory 1004 so that system 1000 can be used to perform some or all of the operations described in at least one of methods 800, 900A, or 900B. In some embodiments, network 1014 is not part of system 1000.

[0341] In some embodiments, the processor 1002 is a central processing unit (CPU), a multiprocessor, a distributed processing readout circuit, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0342] In some embodiments, the computer-readable memory 1004 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor reading circuit (or device or apparatus). For example, the computer-readable memory 1004 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), rigid disk, and / or optical disk. In some embodiments using optical disk, the computer-readable memory 1004 includes compact disk-read-only memory (CD-ROM), compact disk-read / write (CD-R / W), and / or digital video optical disc (DVD).

[0343] In some embodiments, memory 1004 stores computer program code 1006 for causing system 1000 to perform one or more operations of at least one of methods 800, 900A, or 900B. In some embodiments, memory 1004 also stores information for performing at least one of methods 800, 900A, or 900B, as well as information generated during the execution of at least one of methods 800, 900A, or 900B, such as signal group 1020 and user interface 1028, and / or executable instruction sets for performing one or more operations of at least one of methods 800, 900A, or 900B.

[0344] In some embodiments, memory 1004 stores instructions (e.g., computer program code 1006) for interfacing with at least one or more of test device 120, test system 112, test section 120a, test section 120b, the set of test circuits 104, frequency divider circuit 508, bypass circuit 530, or multiplexer 602. The instructions (e.g., computer program code 1006) enable processor 1002 to generate readable instructions from at least one or more of test device 120, test system 112, test section 120a, test section 120b, the set of test circuits 104, frequency divider circuit 508, bypass circuit 530, or multiplexer 602 to effectively implement one or more operations of at least one of methods 800, 900A, or 900B during operation of system 100, circuit 200, circuit 300, integrated circuit 400, circuit 500, circuit 600, or frequency divider circuit 700.

[0345] System 1000 includes an I / O interface 1010. The I / O interface 1010 is coupled to an external circuit system. In some embodiments, the I / O interface 1010 includes a keyboard, keypad, mouse, trackball, touchpad, and / or cursor arrow keys for transmitting information and commands to processor 1002.

[0346] System 1000 also includes a network interface 1012 coupled to processor 1002. Network interface 1012 allows system 1000 to communicate with network 1014, and one or more other computer reading circuits are connected to network 1014. Network interface 1012 includes a wireless network interface such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or a wired network interface such as ETHERNET, USB, or IEEE-884. In some embodiments, at least one of methods 800, 900A, or 900B is implemented in two or more systems 1000, and information (such as signal groups and user interfaces) is exchanged between different systems 1000 via network 1014.

[0347] System 1000 is used to receive information related to a set of data via I / O interface 1010 or network interface 1012. This information is stored as a signal group 1020 in computer-readable medium 1004. In some embodiments, the signal group includes at least one of signal CM, signal FOUT, signal CM', selection signal SEL, or bypass signal BP.

[0348] System 1000 is used to receive information related to the user interface through I / O interface 1010 or network interface 1012. This information is stored as user interface 1028 in computer-readable media 1004.

[0349] Other configurations of the system 1000 are within the scope of one embodiment of this disclosure.

[0350] In some embodiments, one or more of the operations of methods 900A to 900B are not performed. Furthermore, Figures 2 to 3 and Figure 5 The various PMOS or NMOS transistors illustrated in the figures have specific dopant types (e.g., N-type or P-type) and are for illustrative purposes. Embodiments of this disclosure are not limited to specific transistor types, and... Figures 2 to 3 and Figure 5 One or more of the PMOS or NMOS transistors illustrated in the diagram may be replaced by corresponding transistors of different transistor / dopant types. Similarly, the low or high logic values ​​of the various signals used in the above description are also for illustrative purposes. Embodiments of this disclosure are not limited to specific logic values ​​at which signals are activated and / or deactivated. Different logic values ​​are chosen within the scope of various embodiments.

[0351] exist Figures 2 to 3 and Figure 5 Different numbers of transistors are selected within the scope of various embodiments. Figures 1 to 7 Different numbers of individual elements are selected within the scope of various embodiments.

[0352] Those skilled in the art will readily recognize that one or more of the disclosed embodiments achieve one or more of the advantages set forth above. After reading the above specification, those skilled in the art will be able to implement various modifications, equivalent substitutions, and various other embodiments as broadly disclosed herein. Therefore, the intent to protect any embodiment of this disclosure is limited only to the definitions contained in the appended claims and their equivalents.

[0353] One aspect of this description relates to a system for testing a wafer. In some embodiments, the system includes a first circuit for generating a first signal having a first oscillation frequency. In some embodiments, the system further includes a test circuit coupled to the first circuit for generating a second signal in response to the first signal, the second signal representing a value of the first oscillation frequency, and for generating a third signal representing a value of a first capacitance of a first capacitor in the test circuit, the second signal having a second oscillation frequency less than the first oscillation frequency. In some embodiments, the system further includes a test system coupled to the test circuit for receiving the second and third signals and for performing wafer acceptance testing on the first circuit, thereby determining the inductance of the first circuit in response to the second and third signals. In some embodiments, the first circuit includes: a first inductor coupled between a first voltage supply and a first node; and a second inductor coupled between the first voltage supply and a second node. In some embodiments, the test circuit includes: a first capacitor coupled at least to a first node; a second capacitor coupled at least to the first capacitor and a second node; and a cross-coupled transistor pair coupled to at least one of the first capacitor, the second capacitor, the first node, the second node, a first inductor, or a second inductor; wherein the first capacitor and the second capacitor are connected in parallel with the first inductor and the second inductor. In some embodiments, the first capacitor, the second capacitor, the first inductor, the second inductor, and the cross-coupled transistor pair are configured as an inductor-capacitor oscillator circuit. In some embodiments, the test circuit further includes: a third capacitor coupled between a first pad and a second pad, adjacent to the first capacitor, and used to generate a third signal; and a fourth capacitor coupled at least to the second capacitor and the third node. In some embodiments, the test circuit further includes: a buffer circuit coupled to a fourth capacitor and configured to receive a first signal and output a first oscillation signal having a first oscillation frequency; and a frequency divider circuit coupled to the buffer circuit and the test system and configured to receive the first oscillation signal and generate a second oscillation signal in response to the first oscillation signal, the second oscillation signal having a second oscillation frequency, wherein the second oscillation signal is a second signal. In some embodiments, the test circuit further includes: a fifth capacitor coupled to at least the first capacitor and the first node; and a pseudo-buffer circuit coupled to the fifth capacitor.In some embodiments, the cross-coupled transistor pair includes: a first n-type transistor, the first n-type transistor including a first terminal, a second terminal, and a third terminal; and a second n-type transistor, the second n-type transistor including a first terminal, a second terminal, and a third terminal; each of the first terminal of the first n-type transistor, the third terminal of the second n-type transistor, a first node, a first capacitor, and a first inductor being coupled together; each of the first terminal of the second n-type transistor, the third terminal of the first n-type transistor, a second node, a second capacitor, and a second inductor being coupled together; and each of the second terminals of the first n-type transistor and the second terminal of the second n-type transistor being coupled to a reference voltage supply.

[0354] Another aspect of this description relates to a method for performing wafer acceptance testing on a first circuit of an operating system. In some embodiments, this method includes determining, via a test system, a first oscillation frequency of a first circuit of a first inductor-capacitor resonant oscillator, the first inductor-capacitor resonant oscillator including the first circuit and a test circuit. In some embodiments, this method further includes determining, via the test system, a first capacitance of a first capacitor of the first circuit. In some embodiments, this method further includes determining, via the test system, an inductance of the first circuit based on the first oscillation frequency and the first capacitance of the first capacitor. In some embodiments, determining the first oscillation frequency of the first circuit includes: generating a first signal via the first circuit, the first signal having the first oscillation frequency; and generating a second signal via the test circuit in response to the first signal, the second signal representing a value of the first oscillation frequency. In some embodiments, generating the second signal in response to the first signal includes: blocking a DC portion of the first signal and transmitting an AC portion of the first signal via a second capacitor, the second capacitor being coupled to the first circuit and the first capacitor; and outputting a first oscillation signal via a first buffer circuit in response to the AC portion of the first signal, the first buffer circuit being coupled to the second capacitor. In some embodiments, generating a second signal in response to a first signal further includes: generating a second oscillation signal in response to a first oscillation signal via a frequency divider circuit, the second oscillation signal having a second oscillation frequency that is less than the first oscillation frequency, the frequency divider circuit being coupled to a first buffer circuit, wherein the second oscillation signal is a second signal. In some embodiments, generating a second signal in response to a first signal further includes: outputting the first oscillation signal or a bypass signal as a first intermediate signal via a multiplexer in response to a selection signal, the multiplexer being coupled to the first buffer circuit; generating a second oscillation signal in response to the first intermediate signal via a frequency divider circuit, the second oscillation signal having a second oscillation frequency that is less than the first oscillation frequency, the frequency divider circuit being coupled to the multiplexer; and outputting a third oscillation signal in response to the second oscillation signal via a second buffer circuit, the second buffer circuit being coupled to the frequency divider circuit, wherein the third oscillation signal is a second signal, the multiplexer being coupled to the second buffer circuit. In some embodiments, the method further includes: determining whether the frequency divider circuit or the first inductor-capacitor resonant oscillator has malfunctioned. In some embodiments, determining whether the frequency divider circuit or the first inductor-capacitor resonant oscillator has failed includes: determining that the frequency divider circuit has failed in response to the second signal failing to contain an oscillation signal, and the selection signal has a first state; or determining that the frequency divider circuit has not failed in response to the second signal containing an oscillation signal, and the selection signal has a first state.In some embodiments, determining whether the frequency divider circuit or the first inductor-capacitor resonant oscillator has failed further includes: determining that the first inductor-capacitor resonant oscillator has failed in response to the second signal failing to contain an oscillating signal, and the selection signal has a second state different from the first state; or determining that the first inductor-capacitor resonant oscillator has not failed in response to the second signal containing an oscillating signal, and the selection signal has a second state. In some embodiments, determining the first capacitance of the first capacitor of the first circuit includes: measuring the impedance of the second capacitor of the test circuit using an inductor, capacitor, and resistor; determining the second capacitance of the second capacitor of the test circuit based at least on the impedance of the second capacitor of the first circuit and the measurement frequency of the inductor, capacitor, and resistor; and determining the first capacitance of the first capacitor of the first circuit based on the second capacitance of the second capacitor of the first circuit.

[0355] Another aspect of this description relates to a system for testing a wafer. In some embodiments, the system includes a first circuit for generating a first signal having a first oscillation frequency. In some embodiments, the system further includes a test circuit coupled to the first circuit for generating a second signal in response to the first signal, the second signal representing a value of the first oscillation frequency, and for generating a third signal representing a value of a first capacitance of a first capacitor in the test circuit, the second signal having a second oscillation frequency less than the first oscillation frequency. In some embodiments, the system further includes a test system coupled to the test circuit for performing wafer acceptance testing on the first circuit, thereby determining the inductance of the first circuit in response to the second and third signals. In some embodiments, the test system includes a probe coupled to the test circuit for receiving the second and third signals from the test circuit. In some embodiments, the test system further includes a probe card coupled to the probe for receiving the second and third signals from the probe. In some embodiments, the test system further includes a test device coupled to a probe card and used to receive a second signal and a third signal from the probe card, and to determine the inductance of the first circuit. In some embodiments, the first circuit includes: a first inductor coupled between a first voltage supply and a first node; and a second inductor coupled between the first voltage supply and a second node; the test circuit includes: a first capacitor coupled at least to the first node; a second capacitor coupled at least to the first capacitor and the second node; and a cross-coupled transistor pair coupled to at least one of the first capacitor, the second capacitor, the first node, the second node, the first inductor, or the second inductor; the first capacitor and the second capacitor are connected in parallel with the first inductor and the second inductor; and the first capacitor, the second capacitor, the first inductor, the second inductor, and the cross-coupled transistor pair are configured as an inductor-capacitor oscillator circuit.In some embodiments, the test circuit further includes: a third capacitor coupled between a first pad and a second pad, adjacent to the first capacitor, and used to generate a third signal; a fourth capacitor coupled at least to the second capacitor and the third node; a first buffer circuit coupled to the fourth capacitor and a second voltage supply, used to receive the first signal and to output a first oscillation signal having a first oscillation frequency, the second voltage supply being different from the first voltage supply; a multiplexer coupled to the first buffer circuit and the second voltage supply, used to output the first oscillation signal or a bypass signal as a first intermediate signal in response to a selection signal; a frequency divider circuit coupled to the multiplexer and the second voltage supply, used to receive the first intermediate signal and to generate a second oscillation signal in response to the first intermediate signal, the second oscillation signal having a second oscillation frequency; and a second buffer circuit coupled to the frequency divider circuit, the probe, and the second voltage supply, used to receive the second oscillation signal and to output a third oscillation signal in response to the second oscillation signal, the third oscillation signal having a second oscillation frequency, and the third oscillation signal being the second signal.

[0356] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that they can be modified, substituted, and altered in various ways without departing from the spirit and scope of this disclosure.

Claims

1. A system for testing wafers, comprising: A first circuit is used to generate a first signal having a first oscillation frequency; A test circuit coupled to the first circuit, the test circuit being used to generate a second signal in response to the first signal, the second signal representing the value of the first oscillation frequency, and to generate a third signal, the third signal representing the value of the first capacitance of the first capacitor in the test circuit, the second signal having a second oscillation frequency, the second oscillation frequency being less than the first oscillation frequency; as well as A test system coupled to the test circuit and configured to receive the second signal and the third signal, and to perform a wafer acceptance test on the first circuit, thereby determining the inductance of the first circuit in response to the second signal and the third signal.

2. The system of claim 1, wherein the first circuit comprises: A first inductor, the first inductor being coupled between a first voltage supply and a first node; as well as A second inductor is coupled between the first voltage supply and the second node.

3. The system according to claim 2, wherein the test circuit comprises: The first capacitor is coupled to at least the first node; A second capacitor, which is at least coupled to the first capacitor and the second node; as well as A cross-coupled transistor pair, the cross-coupled transistor pair being coupled to at least one of the first capacitor, the second capacitor, the first node, the second node, the first inductor, or the second inductor; The first capacitor and the second capacitor are connected in parallel with the first inductor and the second inductor.

4. A method for performing wafer acceptance testing on a first circuit, the method comprising: The first oscillation frequency of the first circuit of the first inductor-capacitor (LC) resonant oscillator is determined by the test system. The first inductor-capacitor resonant oscillator includes the first circuit and the test circuit. The first capacitance of the first capacitor in the first circuit is determined by the test system. as well as The inductance of the first circuit is determined by the test system based on the first oscillation frequency and the first capacitance of the first capacitor.

5. The method of claim 4, wherein determining the first oscillation frequency of the first circuit comprises: A first signal is generated by the first circuit, and the first signal has the first oscillation frequency. as well as The test circuit responds to the first signal to generate a second signal, the second signal representing the value of the first oscillation frequency.

6. The method of claim 5, wherein generating the second signal in response to the first signal comprises: The second capacitor blocks the DC portion of the first signal and transmits the AC portion of the first signal, and the second capacitor is coupled to the first circuit and the first capacitor. as well as A first oscillation signal is output in response to the AC portion of the first signal via a first buffer circuit, the first buffer circuit being coupled to the second capacitor.

7. The method according to claim 6, wherein, Generating the second signal in response to the first signal further includes: A frequency divider circuit generates a second oscillation signal in response to the first oscillation signal. The second oscillation signal has a second oscillation frequency, which is less than the first oscillation frequency. The frequency divider circuit is coupled to the first buffer circuit. The second oscillation signal is the second signal.

8. A system for testing wafers, comprising: A first circuit is used to generate a first signal having a first oscillation frequency; A test circuit coupled to the first circuit, the test circuit being used to generate a second signal in response to the first signal, the second signal representing the value of the first oscillation frequency, and to generate a third signal, the third signal representing the value of the first capacitance of the first capacitor in the test circuit, the second signal having a second oscillation frequency, the second oscillation frequency being less than the first oscillation frequency; as well as A test system, coupled to the test circuit, is used to perform wafer acceptance testing on the first circuit, thereby determining the inductance of the first circuit in response to the second signal and the third signal. The test system mentioned above includes: A probe, coupled to the test circuit, is used to receive the second signal and the third signal from the test circuit; A probe card, coupled to the probe, and configured to receive the second signal and the third signal from the probe; and A test device coupled to the probe card and used to receive the second signal and the third signal from the probe card, and to determine the inductance of the first circuit.

9. The system of claim 8, wherein... The first circuit includes: A first inductor is coupled between a first voltage supply and a first node; And a second inductor, coupled between the first voltage supply and the second node; The test circuit includes: a first capacitor coupled to at least the first node; a second capacitor coupled to at least the first capacitor and the second node; and a cross-coupled transistor pair coupled to at least one of the first capacitor, the second capacitor, the first node, the second node, the first inductor, and the second inductor. Wherein, the first capacitor and the second capacitor are connected in parallel with the first inductor and the second inductor; and The first capacitor, the second capacitor, the first inductor, the second inductor, and the cross-coupled transistor pair constitute an inductor-capacitor oscillator circuit.

10. The system according to claim 9, wherein, The test circuit also includes: A third capacitor is coupled between the first pad and the second pad, the third capacitor is adjacent to the first capacitor, and is configured to generate the third signal; A fourth capacitor is coupled to at least the second capacitor and the third node; A first buffer circuit, coupled to the fourth capacitor and the second voltage supply, is configured to receive the first signal and output a first oscillation signal having the first oscillation frequency, wherein the second voltage supply is different from the first voltage supply; and A multiplexer, coupled to the first buffer circuit and the second voltage supply, is configured to output the first oscillation signal or a bypass signal as a first intermediate signal in response to a selection signal; A frequency divider circuit, coupled to the multiplexer and the second voltage supply, is configured to receive the first intermediate signal and, in response to the first intermediate signal, generate a second oscillation signal having the second oscillation frequency; and A second buffer circuit, coupled to the frequency divider circuit, the probe, and the second voltage supply, is configured to receive the second oscillation signal and, in response to the second oscillation signal, output a third oscillation signal having the second oscillation frequency, wherein the third oscillation signal is the second signal.

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