Power parameter intelligent sensing and high-reliability storage device based on magnetic storage chip

Abstract

The application relates to the technical field of power data storage, and discloses a power parameter intelligent sensing and high-reliability storage device based on a magnetic storage chip, which comprises a main control microprocessor, a direct memory access controller, a magnetic random access memory, an energy storage capacitor and a hardware latch trigger circuit. When it is monitored that a magnetic field or a power supply voltage is out of limit, the trigger circuit physically pulls down the memory control pin by using the residual electric energy of the capacitor, pure hardware level write blocking is realized, transient data is prevented from being covered by chaotic signals, the microprocessor is configured with discrete interleaving addressing, waveform hash writing is performed on non-continuous sectors to prevent local concentration damage, and a hardware watermark is overwritten in a data frame as a phase anchor point. After reset, the device recombines a continuous waveform through physical reverse mapping and interpolation operation, and deduces a power-off absolute time coordinate in combination with the anchor point. The application effectively improves the safety and reliability of power transient recording data in an extreme fault environment.

Description

Technical Field

[0001] This invention relates to the field of power data storage technology, specifically to a power parameter intelligent sensing and high-reliability storage device based on magnetic storage chips. Background Technology

[0002] When a short-circuit fault or voltage dip occurs in a power system, high-frequency sampling and real-time recording of transient waveform data are required for fault waveform analysis and distance estimation. Currently, mainstream power sensing and recording devices typically use a microprocessor-controlled analog-to-digital converter for continuous sampling, and then sequentially write the digitized power waveform data into a non-volatile memory chip via the device bus. To preserve key waveforms before and after the fault during power outages, the device is often equipped with a software interrupt monitoring circuit. When a voltage drop is detected, the interrupt service routine of the main control chip is triggered, and the processor issues instructions to perform write protection or data sealing operations on the memory. At the same time, an internal timer is used to maintain clock stepping, providing a time axis reference for the waveform recording curve.

[0003] However, in transient processes involving strong electromagnetic interference and extreme power supply failures, traditional storage systems often use single-port buses. When the upper-layer data query process and the lower-layer cyclic write process share the bus, arbitration delays occur, leading to physical frame drops during alternating access of high-frequency sampling points. When a fault causes the device bus to lose power or generates a strong spatial abrupt magnetic field, the protection mechanism relying on the microprocessor software interrupt has inherent physical delays in instruction decoding and interrupt response cycles. Before the software completes the write protection configuration, the conventional power supply network is already paralyzed. At this time, the bus level logic is easily disrupted due to voltage drops, causing the transient data being written to be incorrectly overwritten or damaged. In addition, the commonly used linear sequential storage mode results in a concentrated distribution of continuous time-series sampling points in the physical storage array. Once subjected to directional impacts from localized spatial electromagnetic radiation, data in specific storage areas will face concentrated damage, and due to the lack of a waveform correlation fitting mechanism before and after the time domain, it cannot be repaired. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this invention provides an intelligent sensing and highly reliable storage device for power parameters based on magnetic storage chips. It solves the problems of traditional power recording devices, such as the erroneous overwriting of transient waveforms due to software delays, easy damage to centralized storage, and loss of absolute time coordinates due to power outages, in extreme power supply failures or strong electromagnetic field environments.

[0005] To achieve the above objectives, this invention provides the following technical solution: a power parameter intelligent sensing and high-reliability storage device based on a magnetic storage chip. This device mainly includes: an analog-to-digital converter (ADC), a main control microprocessor, a direct memory access controller (DMI), a magnetic random access memory (MRM), an energy storage capacitor, and a hardware latch trigger circuit. The ADC continuously acquires power waveform signals and converts them into digitized power waveform data frames. The DMI, based on addressing control parameters, bypasses the main control microprocessor and directly and continuously writes these data frames cyclically into the underlying MRM. Simultaneously, the main control microprocessor can independently read historical waveform data through a dual-port access mechanism or bus arbitration. This upper-layer reading process is asynchronous and independent of the lower-layer cyclic writing process, eliminating timing delays caused by bus contention and avoiding physical frame drops during the storage process of high-frequency sampled waveforms.

[0006] In terms of device safety protection, the hardware latch trigger circuit has the ability to monitor multiple related physical parameters in parallel. When the external environment generates a sudden strong magnetic field that exceeds the physical flip-flop threshold of the magnetic tunnel junction array unit, the passive magnetic tunnel junction array generates a resistance jump, and outputs a level trigger state through the bridge conversion circuit; or, when the device power supply bus fails, its analog level signal is lower than the critical safety voltage threshold, and the drop rate extracted by the hardware differentiating circuit reaches the set voltage drop rate threshold parameter, the parameter is determined to be out of limit. When any of the above-mentioned out-of-limit conditions occur, the hardware latch trigger circuit synchronously outputs a trigger signal, using the residual energy of the energy storage capacitor to instantly turn on the internal transistor, forcibly pulling the level of the chip select pin or write enable pin of the magnetic random access memory to a disabled state. The above-mentioned critical safety voltage threshold and physical flip-flop threshold are pre-calibrated based on the device's historical experience data and hardware physical characteristic tests. By bypassing the response delay of software interrupts through pure hardware logic, the bus write permission is physically blocked, thereby preventing the random overwriting or destruction of the recorded transient waveforms caused by the chaotic bus level logic at the moment of power failure.

[0007] To prevent the complete loss of continuous waveform data due to concentrated electromagnetic radiation impacts on local physical blocks of memory, the main control microprocessor configures a discrete interleaving addressing mapping mechanism during the initialization phase. The main control microprocessor controls the write pointer to jump based on addressing control parameters, causing adjacent waveform sampling points in the time series to be distributed in a scattered and discontinuous manner within the physical sectors of the magnetic random access memory. The addressing logic of the forward discrete interleaving mapping is expressed by the following formula: ; In the formula, This indicates the generated non-contiguous physical write address; The physical base address of the circular buffer is obtained according to the physical sector partitioning rules of the underlying memory hardware. The index of the current time series sampling point is obtained by stepping and accumulating the data using the device's internal timer. The physical space jump step parameter is obtained by selecting a constant that is coprime to the total capacity of the circular buffer, based on the device's preset addressing span requirements. This represents the total capacity of the circular buffer, which is determined based on the hardware specifications of the magnetic random access memory.

[0008] After the device is reset by power-on following fault clearance, it enters the data recovery operation mode. The main control microprocessor retrieves the discrete latched data that was blocked and retained before the power failure, along with its corresponding physical write addresses, and performs a physical addressing inverse mapping operation to reconstruct the continuous time series. The logical process of reverse deduction and reconstruction is represented by the following formula: ; In the formula, This indicates the current physical write address corresponding to the discrete latched data; Represents the physical space jump step size parameter Regarding the total capacity of the circular buffer The multiplicative inverse constant is calculated and stored by the main microprocessor using the extended Euclidean algorithm during the initialization phase. During the reverse reconstruction of the continuous time series array, if the verification program detects missing data in some physical blocks, the main microprocessor extracts the valid remaining data points adjacent to the missing nodes on the time series and performs arithmetic linear interpolation or curve fitting to fill in the missing data nodes.

[0009] Furthermore, to address the issue of timer clock pulse loss and subsequent loss of the global absolute time reference due to power outages, a hardware feature extraction logic gate is deployed in series on the data transmission path of the direct memory access controller. This logic gate calculates the rate of change of voltage waveform values ​​within adjacent sampling time intervals in real time. When the absolute value of the rate of change exceeds the voltage mutation rate threshold parameter calibrated based on normal power grid operation data, a synchronization command is output to trigger the data bus control logic, overwriting a hardware feature synchronization watermark in a specific encoding format in the physical space of the low-order feature identifier area of ​​the currently transmitted data frame. After reconstructing a continuous waveform time series, the device performs a global traversal to extract data frames with synchronization watermarks, marks them as phase anchor points, and deduces the absolute electrical phase of the waveform by combining it with a pre-set power grid frequency cycle parameter. Finally, it reverse-engineers the absolute time coordinate at the moment of triggering hardware latching, thereby meeting the requirements for collaborative ranging and tracing of large-scale power grid faults.

[0010] This invention provides a power parameter intelligent sensing and high-reliability storage device based on a magnetic storage chip. It has the following beneficial effects: 1. This invention uses a latch trigger circuit linked with an energy storage capacitor to release electrical energy and turn on the transistor when the monitored physical quantity exceeds the limit, shorting the memory control pin to the common ground. The device uses physical gate circuits to cut off the bus write permission, eliminates microprocessor interrupt response delay, and prevents messy electrical signals from covering transient records.

[0011] 2. This invention constructs a discrete interleaved addressing and interpolation repair linkage mechanism. Based on the jump step size, waveform data is dispersed and written into non-continuous sectors. After reset, the index is deduced using multiplicative inverses and interpolation is used to fill in missing nodes. The underlying storage uses spatial hash distribution to block the concentrated damage of electromagnetic storms to local blocks and reassembles the time series.

[0012] 3. This invention utilizes the linkage between the monitoring node and the bus flow control, compares the waveform variation rate with the hardware logic and overwrites the watermark in the data frame, the processor extracts the watermark and sets it as the phase anchor point to deduce the power failure time coordinate, the signal link is removed from the software execution cycle record identifier, and the timing pulse loss error caused by the power supply failure of the equipment is eliminated.

[0013] 4. This invention is based on a dual-port architecture and pointer monitoring linkage. It compares the logical address difference between read and write pointers in real time. When approaching the boundary, it inserts a hardware wait state to block the extraction instruction. The port isolation mechanism separates the access electrical signals to avoid upper-layer query operations from interfering with the continuous sampling process and causing waveform frame drops. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of the overall hardware architecture of the device of the present invention; Figure 2 This is a microscopic internal diagram of the hardware latch trigger circuit of the present invention; Figure 3 This is the hardware watermark overwrite timing logic diagram of the present invention; Figure 4 This is a diagram of the reverse derivation algorithm model of the present invention; Figure 5 This is a schematic diagram of the dual-port read / write anti-collision method of the present invention; Figure 6 This is a schematic diagram of the device's operation throughout its entire lifecycle. Detailed Implementation

[0015] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0016] Please see the appendix Figure 1 To be continued Figure 6The present invention provides an intelligent sensing and high-reliability storage device for power parameters based on a magnetic storage chip, including an analog-to-digital converter, a main control microprocessor, a direct memory access controller, a magnetic random access memory, an energy storage capacitor, and a hardware latch trigger circuit.

[0017] The data processing operation of this power parameter intelligent sensing and high-reliability storage device based on magnetic storage chips may include the following steps: The main control microprocessor is physically connected to the configuration register of the direct memory access controller via the internal control bus of the device. The main control microprocessor initializes the address mapping rules and establishes the physical spatial correspondence between the time series sampling point index and the internal ring buffer of the magnetic random access memory.

[0018] The main control microprocessor pre-generates addressing control parameters containing source address, destination address, and transmission payload capacity information through software logic. The main control microprocessor then writes the addressing control parameters into the configuration register of the direct memory access controller, thus completing the physical link construction of the underlying data transport path.

[0019] The direct memory access controller performs a single data transfer operation based on addressing control parameters, which internally define the payload capacity parameter for a single transfer. The payload capacity parameter for a single transfer is determined using... This indicates that the number of synchronous sampling channels configured in the device adopts... This indicates that the quantization byte width of a single sample point output by the analog-to-digital converter uses... The calculation formula for the load capacity parameter in the addressing control parameters is as follows: ; In the formula, Confirmed based on the number of parallel sampling circuit branches actually connected to the power transformers on the hardware circuit board; The quantization resolution parameters are extracted based on the configuration of the internal control registers of the analog-to-digital converter chip. The main control microprocessor then calculates these parameters. Set the transmission length boundary for the direct memory access controller to ensure the spatial integrity of a single digital power waveform data frame transfer.

[0020] The analog signal input terminal of the analog-to-digital converter is connected to the output node of the transformer of the external power line, and the digital output terminal of the analog-to-digital converter is connected to the source data input port of the direct memory access controller via the data bus. The analog-to-digital converter continuously acquires power waveform signals, performs quantization and encoding operations, and converts the power waveform signals into digitized power waveform data frames.

[0021] The main control port of the direct memory access controller is connected to the address bus and data bus of the magnetic random access memory, respectively. The direct memory access controller requests and takes over the control of the data bus from the bus arbitrator according to the address control parameters, so that the digitized power waveform data frame bypasses the arithmetic logic unit inside the main control microprocessor and is continuously and cyclically written into the internal storage array of the magnetic random access memory.

[0022] The direct memory access controller bypasses the main microprocessor to perform memory operations, eliminating the time delay caused by the main microprocessor responding to interrupt requests and performing context switching operations, thus ensuring the continuity of waveform data sampling and the accuracy of write timing.

[0023] The monitoring input port of the hardware latch trigger circuit is connected in parallel to the device power supply bus and the external physical environment monitoring node. The control signal output of the hardware latch trigger circuit is connected to the chip select pin or write enable pin of the magnetic random access memory (MRMemory). The anode terminal of the energy storage capacitor is connected to the power input pin of the MRMemory. The minimum capacitance value of the energy storage capacitor is... The calibration calculation formula is as follows: ; In the formula, The transient power consumption representing the physical blocking action. This represents the safe duration required to maintain the disabled state. The rated operating voltage of the device is represented. This represents the lowest logic high level allowed by the memory chip, with actual engineering selection values ​​ranging from 10μF to 47μF.

[0024] The hardware latch trigger circuit monitors the associated physical parameters that characterize the device's operational faults in real time. When the logic gate inside the hardware latch trigger circuit determines that the associated physical parameter has exceeded the limit, it outputs a trigger signal that flips the state. In response to the trigger signal, the hardware latch trigger circuit uses the residual energy maintained by the energy storage capacitor at the moment the device is powered off to pull the level of the chip select pin or write enable pin of the magnetic random access memory down to a logic low level disabled state.

[0025] After the control pin level of the magnetic random access memory drops to the disabled state, the device blocks the bus write permission of the magnetic random access memory by means of pure physical gate circuit disconnection, so as to prevent unstable and messy signals generated by power fluctuations from overwriting the pre-fault transient data that has already been written.

[0026] The data read port of the main control microprocessor is connected to the data output port of the magnetic random access memory. After the fault is cleared and the device is powered on and reset, the main control microprocessor sends a read instruction timing sequence to the magnetic random access memory to read the latched data stored in the magnetic random access memory before the write permission was blocked.

[0027] The main control microprocessor retrieves the addressing control parameters stored in the non-volatile registers, sorts the extracted latched data by address using the physical addressing inverse mapping algorithm, and reassembles the scattered latched data into a time series array arranged continuously according to the time series index. The main control microprocessor reconstructs the transient waveform curves before and after the fault based on the time series array and outputs them to the host computer for fault tracing and analysis.

[0028] In this embodiment, the associated physical parameters characterizing device malfunctions include the device power supply bus voltage, and a voltage drop monitoring path is configured within the hardware latch trigger circuit. The front-end pin of the voltage drop monitoring path is physically connected to the device power supply bus, and a hardware differentiator circuit and a hardware voltage comparator are connected in series internally. The hardware differentiator circuit is constructed using an active operational amplifier topology. The aforementioned equivalent capacitor is connected in series at the inverting input terminal of the operational amplifier, the equivalent resistor is connected in parallel between the inverting input terminal and the output terminal, and the non-inverting input terminal is connected to a common ground. The instantaneous change slope is extracted through this active structure. The hardware voltage comparator has a dual-channel comparison reference input terminal. The device power supply bus directly inputs a continuous analog level signal to the first channel of the hardware voltage comparator. Simultaneously, the hardware differentiator circuit extracts the instantaneous change slope of the analog level signal and inputs the processed signal to the second channel of the hardware voltage comparator.

[0029] The voltage sag rate of the hardware differentiating circuit output is adopted This indicates that the analog level signal input to the power supply bus of the device adopts... This indicates that the equivalent capacitance parameters inside the hardware differentiating circuit are adopted. This indicates that the corresponding equivalent resistance parameters are adopted. The formula for calculating the transient rate of change based on pure hardware gate circuits is as follows: ; In the formula, The real-time current shunting sampling of the device's power supply bus is obtained based on the voltage divider resistor network. and The time constant of the differentiator circuit is determined by the nominal parameters of the resistors and capacitors actually soldered on the printed circuit board, and the product of these resistors and capacitors determines the time constant of the differentiator circuit.

[0030] The hardware voltage comparator compares the amplitude of the analog level signal with the critical safe voltage threshold in real time, and simultaneously compares the voltage drop rate. The voltage sag rate threshold parameter is set. The critical safe voltage threshold is configured according to the IEC61000-4-11 voltage sag standard and is set to 70% of the device's rated supply voltage. The voltage sag rate threshold parameter is obtained through calibration using a laboratory sag simulator based on the nominal hold-time characteristics of the device's switching power supply, with a value range of 10V / ms to 50V / ms. The main control microprocessor uses its built-in digital-to-analog converter output channel to generate a corresponding DC reference voltage, which is then injected into the reference pin of the hardware voltage comparator as the threshold parameter. When the hardware voltage comparator confirms that the analog level signal amplitude is below the critical safe voltage threshold and the voltage sag rate reaches the voltage sag rate threshold parameter, it determines that the associated physical parameter has exceeded the limit and immediately outputs a high-level pulse signal to the subsequent aggregation node.

[0031] In this invention, the associated physical parameters characterizing device malfunctions also include the intensity of an external abrupt magnetic field change. A magnetic field sensing trigger path, parallel to the voltage drop monitoring path, is internally configured within the hardware latching trigger circuit. This magnetic field sensing trigger path utilizes a magnetic tunnel junction array as a passive sensor. This passive sensor operates based on the physical properties of the materials and does not consume the device's standby current. The magnetic tunnel junction array contains a free magnetic layer, an insulating barrier layer, and a fixed magnetic layer. A short-circuit fault in the power device triggers a highly dissipated external abrupt magnetic field in space. When the intensity of this external abrupt magnetic field exceeds the physical flipping threshold of the spin electrons in the magnetic tunnel junction array unit, the magnetization direction of the free magnetic layer reverses polarity.

[0032] The real-time equivalent impedance of the magnetic tunnel junction array is adopted This indicates that the reference resistor inside the array, which is in a parallel magnetized state, uses... This indicates that the resistor in the antiparallel magnetization state uses This indicates that the external abrupt magnetic field strength is expressed using... This indicates that the material's intrinsic physical flip threshold is adopted. The formula for calculating the resistive-state transition model of a passive sensor is as follows: ; In the formula, the step function In variables Output logical scalar one at the time, in the variable Output logic scalar zero at time; and Obtained based on the calibration data given in the factory test of the magnetic tunnel junction chip; Pre-curing is performed based on empirical data of the magnetization coercivity of the internal material of the magnetic tunnel junction array; The magnetic flux density is calculated based on the spatial magnetic flux generated by the actual short-circuit current in the power line, according to the law of electromagnetic induction. The external abrupt magnetic field strength is obtained by... The formula, derived from the Biot-Savart law, is as follows: ; In the formula, This represents the peak value of the short-circuit transient current on the primary side of the current transformer. Represents the physical vertical distance from the passive sensor to the busbar; the magnetic tunnel junction array is arranged in a 2×2 bridge configuration in engineering applications, with a typical room temperature magnetoresistive calibration of 150% to 200%, and a reference resistor in a parallel magnetized state. The typical range is 1kΩ to 5kΩ.

[0033] Under the aforementioned mechanism, the magnetic tunnel junction array undergoes a resistive transition from a low-resistance state to a high-resistance state. The magnetic field sensing trigger path is internally connected to a bridge conversion circuit with a Wheatstone bridge topology. The magnetic tunnel junction array is connected to the sensing arm of the bridge conversion circuit, which converts the bridge arm imbalance caused by the impedance change into an output potential difference. A differential amplifier at the rear of the bridge conversion circuit amplifies this potential difference and inputs the amplified analog voltage to a hardware magnetic comparator configured within the magnetic field trigger path. The main control microprocessor determines the flip-flop threshold based on the magnetization coercivity. Set the corresponding DC reference voltage and inject it into the reference pin of the hardware magnetic comparator; when the amplified analog voltage exceeds the DC reference voltage, the hardware magnetic comparator flips, and then switches to a level-triggered state and outputs it as a trigger signal.

[0034] The trigger aggregation node combines the action signals output from the voltage drop monitoring path and the magnetic field sensing trigger path via a logic OR gate. During normal operation, the device's power supply bus continuously charges the energy storage capacitor through a reverse connection protection diode, maintaining the capacitor at energy saturation. In the event of a bus power failure or a momentary malfunction causing a strong magnetic field interference that paralyzes the conventional power supply network, the energy storage capacitor releases residual energy to provide transient operating energy for the latch drive circuit. The latch drive circuit then activates a pull-down transistor, forcibly shorting the chip select or write enable pin of the magnetic random access memory (MRMemory) to the device's common ground. The level of the chip select or write enable pin is pulled low to a disabled state, effectively blocking bus write access to the MRMemory from the underlying pin structure, ensuring the physical security of the latched data.

[0035] In this embodiment, when initializing the address mapping rules, the main control microprocessor configures discrete interleaved addressing mapping to block the concentrated destructive effect of spatial electromagnetic radiation on local physical storage areas. The main control microprocessor generates an address descriptor linked list as addressing control parameters for the direct memory access controller. This address descriptor linked list instructs the address pointer of the direct memory access controller to jump steps according to a discrete sequence.

[0036] In this invention, the main control microprocessor reads the index of the current time series sampling point from the timer of the device and multiplies the index value by a set physical space jump step parameter. The arithmetic logic unit of the main control microprocessor performs a modulo operation on the aforementioned product result, using the total capacity of the circular buffer as the modulus. The main control microprocessor superimposes the physical base address and the modulo operation result to generate a non-contiguous physical write address, so that adjacent sampling points on the time series exhibit a discrete distribution in the physical address space of the magnetic random access memory.

[0037] Time series sampling point index uses This indicates that the physical space jump step size parameter adopts... This indicates that the total capacity of the circular buffer zone is calculated using... This indicates that the physical base address uses Representation. Physical write address for discrete interleaved addressing. The formula for generating the formula is as follows: ; In the formula, It is generated synchronously based on the step clock beat of the device's timer; and Pre-allocated and acquired according to the underlying physical sector partitioning protocol of the memory; Based on the step size requirements for electromagnetic interference suppression, the main control microprocessor executes Euclidean algorithm software logic during the device's power-on initialization boot program phase to automatically search for and set the first step size relative to the total capacity of the circular buffer. Prime numbers whose greatest common divisor is the logical scalar one are used as parameters for the physical space jump step size. ,Right now The main microprocessor controls the write pointer through coprime mathematical relationships, causing the time series sampling points to traverse the entire circular buffer and avoiding physical address overlap conflicts.

[0038] In this embodiment, after the hardware is latched due to power failure and then reset upon power-on, the device enters the data recovery operation mode. The main control microprocessor executes the physical addressing inverse mapping process to reverse the discretely distributed data sequence. The main control microprocessor reads the discretely stored latched data via the data bus and simultaneously extracts the physical write address corresponding to the latched data. The main control microprocessor calls the subtractor to subtract the physical base address from the physical write address to obtain the spatial location offset.

[0039] The main control microprocessor uses the extended Euclidean algorithm to calculate the multiplicative inverse of the physical space jump step size parameter with respect to the total capacity of the circular buffer. This multiplicative inverse is obtained by... The microprocessor's multiplier multiplies the spatial location offset by the multiplicative inverse, and finally performs a second modulo operation on the total capacity of the circular buffer to reconstruct the corresponding time series sampling point index. The formula for reconstructing the time series sampling point index is as follows: ; In the formula, satisfy The congruence mathematical equation; during the initialization phase, the main control microprocessor uses the extended Euclidean algorithm to calculate the multiplicative inverse and pre-stores the constant result in the internal 32-bit static random access memory to save the logic computing power consumption during the waveform reconstruction phase.

[0040] The main microprocessor, based on the reconstructed time-series sampling point indices, rearranges and reassembles the scattered latched data into a time-series array. The microprocessor then iterates through and verifies the continuity of the index sequence in this time-series array. When the verification program detects data loss in a physical block, the main microprocessor locates the time-series index of the missing data node. The time-series index of the missing data is determined using... express.

[0041] When the verification program determines that only a single point of data is missing, the main control microprocessor extracts valid data points from adjacent nodes in the time series and performs arithmetic interpolation repair operations. The reconstructed values ​​at the missing point location are obtained using... This indicates that the waveform values ​​of the preceding valid data points are adopted. This indicates that the waveform values ​​of subsequent valid data points are adopted. The linear interpolation compensation formula is as follows: ; In the formula, and The data is extracted from the hardware latched sampling data that are immediately adjacent to each other in the time series array. When the verification program determines that two or more consecutive data nodes are missing, the main control microprocessor extracts three valid retained data points before and after the missing interval, and calls the arithmetic logic unit to perform transient curve fitting and reconstruction based on the Lagrange polynomial interpolation algorithm. The main control microprocessor then calculates the reconstructed values ​​(…). (etc.) fill in the missing index nodes of the time series array, thereby ensuring the continuity of the waveform reconstruction curve in the time domain dimension and the high-frequency harmonic fidelity under the condition of large-area data loss.

[0042] In this embodiment, the data transmission path of the direct memory access controller includes a monitoring and interception node. This monitoring and interception node is arranged in series on the data bus between the direct memory access controller and the magnetic random access memory. This node utilizes a field-programmable gate array (FPGA) chip as discrete hardware embedded in the high-level scalable interface bus path. In this invention, the monitoring and interception node is configured with a hardware feature extraction logic gate. This hardware feature extraction logic gate includes a pipelined arithmetic unit and a comparator array. The pipelined arithmetic unit uses a parallel register array structure to complete the online interception of the data stream within a single bus clock cycle. The hardware feature extraction logic gate intercepts the digitized power waveform data frame in real time, sends the waveform sampling payload of the current data frame to the pipelined arithmetic unit to perform arithmetic operations, and determines whether the waveform sampling payload meets the set zero-crossing feature or transient change feature.

[0043] The hardware feature extraction logic gate internally includes a shift register, which temporarily stores the data payload of the previous time tick. When judging transient change characteristics, the hardware feature extraction logic gate calls the internal arithmetic unit to calculate the rate of change of voltage waveform values ​​within adjacent sampling time intervals. The current time series sampling point index uses... This indicates that the waveform payload value of the current data frame adopts... This indicates that the waveform payload value of the previous adjacent data frame is adopted. This indicates that the time interval between adjacent samplings is... This indicates that the rate of change of voltage waveform values ​​is expressed as follows: The formula for calculating the rate of change of voltage waveform values ​​is as follows: ; In the formula, and The feature extraction logic gates extract the data from the data frame payload intercepted by the bus. Based on the operating clock frequency of the analog-to-digital converter, the adjacent sampling time interval is calculated and confirmed. The value is constrained by the operating clock frequency of the analog-to-digital converter. The main control microprocessor configures the phase-locked loop output clock frequency according to the AC sampling standard of the power installation, forcibly stipulating that 256 or 512 points of equally spaced sampling are performed within each power frequency cycle, thereby fixing... The physical time width. Hardware feature extraction logic gates utilize a comparator array for... Perform the absolute value calculation and comparison. The absolute value of the voltage change rate threshold parameter is compared with the set voltage change rate threshold parameter. When the absolute value is greater than or equal to the voltage change rate threshold parameter, the hardware feature extraction logic gate determines that the current waveform meets the transient change feature.

[0044] When the hardware feature extraction logic gate determines that the data frame meets the zero-crossing feature or transient change feature, it outputs a synchronization command to the data bus control logic. The data frame internally includes a waveform sampling load area and a feature identification area. The bus protocol predefines this data frame format as occupying a fixed 32-bit width, with the high 24 bits allocated to the waveform sampling load area and the low 8 bits to the feature identification area. Responding to the synchronization command, the data bus control logic drives the internal multiplexer to overwrite a hardware feature synchronization watermark in the feature identification area of ​​the currently transmitted digital power waveform data frame. This watermark is imprinted in the aforementioned low 8-bit physical space using a preset specific binary sequence encoding format. The device utilizes the underlying physical logic gates to imprint the specific encoding in the underlying data transmission link, avoiding the intervention of the main control microprocessor's software execution cycle in the bus data stream.

[0045] In this invention, the device eliminates the fault and is powered on again for reset. The main control microprocessor restores the discrete addresses of the latched data and assembles a continuous time series array. The main control microprocessor performs a global traversal addressing operation on the time series array, extracts data frames containing hardware feature synchronization watermarks, and sets the extracted hardware feature synchronization watermarks as phase anchor points.

[0046] The main control microprocessor, combined with the set power grid frequency cycle parameter, inversely derives the absolute electrical phase of the power waveform, thereby eliminating timer pulse loss errors during power outages. The time series sampling point index corresponding to the phase anchor point uses... This indicates that the data cutoff point index used when the device blocks write permissions is... This indicates that the latching time in the absolute time coordinate system is adopted. This indicates that the reference absolute time corresponding to the phase anchor point is adopted. The formula for inversely deriving the absolute time coordinate to obtain the global timestamp is as follows: ; Meanwhile, to extract the relative electrical phase characteristics used for fault location, the set power grid frequency period parameter adopts... This indicates that the relative electrical phase at the latching moment adopts... The derivation formula is as follows: ; In the formula, The watermark position is obtained by the main control microprocessor traversing the time series array and reading the watermark position. This is derived from the address pointer register state mapping of the direct memory access controller at the moment when the magnetic random access memory's access rights are cut off; Retrieve based on the historical synchronization timestamps recorded by the high-precision real-time clock chip inside the device; The frequency is obtained by reciprocal conversion based on the fixed power frequency according to the power grid operation standard. The main control microprocessor accurately defines the absolute time coordinate and relative electrical phase at the moment of triggering latching based on the reverse deduction action, and outputs the coordinates for waveform reconstruction analysis.

[0047] In this embodiment, the device maintains parallel operation of the underlying data recording process and the upper-level data query process during normal operation. In this invention, the magnetic random access memory internally encapsulates a physical pin array based on a dual-port access mechanism. This pin array leads outwards to a first data interaction port and a second data interaction port, which are mutually isolated. The control and data wiring harnesses from the direct memory access controller are physically connected to the first data interaction port, and the independent read bus extended from the main microprocessor is connected to the second data interaction port.

[0048] The direct memory access controller continuously and cyclically writes digitized power waveform data frames into the magnetic random access memory using the first data interaction port according to the addressing control parameters. The main control microprocessor, through the aforementioned dual-port access mechanism, uses the second data interaction port to issue a read timing sequence independent of the direct memory access controller, and performs a non-destructive read operation on the historical waveform data already stored in the magnetic random access memory.

[0049] The main microprocessor is internally configured with pointer monitoring logic to compare the low-level hardware write position with the high-level read request position in real time, preventing overlapping conflicts of access instructions at the physical sector level. The current write pointer logical address of the direct memory access controller uses... This indicates that the current read pointer logical address of the main control microprocessor uses... The total capacity of the circular buffer is expressed as follows: It is stated that the main control microprocessor determines the recording and holding time before a fault as specified in the standard, as well as the sampling rate of the analog-to-digital converter. The value of is determined by the following rules: The sampling clock frequency is multiplied by the set waveform time window length, and aligned to an integer multiple of the standard size of the underlying physical sector of the magnetic random access memory (MRM). The MRM selected is a dual-port spin-torque MRM supporting a parallel data bus. The set physical safety interval boundary uses... The formula for the main microprocessor to determine the compliant secure addressing window for asynchronous reads is as follows: ; In the formula, It is extracted in real time based on the existing value in the destination address register inside the direct memory access controller; The target address is determined by parsing the read request instruction issued by the main microprocessor. Extracted based on the underlying space partitioning protocol of the storage array; Based on the maximum byte length conversion setting encompassed by the single burst transfer mechanism in the underlying high-level microcontroller bus architecture protocol, the setting rule is: the product of the single burst transfer length and the reserved anti-jitter margin constant. In a 16-bit bus width engineering configuration, The value is set to 128 bytes to 256 bytes.

[0050] After the arithmetic logic unit of the main microprocessor confirms that the logical address of the read pointer conforms to the above boundary judgment formula, it formally initiates the waveform extraction instruction through the second data interaction port. When the safe addressing window does not meet the above formula constraints, thus causing a potential read conflict, the bus control logic of the main microprocessor actively inserts a hardware wait state into the internal execution core of the microprocessor, blocking the current waveform extraction instruction and delaying the set retry clock cycle until the judgment condition is met, at which point the blocking state is released. The first and second data interaction ports rely on independent row and column decoders to transfer electrical signals and have completely separate internal power supply domains. The read operation and the underlying loop write process of the direct memory access controller run asynchronously and independently through the above hardware isolation link, and the two do not interrupt each other on the time domain response link.

[0051] The device utilizes a pure hardware port isolation architecture to manage concurrent data access actions. The main control microprocessor does not need to request the bus controller to suspend the underlying write command when acquiring waveform data, thereby eliminating the power sampling point loss caused by bus arbitration delay in conventional single-port storage architecture.

[0052] In this embodiment, the device executes its operating logic according to a predefined time-series flow model to cover the lifecycle of data recording and fault reconstruction. In this invention, the device lifecycle encompasses the initialization operation phase, the cyclic operation phase, the hardware fault response phase, and the reset and reconstruction simulation phase. The total device operating time is calculated using... This indicates that the initial running time is calculated using... This indicates that the cycle duration is calculated using... This indicates that the hardware fault response time is based on... It is indicated that the reset and reconstruction simulation duration adopts... The formula for calculating the time-bound evolution of the device's lifecycle is as follows: ; In the formula, It is calculated based on the total number of clock cycles required for the main microprocessor to execute the underlying register configuration instructions; The time stamp difference between the period from when the device is powered on and put into operation until the related physical parameter characterizing the fault exceeds the limit is obtained; It is determined based on the sum of the cascaded delay of the logic gates inside the hardware latch trigger circuit and the transistor conduction time; This is based on the instruction cycle statistics of the main control microprocessor executing the reverse mapping algorithm and arithmetic interpolation repair operation.

[0053] exist During this phase, the main microprocessor starts its internal device timer and establishes address mapping rules. The main microprocessor generates an address descriptor list and writes addressing control parameters, including the physical space jump step size, into the configuration register of the direct memory access controller. The device then jumps... During this phase, the analog-to-digital converter continuously acquires power waveform signals and converts them into digital power waveform data frames. The direct memory access controller takes over control of the data bus based on addressing control parameters and uses coprime mathematical relationships to control the write pointer to jump, continuously writing the data frames into the circular buffer of the magnetic random access memory.

[0054] In During this phase, the hardware feature extraction logic gates intercept data frames in real time at the bus's monitoring and interception nodes, calculating the rate of change of voltage waveform values ​​to identify transient change characteristics. The hardware feature extraction logic gates output synchronization instructions, guiding the data bus control logic to overwrite the hardware feature synchronization watermark in the feature identification area of ​​the data frame. The main control microprocessor, utilizing the bus arbitration mechanism via the second data interaction port, independently initiates waveform extraction instructions to perform read operations without interrupting the underlying direct memory access controller's write process.

[0055] When a short circuit occurs in the physical lines of the power supply network or a busbar loses power, the device forcibly switches off. In this phase, the voltage drop monitoring path and magnetic field sensing trigger path within the hardware latch trigger circuit synchronously perform over-limit comparison actions. When the external sudden magnetic field strength exceeds the physical switching threshold of the magnetic tunnel junction array unit, or when the amplitude of the analog level signal and the voltage drop rate reach preset parameters, a trigger signal for the sink node output state switching is triggered. The latch drive circuit responds to the aforementioned trigger signal by turning on the internal pull-down transistor, guiding the energy storage capacitor to release residual energy to the control pin. The latch drive circuit forcibly shorts the chip select pin or write enable pin of the magnetic random access memory to the device common ground, physically blocking data write access to the bus.

[0056] After the power supply network is restored, the device executes the reset procedure and enters... Phase 1. The main control microprocessor retrieves the latched data retained before the blocking permission in the circular buffer, performs physical addressing inverse mapping using the multiplicative inverse constant, and reassembles the latched data into a time series array. When the main control microprocessor locates a missing data node during the traversal verification phase, it calls the immediately preceding and following retained data points in the time series array to perform arithmetic interpolation repair operations. The main control microprocessor extracts the hardware feature synchronization watermark contained in the data frame, designates the aforementioned watermark as the phase anchor point, and, in conjunction with the power grid frequency cycle parameter, reverse-derives the absolute time coordinate of the moment of triggering latching.

[0057] The device integrates a discrete interleaving addressing mechanism, a listening interception watermark overwrite logic, and a pure hardware latch architecture. It utilizes underlying hardware logic gates and physical energy storage elements to handle data protection actions during power supply anomalies. This hardware control architecture eliminates microprocessor software interrupt response delays and blocks the destructive effects of spatial electromagnetic radiation on local physical storage areas. The device's hardware and software coordination mechanism ensures the temporal continuity of power parameter records and provides a fault transient waveform analysis data model including absolute time coordinates.

Claims

1. A power parameter intelligent sensing and high-reliability storage device based on a magnetic storage chip, characterized in that, Comprise: an analog-to-digital converter, a master microprocessor, a direct memory access controller, a magnetic random access memory, an energy storage capacitor, and a hardware latch trigger circuit; the master microprocessor is configured to initialize an address mapping rule, map a time series sampling point index to a physical write address of an internal ring buffer of the magnetic random access memory, and configure addressing control parameters of the direct memory access controller; the analog-to-digital converter is configured to collect power waveform signals and convert them into digitized power waveform data frames; the direct memory access controller is configured to continuously and cyclically write the digitized power waveform data frames into the magnetic random access memory according to the physical write address, bypassing the master microprocessor, according to the addressing control parameters; the hardware latch trigger circuit is configured to output a trigger signal when an associated physical parameter indicative of a device operation failure is out of limit in real time, and to use residual energy of the energy storage capacitor to pull down a chip select pin or a write enable pin of the magnetic random access memory to a disabled state, thereby physically blocking the write permission of the magnetic random access memory. 2.The magnetic storage chip-based power parameter intelligent sensing and high-reliability storage device of claim 1, wherein, When initializing the address mapping rule, the master microprocessor configures a discrete interleaved addressing mapping for electromagnetic interference resistance: The master microprocessor generates an address descriptor linked list as the addressing control parameters, multiplies the current time series sampling point index by a set physical space jump step parameter, performs a modulo operation based on the total capacity of the ring buffer, and generates non-continuous physical write addresses, so that adjacent sampling points in the time series are discretely distributed in the physical space. The physical space jump step parameter is coprime with the total capacity of the ring buffer. The master microprocessor is further configured to read the latched data retained before the write block in the magnetic random access memory after the device is reset, assemble the latched data into a continuous time series array through physical addressing inverse mapping, and reconstruct a fault transient waveform. 3.The magnetic storage chip-based power parameter intelligent sensing and high-reliability storage device of claim 1, wherein, A hardware feature extraction logic gate is arranged on a monitoring and intercepting node of a data transmission path of the direct memory access controller; The hardware feature extraction logic gate is configured to perform real-time operations on the digitized power waveform data frames to determine whether they meet a preset zero-crossing point feature or transient mutation feature; When the conditions are met, the hardware feature extraction logic gate outputs a synchronization instruction, and through data bus control logic, overwrites a hardware feature synchronization watermark in a feature identification area of the currently transmitted digitized power waveform data frames.

4. The magnetic storage core based chip based power parameter intelligent sensing and high reliable storage device according to claim 3, characterized in that, When determining the transient mutation feature, the hardware feature extraction logic gate specifically calculates the voltage waveform numerical variation rate within the adjacent sampling time interval, and when the absolute value of the variation rate is greater than or equal to a preset voltage mutation rate threshold parameter, it is determined that the transient mutation feature is met. 5.The magnetic storage chip-based power parameter intelligent sensing and high-reliability storage device of claim 1, wherein, The associated physical parameter indicative of a device operation failure includes an external sudden magnetic field strength; The hardware latch trigger circuit includes a magnetic field sensing trigger path, and the magnetic field sensing trigger path uses a magnetic tunnel junction array as a passive sensor. When the external transient magnetic field strength generated by the short circuit of the power device exceeds the physical flipping threshold of the magnetic tunnel junction array unit, the magnetic field sensing trigger path outputs the trigger signal to block the write permission. 6.The magnetic storage chip-based power parameter intelligent sensing and high-reliability storage device of claim 5, wherein, When the external transient magnetic field strength exceeds the physical flipping threshold, the magnetic tunnel junction array occurs a resistance state jump, which is converted into a level trigger state via a bridge conversion circuit and output as the trigger signal. 7.The magnetic storage chip based power parameter intelligent sensing and high reliable storage device of claim 1, wherein, The associated physical parameter of the device operation fault characterization device includes a device power bus voltage; The hardware latch trigger circuit includes a voltage drop monitoring path provided with a hardware differential circuit and a hardware voltage comparator, for real-time monitoring of the analog level signal of the device power bus voltage; When the amplitude of the analog level signal is detected to be lower than the preset critical safety voltage threshold, and the voltage drop rate extracted via the hardware differential circuit reaches the set voltage drop rate threshold parameter, it is determined that the associated physical parameter is out of limit. 8.The magnetic storage chip based power parameter intelligent sensing and high reliable storage device of claim 2, wherein, When the main control microprocessor performs the physical addressing inverse mapping, the physical write address corresponding to the discrete latched data is read, the physical write address is subtracted from the physical base address, multiplied by the multiplicative inverse of the physical space jump step parameter with respect to the total capacity of the ring buffer, and finally the total capacity of the ring buffer is taken modulo operation, thereby inversely restoring the corresponding time series sampling point index; When the main control microprocessor checks that some physical block data is missing, the adjacent valid data points on the time series are used for interpolation repair. 9.The magnetic storage chip based power parameter intelligent sensing and high reliable storage device of claim 3, wherein, After the main control microprocessor assembles the continuous time series array, the data frame containing the hardware feature synchronization watermark is globally traversed and extracted; The extracted hardware feature synchronization watermark is used as a phase anchor point, and the absolute electrical phase of the power waveform is inversely deduced in combination with the set power grid power frequency cycle parameter, so as to define the absolute time coordinate of the trigger latch moment. 10.The magnetic storage chip based power parameter intelligent sensing and high reliable storage device of claim 1, wherein, During the normal operation of the direct memory access controller according to the continuous cyclic write of the addressing control parameter, the main control microprocessor reads the historical waveform data stored in the magnetic random access memory via a bus arbitration or dual-port access mechanism, independently of the read timing of the direct memory access controller; The reading operation and the underlying cyclic write process of the direct memory access controller are independently running and not interrupting each other.

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