On-die automatic voltage trimming method, self-test and repair method and system

Abstract

The application discloses a memory built-in automatic voltage trimming method, a self-test and repair method and system, and relates to the field of memory testing.The memory built-in automatic voltage trimming method comprises the following steps: sequentially reading each group of working voltage parameters stored in advance, and generating a control voltage corresponding to a to-be-tested memory; under each group of working voltage parameters, performing a chip defect test on the to-be-tested memory respectively, taking the number of failure addresses and / or the test pass rate in the test result as the evaluation basis of the advantages and disadvantages of the voltage parameters, and selecting an optimal group of working voltage parameters as the control voltage parameter of the to-be-tested memory.Through the unified test controller, the three functions are cooperatively scheduled, and the whole process of testing, diagnosing, repairing, trimming and verifying is automatically completed under the condition of single power-on; the voltage trimming takes the BIST test result as the evaluation basis, and ensures the effectiveness of detection and repair; and the voltage margin information is used for guiding the allocation of redundant resources, and the active prevention of potential failure is realized.

Description

Technical Field

[0001] This disclosure belongs to the field of semiconductor testing technology, specifically relating to a method for automatic voltage fine-tuning built into a memory, a self-testing and repair method and system. Background Technology

[0002] As semiconductor processes continue to evolve towards more advanced stages (such as 7nm, 5nm and below), embedded memory's area proportion in System-on-a-Chip (SoC) continues to increase, making it one of the most critical components of an SoC. At the same time, memory testing and repair face increasingly severe challenges, mainly due to the following reasons:

[0003] (1) The complexity of memory testing is increasing. With the continuous improvement of memory capacity and density, the physical spacing between memory cells is shrinking and the impact of process fluctuations is intensifying. Various new fault modes, such as dynamic read interference faults and write interference faults, are constantly emerging. Traditional fixed test algorithms are no longer able to cover all fault types. Once the chip is fabricated, if it is found that the original test algorithm cannot effectively detect certain faults during the CP test (Chip Probe) or FT test (Final Test) stage, the behavior of the test algorithm in the existing technology cannot be modified. This makes it impossible for test engineers to flexibly adjust the test strategy after fabrication, which seriously restricts the improvement of test coverage and yield.

[0004] (2) There is a lack of effective means to adjust the inter-chip differences in memory operating voltage. In non-volatile memories such as MRAM and eFlash, there are significant differences in control voltages such as reference voltage, read voltage, and write voltage between different chips. In traditional solutions, these voltages need to be calibrated one by one by external testing equipment before leaving the factory, which is time-consuming and costly. Although some solutions have proposed the idea of ​​using BIST (Built-In Self-Test) for voltage adjustment, the adjustment process still requires the intervention of external test commands and cannot achieve truly fully automatic voltage fine-tuning.

[0005] (3) Defect address repair relies on external operations, which is inefficient. In existing memory repair technologies, after BIST detects a defect address, it is often necessary to output the defect information to the outside, and the redundant replacement operation is completed by external testing equipment or laser trimming equipment. This repair method that relies on external equipment increases the testing complexity, prolongs the testing time, and cannot complete the repair autonomously after the chip is powered on.

[0006] (4) The three main functions of the existing MBIST IP (Memory Built-In Self-Test IP) are fragmented and lack a coordination mechanism. In current MBIST IP products on the market, the testing function, repair function, and voltage fine-tuning function are often independent of each other. The testing algorithm is fixed and cannot be dynamically adjusted according to the repair or voltage fine-tuning results; repair requires external intervention and cannot be seamlessly integrated with the testing process; voltage adjustment cannot be completed automatically, and the adjustment results cannot be fed back to the testing algorithm for verification. This fragmented architecture leads to the need for multiple external interventions and multiple power-on and power-off cycles in the testing process, which multiplies the testing time, and the degree of automation is far from ideal.

[0007] In summary, the existing technology lacks a memory BIST & BISR IP solution that can organically integrate the three major functions of reconfigurable test algorithm, automatic defect address repair, and automatic voltage fine-tuning, and support closed-loop iterative optimization in the CP / FT stage. There is an urgent need to develop a new memory-built-in self-test and repair system and method to solve the current defects and deficiencies. Summary of the Invention

[0008] (a) Technical problems to be solved

[0009] In view of this, the main objective of this disclosure is to provide a memory-integrated self-test and repair system and method, in order to at least partially solve the above-mentioned technical problems.

[0010] (II) Technical Solution

[0011] To achieve the above objectives, as a first aspect of this disclosure, a method for built-in automatic voltage fine-tuning in a memory is proposed, comprising the following steps:

[0012] The built-in program in the memory sequentially reads each set of pre-stored operating voltage parameters and generates the control voltage corresponding to the memory under test; each set of operating voltage parameters is pre-stored in the SoC chip in the memory under test and is connected to the memory under test through an interface.

[0013] Under each set of operating voltage parameters, chip defect tests are performed on the memory under test. The number of failed addresses and / or the test pass rate in the test results are used as the evaluation criteria for the quality of the voltage parameters. The optimal set of operating voltage parameters is selected as the control voltage of the memory under test.

[0014] The evaluation criteria for the quality of the voltage parameters also take into account factors such as the adjustment flag signal and the number of failure addresses, and selects the set of operating voltage parameters that maximizes the pass rate of the memory under test and minimizes the number of failure addresses as the optimal set.

[0015] The evaluation criteria for voltage parameters also include the failure types recorded under each set of operating voltage parameters during the testing of the memory under test, and the optimal set of operating voltage parameters with the highest subsequent repair success rate and the lowest redundant resource consumption is selected based on a pre-established voltage-fault feature mapping table.

[0016] As a second aspect of this disclosure, a memory-built-in self-test and repair method is also proposed, comprising the following steps:

[0017] Step S1: Receive the test start command and configuration parameters of the reconfigurable test algorithm;

[0018] Step S2: Combine and generate the target test algorithm;

[0019] Step S3: Using the built-in automatic voltage fine-tuning method of the memory as described above, select the optimal set of operating voltage parameters of the memory under test and use them as the control voltage for solidification.

[0020] Step S4: Under optimal control voltage conditions, the memory under test automatically executes the built-in self-test program.

[0021] Step S5: If a failed storage unit is detected, the automatic repair process is triggered;

[0022] Step S6: Perform a targeted readback test on the repaired defect address to verify the effectiveness of the repair;

[0023] Step S7: The repair mapping relationship and the optimal operating voltage parameters are fixed in a predetermined storage cell in the memory under test;

[0024] Step S8: Output the test results and repair status.

[0025] As a third aspect of this disclosure, a built-in self-test and repair system for memory is also proposed. This system is integrated within the SoC chip of the memory under test (MDT) and connected to the MDT via a standard interface. The built-in self-test and repair system includes an automatic voltage adjustment module, which comprises:

[0026] The parameter register is used to store multiple sets of operating voltage parameters of the memory under test.

[0027] A voltage generation control circuit is used to generate a control voltage corresponding to the memory under test based on a set of working voltage parameters stored in a parameter register.

[0028] The parameter control circuit is used to drive the parameter register to output each set of working voltage parameters sequentially to the voltage generation control circuit, which then drives the voltage generation control circuit to generate the control voltage corresponding to the memory under test. The circuit also calls the reconfigurable test algorithm module inside the memory under test to perform chip defect tests on the memory under test under each set of working voltage parameters. The number of failed addresses and / or the test pass rate in the test results are used as the evaluation criteria for the quality of the working voltage parameters. The optimal set of working voltage parameters for the memory under test is selected as the control voltage for the memory under test.

[0029] (III) Beneficial Effects

[0030] Based on the above technical solution, the memory-built-in self-testing and repair method and system disclosed herein, compared with the prior art, has at least one of the following beneficial effects:

[0031] 1. The closed-loop automated process disclosed herein significantly improves testing efficiency. In existing technologies, testing, repair, and voltage adjustment need to be performed step by step, and multiple external devices need to be involved, requiring multiple power cycles. This disclosure achieves coordinated scheduling of the three functions through a unified test controller, automatically completing the entire process of "testing -> diagnosis -> repair -> fine-tuning -> verification" under a single power-on condition, reducing the testing time from seconds to milliseconds to hundreds of milliseconds.

[0032] 2. Collaborative iterative optimization improves test accuracy and yield. Voltage fine-tuning uses BIST test results as the evaluation basis, rather than simply relying on external flag signals; targeted verification is automatically triggered after repair to ensure the effectiveness of the repair; voltage margin information is used to guide the allocation of redundant resources, enabling proactive prevention of potential failures. This triple collaborative mechanism results in significantly higher test coverage and product yield than traditional solutions where each function operates independently.

[0033] 3. Adaptive strategy to optimize redundant resource utilization. The redundancy analysis circuit dynamically selects the repair strategy based on the failure address distribution pattern, avoiding resource waste or repair failure caused by a fixed strategy. The introduction of voltage margin information makes the repair decision more intelligent, upgrading "passive repair" to "active prevention".

[0034] 4. The combination of incremental repair and reconfigurable algorithms significantly reduces the testing cost in the FT stage. When a new fault is discovered in the FT stage, it is not necessary to re-execute the full-chip test. Instead, test elements are added through the reconfigurable architecture, and incremental repair and targeted verification are performed on the newly added defect addresses, avoiding the high time cost of retesting the entire chip.

[0035] 5. Reconfigurable test algorithms overcome the limitation of being unadjustable after tape-out. Through element-based and modular design of test components, the composition and sequence of test algorithms can be flexibly adjusted during the CP / FT testing phase, effectively addressing newly discovered fault modes after tape-out. This architecture, in synergy with the voltage fine-tuning and repair modules, enables a complete closed-loop iterative capability: algorithm adjustment → defect detection → incremental repair → voltage re-optimization.

[0036] 6. Prioritizing voltage fine-tuning and repair to optimize resource allocation. For voltage-sensitive memories such as MRAM, performing voltage fine-tuning first can eliminate "false failures" caused by uncalibrated voltage, reduce unnecessary redundant resource consumption, and allocate limited redundant resources to truly failed memory cells. Further voltage optimization after repair further ensures the operational reliability of redundant cells. Attached Figure Description

[0037] Figure 1 This is a block diagram of the overall architecture of the memory-built-in self-test and repair system disclosed herein;

[0038] Figure 2 This is a flowchart illustrating the generation process of the reconfigurable test algorithm disclosed herein;

[0039] Figure 3 This is a flowchart illustrating the built-in self-test and repair method for memory disclosed herein.

[0040] Figure 4 This is a flowchart illustrating the collaborative process of the automatic voltage fine-tuning and testing algorithm module disclosed herein.

[0041] Figure 5 This is a flowchart illustrating the collaborative process between the test algorithm and the automatic repair module disclosed herein.

[0042] Figure 6 This is a flowchart illustrating the collaborative process of the voltage fine-tuning and automatic repair module disclosed herein. Detailed Implementation

[0043] To make the objectives, technical solutions, and advantages of this disclosure clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0044] To address the aforementioned shortcomings of existing technologies, this disclosure provides a memory-integrated self-test and repair method and system with an automatic voltage fine-tuning and reconfigurable test algorithm architecture. By integrating automatic voltage fine-tuning functionality, it can automatically scan the memory's operating voltage and select the optimal voltage value during the BIST testing process without external testing equipment intervention, quickly completing factory voltage adjustments. Through information interaction and scheduling coordination mechanisms among the three functions—automatic voltage fine-tuning, reconfigurable test algorithm, and automatic repair—it achieves a collaborative closed-loop architecture of "test -> diagnosis -> repair -> fine-tuning -> re-verification," ensuring the reliability of testing and repair work. Specifically, this disclosure provides a memory-integrated self-test and repair system (IP / IP core) with an automatic voltage fine-tuning and reconfigurable test algorithm architecture, including the following modules:

[0045] (I) Overall Architecture

[0046] The IP disclosed herein is integrated within a SoC chip and connects to the memory under test, such as SRAM, MRAM, eFlash, etc., via a standard interface. The IP includes, for example, a test controller, a reconfigurable algorithm state machine, a test vector generator, an address generator, a data generator, a comparator, a diagnostic tool, redundancy analysis and repair circuitry, an automatic voltage fine-tuning circuit, and external interfaces such as JTAG / IEEE 1500 / IEEE 1149.1.

[0047] The test controller is the core scheduling unit of this IP. Through a unified state machine and information bus, it realizes the coordinated scheduling and information sharing of the reconfigurable test algorithm module, automatic repair module and automatic voltage fine-tuning module.

[0048] (ii) Automatic voltage fine-tuning module

[0049] The automatic voltage fine-tuning module achieves its voltage fine-tuning function through an automatic voltage fine-tuning circuit.

[0050] The automatic voltage fine-tuning circuit includes, for example, a parameter register, a voltage generation control circuit, and a parameter control circuit. The parameter register stores multiple sets of operating voltage parameters for the memory. The voltage generation control circuit generates a corresponding control voltage based on a specific set of operating voltage parameters stored in the parameter register. The parameter control circuit drives the parameter register to sequentially output each set of operating voltage parameters to the voltage generation control circuit, which then generates the corresponding memory control voltage. Simultaneously, it invokes a reconfigurable test algorithm module to perform chip defect testing on the memory under different control voltages. The test results, such as the number of failed addresses or the test pass rate, are used as the evaluation criteria for the quality of the operating voltage parameters, rather than simply relying on externally input adjustment flag signals. Therefore, by comprehensively considering the adjustment flag signals and the number of failed addresses, the optimal operating voltage parameter is selected, maximizing the memory's test pass rate and minimizing the number of failed addresses.

[0051] Preferably, after selecting the optimal operating voltage parameters, the parameter control circuit uses them as the control voltage to call the reconfigurable test algorithm module again to perform chip defect testing on the memory, triggering the final verification test to confirm the optimization effect.

[0052] As a preferred option, when evaluating the control voltage test results, the parameter control circuit not only records the failure address and number, but also the failure type (such as fixed fault, switching fault, etc.) under each set of working voltage parameters. Based on the pre-established voltage-fault feature mapping table, it assists in selecting better working voltage parameters. Thus, the final selection is not the voltage with the highest pass rate, but the voltage that maximizes the success rate of subsequent repairs and minimizes the consumption of redundant resources.

[0053] The specific implementation methods for this step include:

[0054] 1. Add a failure type classifier to the back end of the BIST comparator; it automatically classifies failures based on the execution stage of the reconfigurable test algorithm (such as MarchC) and the failure data pattern (for example, classifying failures where the read 0 / 1 does not match the expectation as SAF (Stabilized Failure), classifying failures where two consecutive reads are different as TF (Transition Failure), etc.).

[0055] 2. Expand the record unit: Add a field to the storage unit that records the failure address to store the failure type code;

[0056] 3. Establish an evaluation function: Embed an evaluation model in the automatic voltage fine-tuning circuit (parameter control circuit). This evaluation model receives the following inputs: voltage value V, a list of failure addresses measured at that voltage, and the corresponding failure types. The logic of the evaluation model is to prioritize voltages that can "aggregate" faults. For example, if 90% of the failure types at voltage V1 are simple SAF (Self-Fault Aberration), while at voltage V2, the failure types include both SAF and complex TF (Transition Fault), then the system will prioritize V1. This is because concentrated, simple faults are easier to repair efficiently through redundant rows / columns. Only when high-priority voltages fail the repair verification will the system fall back to the solution with the highest pass rate.

[0057] (III) Reconfigurable test algorithm module

[0058] The reconfigurable test algorithm module decomposes the behavior of the memory test algorithm into several independent test elements, each corresponding to a basic sequence of memory read and write operations. The test elements are stored in the Test Element Register File inside the IP.

[0059] The test elements include, but are not limited to:

[0060] *Read / write operations in the address incrementing / decrementing direction (March element);

[0061] *Read / write operations under specific data backgrounds (such as all 0s, all 1s, checkerboard patterns, etc.) (data background switching);

[0062] *Hammer test element (n consecutive read / write operations on the same address, n is configurable).

[0063] Therefore, in typical application examples, users only need to prepare a few basic elements such as "address incrementing read", "address decrementing write", and "data background switching" to combine and generate standard test algorithms such as March C+ and March SR, or to define new custom algorithms.

[0064] like Figure 2 As shown, the reconfigurable test algorithm module is implemented, for example, through a reconfigurable algorithm state machine. The reconfigurable algorithm state machine can dynamically generate new test algorithms by combining user-specified test elements in a set order according to externally input algorithm element selection signals, such as through a JTAG interface or the send_command instruction of the test machine. Users only need to prepare a small number of basic elements to combine and generate common standard test algorithms such as March C+.

[0065] Furthermore, users can set the number of consecutive read / write operations (n) in the Hammer test element through an external interface, thereby increasing the read / write intensity in a targeted manner when detecting dynamic read interference faults, while maintaining a low test time cost in regular tests.

[0066] (iv) Automatic Repair Module

[0067] The automatic repair module is primarily implemented through an Automatic Repair Circuit (BISR). This BISR includes a redundancy resource allocation circuit, a defect address register, an address remapping circuit, and non-volatile memory units (such as eFuse). Each functional module of the BISR is implemented using conventional hardware or software. However, after redundancy replacement is completed, the test controller automatically schedules the reconfigurable test algorithm module to perform targeted readback testing only on the replaced defective addresses to verify the effectiveness of the redundancy replacement. If the verification reveals that the redundancy replacement has failed, redundant resources are reallocated and verification is performed again. Furthermore, during the Final Test (FT) stage, if the user adds a test algorithm through the reconfigurable test algorithm module and detects a new defective address, the BISR does not need to re-execute the full-chip test; it only performs incremental redundancy allocation and mapping on the newly added defective address, and performs targeted verification again after the repair is completed.

[0068] Collaborative working mechanism of the three functional modules

[0069] Unlike existing technologies, the three functional modules in this disclosure do not operate independently, but rather achieve information sharing and closed-loop iteration through a test controller. The specific collaboration mechanism is as follows:

[0070] 1. Synergy between testing algorithms and automatic voltage fine-tuning

[0071] In existing technologies, voltage fine-tuning and functional testing are two separate steps: first, the voltage is adjusted by an external device, and then a test algorithm is run for verification, which is inefficient. For example... Figure 4 As shown in this disclosure, the reconfigurable test algorithm module and the automatic voltage fine-tuning module achieve collaborative iterative optimization through a test controller:

[0072] The voltage fine-tuning driven test algorithm is adaptive: During the scanning of the working voltage parameters, the automatic voltage fine-tuning circuit calls the reconfigurable test algorithm module to perform a complete BIST test for each set of working voltage parameters. The test results (number of failure addresses, distribution of failure types) are fed back to the parameter control circuit in real time as a quantitative evaluation index of the quality of the working voltage parameter.

[0073] Intelligent voltage selection: The parameter control circuit not only records the adjustment flag signals under each working voltage parameter, but also takes into account the number of failure addresses and selects the working voltage parameter with the fewest failure addresses and the highest test pass rate as the optimal factory voltage.

[0074] Re-verification after fine-tuning: After the optimal operating voltage parameters are fixed, the test controller automatically triggers a complete round of reconfigurable test algorithms to perform final verification of the memory under optimal voltage conditions, ensuring the effectiveness of the repair and fine-tuning. The algorithm for this round of verification can be dynamically reconfigured based on the fault types found in the previous tests—for example, if a dynamic read interference fault is detected in the previous tests, a Hammer test element is automatically inserted into the verification algorithm.

[0075] Unlike traditional solutions, which require external automated testing equipment to calibrate each chip individually, taking several seconds per chip and requiring manual intervention, the BIST disclosed in this paper can achieve internal automated scanning, completing the process in milliseconds and automatically selecting the optimal control voltage.

[0076] 2. Synergy between testing algorithms and automatic repair

[0077] In existing technologies, testing and repair are independent steps performed sequentially: first, full-chip testing is completed, all defect addresses are recorded, and then redundant resources are allocated all at once. This approach cannot dynamically adjust the testing strategy based on the progress of the repair.

[0078] like Figure 5 As shown, the reconfigurable test algorithm module and automatic repair module in this disclosure can achieve real-time interaction and dynamic adjustment through the test controller:

[0079] First, perform a full-chip test at the optimal voltage, record all defect addresses, and then repair the defect addresses;

[0080] Post-repair targeted retest: After the defective address is replaced with a redundant one, the test controller automatically triggers a targeted readback test for the repaired address to verify the effectiveness of the redundant replacement, rather than simply assuming that the repair was successful.

[0081] Secondary repair after algorithm adjustment: If the user adjusts the test algorithm in the FT stage through the reconfigurable architecture, after the new algorithm detects the new failure address, it will automatically repair the module incrementally update the redundant mapping relationship without re-executing the full-chip test, which greatly shortens the test time in the FT stage.

[0082] Adaptive repair strategy: The failure address distribution information recorded by the diagnostic tool is transmitted to the redundancy analysis circuit in real time. The redundancy analysis circuit can dynamically select the optimal repair strategy (redundant row replacement, redundant column replacement, or mixed row and column replacement) according to the failure distribution pattern (row-based failure, column-based failure, random failure), instead of using a fixed strategy.

[0083] The traditional approach involves first completing full-chip testing, then recording all defects, and finally allocating redundancy all at once, with no automatic verification after repair. In contrast, this disclosure involves testing and repairing simultaneously, using an adaptive strategy, targeted verification after repair, and incremental updates, truly achieving automated closed-loop repair.

[0084] 3. Synergy between voltage fine-tuning and automatic repair

[0085] like Figure 6 As shown, the synergy between voltage fine-tuning and automatic repair is another key innovative technology that distinguishes it from existing technologies:

[0086] Fine-tuning takes precedence over repair: In certain memory types, especially voltage-sensitive memories such as MRAM, some memory cells that were initially misjudged as faulty may return to normal operation after voltage fine-tuning. In this disclosure, the test controller performs voltage fine-tuning first by default, followed by defect detection and repair, to avoid false failures caused by uncalibrated voltage, thereby reducing unnecessary redundant resource consumption.

[0087] Voltage re-optimization after repair: After performing redundancy replacement, since the electrical characteristics of the redundant storage cells may differ slightly from the original cells, the test controller can automatically re-trigger the voltage fine-tuning process to find the optimal operating voltage under the circuit topology after redundancy replacement.

[0088] Resource-aware repair strategy: The automatic voltage fine-tuning circuit provides voltage margin information to the redundancy analysis circuit. If the read / write margin of a memory cell is close to the critical value under the current operating voltage parameters, the cell is marked as a "weak cell." Even if the current test passes, it is considered a potential failure risk and is prioritized for replacement with redundant resources. This mechanism upgrades repair from "passively responding to failures that have already occurred" to "actively preventing potential failures," significantly improving the long-term reliability of the memory.

[0089] Traditional solutions in the prior art involve voltage fine-tuning and repair being performed independently. Faults are detected first, and redundancy is then allocated, making it impossible to distinguish between "true failures" and "false failures." They lack voltage margin sensing capabilities, only addressing failed cells and failing to prevent potential failures. In contrast, this disclosure prioritizes fine-tuning -> eliminates false failures -> uses voltage margin to guide weak cell prevention -> optimizes voltage after repair, enabling intelligent and proactive repair.

[0090] As shown in Table 1, the above-mentioned synergistic mechanism brings a systemic advantage that goes beyond the simple addition of parts:

[0091] Table 1 Performance Comparison of Integrated Collaboration and Function Stacking

[0092]

[0093] (v) Overall Work Process

[0094] In a preferred embodiment, such as Figure 3 As shown, the workflow of the memory-built-in self-test and repair system (IP) disclosed herein is as follows:

[0095] Step S1: The IP receives the test start command and algorithm configuration parameters through an external interface (JTAG / IEEE 1500 / IEEE 1149.1). The configuration parameters include: algorithm element sequence (specifying the execution order of each test element), the number of consecutive read / write operations n for the Hammer test element, voltage scan range (start parameter, end parameter, step value), and repair strategy selection (forced row priority / forced column priority / adaptive), etc.

[0096] Step S2: The reconfigurable algorithm state machine reads the corresponding test element micro-operation sequence from the test element register file according to the received algorithm element selection signal, and combines them in the configured order to generate the target test algorithm.

[0097] Step S3 (Voltage fine-tuning priority, for voltage-sensitive memories such as MRAM): The test controller sends a start signal to the automatic voltage fine-tuning circuit via the scheduling information bus. The automatic voltage fine-tuning circuit starts voltage scanning according to the process in Example 3. For each set of operating voltage parameters, the test controller schedules the reconfigurable algorithm state machine to perform a complete BIST test, feeding back the number of failed addresses to the parameter control circuit in real time. The parameter control circuit integrates the trimming flag signal and the number of failed addresses, selects the optimal voltage value, and stores it in a non-volatile memory cell.

[0098] For voltage-insensitive memories such as SRAM, this step can be skipped or postponed. The memory type is determined through a type configuration register written via an external interface.

[0099] Step S4: Under optimal voltage conditions, the test controller formally executes the BIST test. The test vector generator generates test stimuli, the address generator generates addresses according to the address sequence specified by the reconfigurable algorithm state machine, and the data generator generates the corresponding test data. These three components work together to apply the test vector to the memory under test. The comparator reads the actual output of the memory and compares it with the expected value, and the diagnostic unit records the failure address.

[0100] Step S5: If the diagnostic tool detects a failed memory cell, the test controller triggers an automatic repair process via the scheduling information bus. The redundancy analysis circuit (BIRA) adaptively selects a redundancy row / column allocation strategy based on the failure address distribution, and the address remapping circuit completes the switching from the defective address to the redundant address.

[0101] Step S6 (Repair Verification): After the redundancy replacement is completed, the test controller automatically schedules the reconfigurable algorithm module to perform a targeted readback test on the replaced defective address. If the verification passes, proceed to step S7; if the verification fails, return to step S5 to reallocate redundant resources.

[0102] Step S7 (Post-repair fine-tuning, optional): If the memory type is voltage-sensitive MRAM, the test controller automatically triggers a second round of voltage fine-tuning to find the optimal operating voltage under the circuit topology after redundancy replacement. The execution process of the second round of fine-tuning is the same as step S3, but the test object is the memory (including redundant cells) that has completed redundancy replacement. Post-repair fine-tuning ensures that redundant cells operate under optimal voltage conditions.

[0103] Step S8: Repair the mapping relationship and the optimal operating voltage parameters and store them in a non-volatile memory cell (eFuse).

[0104] Step S9: The test results (total number of pass / fail, number of failed addresses, and repair status) and repair status are output through an external interface.

[0105] The priority order of steps S3 (voltage fine-tuning) and S5 (automatic repair) can be configured via an external interface according to the memory type: for voltage-sensitive memories such as MRAM, S3 is executed first by default; for voltage-insensitive memories such as SRAM, S3 can be skipped or delayed until after S7. Step S7 (post-repair fine-tuning) is an optional step, which can be enabled or disabled through the type configuration register.

[0106] This disclosure also discloses a method for built-in automatic voltage fine-tuning in a memory, comprising the following steps:

[0107] The built-in program in the memory sequentially reads each set of operating voltage parameters stored in the register and generates the control voltage corresponding to the memory under test; the register is located in the SoC chip inside the memory under test and is connected to the memory under test through an interface;

[0108] The reconfigurable test algorithm module inside the memory under test is invoked to perform chip defect tests on the memory under test under each set of operating voltage parameters. The number of failed addresses and / or the test pass rate in the test results are used as the evaluation criteria for the quality of the operating voltage parameters, and the optimal set of operating voltage parameters is selected as the control voltage of the memory under test.

[0109] Among them, taking into account factors such as the adjustment flag signal and the number of failed addresses, the set of operating voltage parameters that maximizes the test pass rate of the memory under test and minimizes the number of failed addresses is selected as the optimal operating voltage parameters.

[0110] In this process, after selecting the optimal set of operating voltage parameters, the reconfigurable test algorithm module is called again to perform chip defect testing on the memory under test, using these parameters as the control voltage, to confirm the optimization effect.

[0111] This disclosure also discloses a built-in self-testing and repair method for memory, including the following steps:

[0112] Step S1: Receive the test start command and configuration parameters of the reconfigurable test algorithm;

[0113] Step S2: Combine and generate the target test algorithm;

[0114] Step S3: Using the built-in automatic voltage fine-tuning method of the memory as described above, select the optimal set of operating voltage parameters of the memory under test as the control voltage and fix it.

[0115] Step S4: Under optimal control voltage conditions, the built-in program in the memory automatically executes the built-in self-test items in the memory.

[0116] Step S5: If a failed storage unit is detected, the automatic repair process is triggered;

[0117] Step S6: Perform a targeted readback test on the repaired defects to verify the effectiveness of the repair;

[0118] Step S7: The repaired mapping relationship and the optimal set of working voltage parameters are permanently stored in a non-volatile memory unit;

[0119] Step S8: Output the test results and repair status.

[0120] The step S2, which generates the target test algorithm, is achieved by combining test elements. These test elements include: read / write operations in the address increment / decrement direction; read / write operations under specific data contexts; and Hammer test elements.

[0121] The step S2, which involves generating the target test algorithm, combines the user-specified test elements in a set order according to the externally input algorithm element selection signal or the send_command instruction from the test machine, to dynamically generate a new test algorithm.

[0122] In step S2, users can set the number of consecutive read / write operations n in the Hammer test element through an external interface. This allows for targeted increases in read / write intensity when detecting dynamic read interference faults, while maintaining a low test time cost during regular tests.

[0123] In step S4, during the execution of the built-in self-test project of the memory, the memory cell is also marked based on the voltage margin information. If its read / write margin is close to the critical value, it is marked as a weak cell. Even if the current test passes, it is regarded as a potential failure risk and redundant resources are allocated to replace it first.

[0124] In step S5, during the FT stage, if the user adds a test algorithm through the reconfigurable test algorithm module and detects a new defect address, the automatic repair circuit will only perform incremental redundancy allocation and mapping on the newly added defect address, and perform targeted verification again after the repair is completed.

[0125] In step S6, if the verification finds that the redundancy replacement has failed, the redundant resources are reallocated and verified again.

[0126] Specifically, for voltage-sensitive memory MRAM, step S3 is executed between steps S2 and S4; for voltage-insensitive memory SRAM, step S3 can be delayed until between steps S6 and S7.

[0127] In step S6, after the repair is completed, since the electrical characteristics of the redundant unit may differ from those of the original unit, the voltage fine-tuning process can be automatically re-triggered to achieve a two-layer closed-loop iteration of "repair → fine-tuning".

[0128] This disclosure also discloses a memory-built-in program / instruction set stored in the SoC chip of the memory under test, used to execute the memory-built-in self-test and repair method described above.

[0129] This disclosure also discloses a storage medium on which the program / instruction set described above is stored.

[0130] The present disclosure will be further illustrated below through specific embodiments. It should be noted that the following embodiments are merely illustrative and not intended to limit the present disclosure.

[0131] Example 1: Memory-Built Self-Test and Repair IP (MBIST & BISR IP)

[0132] This embodiment provides a memory-integrated self-test and repair IP / system with an automatic voltage trimming and reconfigurable test algorithm architecture. The IP is integrated within a SoC chip and connects to the memory under test (such as SRAM, MRAM, eFlash, etc.) via a standard memory interface. The core components of the IP include: a test controller, a reconfigurable algorithm state machine (FSM), a test pattern generator, an address generator, a data generator, a comparator, a diagnostic tool, redundancy analysis and repair circuitry (BIRA & BISR), an automatic voltage trimming circuit, and external interfaces (JTAG / IEEE 1500 / IEEE 1149.1).

[0133] The test controller is the core scheduling unit of this IP, implemented using a finite state machine (FSM). Internally, the test controller includes a unified status register and a scheduling information bus. The status register records the current stage of the test process (idle, voltage fine-tuning, functional testing, defect diagnosis, repair analysis, redundancy replacement, repair verification, post-repair fine-tuning, result output). The scheduling information bus transmits control signals and status feedback between the functional modules. Through the unified scheduling information bus, the test controller achieves coordinated scheduling and information sharing among the reconfigurable test algorithm module, automatic repair module, and automatic voltage fine-tuning module.

[0134] In terms of specific circuit implementation, the test controller adopts a two-level state machine structure: the main state machine is responsible for macroscopic process control (i.e., the jumps and scheduling of each step from S1 to S9), and the sub-state machines are responsible for the microscopic operation timing within each functional module. The main state machine and the sub-state machines are synchronized through handshake signals. The test controller also includes a configuration register group for storing algorithm configuration parameters, voltage scan range parameters, repair strategy selection parameters, etc., written externally via the JTAG / IEEE 1500 interface.

[0135] The BIST controller connects to the memory via a dedicated test interface. In test mode, the test controller takes over the memory's address, data, and control lines through the test interface, applies test vectors, and reads the responses. Functional paths and test paths are isolated using a test collar or multiplexer to ensure that functional logic and test logic do not conflict.

[0136] Example 2: Reconfigurable Test Algorithm Architecture

[0137] This embodiment describes in detail the hardware implementation scheme of the reconfigurable test algorithm module.

[0138] The reconfigurable test algorithm architecture decomposes the behavior of the memory test algorithm into several independent test elements. Each test element corresponds to a basic memory read / write operation sequence. Test elements are stored in the Test Element Register File within the IP. Specifically, the predefined test elements in this embodiment include, but are not limited to:

[0139] Element E0: Read operation in the address increment direction;

[0140] Element E1: Write operation in the address increment direction;

[0141] Element E2: Read operation in the direction of address decrement;

[0142] Element E3: Write operation in the direction of address decrement;

[0143] Element E4: Read operations under specific data contexts (all 0s, all 1s, checkerboard patterns, etc.);

[0144] Element E5: Write operation in a specific data context;

[0145] Element E6: The Hammer test element performs multiple consecutive read and write operations on the same address;

[0146] Element E7: Address jump read operation (used to detect read interference faults).

[0147] Each test element is implemented at the hardware level as an independent sequence of micro-operations, which are executed by a reconfigurable algorithm state machine.

[0148] The reconfigurable algorithm state machine is the core circuit for realizing algorithm reconfigurability. This state machine consists of three main components: an algorithm configuration register, an element sequence pointer, and an element execution engine.

[0149] Algorithm Configuration Register: Stores the algorithm element sequence configuration information written by the user through the external interface (JTAG / IEEE 1500). The configuration information is in the format of an element number sequence. For example, a configuration value of {E0, E1, E4, E2, E3, E6(n=5)} indicates that elements E0, E1, E4, E2, E3, and Hammer test element E6 with 5 consecutive read / write attempts will be executed sequentially.

[0150] Element sequence pointer: Points to the position of the currently executed test element in the algorithm configuration register. The pointer automatically increments after each test element is executed, pointing to the next element.

[0151] Element execution engine: Based on the test element number pointed to by the element sequence pointer, it reads the corresponding micro-operation sequence from the test element register file and drives the address generator, data generator and memory control signals to complete the execution of the element.

[0152] Users can set the number of consecutive read / write operations, n (where n is a positive integer), in Hammer test element E6 via an external interface. This value is stored in the parameter field of the algorithm configuration register. When detecting dynamic read interference faults (dRDF), users can set a larger n value to increase read / write intensity; in regular tests, a smaller n value can be set to control the test time.

[0153] Typical application example: Users only need to prepare the four basic elements E0 to E3 mentioned above, and combine them in a specific order to generate the March C+ standard test algorithm. Specifically, each March element in the March C+ algorithm can be mapped as: write all 0s (E1 + data background 0), read 0 and write 1 (E0 + E1 + data background switching), read 1 and write 0 (E2 + E3 + data background switching), etc. By rearranging and combining the elements, standard test algorithms such as March SR and March SS can also be generated, or entirely new test algorithms can be customized based on newly discovered fault modes after tape-out.

[0154] In terms of hardware implementation, the reconfigurable algorithm state machine is designed at the RTL level using Verilog HDL. The circuit area overhead after synthesis increases by no more than 15% compared to the traditional fixed algorithm BIST controller, but the flexibility is significantly improved.

[0155] Example 3: Automatic Voltage Fine-Tuning Circuit

[0156] This embodiment describes in detail the hardware implementation scheme of the automatic voltage fine-tuning module and its coordination mechanism with the testing algorithm.

[0157] The automatic voltage fine-tuning circuit includes: a parameter register, a voltage generation control circuit, and a parameter control circuit.

[0158] Parameter register: Used to store multiple sets of operating voltage parameters. Each set of parameters corresponds to a set of control voltage settings, including reference voltage (Vref), read voltage (Vread), and write voltage (Vwrite). The parameter register is implemented using an addressable register file, and each set of parameters is assigned a unique index number (0, 1, 2, ..., M-1), where M is the total number of parameter sets.

[0159] Voltage generation control circuit: Receives digital parameters from the parameter register, converts them into corresponding analog control voltages via a digital-to-analog converter (DAC), and compares each generated control voltage with an externally input target reference voltage. The comparison result is output as a trimming flag signal. The number of oscillations of the trimming flag signal reflects how close the current control voltage is to the target voltage.

[0160] Parameter control circuit: This is the core control unit for automatic voltage fine-tuning. Unlike existing technologies that rely solely on adjustment flag signals to select operating voltage parameters, the parameter control circuit of this disclosure simultaneously invokes the reconfigurable test algorithm module to perform a complete BIST test on the memory while scanning each operating voltage parameter. The test results (number of failed addresses, test pass rate) are used as a quantitative evaluation index of the quality of the operating voltage parameters.

[0161] The specific workflow of automatic voltage fine-tuning is as follows:

[0162] Step VT1: The parameter control circuit causes the parameter register to output the working voltage parameters from group 0 to group M-1 sequentially to the voltage generation control circuit.

[0163] Step VT2: For each set of operating voltage parameters, the voltage generation control circuit generates the corresponding control voltage and outputs a trimming flag signal. The parameter control circuit counts the number of oscillations of the trimming flag signal within a fixed time window to obtain the first evaluation index.

[0164] Step VT3 (Key Innovation Step): Under the same set of operating voltage parameters, the test controller schedules the reconfigurable algorithm state machine to execute a complete BIST test. The test vector generator, address generator, and data generator work together to apply the test algorithm generated by the reconfigurable algorithm state machine to the memory under test. The comparator reads the actual output of the memory and compares it with the expected value, and the diagnostic unit records the number and distribution of failed addresses. The number of failed addresses is fed back to the parameter control circuit as a second evaluation metric.

[0165] Step VT4: The parameter control circuit combines the first evaluation index (number of oscillations of the adjustment flag signal) and the second evaluation index (number of failure addresses) to select the optimal operating voltage parameters according to the following selection rules:

[0166] First, select parameter groups whose oscillation count of the adjustment flag signal is greater than the preset threshold (i.e., the control voltage is close enough to the target voltage);

[0167] Among the filtered parameter groups, the parameter group that maximizes the memory test pass rate (i.e. minimizes the number of failed addresses) is selected as the optimal operating voltage parameter.

[0168] Step VT5: The optimal operating voltage parameters are stored in a non-volatile memory cell (such as eFuse) for use when the chip is working normally.

[0169] The aforementioned automatic voltage fine-tuning process is completed automatically within BIST, eliminating the need for external ATE equipment to calibrate each chip individually, thus reducing the calibration time of several seconds per chip in traditional solutions to the millisecond level.

[0170] Example 4: Automatic Repair Circuit (BISR)

[0171] This embodiment describes in detail the hardware implementation scheme of the automatic repair module and its coordination mechanism with the testing algorithm.

[0172] The Automatic Repair Circuit (BISR) includes: a Redundancy Allocation Circuit, a Fault Address Register, an Address Remapping Circuit, and non-volatile memory cells (such as eFuse).

[0173] Built-in Redundancy Analysis (BIRA) circuit: Receives the failure address distribution information output by the diagnostic tool, executes a redundancy analysis algorithm, and determines the optimal matching scheme between failure addresses and redundant resources (redundant rows / columns). The core of the BIRA circuit is a redundancy analysis algorithm engine implemented using a finite state machine. This engine dynamically selects the optimal repair strategy based on the distribution pattern of failure addresses (row-based failure, column-based failure, random failure).

[0174] *If the failed addresses are concentrated in a few rows, the redundant row replacement strategy should be used first.

[0175] *If the failed addresses are concentrated in a few columns, the redundant column replacement strategy should be used first.

[0176] If the failure addresses are randomly distributed, a row-column hybrid replacement strategy is adopted, and the optimal solution is found by solving the row / column coverage optimization problem (NP-complete problem).

[0177] When allocating redundant resources, the redundancy resource allocation circuit also receives voltage margin information from the automatic voltage fine-tuning circuit. If the read / write margin of a memory cell under the current operating voltage parameters is lower than a preset threshold, even if the cell has passed the current test, it is marked as a weak cell and will be given priority for allocation of redundant resources during the redundancy resource allocation process. This mechanism upgrades the repair process from passively responding to existing failures to actively preventing potential failures.

[0178] Defect Address Register: Employing a First-In-First-Out (FIFO) or Content-Addressable Memory (CAM) structure, this register temporarily stores the failure addresses detected by the diagnostic tool. The defect address register supports incremental updates—when a new test algorithm detects a new failure address during the FT phase, the new address can be appended to the register without overwriting existing records.

[0179] Address remapping circuit: Based on the repair mapping relationship output by the redundancy resource allocation circuit, the operation of accessing the defective address is remapped to the corresponding redundant address when the chip is working normally. The address remapping circuit is implemented using a comparator array—the input address is compared in parallel with all defective addresses stored in the defective address register, and if they match, the corresponding redundant address is output.

[0180] Non-volatile memory cells: Implemented using an eFuse (electrically programmable fuse) array. The repair mapping relationship (the correspondence table of defective addresses -> redundant addresses) is written to the eFuse after repair is completed via programming. Each time the chip powers on, the BISR circuit reads the repair mapping relationship from the eFuse and loads it into the address remapping circuit.

[0181] The specific workflow of the automatic repair module is as follows:

[0182] Step RE1: During the BIST test, the diagnostic tool detects the failure address in real time and writes the detected failure address into the defect address register.

[0183] Step RE2: The redundancy resource allocation circuit reads the failure address information from the defect address register and executes the redundancy analysis algorithm. During the analysis, the distribution pattern of the failure addresses (row-based / column-based / random) and the voltage margin information (weak cell marker) from the voltage fine-tuning circuit are comprehensively considered to dynamically select the optimal repair strategy and generate a repair mapping relationship.

[0184] Step RE3: The address remapping circuit completes the switching from the defective address to the redundant address based on the repair mapping relationship.

[0185] Step RE4 (Targeted Verification After Repair): After the redundancy replacement is completed, the test controller automatically schedules the reconfigurable algorithm module to perform a targeted readback test only on the replaced defective addresses to verify the effectiveness of the redundancy replacement. The address range of the targeted readback test is limited to all defective addresses recorded in the defective address register, rather than the entire chip address space, thus keeping the verification time within a very small range. If the verification passes, the repair mapping relationship is permanently stored in eFuse; if the verification fails, the process returns to step RE2 to reallocate redundant resources.

[0186] Step RE5 (Incremental Repair): During the FT phase, if the user adds a test algorithm through the reconfigurable architecture, and the new algorithm detects a new faulty address, the automatic repair circuit does not need to re-execute the full-chip test. Instead, it performs incremental redundancy allocation and mapping only for the newly added defective address. Specifically, the newly detected faulty address is appended to the defective address register; the redundancy resource allocation circuit performs redundancy analysis only for the newly added address; the address remapping circuit incrementally updates the mapping relationship; and targeted verification is performed. This incremental repair mechanism significantly shortens the testing time during the FT phase.

[0187] Finally, it should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the systems or apparatus disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and relevant parts can be referred to the method section.

[0188] The above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit it. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A method for built-in automatic voltage fine-tuning in a memory, characterized in that, Includes the following steps: The built-in program in the memory sequentially reads each set of pre-stored operating voltage parameters and generates the control voltage corresponding to the memory under test; each set of operating voltage parameters is pre-stored in the SoC chip in the memory under test and is connected to the memory under test through an interface. Under each set of operating voltage parameters, chip defect tests are performed on the memory under test. The number of failed addresses and / or the test pass rate in the test results are used as the evaluation criteria for the quality of the voltage parameters. The optimal set of operating voltage parameters is selected as the control voltage of the memory under test.

2. The memory-integrated automatic voltage fine-tuning method according to claim 1, characterized in that, The evaluation criteria for the quality of voltage parameters also take into account factors such as the adjustment flag signal and the number of failure addresses, and selects the set of operating voltage parameters that maximizes the pass rate of the memory under test and minimizes the number of failure addresses as the optimal set.

3. The memory-integrated automatic voltage fine-tuning method according to claim 1, characterized in that, The evaluation criteria for voltage parameters also include the failure types recorded under each set of operating voltage parameters during the testing of the memory under test, and the optimal set of operating voltage parameters with the highest subsequent repair success rate and the lowest redundant resource consumption is selected based on a pre-established voltage-fault feature mapping table.

4. A built-in self-test and repair method for memory, characterized in that, Includes the following steps: Step S1: Receive the test start command and configuration parameters of the reconfigurable test algorithm; Step S2: Combine and generate the target test algorithm; Step S3: Using the built-in automatic voltage fine-tuning method for memory as described in any one of claims 1-3, select the optimal set of operating voltage parameters for the memory under test and use them as the control voltage for solidification. Step S4: Under optimal control voltage conditions, the memory under test automatically executes the built-in self-test program. Step S5: If a failed storage unit is detected, the automatic repair process is triggered; Step S6: Perform a targeted readback test on the repaired defect address to verify the effectiveness of the repair; Step S7: The repair mapping relationship and the optimal operating voltage parameters are fixed in a predetermined storage cell in the memory under test; Step S8: Output the test results and repair status.

5. The memory-built-in self-test and repair method according to claim 4, characterized in that, Step S2, which generates the target test algorithm, is achieved by combining test elements; these test elements include: read / write operations in address increment / decrement directions; read / write operations under specific data contexts; Hammer test elements; and / or Step S2, which involves generating the target test algorithm, combines user-specified test elements in a set order based on externally input algorithm element selection signals or the send_command command from the test equipment, to dynamically generate a new test algorithm; and / or In step S2, users can set the number of consecutive read / write operations n in the Hammer test element through an external interface, which can increase the read / write intensity in a targeted manner when detecting dynamic read interference faults, while maintaining a low test time cost in regular tests.

6. The memory-built-in self-test and repair method according to claim 4, characterized in that, In step S4, during the execution of the built-in self-test project of the memory, the memory cell is also marked based on the voltage margin information. If its read / write margin is close to the critical value, it is marked as a "weak cell". Even if the current test passes, it is regarded as a potential failure risk and redundant resources are allocated to replace it first. In step S5, during the final testing phase, if the user adds a test algorithm through the reconfigurable test algorithm module and detects a new defect address, the automatic repair circuit will only perform incremental redundancy allocation and mapping on the newly added defect address, and perform targeted verification again after the repair is completed. In step S6, if the verification finds that the redundancy replacement has failed, the redundant resources are reallocated and the verification is performed again. For voltage-sensitive memory (MRAM), step S3 is executed between steps S2 and S4; for voltage-insensitive memory (SRAM), step S3 is delayed until between steps S6 and S7.

7. The memory-built-in self-test and repair method according to claim 4, characterized in that, Step S3 is executed between steps S2 and S4, and the voltage fine-tuning process will be automatically re-triggered when the repair is completed in step S6, thus realizing a two-layer closed-loop iteration of repair and fine-tuning.

8. A memory-integrated self-test and repair system, wherein the memory-integrated self-test and repair system is integrated within the SoC chip of the memory under test and connected to the memory under test via a standard interface; characterized in that, The built-in self-test and repair system of the memory includes an automatic voltage fine-tuning module, which includes: The parameter register is used to store multiple sets of operating voltage parameters of the memory under test. A voltage generation control circuit is used to generate a control voltage corresponding to the memory under test based on a set of working voltage parameters stored in a parameter register. The parameter control circuit is used to drive the parameter register to output each set of working voltage parameters sequentially to the voltage generation control circuit, which then drives the voltage generation control circuit to generate the control voltage corresponding to the memory under test. The circuit also calls the reconfigurable test algorithm module inside the memory under test to perform chip defect tests on the memory under test under each set of working voltage parameters. The number of failed addresses and / or the test pass rate in the test results are used as the evaluation criteria for the quality of the working voltage parameters. The optimal set of working voltage parameters for the memory under test is selected as the control voltage for the memory under test.

9. The memory-built-in self-test and repair system according to claim 8, characterized in that, The evaluation criteria for the quality of the operating voltage parameters also include the failure type recorded under each set of operating voltage parameters when the memory under test is tested, and the set of operating voltage parameters with the highest subsequent repair success rate and the lowest redundant resource consumption is selected as the control voltage of the memory under test based on a pre-established voltage-fault feature mapping table.

10. The memory-built-in self-test and repair system according to claim 8, characterized in that, The built-in self-testing and repair system of the memory also includes a reconfigurable test algorithm module and an automatic repair module. The reconfigurable test algorithm module is used to generate a target test algorithm based on user input parameters combined with test elements. The automatic repair module is used to automatically repair defects discovered by the reconfigurable test algorithm module. The test elements include: read / write operations in address incrementing / decrementing directions; read / write operations under specific data contexts; and Hammer test elements. When executing the built-in self-test project in the memory, the reconfigurable test algorithm module also marks the memory cell based on the voltage margin information. If its read / write margin is close to the critical value, it is marked as a "weak cell". Even if the current test passes, it is regarded as a potential failure risk and redundant resources are allocated to replace it first. During the final testing phase, if the user adds a test algorithm through the reconfigurable test algorithm module and detects a new defect address, the automatic repair module will only perform incremental redundancy allocation and mapping on the newly added defect address, and perform targeted verification again after the repair is completed. If the automatic repair module verifies that the redundant replacement has failed, it will reallocate the redundant resources and verify again.

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