A voltage clamping and monitoring integrated high current rate of change thyristor hard trigger circuit and method

Abstract

The application discloses a high-current change rate thyristor strong trigger circuit and method with voltage clamping and monitoring integration, and belongs to the technical field of pulse power. In the application, a three-order RLC discharge topology is adopted for a pulse forming circuit, a resonance network is formed through an energy storage capacitor, a compensation capacitor and line stray parameters, the three-order RLC resonance discharges, a high-amplitude and high-gradient trigger pulse is generated, and conduction delay is compressed to within several microseconds. After the trigger pulse ends, a voltage clamping branch utilizes a power MOSFET switch to provide a low-impedance discharge path for gate leakage current, reduces NPN transistor common base current gain, and suppresses high-temperature false conduction. A series voltage-sharing monitoring unit is based on voltage-to-frequency conversion and optical fiber isolation, can collect thyristor terminal voltage in real time and feed back to a control system, and realizes rapid fault identification and protection. The application has the functions of fast turn-on, high-temperature blocking enhancement and online monitoring, and is suitable for microsecond-level pulse width and hundred-kilovolt ampere-level strong current impact working conditions.

Description

Technical Field

[0001] This invention relates to the field of pulse power technology, specifically to a high current change rate thyristor strong triggering circuit and method that integrates voltage clamping and monitoring. Background Technology

[0002] In high-power pulse applications such as compact ring feeding and electromagnetic emission, thyristors are the ideal choice as the main switching device due to their high voltage withstand capability and large current carrying capacity. However, these applications typically require microsecond-level pulse widths, hundreds of kiloampere-level peak currents, and extremely high current change rates, which place stringent requirements on the thyristor's turn-on performance.

[0003] Traditional pulse transformer induction triggering, as the mainstream gate drive scheme, typically operates as follows: After the control system sends a trigger signal, the pulse transformer performs electrical isolation and voltage amplitude conversion. The induced voltage generated on the secondary side of the transformer is converted to DC level by a rectifier circuit, and then applied between the gate and cathode of the thyristor through a current-limiting resistor to form a trigger pulse. If the rectification stage is omitted, the gate is directly driven by the AC induced voltage. The amplitude, leading-edge steepness, and pulse width of the trigger pulse are mainly determined by the transformer turns ratio, core saturation characteristics, and primary-side energy storage capacitor parameters. Due to its simple structure, good electrical isolation performance, and low cost, this scheme has long been widely used in small and medium power pulse power supplies. A typical topology of traditional pulse transformer triggering is shown below. Figure 1 As shown.

[0004] However, traditional pulse transformer triggering methods have significant limitations under microsecond pulse high-current impact conditions. First, constrained by transformer leakage inductance, distributed capacitance, and core frequency characteristics, the rise rate of the secondary output trigger current is usually insufficient, and the amplitude is difficult to meet the requirements for rapid turn-on. The measured conduction delay time is as long as tens of microseconds or more. In thyristor series applications, the turn-on times of each device are highly dispersed, and the overvoltage that the first device to turn on can withstand can reach 1.5 times the charging voltage, seriously threatening device safety. Second, traditional triggering modules only have the function of applying the gate pulse and do not include a cathode short-circuit clamping branch. Under repeated frequency operation conditions, the junction temperature rises, leading to an exponential increase in leakage current. Due to the lack of a discharge path, the common-base current gain increases, and the device is prone to false turn-on in the forward blocking state, causing system runaway.

[0005] While existing strong triggering techniques have improved the amplitude and leading edge steepness of the trigger current to some extent, they mostly focus on optimizing the pulse forming circuit and fail to ensure the blocking performance of devices under high-temperature conditions, and also lack systematic methods to improve the conduction consistency of series switches. Therefore, this invention proposes a high-current-change-rate thyristor strong triggering method that integrates voltage clamping and monitoring. Through the coordinated design of the strong triggering circuit and the voltage clamping branch, it achieves the dual goals of improving turn-on speed and enhancing blocking performance. Summary of the Invention

[0006] The purpose of this invention is to provide a high current change rate thyristor strong triggering circuit and method that integrates voltage clamping and monitoring, and has the functions of fast turn-on, high temperature blocking enhancement and online monitoring. It is suitable for microsecond-level pulse width and high current impact conditions of hundreds of kiloamperes.

[0007] To achieve the above objectives, the technical solution adopted by the present invention is as follows: A high current change rate thyristor strong triggering circuit integrating voltage clamping and monitoring includes: a pulse forming circuit, a voltage clamping branch, a series voltage equalization monitoring unit, a floating power supply circuit, and a thyristor. The pulse forming circuit is connected to the voltage clamping branch, which is connected to the cathode of one thyristor. The series voltage equalization monitoring unit is connected to the gate of the thyristor and the pulse forming circuit. The cathode of the thyristor is connected to a high voltage, and the anode of the thyristor is connected to the cathode of another thyristor. The floating power supply circuit is connected to the series voltage equalization monitoring unit and the pulse forming circuit. The pulse forming circuit is used to generate a strong trigger pulse between the gate and cathode of the thyristor, thereby compressing the equivalent turn-on delay of the thyristor. The voltage clamping branch is used to conduct after the strong trigger pulse fades, to establish a low-impedance discharge channel for the gate leakage current, to clamp the voltage between the gate and cathode, to suppress the common base current gain of the NPN transistor unit, and to prevent the thyristor from being mis-turned on in the forward blocking state. The series voltage equalization monitoring unit is used to collect the thyristor terminal voltage in real time.

[0008] Furthermore, the series voltage equalization monitoring unit includes a signal driving board and multiple electro-optical conversion circuits, photoelectric conversion circuits, and voltage-frequency conversion branches. The signal driving board is connected to multiple electro-optical conversion circuits. Each electro-optical conversion circuit is connected to a photoelectric conversion circuit. The photoelectric conversion circuit is connected to a pulse forming circuit. The pulse forming circuit is connected to a voltage clamping branch and a voltage-frequency conversion branch. The voltage clamping branch is connected to the cathode of a thyristor. The voltage-frequency conversion branch is connected to the gate of the thyristor. The voltage-frequency conversion branch is also connected to the photoelectric conversion circuit. The floating power supply circuit connects all the photoelectric conversion circuits and the pulse forming circuit.

[0009] Further, the pulse forming circuit includes a charging power supply, a first discharge circuit current-limiting resistor, a charging circuit current-limiting resistor, a second discharge circuit current-limiting resistor, a line stray resistor, a line stray inductor, a compensation capacitor, an energy storage capacitor, a first switch, and a pulse forming circuit switch. The voltage clamping branch includes a voltage clamping branch switch. The negative terminal of the charging power supply is grounded, and the positive terminal is connected to the charging circuit current-limiting resistor. The charging circuit current-limiting resistor is connected to the first switch. The first switch is connected to the energy storage capacitor and the first discharge circuit current-limiting resistor. The energy storage capacitor is grounded. The first discharge circuit current-limiting resistor is connected in parallel with the compensation capacitor. The first discharge circuit current-limiting resistor is connected to the drain of the pulse forming circuit switch. The source of the pulse forming circuit switch is connected to the drain of the voltage clamping branch switch and the gate of the thyristor. The cathode of the thyristor and the source of the voltage clamping branch switch are connected to the line stray resistor. The line stray resistor is connected to the line stray inductor. The line stray inductor is grounded.

[0010] Furthermore, the voltage clamping branch switch and the pulse forming circuit switch are power MOSFETs.

[0011] Furthermore, the series voltage equalization monitoring unit also includes a high-resistance voltage divider network and a differential amplifier circuit. The high-resistance voltage divider network and the differential amplifier circuit are arranged between the voltage-to-frequency conversion branch and the gate of the thyristor. The gate of the thyristor is connected to the high-resistance voltage divider circuit, the high-resistance voltage divider circuit is connected to the differential amplifier circuit, and the differential amplifier circuit is connected to the voltage-to-frequency conversion circuit. The high-resistance voltage divider network is composed of multiple high-voltage resistors connected in series, which is used to attenuate the voltage signal across the thyristor into a low-voltage differential signal. The differential amplifier circuit is used to perform signal conditioning on the low-voltage differential signal.

[0012] This invention also provides a high current rate of change thyristor strong triggering method integrating voltage clamping and monitoring, applied to the aforementioned high current rate of change thyristor strong triggering circuit integrating voltage clamping and monitoring, comprising: Step 1: The control system issues a trigger command, which is transmitted to the pulse forming circuit via the signal drive board, electro-optical conversion circuit, and photoelectric conversion circuit; the control pulse forming circuit switch is closed, and the voltage clamping branch switch is kept off; the energy storage capacitor is charged to the preset voltage by the charging power supply through the charging circuit current limiting resistor and the first switch; the energy storage capacitor discharges to the thyristor gate through the resonant network formed by the first discharge circuit current limiting resistor and the compensation capacitor, and the pulse forming circuit switch, forming a strong trigger pulse with high amplitude and high leading edge steepness, driving the thyristor to conduct quickly; Step 2: After the trigger pulse ends, the control pulse forming circuit switch is turned off and the voltage clamping branch switch is closed; the energy storage capacitor forms a discharge path through the first discharge circuit current limiting resistor, the voltage clamping branch switch and the second discharge circuit current limiting resistor, providing a low-impedance discharge path for the gate leakage current, while clamping the gate-cathode voltage, suppressing the common base current gain of the NPN transistor unit, and preventing the thyristor from being mis-turned on in the forward blocking state; Step 3: The series voltage equalization monitoring unit collects the thyristor terminal voltage through a high-resistance voltage divider network, attenuating the high-voltage signal into a low-voltage differential signal; the differential amplifier circuit conditions the low-voltage differential signal; the voltage-frequency conversion branch converts the conditioned analog voltage into a PWM signal whose duty cycle is positively correlated with the voltage amplitude; the electro-optical conversion circuit converts the PWM signal into an optical signal, which is transmitted to the front-end control system via optical fiber; Step 4: The control system measures the duty cycle of the PWM signal of each channel and deduces the voltage value of each thyristor terminal; when the signal of any thyristor position is abnormally lost or the duty cycle deviates from the preset threshold, the faulty thyristor position is identified and subsequent trigger pulses are blocked in an instant to achieve active safety protection.

[0013] Furthermore, in step 1, the trigger current amplitude is set to be more than 5 times the rated conduction current of the thyristor.

[0014] In summary, the present invention has at least one of the following beneficial technical effects: 1. A third-order RLC strong trigger pulse generation circuit is adopted. The compensation capacitor and the loop inductor form a high-frequency resonant network, which generates rich high-frequency components in the discharge current. The trigger current has the significant advantages of high amplitude and extremely steep leading edge. It can compress the conduction delay time of high current change rate thyristors to within a few microseconds, greatly improve the dynamic voltage equalization performance of the series valve group under strong current impact, and effectively suppress the risk of overvoltage of the first-turn-on device.

[0015] 2. A voltage clamping branch is set up to conduct in a timely manner after the trigger pulse ends, providing a low-impedance discharge path for the gate leakage current. At the same time, the gate-cathode voltage is clamped, suppressing the common-base current gain of the NPN transistor to approximately zero at high temperatures. This physically cuts off the path of leakage current regeneration amplification and triggering mis-conduction, significantly improving the system's operational reliability under high-temperature conditions with repetitive frequencies.

[0016] 3. The fiber optic isolated series voltage equalization monitoring scheme based on voltage-frequency conversion is adopted. The terminal voltage information is transmitted by pulse duty cycle, which has strong anti-interference ability and low transmission delay. It realizes real-time acquisition and online monitoring of the terminal voltage of each thyristor in the series valve group. When the voltage of any tube is abnormal, the fault location can be quickly identified and the trigger pulse can be blocked, providing active safety protection capability.

[0017] 4. By organically integrating strong triggering, voltage clamping, and voltage equalization monitoring, a functional closed loop of "triggering turn-on - clamping protection - monitoring feedback" is formed, providing a systematic solution for the reliable application of high current change rate thyristors under microsecond-level pulse width and hundreds of kiloampere-level strong current impact conditions. Attached Figure Description

[0018] Figure 1 This is a traditional trigger circuit topology diagram; Figure 2 This is a block diagram of the high current change rate thyristor strong triggering circuit that integrates voltage clamping and monitoring in this invention; Figure 3 The waveform diagram is for an ideal strong trigger. Figure 4 This is a topology diagram of a pulse forming circuit; Figure 5 This is a schematic diagram of the third-order equivalent circuit model of the present invention; Figure 6 This is a schematic diagram of the equivalent circuit of the cathode short-circuit branch of the present invention (where (a) is the equivalent simplified circuit and (b) is the MOSFET equivalent circuit). Figure 7 This is a schematic diagram of the floating power supply circuit of the present invention; Figure 8 This is a schematic diagram of the circuit topology of the series voltage equalization monitoring unit of the present invention. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0020] Circuit Example: like Figure 2As shown, this invention provides a high current change rate thyristor strong triggering circuit integrating voltage clamping and monitoring, comprising a pulse forming circuit, a voltage clamping branch, a series voltage equalization monitoring unit, a floating power supply circuit, and a thyristor. The pulse forming circuit is connected to the voltage clamping branch, which is connected to the cathode of one thyristor. The series voltage equalization monitoring unit is connected to the gate of the thyristor and the pulse forming circuit. The cathode of the thyristor is connected to a high voltage, and the anode of the thyristor is connected to the cathode of another thyristor. The floating power supply circuit is connected to the series voltage equalization monitoring unit and the pulse forming circuit. The pulse forming circuit generates a high-amplitude, high-lead-steep strong trigger pulse between the gate and cathode of the thyristor, compressing the equivalent turn-on delay of the thyristor to within a few microseconds. The voltage clamping branch turns on after the strong trigger pulse fades, establishing a low-impedance discharge path for the gate leakage current. At the same time, it clamps the voltage between the gate and cathode, suppressing the common-base current gain of the NPN transistor unit and preventing the thyristor from mis-turning on in the forward blocking state. The series voltage equalization monitoring unit collects the thyristor terminal voltage in real time, and after conditioning and conversion, generates a PWM signal with a duty cycle carrying voltage information. This signal is then transmitted to the front-end control system via fiber optic isolation. When any thyristor terminal voltage monitoring signal is abnormal, the control system quickly locates the faulty transistor and immediately blocks the trigger pulse.

[0021] Based on the triggering characteristics of high current rate thyristors, this invention designs a complete triggering system. The entire system's workflow can be summarized into four stages: signal transmission, pulse formation, clamping protection, and status monitoring. These four stages are closely linked in timing, jointly ensuring the reliable turn-on and safe operation of the high current rate thyristor under high current surge conditions. The following sections will provide a detailed description of each part: 1. Pulse forming circuit The pulse forming circuit adopts a third-order RLC discharge topology and utilizes the high-frequency oscillation characteristics of the compensation capacitor and the loop inductance to generate a strong trigger pulse with high amplitude and high leading edge steepness. Figure 4 A strong triggering circuit topology with cathode short-circuit function is presented. This circuit includes a charging power supply E, a first discharge circuit current-limiting resistor R1, a charging circuit current-limiting resistor R2, a second discharge circuit current-limiting resistor R3, and a line stray resistance R. stray Stray inductance L strayThe system consists of a compensation capacitor C1, an energy storage capacitor C2, a first switch S1, a pulse forming circuit switch Q2, and a voltage clamping branch switch Q1. The specific connections are as follows: the negative terminal of the charging power supply E is grounded, and its positive terminal is connected to the first end of the charging circuit current-limiting resistor R2; the second end of the charging circuit current-limiting resistor R2 is connected to the first end of the first switch S1; the second end of the first switch S1 is connected to the first end of the energy storage capacitor C2 and the first end of the first discharge circuit current-limiting resistor R1; the second end of the energy storage capacitor C2 is grounded; the second end of the first discharge circuit current-limiting resistor R1 is connected to the first end of the compensation capacitor C1 and the drain of the pulse forming circuit switch Q2; the second end of the compensation capacitor C1 is grounded; the source of the pulse forming circuit switch Q2 is connected to the drain of the voltage clamping branch switch Q1 and the gate of the thyristor; the cathode of the thyristor and the source of the voltage clamping branch switch Q1 are connected to the line stray resistance R. stray The first terminal; stray resistance R of the line stray The second terminal is connected to the stray inductance L. stray The first terminal; stray inductance L of the line stray The second terminal is grounded. The current-limiting resistor R1 of the first discharge circuit is connected in parallel with the compensation capacitor C1 to form a resonant discharge network.

[0022] The circuit has two clearly defined working loops: loop ① is the main pulse forming loop, consisting of energy storage capacitor C2, current-limiting resistor R1 of the first discharge loop, switch Q2 of the pulse forming loop, and stray inductance L of the line. stray Line stray resistance R stray The first circuit, along with the compensation capacitor C1, forms a closed loop; circuit ② is a leakage current discharge circuit, consisting of the energy storage capacitor C2, the first discharge circuit current-limiting resistor R1, the voltage clamping branch switch Q1, and the second discharge circuit current-limiting resistor R3, forming a closed loop. The second discharge circuit current-limiting resistor R3 is connected between the source of the voltage clamping branch switch Q1 and the cathode of the thyristor, and is actually the line stray resistance R. stray A current-limiting resistor that is part of or set separately.

[0023] The timing sequence of the pulse forming circuit is as follows: Phase 1 (Strong Trigger Phase): Upon receiving the trigger command, the pulse forming circuit switch Q2 closes, while the voltage clamping branch switch Q1 remains off. The energy stored in the energy storage capacitor C2 is released via circuit ①. The discharge current flows sequentially through the first discharge circuit current-limiting resistor R1, the pulse forming circuit switch Q2, the line stray parameters, and the compensation capacitor C1, finally injecting into the thyristor gate. In this phase, the compensation capacitor C1 not only participates in current formation as a component of the discharge circuit but also plays a role in compensating and shaping the pulse waveform. At the beginning of the discharge, the terminal voltage of the compensation capacitor C1 is zero, equivalent to a short circuit, allowing the initial discharge current to achieve the maximum rise rate. As the compensation capacitor C1 gradually charges, the discharge current waveform is appropriately broadened, ensuring sufficient pulse width.

[0024] Phase Two (Clamping Maintenance Phase): After the triggering process ends, the pulse forming circuit switch Q2 turns off, and the voltage clamping branch switch Q1 closes. Circuit ② is put into operation, and the energy storage capacitor C2 passes through the first discharge circuit current-limiting resistor R1, the voltage clamping branch switch Q1, and the line stray resistance R. stray A continuous discharge path is formed, but the voltage has been significantly lowered at this point, and the discharge current is very small. It is only necessary to maintain the conduction state of the clamping branch. This stage will continue until the end of the discharge cycle, ensuring that the gate-cathode of the thyristor remains in a low-resistance clamping state until the next trigger pulse arrives.

[0025] To meet the stringent requirements of thyristors for gate trigger pulses under high-current surge conditions, and to achieve rapid, stable, and reliable turn-on while effectively compressing the turn-on delay time, the pulse forming circuit proposed in this invention must satisfy the following design constraints: (a) Constraints on the amplitude of the trigger pulse current. To ensure that sufficient electrons are injected into the gate during the initial stage of conduction to quickly establish the internal positive feedback process, the amplitude of the trigger current should have sufficient driving capability. Preferably, its amplitude is set to more than five times the rated conduction current.

[0026] (ii) Constraints on the steepness of the trigger pulse leading edge. The rise rate of the pulse leading edge directly affects the conduction delay characteristics of the device. Increasing the rate of change of current (di / dt) helps to compress the conduction delay time, especially for series applications. A steeper pulse leading edge can significantly reduce the dynamic voltage imbalance caused by the inconsistent turn-on times of each device. Preferably, the trigger current rise time should be less than 1 μs, and the corresponding current rise rate should be not less than 1 A / μs.

[0027] (iii) Constraints on the gate trigger voltage range. To avoid the device failing to conduct effectively due to excessively low voltage, or irreversible damage to the gate structure due to excessively high voltage, the gate trigger voltage should be optimized according to the device characteristics. Preferably, the gate voltage should be controlled within the range of 5V to 10V while ensuring trigger power.

[0028] (iv) Constraints on the duration of high current holding. The duration of high-amplitude trigger current injection should be moderate. Excessive high current holding not only fails to further improve conduction performance but also increases the loss burden on the drive circuit. Preferably, the high current holding time is set to about 2μs. Once the gate charge injection is sufficient to maintain the internal positive feedback and fully expand the conduction region, the gate current can be reduced to a level that only needs to maintain the conduction state.

[0029] Ideal strong trigger waveform as follows Figure 3 As shown.

[0030] To facilitate theoretical analysis of the current characteristics of the third-order circuit, for the discharge circuit ①, taking the closing moment of the pulse forming circuit switch Q2 as the starting point (t=0), the original circuit is simplified equivalently to obtain the following: Figure 5 The diagram shows a third-order equivalent circuit model. In the figure, R is defined as the current-limiting resistor R1 of the first discharge circuit and the stray resistance R of the line. stray The equivalent resistance after series connection, where L is the sum of the equivalent series inductances of the circuit, satisfies L=L stray According to Kirchhoff's laws, the circuit equations are as follows: (1); (2); In the formula, Main circuit current, ; For the current flowing through the capacitor C 1 current, ; For the resistance R 1 current, and ,but ; Transform equations (1) and (2) to Domain, considering capacitance The initial voltage is With all other initial conditions set to 0, we can obtain: (3); make ; ; ; ; Solving equation (3) yields: (4); Let the denominator Let its three roots be Based on the discriminant value, the inverse Laplace transform is performed in the following three cases to obtain the trigger current. Time-domain expression: When the three roots are distinct real roots: (5); When there is a pair of double roots and a single root Time (i.e.) ): (6); When the three roots are triple roots ( ): (7); Based on the above three scenarios and combined with the actual circuit parameters, the precise expression for the trigger current with respect to time can be derived.

[0031] 2. Voltage clamping branch The voltage clamping branch is connected in parallel between the thyristor gate and cathode, consisting of voltage clamping branch switch Q1 and a low-resistance path (i.e., line stray resistance R). stray and stray inductance of the line L stray It is composed of series combinations. The voltage clamping branch switch Q1 uses a low-power, high-current-carrying-capacity power MOSFET, which can be equivalent to an on-state resistor R in the forward conduction state. ds Its resistance is typically in the milliohm range.

[0032] Transistors exhibit high current gain under high current conditions, which accelerates the internal feedback process and helps maintain conduction. However, under low current conditions, to enhance the blocking capability of the device, its current gain needs to be appropriately reduced. The voltage clamping branch is designed to address this need. When a trigger current is applied to the gate, the voltage clamping branch switch Q1 remains off, and the leakage current discharge circuit does not participate in operation; when the gate trigger current is removed, the voltage clamping branch switch Q1 closes, the discharge circuit engages, and the transistor's current gain is reduced. At this time, Figure 4 The circuit shown can be equivalent to Figure 6 The simplified form of (a) further equates switch Q1 to an on-state resistance. R ds Later obtained Figure 6 The equivalent circuit shown in (b)

[0033] like Figure 6 As shown in (b), when the cathode short-circuit branch is conducting, the junction voltage VJ3 of thyristor J3 is determined by the leakage current and the on-state resistance R. ds The product determines that, i.e. .in i leak This is the gate leakage current, in the milliampere range. Because this voltage is very small, lower than the forward voltage drop of junction J3, current cannot flow through junction J3 and instead flows out from the G terminal. At this time, the anode current... iA Includes the current flowing through junction J3 AND gate leakage current Two parts. Further analysis shows that when junction J3 is in reverse bias, the junction bias voltage is very small, and the leakage current component is much larger than the current flowing through junction J3, that is... >> This results in a small common-base current gain in the NPN transistor. This effectively enhances the blocking capability of GTO-like circuits. In the on-state, Q1 is off, and the cathode short-circuit branch does not operate. This does not affect the normal conduction of the device.

[0034] 3. Series equalization monitoring unit The series equalization monitoring unit is connected in parallel between the anode and cathode of each thyristor, such as... Figure 8 As shown, the system includes a signal driver board, multiple electro-optical conversion circuits, photoelectric conversion circuits, and a voltage-to-frequency conversion branch. The signal driver board connects to multiple electro-optical conversion circuits, each of which is connected to a corresponding photoelectric conversion circuit via an optical fiber. Each photoelectric conversion circuit is connected to a pulse forming circuit, which in turn connects to a voltage clamping branch and a voltage-to-frequency conversion branch. The voltage clamping branch is connected to the cathode of a thyristor, and the voltage-to-frequency conversion branch is connected to the gate of the thyristor. Furthermore, the voltage-to-frequency conversion branch is also fed back to the photoelectric conversion circuit. A floating power supply circuit connects all the photoelectric conversion circuits and the pulse forming circuit.

[0035] The core function of the series voltage equalization monitoring unit is to collect the voltage at each thyristor terminal in real time. It adopts a fiber optic isolation transmission scheme based on voltage-frequency conversion and is mainly composed of four cascaded functions: a high-impedance voltage divider network, a differential amplifier circuit, a voltage-frequency conversion circuit, and an electro-optic conversion circuit.

[0036] The first-stage high-impedance voltage divider network consists of multiple high-voltage resistors connected in series. This network attenuates the voltage signal across the thyristor, which can reach several kilovolts, to a low-voltage differential signal in the range of a few volts. The reason for using multiple series resistors instead of a single resistor is twofold: first, to improve voltage withstand capability and avoid a single resistor bearing excessively high voltage; second, to precisely control the attenuation ratio through multiple voltage divisions, and to achieve common-mode rejection by configuring different voltage division ratios at the positive and negative terminals. The first end of the high-impedance voltage divider network is connected to the anode of the thyristor (or a voltage-equalizing resistor connected in parallel with the thyristor), and the second end is connected to the cathode of the thyristor. In the specific connection, a high-impedance voltage divider network and a differential amplifier circuit are set between the voltage-to-frequency conversion branch and the gate of the thyristor. The gate of the thyristor is connected to the first end of the high-impedance voltage divider network, which is also connected to the anode of the thyristor. The second end of the high-impedance voltage divider network is connected to the input terminal of the differential amplifier circuit.

[0037] The second-stage differential amplifier circuit: The attenuated differential signal is fed into a differential amplifier composed of precision operational amplifiers for signal conditioning. The advantage of differential amplification is that it can effectively suppress common-mode noise on the high-voltage bus. In pulsed power systems, drastic di / dt changes can induce significant common-mode interference on the bus. The differential structure can largely cancel it out, ensuring the purity of the sampled signal.

[0038] The third-stage voltage-to-frequency conversion circuit: The amplified analog voltage signal is fed into the voltage-to-frequency conversion stage. This circuit linearly generates a pulse width modulation (PWM) signal with a corresponding duty cycle based on the input voltage amplitude—the higher the input voltage, the larger the duty cycle of the output PWM signal; the lower the input voltage, the smaller the duty cycle of the output PWM signal. Thus, the analog voltage information is converted into a digital pulse signal, facilitating long-distance transmission in environments with strong electromagnetic interference.

[0039] The fourth-stage electro-optical conversion circuit: After being driven, the PWM signal is sent to the electro-optical conversion module, converted into an optical signal, and transmitted to the front-end control system through optical fiber. Optical fiber, as the transmission medium, inherently possesses perfect electrical isolation characteristics; its isolation voltage level depends on the insulation strength of the fiber itself, and in engineering applications, it can reach tens of kilovolts or more.

[0040] After receiving the optical signals uploaded by each monitoring unit and converting them into electrical pulses, the control system can deduce the current terminal voltage value of each high current rate thyristor by measuring the duty cycle of the PWM signal of each channel. When the signal of a certain thyristor is abnormally lost or the duty cycle deviates from the preset threshold, the system can quickly identify the faulty thyristor and immediately block subsequent trigger pulses.

[0041] 4. Floating power supply circuit To achieve electrical isolation between the high and low voltage sides, the driver board power supply adopts a floating power supply scheme based on a toroidal magnetic transformer. For example... Figure 7 As shown, the power supply circuit includes a primary high-frequency adjustable power supply, a toroidal magnetic transformer, a rectifier bridge, a filter capacitor, and a three-terminal voltage regulator. The specific connections are as follows: the output of the primary high-frequency adjustable power supply is connected to the primary high-voltage conductor, which passes through the toroidal magnetic core as one turn of the primary winding; N turns of coil are uniformly wound on the toroidal magnetic core as the secondary winding, and the two ends of the secondary winding are connected to the AC input of the rectifier bridge; the DC output of the rectifier bridge is connected in parallel with a filter capacitor and then to the input of the three-terminal voltage regulator; the output of the three-terminal voltage regulator is connected to the energy storage capacitor C2 in the pulse forming circuit, providing the operating voltage for the energy storage capacitor C2. The insulation withstand voltage capability of the entire power supply circuit is determined by the withstand voltage rating of the high-voltage conductor passing through the magnetic core. For a toroidal transformer structure with one turn on the primary side and N turns on the secondary side, according to Faraday's law of electromagnetic induction, the expression for the induced voltage U in the magnetic core is: (8); In the formula, This refers to the number of coil turns. This is the cross-sectional area of ​​the coil; B 0 represents the magnetic field strength; ω represents the angular velocity of the magnetic field.

[0042] In addition, the present invention also provides a high current change rate thyristor strong triggering method that integrates voltage clamping and monitoring. This method is applied to the above-mentioned circuit and specifically includes the following steps.

[0043] Step 1: Strong Trigger Phase The control system issues a trigger command, which is transmitted to the pulse forming circuit via the signal driver board, electro-optical conversion circuit, and photoelectric conversion circuit. The control pulse forming circuit switch Q2 is closed, while the voltage clamping branch switch Q1 remains closed. The energy storage capacitor C2 is charged to a preset voltage by the charging power supply E through the charging circuit current-limiting resistor R2 and the first switch S1. The energy storage capacitor C2 discharges to the thyristor gate through the resonant network formed by the first discharge circuit current-limiting resistor R1 and the compensation capacitor C1, and the pulse forming circuit switch Q2, forming a strong trigger pulse with high amplitude and high leading-edge steepness, driving the thyristor to conduct rapidly. Specifically: The trigger command generated by the signal generator is converted into an optical signal via electro-optical conversion. This signal is then transmitted through an optical fiber across the high- and low-voltage isolation strip to the high-voltage side trigger board. The optical fiber conversion circuit then restores the signal to an electrical signal, which, after logic shaping and judgment, drives the pulse forming circuit. Optical fiber transmission ensures electrical isolation of several kilovolts or even higher voltage levels between the high- and low-voltage sides. Upon receiving a valid trigger command, the pulse forming circuit switch Q2 closes, while the voltage clamping branch switch Q1 remains off. At this time, the energy storage capacitor C2 has been charged to the preset voltage U0 by the charging power supply E through the charging circuit current-limiting resistor R2 and the first switch S1. The energy stored in the energy storage capacitor C2 is released through the main pulse forming circuit. The discharge current flows sequentially through the first discharge circuit current-limiting resistor R1, the pulse forming circuit switch Q2, the line stray resistance Rstray, the line stray inductance Lstray, and the compensation capacitor C1, finally injecting into the thyristor gate. During the initial discharge phase, the voltage across the compensation capacitor C1 is zero, equivalent to a short circuit, allowing the initial discharge current to achieve its maximum rise rate. As the compensation capacitor C1 gradually charges, the discharge current waveform is appropriately broadened, ensuring sufficient pulse width. Through parameter matching of the third-order RLC resonant network, the amplitude of the trigger current can reach more than 5 times the rated conduction current of the thyristor, the current rise time is less than 1μs, the gate trigger voltage is controlled between 5V and 10V, and the high current holding time is approximately 2μs. This compresses the equivalent conduction delay of the thyristor to within a few microseconds, effectively improving the dynamic voltage equalization performance of the series valve group.

[0044] Step 2: Clamping Maintenance Phase After the trigger pulse ends, the control pulse forming circuit switch Q2 turns off, and the voltage clamping branch switch Q1 closes; the energy storage capacitor C2 passes through the first discharge circuit current limiting resistor R1, the voltage clamping branch switch Q1, and the line stray resistance R stray This forms a discharge path, providing a low-impedance discharge path for the gate leakage current, while simultaneously clamping the gate-cathode voltage to suppress the common-base current gain of the NPN transistor unit, preventing the thyristor from falsely turning on under forward blocking conditions. Specifically: When the gate trigger current is removed, the pulse forming circuit switch Q2 turns off, the voltage clamping branch switch Q1 closes, and the leakage current discharge circuit is put into operation. At this time, the voltage clamping branch switch Q1 is equivalent to a milliohm-level on-state resistance. The junction voltage of the thyristor J3 junction Gate leakage current With on-state resistance The product determines (formula: Because the junction voltage is very small, lower than the forward voltage drop of junction J3, current cannot flow through junction J3 and instead flows out through the gate. This suppresses the common-base current gain αN of the NPN transistor to approximately zero under low current conditions, i.e., αN≈0, effectively improving the stability of the thyristor in the high-temperature forward blocking state. This stage continues until the discharge cycle of the energy storage capacitor C2 ends, ensuring that the gate-cathode remains in a low-resistance clamped state before the next trigger pulse arrives. In the on-state, the voltage clamping branch switch Q1 is turned off, the voltage clamping branch does not work, αN returns to its normal value, and the normal conduction of the device is not affected.

[0045] Step 3: Pressure Equalization Monitoring Stage The series voltage equalization monitoring unit acquires the thyristor terminal voltage through a high-resistance voltage divider network, attenuating the high-voltage signal into a low-voltage differential signal; the differential amplifier circuit conditions the low-voltage differential signal; the voltage-to-frequency conversion branch converts the conditioned analog voltage into a PWM signal whose duty cycle is positively correlated with the voltage amplitude; the electro-optical conversion circuit converts the PWM signal into an optical signal, which is then transmitted to the front-end control system via optical fiber. Specifically: A series voltage equalization monitoring unit is connected in parallel between the anode and cathode of each thyristor to continuously collect the terminal voltage across each thyristor. A high-resistance voltage divider network attenuates the voltage signal, which can reach several kilovolts, across the thyristors to a low-voltage differential signal in the range of several volts. By connecting multiple stages in series, the withstand voltage is improved and common-mode rejection is achieved. A differential amplifier circuit conditions the low-voltage differential signal, effectively suppressing common-mode noise on the high-voltage bus and ensuring the purity of the sampled signal. A voltage-to-frequency conversion circuit linearly converts the conditioned analog voltage into a PWM signal with a corresponding duty cycle. The higher the input voltage, the larger the duty cycle of the output PWM signal, and the lower the input voltage, the smaller the duty cycle of the output PWM signal, thus converting the analog voltage information into a digital pulse signal. An electro-optical conversion circuit converts the PWM signal into an optical signal and transmits it to the front-end control system via optical fiber, achieving electrical isolation between the high-voltage side and the low-voltage side.

[0046] Step 4: Fault Protection Phase The control system measures the duty cycle of the PWM signal in each channel and deduces the voltage value at each thyristor terminal. When the signal at any thyristor position is abnormally lost or the duty cycle deviates from the preset threshold, the faulty thyristor position is identified and subsequent trigger pulses are immediately blocked to achieve active safety protection. Specifically: After receiving the optical signals uploaded by each monitoring unit and converting them into electrical pulses, the front-end control system measures the duty cycle of the PWM signals in each channel to deduce the current terminal voltage value of each high-current-rate-change thyristor. When the signal of a certain thyristor position is abnormally lost or the duty cycle deviates from the preset threshold, the system can quickly identify the faulty thyristor position and immediately block subsequent trigger pulses, realizing the system's active safety protection and ensuring the reliable operation of the thyristor series valve group under microsecond-level pulse width and hundreds of kiloampere-level high-current impact conditions.

[0047] Furthermore, this invention also provides key component selection principles, specifically: Regarding component selection, this invention follows the following principles: Photoelectric conversion module: Utilizing an electro-optical / photoelectric conversion combination suitable for high-speed digital signal transmission, this module, in conjunction with a logic shaping chip, completes the isolated transmission and signal conditioning of the trigger signal. The fiber optic transmission link must meet the pulse width requirements of the trigger pulse to ensure that the high-speed signal is not distorted during transmission.

[0048] Power switching devices: Both the pulse forming loop switch Q2 and the voltage clamping branch switch Q1 are power MOSFETs with extremely low on-state resistance, fast switching response, and high current carrying capacity. The pulse forming loop switch Q2 needs to withstand the large current surge during triggering, while the on-resistance of the voltage clamping branch switch Q1 directly determines R. ds Whether it is low enough to effectively suppress leakage current gain. Both need to have nanosecond-level switching speeds to meet the timing requirements of high-frequency resonant discharge.

[0049] Magnetic components: The levitation power supply transformer uses a magnetic core material with high permeability and low high-frequency loss. While meeting the induced voltage requirements of formula (8), the volume of the magnetic core is controlled within a reasonable range.

[0050] Monitoring circuit components: The operational amplifier is a precision operational amplifier with high slew rate, wide bandwidth, and low offset voltage characteristics to ensure the dynamic accuracy of high-frequency signal conditioning. The voltage-to-frequency conversion circuit adopts a high-linearity conversion scheme to ensure a strict linear relationship between the PWM duty cycle and the input voltage, and the nonlinearity error should be controlled within an acceptable range. The electro-optical conversion module uses components that match the aforementioned photoelectric conversion to ensure the integrity and reliability of the optical signal in the transmission link.

[0051] Embodiments of the present invention may be provided as methods, circuits, or computer program products. Therefore, the present invention may take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0052] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (circuits), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0053] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0054] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0055] Contents not described in detail in this specification are prior art known to those skilled in the art. It is hereby indicated that the above description is intended to help those skilled in the art understand this invention, but does not limit the scope of protection of this invention. Any equivalent substitutions, modifications, improvements, or simplifications of the above descriptions that do not depart from the essential content of this invention fall within the scope of protection of this invention.

Claims

1. A high current change rate thyristor strong triggering circuit integrating voltage clamping and monitoring, characterized in that, include: The system comprises a pulse forming circuit, a voltage clamping branch, a series voltage equalization monitoring unit, a floating power supply circuit, and a thyristor. The pulse forming circuit is connected to the voltage clamping branch, which is connected to the cathode of one thyristor. The series voltage equalization monitoring unit is connected to the gate of the thyristor and the pulse forming circuit. The cathode of the thyristor is connected to a high voltage, and the anode of the thyristor is connected to the cathode of another thyristor. The floating power supply circuit is connected to the series voltage equalization monitoring unit and the pulse forming circuit. The pulse forming circuit is used to generate a strong trigger pulse between the gate and cathode of the thyristor, thereby compressing the equivalent turn-on delay of the thyristor. The voltage clamping branch is used to conduct after the strong trigger pulse fades, to establish a low-impedance discharge channel for the gate leakage current, to clamp the voltage between the gate and cathode, to suppress the common base current gain of the NPN transistor unit, and to prevent the thyristor from being mis-turned on in the forward blocking state. The series voltage equalization monitoring unit is used to collect the thyristor terminal voltage in real time.

2. The high current change rate thyristor strong triggering circuit integrating voltage clamping and monitoring according to claim 1, characterized in that, The series voltage equalization monitoring unit includes a signal driver board and multiple electro-optic conversion circuits, photoelectric conversion circuits, and voltage-frequency conversion branches. The signal driver board is connected to multiple electro-optic conversion circuits. Each electro-optic conversion circuit is connected to a photoelectric conversion circuit. The photoelectric conversion circuit is connected to a pulse forming circuit. The pulse forming circuit is connected to a voltage clamping branch and a voltage-frequency conversion branch. The voltage clamping branch is connected to the cathode of a thyristor. The voltage-frequency conversion branch is connected to the gate of the thyristor. The voltage-frequency conversion branch is also connected to the photoelectric conversion circuit. The floating power supply circuit connects all the photoelectric conversion circuits and the pulse forming circuit.

3. The high current change rate thyristor strong triggering circuit integrating voltage clamping and monitoring according to claim 2, characterized in that, The pulse forming circuit includes a charging power supply, a first discharge circuit current-limiting resistor, a charging circuit current-limiting resistor, a second discharge circuit current-limiting resistor, a line stray resistor, a line stray inductor, a compensation capacitor, an energy storage capacitor, a first switch, and a pulse forming circuit switch. The voltage clamping branch includes a voltage clamping branch switch. The negative terminal of the charging power supply is grounded, and the positive terminal is connected to the charging circuit current-limiting resistor. The charging circuit current-limiting resistor is connected to the first switch. The first switch is connected to the energy storage capacitor and the first discharge circuit current-limiting resistor. The energy storage capacitor is grounded. The first discharge circuit current-limiting resistor is connected in parallel with the compensation capacitor. The first discharge circuit current-limiting resistor is connected to the drain of the pulse forming circuit switch. The source of the pulse forming circuit switch is connected to the drain of the voltage clamping branch switch and the gate of the thyristor. The cathode of the thyristor and the source of the voltage clamping branch switch are connected to the line stray resistor. The line stray resistor is connected to the line stray inductor. The line stray inductor is grounded.

4. The high current change rate thyristor strong triggering circuit integrating voltage clamping and monitoring according to claim 3, characterized in that, The voltage clamping branch switch and pulse forming circuit switch are power MOSFETs.

5. The high current change rate thyristor strong triggering circuit integrating voltage clamping and monitoring according to claim 1, characterized in that, The series voltage equalization monitoring unit further includes a high-resistance voltage divider network and a differential amplifier circuit. The high-resistance voltage divider network and the differential amplifier circuit are arranged between the voltage-to-frequency conversion branch and the gate of the thyristor. The gate of the thyristor is connected to the high-resistance voltage divider circuit, the high-resistance voltage divider circuit is connected to the differential amplifier circuit, and the differential amplifier circuit is connected to the voltage-to-frequency conversion circuit. The high-resistance voltage divider network is composed of multiple high-voltage resistors connected in series, which is used to attenuate the voltage signal across the thyristor into a low-voltage differential signal. The differential amplifier circuit is used to perform signal conditioning on the low-voltage differential signal.

6. A high-current-rate-change-of-change-of-change-of-change-of-change-of-thyristor strong triggering method integrating voltage clamping and monitoring, applied to the high-current-rate-change-of ...thyristor strong triggering circuit integrating voltage clamping and monitoring as described in any one of claims 1-5, characterized in that, include: Step 1: The control system issues a trigger command, which is transmitted to the pulse forming circuit via the signal drive board, electro-optical conversion circuit, and photoelectric conversion circuit; the control pulse forming circuit switch is closed, and the voltage clamping branch switch is kept off; the energy storage capacitor is charged to the preset voltage by the charging power supply through the charging circuit current limiting resistor and the first switch; the energy storage capacitor discharges to the thyristor gate through the resonant network formed by the first discharge circuit current limiting resistor and the compensation capacitor, and the pulse forming circuit switch, forming a strong trigger pulse with high amplitude and high leading edge steepness, driving the thyristor to conduct quickly; Step 2: After the trigger pulse ends, the control pulse forming circuit switch is turned off and the voltage clamping branch switch is closed; the energy storage capacitor forms a discharge path through the first discharge circuit current limiting resistor, the voltage clamping branch switch and the second discharge circuit current limiting resistor, providing a low-impedance discharge path for the gate leakage current, while clamping the gate-cathode voltage, suppressing the common base current gain of the NPN transistor unit, and preventing the thyristor from being mis-turned on in the forward blocking state; Step 3: The series voltage equalization monitoring unit collects the thyristor terminal voltage through a high-resistance voltage divider network, attenuating the high-voltage signal into a low-voltage differential signal; the differential amplifier circuit conditions the low-voltage differential signal; the voltage-frequency conversion branch converts the conditioned analog voltage into a PWM signal whose duty cycle is positively correlated with the voltage amplitude; the electro-optical conversion circuit converts the PWM signal into an optical signal, which is transmitted to the front-end control system via optical fiber; Step 4: The control system measures the duty cycle of the PWM signal in each channel and deduces the voltage value at each thyristor terminal; When the signal of any tube position is abnormally lost or the duty cycle deviates from the preset threshold, the faulty tube position is identified and subsequent trigger pulses are blocked in an instant, so as to achieve active safety protection.

7. The high current change rate thyristor strong triggering method integrating voltage clamping and monitoring according to claim 6, characterized in that, In step 1, the trigger current amplitude is set to be more than 5 times the rated conduction current of the thyristor.

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