A fusion transmission system and method based on digital video interface physical layer

Abstract

The application discloses a fusion transmission system and method based on a digital video interface physical layer, and relates to the technical field of high-speed image data transmission. In view of the problem that the existing long-distance image transmission scheme is difficult to consider single-line fusion function, supply chain openness and cost controllability, the application multiplexes standard digital video interface physical layer resources: the system comprises a remote component and a near-end host component connected through a standard cable, the remote end encodes the RAW data output by an image sensor through a self-defined packing protocol, frames and codes the RAW data, and transmits the RAW data through a data channel through a general pure physical layer sending chip; the near end decodes and recovers the original image data through a receiving chip and a programmable logic device, and simultaneously realizes tile-level reverse power supply and host active reverse control through the cable. The application can eliminate the blanking period overhead of the standard video protocol, has the advantages of stable transmission, supply chain openness and cost controllability, and is suitable for long-distance image acquisition scenes such as medical endoscopes and industrial vision.

Description

Technical Field

[0001] This invention relates to the field of video signal transmission technology, and in particular to a video, power supply and reverse control integrated transmission system and method based on the physical layer of a digital video interface. Background Technology

[0002] In applications such as medical imaging, automotive driver assistance, industrial visual inspection, and drone reconnaissance, remote image acquisition devices typically require cable connections of several meters to tens of meters to achieve three main functions: high-bandwidth video transmission, remote power supply, and real-time control. Image sensors generally support 1080p@60 to 4K@60 resolutions with bit depths of RAW10 / RAW12 / RAW14, requiring the link to have a throughput of several Gbps and latency within milliseconds. Due to size limitations, remote devices cannot have built-in batteries and must be powered by the host through cables, requiring several watts of power. The host also needs to adjust sensor exposure, gain, and other parameters in real time according to the scene, controlling latency to be less than 1ms.

[0003] Currently, the mainstream long-distance image transmission solutions mainly fall into the following four categories: I. MIPI to LVDS Multi-core Cable Solution. A bridging chip converts MIPI CSI-2 to sub-LVDS serial signals for transmission via multi-core cables. At high data rates, the effective transmission distance is only 1-2 meters, increasing to approximately 3-5 meters with the addition of an equalizer; significant crosstalk occurs when multiple differential pairs are transmitted in parallel, making it susceptible to electromagnetic interference; the cables have a large number of cores and are non-standardized.

[0004] II. Dedicated SerDes Solutions (GMSL / FPD-Link, etc.). These solutions utilize dedicated serializer / deserializer chips from ADI or TI, enabling video, control, and power supply transmission via a single coaxial cable, technically achieving three-in-one integration. However, the chip supplier market is dominated by a duopoly of ADI and TI (ADI holds over 90% market share in the automotive SerDes market, and TI holds approximately 70% in the display field), and supply fluctuations could lead to supply disruptions. Furthermore, the protocol stack is proprietary, development relies on original manufacturer support, and the overall cost is high.

[0005] III. Fiber Optic Transmission Solution. At the remote end, an optical transceiver module converts the electrical signal into an optical signal for transmission via fiber optic cable. However, optical modules are costly, increasing power consumption and size at the remote end; the bending radius of optical fibers is limited, making them unsuitable for scenarios involving repeated bending; and a separate power supply is required, preventing full-function integration on a single cable.

[0006] IV. Standard Digital Video Interface Solutions (HDMI / DisplayPort, etc.). These solutions offer standardized cables, excellent physical layer performance, an open supply chain, and low cost. However, they suffer from fundamental limitations at the standard protocol layer: they only support RGB / YUV and cannot transmit RAW data; the forced blanking period overhead is approximately 16.2% (based on 1080p60 CEA-861 timing); the power supply direction is from source to receiver, and the current is only in the milliampere range (minimum 55mA at the HDMI +5V pin source and maximum 10mA at the receiver), far from meeting watt-level power supply requirements; and the control direction is fixed, preventing the host from actively controlling remote sensors.

[0007] In summary, a fully functional dedicated SerDes solution has a closed supply chain and high costs, while a low-cost solution with an open supply chain has missing functions or transmission shortcomings. There is currently no solution that can simultaneously meet all three requirements. Summary of the Invention

[0008] The purpose of this invention is to provide a converged transmission system and method based on the physical layer of a digital video interface. It aims to solve the problems of closed supply chains and high costs in existing long-distance image transmission solutions, which are characterized by complete functions and closed supply chains, and low costs and missing functions or transmission shortcomings, by reusing the physical layer channels and pin resources of the standard digital video interface and using a general-purpose pure physical layer chip with programmable logic devices to customize the transmission protocol. The invention achieves the convergence of high-bandwidth RAW video transmission, watt-level reverse power supply and millisecond-level reverse control on a single standard cable.

[0009] To achieve the above objectives, the present invention provides a converged transmission system based on the physical layer of a digital video interface, comprising a remote component and a near-end host component connected by a standard digital video interface cable. The remote component includes an image sensor, a first programmable logic device, and a pure physical layer transmission chip; the image sensor outputs RAW format raw image data; the first programmable logic device receives the RAW format raw image data, organizes the image data into a custom data frame containing a frame start identifier segment, a valid pixel data segment, and a frame end identifier segment according to a custom packetization protocol, and outputs it to the pure physical layer transmission chip after encoding; the pure physical layer transmission chip converts the parallel encoded data into a high-speed differential serial signal, which is transmitted through the data channel of the standard digital video interface cable; The near-end host component includes a pure physical layer receiver chip and a second programmable logic device; the pure physical layer receiver chip receives high-speed differential serial signals from the standard digital video interface cable, and outputs parallel data to the second programmable logic device after serial-to-parallel conversion, signal equalization and clock recovery; the second programmable logic device decodes the parallel data, parses and verifies the custom packetization protocol, and recovers the original RAW format image data. The near-end host component provides operating power to the far-end component through the power pin of the standard digital video interface cable, with the power supply direction being opposite to the standard power supply direction of the digital video interface. The near-end host component acts as the master device of the control bus and sends control commands to the far-end component through the auxiliary channel of the standard digital video interface cable; the first programmable logic device responds to the control commands and completes the parameter configuration of the far-end component.

[0010] Preferably, both the pure physical layer transmitting chip and the pure physical layer receiving chip are general-purpose pure physical layer chips used to implement physical layer signal processing such as parallel-to-serial conversion, serial-to-parallel conversion, signal equalization, pre-emphasis, and clock recovery.

[0011] Preferably, the frame start identifier segment of the custom packetization protocol includes a frame synchronization code, a frame count field, and an image configuration parameter field; the effective pixel data segment includes multiple rows of pixel data, with a row synchronization identifier set before each row of pixel data and a row check field set at the end of each row of pixel data; the frame end identifier segment includes a frame end synchronization code and a frame status field.

[0012] Preferably, the near-end host component provides operating power to the far-end component through the power pin of the standard digital video interface cable, with the power supply direction opposite to the standard power supply direction of the digital video interface.

[0013] Preferably, the output interface of the image sensor includes at least one of MIPI CSI-2, Sub-LVDS, and SLVS-EC.

[0014] A converged transmission method based on the physical layer of a digital video interface, applied to the system described in any one of claims 1-5, comprising: The remote component acquires raw image data in RAW format. The first programmable logic device organizes the image data into custom data frames containing a frame start identifier segment, a valid pixel data segment, and a frame end identifier segment according to a custom packetization protocol. After encoding, the data is converted into a high-speed differential serial signal by a pure physical layer transmission chip and transmitted to the near-end host component through the data channel of a standard digital video interface cable. The near-end host component completes serial-to-parallel conversion, signal equalization and clock recovery through the pure physical layer receiving chip, and then decodes, parses and verifies the protocol through the second programmable logic device to recover the original RAW format image data; The near-end host component provides operating power to the far-end component through the power pins of the standard digital video interface cable, with the power supply direction opposite to the standard power supply direction of the digital video interface; The near-end host component acts as the master device of the control bus, and sends control commands to the far-end component through the auxiliary channel of the standard digital video interface cable. The first programmable logic device of the far-end component responds to the control commands and completes the configuration of the far-end parameters.

[0015] Preferably, the first programmable logic device of the remote component responds to the control command through an internally integrated I2C slave device bridging module; the I2C slave device bridging module is configured with at least two I2C access addresses, the first address corresponding to the local register access of the first programmable logic device, and the second address corresponding to the transparent forwarding of the image sensor control bus.

[0016] Preferably, the first programmable logic device adaptively switches the encoding scheme and data channel mapping strategy according to the adopted digital video interface physical layer standard; the digital video interface physical layer standard includes TMDS physical layer, FRL physical layer and DisplayPort physical layer.

[0017] Preferably, the second programmable logic device performs frame-level and line-level dual CRC checks on the custom data frame to locate erroneous data and report the transmission status.

[0018] Preferably, the TMDS physical layer uses 8b / 10b encoding, the FRL physical layer uses 16b / 18b encoding, the DisplayPort 1.x physical layer uses ANSI 8b / 10b encoding, and the DisplayPort 2.x physical layer uses 128b / 132b encoding.

[0019] According to specific embodiments provided by the present invention, the present invention discloses the following technical effects: (1) Improved transmission efficiency This invention completely eliminates the horizontal and vertical blanking period overhead mandated by standard digital video interfaces through a custom packetization protocol, directly mapping the RAW pixel data output by the image sensor to the physical layer data channel for transmission. Bandwidth utilization is increased from approximately 83.8% of the standard digital interface to over 95%.

[0020] (2) Improved power supply capacity This invention utilizes the existing power pins in standard digital video interface cables to reverse the power supply direction, turning the host end into the remote device. At the same time, it increases the current supply capability from the standard milliampere level to the ampere level, with a power supply of 5W~10W, which can meet the watt-level operating power requirements of remote image acquisition equipment without the need for additional independent power cables or built-in batteries.

[0021] (3) Improved real-time control This invention utilizes an auxiliary channel in a standard digital video interface cable to reverse the master-slave role of the control bus, allowing the host device to actively initiate communication. Control commands are directly transmitted through the I2C Slave bridge inside the FPGA, with an end-to-end control latency of less than 1ms. This meets the frame-level real-time adjustment requirements for parameters such as exposure and gain under conditions such as sudden changes in scene lighting.

[0022] (4) Supply chain openness and cost controllability This invention abandons dedicated serializer / deserializer chips and instead uses commercially available general-purpose pure physical layer chips. There are many suppliers (TI, NXP, ST, Realtek, etc.), so there is no risk of dependence on a single supplier. The FPGA logic is completely independently developed and does not rely on third-party proprietary protocol stacks, giving downstream manufacturers complete technical autonomy and customization flexibility.

[0023] (5) Single-line integration and remote miniaturization This invention achieves high-bandwidth RAW video transmission, remote device power supply, and active real-time control of the host simultaneously using a single standard digital video interface cable. Compared to LVDS solutions which require multi-core cables and independent control lines, and fiber optic solutions which require independent power lines, this significantly reduces the complexity of the cabling system. The remote component only requires an image sensor, an FPGA, and a general-purpose PHY chip to complete all functions, which is beneficial for the miniaturization and low-power design of remote devices.

[0024] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This is a block diagram of the overall architecture of the converged transmission system according to Embodiment 1 of the present invention; Figure 2 This is a schematic diagram of the frame structure of the custom packetization protocol in Embodiment 1 of the present invention; Figure 3 This is a circuit block diagram illustrating the reverse power supply and reverse control in Embodiment 1 of the present invention; Figure 4 This is a schematic diagram comparing three compatible physical layer channel mappings in Embodiment 2 of the present invention. Detailed Implementation

[0027] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0028] Example 1 like Figure 1 As shown, this embodiment provides a converged transmission system based on the physical layer of a digital video interface, including a remote component and a near-end host component, which are connected by a standard digital video interface cable (such as an HDMI-compatible cable or a DP-compatible cable with a length of 3 to 15 meters).

[0029] I. Remote Components The remote components include an image sensor, a first programmable logic device (FPGA), and a pure physical layer transmitter chip.

[0030] The image sensor uses a CMOS image sensor and outputs raw image data in RAW10 / RAW12 / RAW14 format. It supports high-speed serial interfaces such as MIPI CSI-2, Sub-LVDS, or SLVS-EC, with resolutions ranging from 1080p@60 to 4K@60. Typical applications include, but are not limited to, medical endoscopes, industrial cameras, and automotive cameras.

[0031] The first programmable logic device (remote FPGA) performs the following core functions: High-speed serial receiver module: Performs deserialization, channel alignment, and verification of high-speed serial data (MIPI CSI-2 / Sub-LVDS / SLVS-EC) from the image sensor, and recovers parallel pixel data and synchronization signals. For the SLVS-EC interface, the FPGA needs to implement the corresponding deserialization and clock recovery logic to restore the serial data to parallel RAW pixel data.

[0032] Row buffer module: The double buffering mechanism is implemented using the FPGA's internal BRAM to cache complete data rows to adapt to the timing requirements of the custom packing protocol.

[0033] Custom Packaging Module: Packs RAW pixel data according to a custom packaging protocol, constructs frame headers, data lines, and frame tails, completely eliminating the overhead of standard video blanking period.

[0034] Encoding Module: Implements an encoding algorithm matching the selected physical layer using pure digital logic within the FPGA. For TMDS mode, standard 8b / 10b encoding is used; for FRL mode, 16b / 18b encoding is used; and for the DP interface, ANSI 8b / 10b or 128b / 132b encoding is used. The encoded parallel data is output to a pure PHY transmitter chip. All the above encoding algorithms are implemented internally within the FPGA using combinational logic or a very short pipeline, without relying on external encoding chips.

[0035] Parallel data transmission interface: Outputs multi-channel parallel data (e.g., 3 channels × 10 bits in TMDS mode, 4 channels × 18 bits in FRL mode, and 4 channels × 10 bits in DP mode) and the corresponding reference clock to the pure PHY transmission chip.

[0036] I2C Slave Bridge: Implements I2C slave logic within the FPGA, responding to I2C read / write requests initiated by the host through an auxiliary channel.

[0037] Power management interface: Receives DC power input from the cable power pin and controls the external power management IC to complete the power-on sequence of each module.

[0038] The pure PHY chip uses a commercially available general-purpose pure PHY chip, which only performs physical layer signal processing, including: parallel-to-serial conversion (serializing parallel data into high-speed differential signals), signal pre-emphasis and driving (compensating for high-frequency attenuation in cables), and differential signal output (driving multiple pairs of data channels and an optional clock channel). The pure PHY chip does not include any protocol layer processing (such as EDID management, HDCP, DPCD link training, audio packaging, etc.), and has numerous suppliers (TI, NXP, ST, Realtek, etc.), making the supply chain open.

[0039] II. Near-end host components The near-end host components include a pure physical layer receiver chip, a second programmable logic device (FPGA), and an image signal processor.

[0040] The pure physical layer receiver chip uses a commercially available general-purpose pure physical layer chip paired with the transmitter to perform: signal equalization (compensating for high-frequency attenuation in 3-15 meter cables), clock recovery (restoring the reference clock from the clock channel or extracting the embedded clock from the data stream), and serial-to-parallel conversion (restoring serial differential signals to parallel data).

[0041] The second programmable logic device (main FPGA) undertakes the following core functions: Decoding and receiving module: Completes the decoding corresponding to the encoding of the sending end, including character / symbol alignment, channel alignment and runtime difference verification.

[0042] Protocol parsing module: Identifies frame header synchronization code, extracts valid pixel data, and parses each line according to the frame structure.

[0043] CRC check module: Performs cyclic redundancy check on each frame and each data line. When an error occurs, it marks the frame / line and reports it to the host.

[0044] Data output module: Restores the valid pixel data that has passed verification to parallel RAW format and outputs it to the ISP via a standard interface (such as MIPI CSI-2 or parallel bus).

[0045] I2C Master Controller: As the master device on the I2C bus, it actively initiates read and write operations to remote devices, supporting speeds of 100kbps / 400kbps / 1Mbps, and sends commands through auxiliary channels (I2C-over-AUX mode of DDC or AUX channel).

[0046] Reverse power supply control module: Enables the host power conversion circuit and monitors the output voltage / current, realizing programmable current limiting and overcurrent / overvoltage protection.

[0047] The image signal processor (ISP) receives RAW data output from the FPGA, performs de-mosaicing, black level correction, white balance, color correction, noise reduction, sharpening and other processing, and then outputs a standard video stream (RGB / YUV) to the display terminal or storage unit.

[0048] III. Reverse Power Supply Scheme like Figure 3 As shown, the near-end host component uses the power pins in the standard digital video interface cable to reverse the power supply direction from the standard "transmitter → receiver" to "host (receiver) → remote (transmitter)," increasing the power supply capacity to 5~10W to meet the watt-level power supply requirements of remote devices.

[0049] The power supply pin carries a predetermined DC voltage, the specific value of which depends on the type of digital video interface selected and its electrical specifications. For HDMI-compatible interfaces, the standard voltage is +5V using Pin 18 (+5V Power pin) of the HDMI cable; for DisplayPort-compatible interfaces, the standard voltage is +3.3V using the DP_PWR pin of the DP cable; for USB-C DP AltMode, when DisplayPort signals are transmitted through the USB-C interface, the VBUS pin voltage can be any of 5V, 9V, 15V, or 20V, and the reverse power supply method of this invention also applies.

[0050] This invention does not change the standard voltage definition of the power supply pins, but achieves a leap in power level by increasing the current supply capability (from the milliampere level to the ampere level), with a supply current of 1A~2A and a supply power of 5~10W.

[0051] The host-side power supply circuit includes: a DC-DC converter (converting system power to a predetermined DC voltage), programmable current limiting (controlled by an FPGA, supporting multiple current limiting settings), protection functions (soft start, overcurrent protection, overvoltage protection, short circuit protection), and enable control (controlled by the FPGA based on the handshake state to control the power output). The remote-end power receiving circuit includes: input protection (TVS transient suppression diode, reverse connection protection), power conversion (generating the required voltages for each module via an LDO or DC-DC converter: 3.3V, 1.8V, 1.2V), and power-on sequence control (controlled by a power management IC or FPGA to manage the power-on sequence of each voltage rail).

[0052] IV. Reverse Control Scheme In this embodiment, the near-end host component uses the auxiliary channel in the standard digital video interface cable to reverse the master-slave role of the control bus from the standard "sender reads receiver EDID" to "host acts as I2C Master and remote acts as I2C Slave", thereby realizing the host's active real-time control of the remote sensor.

[0053] The auxiliary channels are HDMI's DDC channel (Pin15 SCL, Pin16 SDA) or DisplayPort's AUX channel (supporting I2C-over-AUX protocol).

[0054] The remote FPGA internally implements I2C slave logic to respond to I2C read / write requests initiated by the host through an auxiliary channel. The I2C address design is as follows: Address 0x5A is used to access the FPGA local registers (version reading, sensor reset, LED control, temperature / voltage monitoring, error status query); Address 0x6C is used for transparent forwarding to the image sensor I2C bus (configuring all parameters such as exposure, gain, and white balance); Address 0x5D is used for transparent forwarding to the pure PHY transmitter chip I2C bus (configuring the PHY chip's operating mode, pre-emphasis, and other parameters).

[0055] I2C transactions are directly bridged through the FPGA's internal logic without going through any protocol stack processing, resulting in an end-to-end control latency of less than 1ms, which meets the requirements for frame-level real-time parameter adjustment.

[0056] V. Custom Packaging Protocol like Figure 2As shown, the custom packetization protocol completely abandons the horizontal and vertical blanking periods and standard video format constraints mandated by the standard digital video interface, and reorganizes the raw pixel data output by the image sensor into a custom frame structure that facilitates synchronous capture, error detection and recovery at the receiving end.

[0057] The frame structure includes the following components: (1) Frame header line, located at the beginning of the frame, and its field definitions are shown in Table 1.

[0058] Table 1. Frame Header Line Field Definition Table

[0059] (2) Data rows (N rows in total), arranged consecutively after the frame header, and the field definitions of each row of data are shown in Table 2.

[0060] Table 2 Data Row Field Definition Table

[0061] (3) Frame end line, located at the end of the frame, and its field definitions are shown in Table 3.

[0062] Table 3. Frame Tail Line Field Definition Table

[0063] The configuration parameters in the frame header enable the receiver to adaptively parse the data without prior knowledge of the sensor configuration; dual CRC checks allow the receiver to accurately locate the data line where the error occurred.

[0064] The bit width, synchronization code, and CRC check value of each of the above fields can be adjusted according to the actual application scenario without changing the overall frame structure framework of the present invention.

[0065] For interfaces using 3 pairs of TMDS data channels (such as HDMI 2.0 and below / DVI), the three data channels carry the bit segments of the pixel data respectively: channel 0 carries the low-order part of the pixel data (such as bits [3:0] in RAW12), channel 1 carries the middle part of the pixel data (such as bits [7:4] in RAW12), and channel 2 carries the high-order part of the pixel data (such as bits [11:8] in RAW12). For interfaces using 4 pairs of data channels (such as 4-Lane mode of HDMI 2.1 FRL and 4-Lane mode of DisplayPort), the fourth pair of channels is used to carry additional data, or it can be configured as 3-Lane mode through the mode selection register inside the FPGA to reduce power consumption. The original 8-bit data of each channel is encoded into parallel characters after being encoded by an encoding scheme that matches the selected physical layer, and then serialized into high-speed differential signals by the pure PHY chip.

[0066] The clocking scheme is as follows: In TMDS mode, the FPGA generates a TMDS reference clock based on the sensor output pixel clock, which is multiplied by a PLL and then output to the clock channel of the PHY chip. In FRL and DP modes, the reference clock is only used for the FPGA's internal encoding logic. The PHY chip uses an internal oscillator or an external reference clock to generate a serial bit clock, which is transmitted synchronously with the data stream. The receiving PHY chip extracts the embedded clock from the data stream. The receiving pure PHY receiving chip recovers the serial bit clock from the clock channel (TMDS mode) or extracts the embedded clock from the data stream (FRL / DP mode), and recovers the pixel clock after frequency division. The FPGA uses this clock to sample multi-channel parallel data.

[0067] VI. Multi-physical layer compatibility like Figure 4 As shown, the custom packetization protocol and FPGA encoding / decoding logic of this invention are compatible with TMDS, FRL, and DP physical layer channel mappings. The FPGA's internal mode selection register automatically loads the corresponding channel mapping configuration and encoding parameters upon power-up by detecting the selected interface type, without requiring modification of the FPGA logic code. The channel configuration and encoding methods for each physical layer mode are shown in Table 4.

[0068] Table 4 Comparison of Three Physical Layer Modes

[0069] The channel mapping strategies inside the FPGA differ in the three modes, but the core data packaging and protocol parsing logic remains unchanged.

[0070] Example 2 This embodiment provides a fusion transmission method based on the physical layer of a digital video interface. This method is implemented based on the system described in Embodiment 1 and specifically includes the following steps: I. Video Transmission The remote component acquires raw image data in RAW format. The raw RAW data output by the image sensor is transmitted to the first programmable logic device via a high-speed serial interface. The first programmable logic device deserializes, aligns, and verifies the high-speed serial data, and then organizes the RAW pixel data into custom data frames according to a custom packetization protocol: a frame start identifier segment containing a frame synchronization code, frame count, total number of rows, image configuration parameters, and a check field is inserted at the beginning of the frame; then multiple rows of valid pixel data segments are arranged consecutively, each row containing a row synchronization identifier, valid pixel data, and a row check field; and a frame end identifier segment containing a frame end synchronization code, frame status, and a check field is inserted at the end of the frame.

[0071] After packaging, the first programmable logic device encodes the data according to the adopted digital video interface physical layer standard, and the encoded parallel data is output to the pure physical layer transmitter chip. The pure physical layer transmitter chip converts the parallel encoded data into a high-speed differential serial signal, which is then transmitted through the data channel of the standard digital video interface cable.

[0072] The physical layer receiver chip of the near-end host component receives high-speed differential serial signals from the cable. After signal equalization, clock recovery, and serial-to-parallel conversion, it is restored to parallel data and output to the second programmable logic device. After decoding, the second programmable logic device identifies the start-of-frame identifier to capture frame synchronization, parses each line of valid pixel data sequentially, and performs verification on each frame and each data line. The valid pixel data that passes the verification is restored to parallel RAW format and output to the image signal processor.

[0073] II. Reverse power supply The near-end host component supplies operating power to the far-end component through the power pins of the standard digital video interface cable, with the power supply direction opposite to the standard power supply direction of the digital video interface.

[0074] The power supply circuit of the near-end host component converts the system power into a predetermined DC voltage and outputs it to the power pin of the cable. The power supply enable and current limiting are controlled by the second programmable logic device. The far-end component receives DC power input through the power pin, and after the power management module completes the voltage conversion and power-on timing control, it supplies power to each power-consuming module at the far end.

[0075] III. Reverse Control The near-end host component acts as the master device of the control bus, sending control commands to the remote component through the auxiliary channel of the standard digital video interface cable.

[0076] The second programmable logic device internally implements an I2C master controller, which actively initiates I2C read / write requests and sends them to the remote end via an auxiliary channel. The first programmable logic device in the remote component internally implements an I2C slave bridging module, which responds to I2C read / write requests initiated by the near-end host. This I2C slave bridging module is configured with multiple I2C access addresses, corresponding to local register access of the first programmable logic device and transparent forwarding of the image sensor control bus. I2C transactions are directly bridged through the internal logic of the first programmable logic device, without going through a protocol stack.

[0077] The video transmission step, reverse power supply step, and reverse control step mentioned above all share the same standard digital video interface cable. The video transmission step and the reverse power supply step are independent of each other and can be executed in parallel, while the reverse control step can be initiated at any time during the video transmission process.

[0078] The above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Those skilled in the art can flexibly select other technical features according to actual needs. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should fall within the protection scope of the claims of the present invention. To avoid obscuring the core technical solutions of the present invention, well-known construction processes, operating conditions, etc., are not described in detail in this document.

Claims

1. A converged transmission system based on the physical layer of a digital video interface, characterized in that, This includes remote and near-end host components connected via standard digital video interface cables; The remote component includes an image sensor, a first programmable logic device, and a pure physical layer transmission chip; the image sensor outputs RAW format raw image data; the first programmable logic device receives the RAW format raw image data, organizes the image data into a custom data frame containing a frame start identifier segment, a valid pixel data segment, and a frame end identifier segment according to a custom packetization protocol, and outputs it to the pure physical layer transmission chip after encoding; The pure physical layer transmitting chip converts parallel encoded data into high-speed differential serial signals, which are then transmitted through the data channel of the standard digital video interface cable. The near-end host component includes a pure physical layer receiver chip and a second programmable logic device; the pure physical layer receiver chip receives high-speed differential serial signals from the standard digital video interface cable, and outputs parallel data to the second programmable logic device after serial-to-parallel conversion, signal equalization and clock recovery. The second programmable logic device decodes the parallel data, parses and verifies the custom packing protocol, and recovers the original RAW format image data; The near-end host component acts as the master device of the control bus and sends control commands to the far-end component through the auxiliary channel of the standard digital video interface cable; the first programmable logic device responds to the control commands and completes the parameter configuration of the far-end component.

2. The converged transmission system based on the physical layer of a digital video interface according to claim 1, characterized in that: Both the pure physical layer transmitting chip and the pure physical layer receiving chip are general-purpose pure physical layer chips used to implement physical layer signal processing such as parallel-to-serial conversion, serial-to-parallel conversion, signal equalization, pre-emphasis, and clock recovery.

3. The converged transmission system based on the physical layer of a digital video interface according to claim 1, characterized in that: The custom packetization protocol's frame start identifier segment includes a frame synchronization code, a frame count field, and an image configuration parameter field; the valid pixel data segment includes multiple rows of pixel data, with a row synchronization identifier set before each row of pixel data and a row check field set at the end of each row of pixel data; the frame end identifier segment includes a frame end synchronization code and a frame status field.

4. The converged transmission system based on the physical layer of a digital video interface according to claim 1, characterized in that: The near-end host component provides operating power to the far-end component through the power pins of the standard digital video interface cable, with the power supply direction opposite to the standard power supply direction of the digital video interface. The power supply is 1A to 2A, with a power output of 5W to 10W.

5. The converged transmission system based on the physical layer of a digital video interface according to claim 1, characterized in that: The output interface of the image sensor includes at least one of MIPI CSI-2, Sub-LVDS, and SLVS-EC.

6. A fusion transmission method based on the physical layer of a digital video interface, applied to the system described in any one of claims 1-5, characterized in that, include: The remote component acquires raw image data in RAW format. The first programmable logic device organizes the image data into custom data frames containing a frame start identifier segment, a valid pixel data segment, and a frame end identifier segment according to a custom packetization protocol. After encoding, the data is converted into a high-speed differential serial signal by a pure physical layer transmission chip and transmitted to the near-end host component through the data channel of a standard digital video interface cable. The near-end host component completes serial-to-parallel conversion, signal equalization and clock recovery through the pure physical layer receiving chip, and then decodes, parses and verifies the protocol through the second programmable logic device to recover the original RAW format image data; The near-end host component provides operating power to the far-end component through the power pins of the standard digital video interface cable, with the power supply direction opposite to the standard power supply direction of the digital video interface; The near-end host component acts as the master device of the control bus, and sends control commands to the far-end component through the auxiliary channel of the standard digital video interface cable. The first programmable logic device of the far-end component responds to the control commands and completes the configuration of the far-end parameters.

7. The fusion transmission method based on the physical layer of a digital video interface according to claim 6, characterized in that: The first programmable logic device of the remote component responds to the control command through an internally integrated I2C slave bridging module; the I2C slave bridging module is configured with at least two I2C access addresses, the first address corresponding to the local register access of the first programmable logic device, and the second address corresponding to the transparent forwarding of the image sensor control bus.

8. The fusion transmission method based on the physical layer of a digital video interface according to claim 6, characterized in that: The first programmable logic device adaptively switches the encoding scheme and data channel mapping strategy according to the adopted digital video interface physical layer standard; the digital video interface physical layer standard includes TMDS physical layer, FRL physical layer and DisplayPort physical layer.

9. The fusion transmission method based on the physical layer of a digital video interface according to claim 6, characterized in that: The second programmable logic device performs frame-level and line-level dual CRC checks on the custom data frame to locate erroneous data and report the transmission status.

10. The fusion transmission method based on the physical layer of a digital video interface according to claim 8, characterized in that: The TMDS physical layer uses 8b / 10b encoding, the FRL physical layer uses 16b / 18b encoding, the DisplayPort 1.x physical layer uses ANSI 8b / 10b encoding, and the DisplayPort 2.x physical layer uses 128b / 132b encoding.

Images