Semiconductor memory and methods of manufacturing the same

Abstract

The application provides a semiconductor memory and a manufacturing method thereof, and relates to the technical field of semiconductors, and aims to solve the problem that, in the prior art, a structure collapses or deforms due to lack of effective mechanical support when a high aspect ratio structure is manufactured. The semiconductor memory comprises a capacitor structure, a first support structure, a second support structure and a plurality of first horizontally oriented active layers. The plurality of active layers are arranged at intervals in a vertical orientation, and the active layers form source and drain regions at two ends of the first horizontal orientation. The capacitor structure is located at the end of the active layer along the first horizontal orientation, and the capacitor structure is connected to the drain region. The capacitor structure comprises a plurality of capacitor plates arranged at intervals in a vertical orientation. The first support structure is located at two ends of the capacitor structure along a second horizontal orientation and extends along the vertical orientation, and is used to provide lateral mechanical support for the capacitor structure. The second support structure is located between two adjacent capacitor plates. The structure is not prone to collapse or deformation.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a semiconductor memory and a method for manufacturing the same. Background Technology

[0002] In the field of semiconductor technology, as the storage density of dynamic random access memory (DRAM) continues to increase, the traditional two-dimensional planar structure can no longer meet the capacity requirements due to the limitations of physical miniaturization. This forces semiconductor memory to transform into a three-dimensional stacked architecture. In a three-dimensional stacked architecture, in order to ensure sufficient capacitance within an extremely small planar size to meet read and data retention requirements, the etched structure typically needs to have a high aspect ratio.

[0003] However, the manufacturing methods provided by the related technologies are prone to structural collapse or deformation when manufacturing such high aspect ratio trench or hole structures due to the lack of effective mechanical support. This results in poor structural stability of semiconductor memories under high aspect ratio conditions and a higher risk of device short circuits or failures. Summary of the Invention

[0004] The first aspect of this application aims to provide a semiconductor memory that solves the technical problem that structural collapse or deformation is prone to occur when manufacturing high aspect ratio structures due to the lack of effective mechanical support.

[0005] The semiconductor memory provided in the first aspect of this application includes: Multiple active layers with a first horizontal orientation are arranged at intervals in a vertical orientation, and the active layers form source and drain regions at both ends of the first horizontal orientation, respectively. A capacitor structure is located at the end of the active layer along the first horizontal orientation, the capacitor structure is connected to the drain region, and the capacitor structure includes a plurality of capacitor plates arranged at intervals in the vertical orientation; and A first support structure and a second support structure, wherein the first support structure is located at both ends of the capacitor structure along the second horizontal orientation and extends along the vertical orientation, for providing lateral mechanical support for the capacitor structure, the second horizontal orientation being perpendicular to the first horizontal orientation; the second support structure is located between two adjacent capacitor plates.

[0006] Furthermore, the first support structure and the second support structure are aligned in the vertical orientation.

[0007] Furthermore, along the first horizontal orientation, both the first support structure and the second support structure are provided with multiple components.

[0008] Furthermore, the capacitor structure also includes a capacitor dielectric layer and an upper electrode plate. The capacitor dielectric layer covers the upper surface, lower surface, and side surface of the capacitor electrode plate, and the two second support structures spaced apart in the first horizontal orientation are separated by the capacitor dielectric layer; the upper electrode plate covers the capacitor dielectric layer.

[0009] Furthermore, the semiconductor memory also includes a substrate and a mask layer, the substrate being located at the bottom layer of the vertical orientation and the mask layer being located at the top layer of the vertical orientation; the first support structure extends downward from above the mask layer to the substrate to form a three-sided surrounding structure around the capacitor structure.

[0010] Furthermore, the semiconductor memory further includes bit lines and a plurality of word lines, the bit lines being located at the end of the active layer away from the capacitor structure, and the bit lines being connected to the source regions of each of the active layers; the plurality of word lines and the plurality of active layers are alternately arranged in the vertical orientation, and the word lines at least partially surround the active layers.

[0011] Furthermore, the material of the first support structure includes silicon, oxygen, carbon, and nitrogen, and the material of the second support structure includes silicon nitride.

[0012] The beneficial effects of the semiconductor memory in this application are: By providing first support structures at both ends of the capacitor structure along the second horizontal orientation and extending these structures vertically, effective mechanical support can be provided laterally to the capacitor structure, effectively preventing it from tipping over or twisting and improving the device's mechanical strength. Furthermore, by providing a second support structure between two adjacent capacitor plates, the capacitor plates are mechanically reinforced, preventing deformation caused by their own weight or process stress. This further ensures the verticality and geometric stability of the capacitor structure, effectively solving the problem of structural collapse or deformation that often occurs when manufacturing high aspect ratio structures due to a lack of effective mechanical support. Moreover, the first and second support structures can form a grid-like support system in the semiconductor memory, ensuring sufficient mechanical strength while also guaranteeing a dense arrangement of the capacitor structure to improve storage density.

[0013] The second aspect of this application aims to provide a method for manufacturing a semiconductor memory, thereby solving the technical problem that structural collapse or deformation is prone to occur when manufacturing high aspect ratio structures due to the lack of effective mechanical support.

[0014] The second aspect of this application provides a method for manufacturing a semiconductor memory, comprising the following steps: A substrate is provided, and a stacked structure is formed on the top surface of the substrate, the stacked structure comprising alternating active layers and sacrificial layers; Forming the first supporting structure; A source region and a drain region are formed at both ends of the active layer along the first horizontal orientation, respectively; A capacitor structure is formed at one end of the active layer along the first horizontal orientation, the capacitor structure is connected to the drain region, and the capacitor structure includes a plurality of capacitor plates arranged at intervals in the vertical orientation. A second support structure is formed between two adjacent capacitor plates.

[0015] Furthermore, the step of forming the source region includes: The stacked structure is etched along the vertical orientation to form a first hole; Etching is performed within the first hole along the first horizontal orientation to form a first transverse groove, thereby releasing the sacrificial layer and thinning the active layer; The active layer exposed by the first transverse trench is doped to form the source region.

[0016] Furthermore, it also includes: forming a mask layer on the top surface of the stacked structure; the step of forming the first support structure includes: The mask layer is etched along the vertical orientation to form support structure trenches; A second transverse groove is formed by etching along the second horizontal orientation within the groove of the support structure; Deposit support material in the support structure trench and the second transverse trench to form the first support structure, such that the first support structure is spaced apart between two adjacent active layers in the vertical orientation.

[0017] Further, the step of forming the capacitor structure includes: A first trench is formed in the mask layer, the first trench extending along the second horizontal orientation and penetrating the stacked structure; A second trench is formed, and the sacrificial layer is etched laterally in the second trench to release space, wherein the second trench includes a first sub-groove extending along the first horizontal orientation and a second sub-groove extending along the second horizontal orientation; Conductive material is deposited within the space to form multiple capacitor plates spaced apart along the vertical orientation.

[0018] Further, the step of forming the second support structure includes: A sacrificial material layer is filled between two adjacent capacitor plates; The sacrificial material layer is etched back to form a transverse groove, and a portion of the sacrificial material layer remains to form the second support structure.

[0019] Furthermore, the step of forming the capacitor structure further includes: A capacitor dielectric layer is deposited in the transverse groove, and the capacitor dielectric layer covers the upper surface, lower surface and sidewall of the capacitor plate; The upper electrode is deposited on the capacitor dielectric layer; A conductive filler layer is deposited in the area enclosed by the upper electrode plate.

[0020] The beneficial effects of the semiconductor memory manufacturing method described in this application are: In this semiconductor memory manufacturing method, by forming a first support structure on the side of the capacitor structure, mechanical support can be formed on the side of the capacitor structure to counteract the lateral stress generated by removing the sacrificial layer during the formation of the vertically spaced capacitor plates, prevent the slender capacitor structure from tilting or collapsing, and improve the mechanical stability of the semiconductor memory under high aspect ratio.

[0021] Simultaneously, by forming a second support structure between two adjacent capacitor plates, and using the gap between the capacitor plates as support points, the dispersed capacitor plates are mechanically reinforced without occupying additional surrounding space. This method can maintain the precise spacing between the capacitor plates, preventing deformation of the capacitor plates due to their own weight or process stress, thereby ensuring that the manufactured semiconductor memory has good storage performance. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments or background art of this application, the drawings used in the description of the embodiments or background art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0023] Figure 1 This is a front cross-sectional view of the manufacturing method provided in the embodiments of this application, in which a multilayer structure is formed on a substrate; Figure 2 This is a top cross-sectional view of the manufacturing method for forming the trench isolation sacrificial structure provided in the embodiments of this application; Figure 3 This is a front cross-sectional view of the manufacturing method for forming the first hole provided in the embodiments of this application; Figure 4 A top cross-sectional view of the first hole formed in the manufacturing method provided in the embodiments of this application; Figure 5 This is a front cross-sectional view of the release of the sacrificial layer and the thinning of the active layer in the manufacturing method provided in the embodiments of this application; Figure 6This is a front cross-sectional view of the manufacturing method for forming the word line sacrificial layer provided in the embodiments of this application; Figure 7 This is a top cross-sectional view of the manufacturing method for forming the word line sacrificial layer provided in the embodiments of this application; Figure 8 This is a front cross-sectional view of the manufacturing method for forming a capacitor trench isolation sacrificial structure provided in the embodiments of this application; Figure 9 This is a top cross-sectional view of the manufacturing method provided in the embodiments of this application, in which a capacitor trench isolation sacrificial structure is formed. Figure 10 This is a front cross-sectional view of the manufacturing method provided in the embodiments of this application, in which the gaps in the capacitor support structure are formed. Figure 11 A top cross-sectional view of the formation of the capacitor support structure gap in the manufacturing method provided in the embodiments of this application; Figure 12 A side cross-sectional view of the formation of the transverse capacitor support structure gap in the manufacturing method provided in the embodiments of this application; Figure 13 This is a front cross-sectional view of the manufacturing method for forming the first support structure provided in the embodiments of this application; Figure 14 This is a top cross-sectional view of the manufacturing method for forming the first support structure provided in the embodiments of this application; Figure 15 This is a side cross-sectional view of the manufacturing method for forming the first support structure provided in the embodiments of this application; Figure 16 A top cross-sectional view of the manufacturing method for forming an independent active region provided in the embodiments of this application; Figure 17 This is a top cross-sectional view of the manufacturing method for forming the isolation region provided in the embodiments of this application; Figure 18 This is a front cross-sectional view of the manufacturing method for forming word line gaps provided in the embodiments of this application; Figure 19 A top cross-sectional view of the word line gaps formed in the manufacturing method provided in the embodiments of this application; Figure 20 This is a front cross-sectional view of the manufacturing method for forming word lines provided in the embodiments of this application; Figure 21 This is a top cross-sectional view of the manufacturing method for forming character lines provided in the embodiments of this application; Figure 22 This is a front cross-sectional view of the engraved lettering in the manufacturing method provided in the embodiments of this application; Figure 23 This is a top cross-sectional view of the engraved lettering in the manufacturing method provided in the embodiments of this application; Figure 24This is a front cross-sectional view of the manufacturing method for forming word line isolation provided in the embodiments of this application; Figure 25 This is a top cross-sectional view of the manufacturing method provided in the embodiments of this application, showing the formation of word line isolation. Figure 26 This is a front cross-sectional view of the manufacturing method providing an embodiment of the present application, showing the exposed active region. Figure 27 A top cross-sectional view of the exposed active region in the manufacturing method provided in the embodiments of this application; Figure 28 This is a front cross-sectional view of the manufacturing method for forming the source region and bit line in the embodiment of this application; Figure 29 This is a top cross-sectional view of the manufacturing method for forming the source region and bit line in the embodiment of this application; Figure 30 This is a front cross-sectional view of the manufacturing method for forming the second trench provided in the embodiments of this application; Figure 31 This is a top cross-sectional view of the manufacturing method provided in the embodiments of this application, showing the formation of the second trench. Figure 32 This is a front cross-sectional view of the manufacturing method for forming a capacitor isolation structure provided in the embodiments of this application; Figure 33 This is a side cross-sectional view of the manufacturing method for forming a capacitor isolation structure provided in the embodiments of this application; Figure 34 This is a front cross-sectional view of the manufacturing method for forming gaps in capacitor plates provided in the embodiments of this application; Figure 35 A top cross-sectional view of the formation of capacitor plate gaps in the manufacturing method provided in the embodiments of this application; Figure 36 A side cross-sectional view of the formation of capacitor plate gaps in the manufacturing method provided in the embodiments of this application; Figure 37 This is a front cross-sectional view of the manufacturing method for forming capacitor plates provided in the embodiments of this application; Figure 38 A top cross-sectional view of the capacitor plates formed in the manufacturing method provided in the embodiments of this application; Figure 39 A side cross-sectional view of the capacitor plates formed in the manufacturing method provided in the embodiments of this application; Figure 40 This is a front cross-sectional view of the manufacturing method for forming the second support structure provided in the embodiments of this application; Figure 41 This is a top cross-sectional view of the manufacturing method for forming the second support structure provided in the embodiments of this application; Figure 42A side cross-sectional view of the manufacturing method for forming the second support structure provided in the embodiments of this application; Figure 43 This is a front cross-sectional view of a semiconductor memory obtained according to the manufacturing method provided in the embodiments of this application; Figure 44 This is a top cross-sectional view of a semiconductor memory obtained according to the manufacturing method provided in the embodiments of this application; Figure 45 This is a side cross-sectional view of a semiconductor memory obtained according to the manufacturing method provided in the embodiments of this application; Figure 46 This is a side cross-sectional view of a semiconductor memory obtained according to the manufacturing method provided in the embodiments of this application, taken from another section. Figure 47 A flowchart illustrating the manufacturing method provided in the embodiments of this application; Figure 48 A flowchart illustrating the formation of the first support structure in the manufacturing method provided in this application embodiment; Figure 49 This is a flowchart illustrating the process of forming a capacitor structure in the manufacturing method provided in this application embodiment; Figure 50 This is a top cross-sectional view of a semiconductor memory obtained according to a manufacturing method provided in another embodiment of this application; Figure 51 This is a side cross-sectional view of a semiconductor memory obtained according to a manufacturing method provided in another embodiment of this application.

[0024] Explanation of reference numerals in the attached figures: 101-Substrate; 102-Layered structure; 1021-Sacrificial layer; 1022-Active layer; 103-Sacrificial active layer; 104-Mask layer; 201 - First isolation layer; 202 - First sacrificial layer; 203 - First filling area; 301 - First hole; 302 - First transverse groove; 303 - First dielectric layer; 304 - Word line sacrificial layer; 305 - Word line isolation layer; 401 - Second filling area; 402 - Second isolation layer; 403 - Second sacrificial layer; 501 - Support structure groove; 502 - Second transverse groove; 503 - First support structure; 601 - Third transverse groove; 602 - First isolation zone; 701 - Second hole; 702 - Fourth transverse groove; 703 - First conductive layer; 704 - Fifth transverse groove; 705 - Third isolation layer; 706 - Third sacrificial layer; 707 - Source region; 708 - First contact region; 709 - Second conductive layer; 801-First trench; 802-Second trench; 803-Fourth isolation layer; 804-Sixth transverse trench; 805-Drain region; 806-Capacitor plate; 807-Fourth sacrificial layer; 808-Seventh transverse trench; 809-Second dielectric layer; 810-Fourth conductive layer; 811-Conductive filling layer; 812-Second support structure. Detailed Implementation

[0025] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, specific embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0026] like Figures 43 to 45 As shown, this embodiment provides a semiconductor memory, including an active layer 1022, a capacitor structure, a first support structure 503, and a second support structure 812. The active layers 1022 are arranged in a first horizontal orientation and have multiple layers. These multiple active layers 1022 are arranged at intervals in a vertical orientation, and a source region 707 and a drain region 805 are formed at both ends of the active layers 1022 in the first horizontal orientation, respectively. The capacitor structure is located at the end of the active layers 1022 along the first horizontal orientation and is connected to the drain region 805. The capacitor structure includes multiple capacitor plates 806 arranged at intervals in a vertical orientation. The first support structure 503 is located at both ends of the capacitor structure along a second horizontal orientation and extends along the vertical orientation, providing lateral mechanical support for the capacitor structure. The second horizontal orientation is perpendicular to the first horizontal orientation. The second support structure 812 is located between two adjacent capacitor plates 806.

[0027] By providing first support structures 503 at both ends of the capacitor structure along the second horizontal orientation and extending the first support structures 503 in the vertical orientation, effective mechanical support can be provided for the capacitor structure in the lateral direction, effectively preventing the capacitor structure from tilting or twisting and improving the mechanical strength of the device. Furthermore, by providing a second support structure 812 between two adjacent capacitor plates 806, the capacitor plates 806 can be mechanically reinforced, avoiding deformation caused by their own weight or process stress, further ensuring the verticality and geometric stability of the capacitor structure. This effectively solves the problem of structural collapse or deformation that easily occurs when manufacturing high aspect ratio structures due to a lack of effective mechanical support. Moreover, the first support structure 503 and the second support structure 812 can form a grid-like support system in the semiconductor memory, ensuring sufficient mechanical strength while also ensuring a dense arrangement of the capacitor structure to improve storage density.

[0028] It should be noted that in this embodiment, "first horizontal orientation," "second horizontal orientation," and "vertical orientation" can be referred to as... Figures 43 to 45The direction indicated by the corresponding arrow.

[0029] In this embodiment, the semiconductor memory can be 3D DRAM (3D Dynamic Random-Access Memory).

[0030] Please continue to refer to Figure 43 In this embodiment, the first support structure 503 and the second support structure 812 are aligned in vertical orientation.

[0031] By aligning the first support structure 503 located on the side of the capacitor structure with the second support structure 812 located between adjacent capacitor plates 806 in a vertical orientation, the lateral support force can be directly transmitted to the internal support points between the capacitor plates 806, avoiding the twisting or even breakage of the capacitor plates 806 due to support misalignment, effectively reducing the residual stress concentration inside the semiconductor memory, and achieving a uniform distribution of support stress.

[0032] Please continue to refer to Figure 43 In this embodiment, along the first horizontal orientation, both the first support structure 503 and the second support structure 812 are provided with multiple components.

[0033] By setting multiple first support structures 503 and second support structures 812 along the first horizontal orientation, a distributed skeleton support is formed in the capacitor structure, which can increase the effective area of ​​the support structure and avoid torsional deformation of the capacitor plate 806 due to local stress concentration. This is especially suitable for semiconductor memories with large array aspect ratios.

[0034] Please continue to refer to Figure 43 In this embodiment, the capacitor structure may further include a capacitor dielectric layer and an upper electrode plate, wherein the capacitor dielectric layer covers the upper surface, lower surface and side surface of the capacitor electrode plate 806, and the two second support structures 812 spaced apart in the first horizontal orientation are separated by the capacitor dielectric layer; the upper electrode plate covers the capacitor dielectric layer.

[0035] This capacitor structure reuses the upper and lower surfaces of the capacitor plate 806 by having a dielectric layer cover the upper surface, lower surface, and side surface of the capacitor plate 806, and then covering the upper plate with the dielectric layer. This configuration can increase the capacitance by 1.5 to 1.9 times, reduce the required capacitor size, and increase the in-plane density.

[0036] In addition, by configuring the capacitor dielectric layer to cover the upper surface, lower surface and side surface of the capacitor plate 806, all-round insulation protection of the capacitor plate 806 can be achieved, reducing the risk of leakage current.

[0037] Please continue to refer to Figure 45In this embodiment, the semiconductor memory may further include a substrate 101 and a mask layer 104, wherein the substrate 101 is located at the bottom layer of the vertical orientation and the mask layer 104 is located at the top layer of the vertical orientation; the first support structure 503 extends downward from above the mask layer 104 to the substrate 101 to form a three-sided surrounding structure around the capacitor structure.

[0038] This configuration allows the first support structure 503 to become a continuous support structure spanning the entire stack height, enabling the lateral mechanical support force to be directly transferred to the mask layer 104 and the substrate 101, thereby suppressing the risk of the capacitor array tipping over during the process.

[0039] like Figure 46 As shown, in this embodiment, the semiconductor memory may further include bit lines and multiple word lines. The bit lines are located at the end of the active layer 1022 away from the capacitor structure, and the bit lines are connected to the source region 707 of each active layer 1022. The multiple word lines are arranged alternately with the multiple active layers 1022 in a vertical orientation, and the word lines partially surround the active layer 1022.

[0040] This configuration allows the semiconductor memory to have a planar stacked structure, which greatly reduces the manufacturing difficulty compared to a fully encircled gate structure.

[0041] like Figure 50 and Figure 51 As shown, in another embodiment, the word lines can also be configured to completely surround the active layer 1022. This configuration results in a surround structure for the semiconductor memory, with the first dielectric layer 303 completely surrounding the active layer 1022, which can effectively improve gate control capability.

[0042] In this embodiment, the first support structure 503 can be made of silicon, oxygen, carbon, and nitrogen, and the second support structure 812 can be made of silicon nitride.

[0043] By using silicon-oxygen-carbon-nitrogen (SiO2-CNO) as the material for the first support structure 503, its high density provides better lateral support for the capacitor structure. Furthermore, SiO2-CNO has a better etch selectivity than interlayer silicon oxide, preventing it from being etched during the removal of the sacrificial layer 1021. By using silicon nitride as the material for the second support structure 812, its moderate mechanical strength prevents the capacitor plate 806 from collapsing. Moreover, the difference in etch selectivity between silicon nitride and SiO2-CNO ensures that the first support structure 503 is not damaged during partial etchback of the second support structure 812. This heterogeneous dual-support material combination ensures that both the main lateral support and the micro-supports between the capacitor plate 806 achieve optimal mechanical properties, while maximizing the process window to reduce the risk of mis-etching of the support structure.

[0044] like Figure 47 As shown, this embodiment also provides a method for manufacturing a semiconductor memory, including the following steps: S100: As Figure 1 As shown, a substrate 101 is provided, and a stacked structure 102 is formed on the top surface of the substrate 101. The stacked structure 102 includes an active layer 1022 and a sacrificial layer 1021 that are stacked alternately.

[0045] In this step, the substrate 101 can be made of single-crystal silicon; the stacked structure 102 is formed by stacking alternating deposited active layer 1022 and sacrificial layer 1021. The active layer 1022 can be made of single-crystal silicon, and the sacrificial layer 1021 can be made of single-crystal germanium silicon. Due to the different germanium concentrations in the materials, the active layer 1022 and the sacrificial layer 1021 have a high etching selectivity. The active layer 1022 and the sacrificial layer 1021 can be obtained by epitaxy.

[0046] Please continue to refer to Figure 1 Specifically, a sacrificial active layer 103 is formed above the stacked structure 102. The sacrificial active layer 103 can also be made of single-crystal silicon and can be obtained by epitaxy. A mask layer 104 is also formed above the sacrificial active layer 103. The mask layer 104 can be made of one or more of the following materials: silicon oxide, silicon nitride, silicon oxynitride, and amorphous carbon. The mask layer 104 can be obtained by vapor deposition.

[0047] S200: such as Figures 13 to 15 As shown, the first support structure 503 is formed.

[0048] S300: such as Figure 37 and Figure 38 As described above, a source region 707 and a drain region 805 are formed at both ends of the active layer 1022 along the first horizontal orientation, respectively.

[0049] By forming source region 707 and drain region 805 at both ends of the active layer 1022 along the first horizontal orientation, an effective channel region can be defined to establish ohmic contacts with external circuits. Source region 707 serves as the signal input / output terminal of the semiconductor memory, used for electrical connection to bit lines; drain region 805 is used to connect to a capacitor structure for charge storage and release, thereby completing data writing, holding, and reading operations under word line control.

[0050] S400: such as Figure 40 As shown, a capacitor structure is formed at one end of the active layer 1022 along the first horizontal orientation. The capacitor structure is connected to the drain region 805. The capacitor structure includes a plurality of capacitor plates 806 arranged at intervals in a vertical orientation.

[0051] By arranging multiple spaced capacitor plates 806 in a vertical orientation, the unit storage area can be increased without increasing the horizontal projected area, thereby improving the storage capacity of the semiconductor memory in this embodiment.

[0052] By forming a first support structure 503 on the side of the capacitor structure, mechanical support can be formed on the side of the capacitor structure to counteract the lateral stress generated by removing the sacrificial layer 1021 during the formation of the vertically spaced capacitor plates 806, prevent the slender capacitor structure from tilting or collapsing, and improve the mechanical stability of the semiconductor memory under high aspect ratio.

[0053] S500: Please refer to the following: Figure 40 A second support structure 812 is formed between two adjacent capacitor plates 806.

[0054] By forming a second support structure 812 between two adjacent capacitor plates 806, and using the gap between the capacitor plates 806 as support points, the dispersed capacitor plates 806 are mechanically reinforced without occupying additional surrounding space. This method can maintain the precise spacing between the capacitor plates 806, preventing deformation of the capacitor plates 806 due to their own weight or process stress, thereby ensuring that the manufactured semiconductor memory has good storage performance.

[0055] The manufacturing method of this semiconductor memory also includes: like Figure 2 As shown, a first filling region 203 is formed in the stacked structure 102. Specifically, the first filling region 203 includes a first isolation layer 201 and a first sacrificial layer 202 deposited sequentially. The first isolation layer 201 can be made of silicon oxide and can be obtained by atomic layer deposition. The first sacrificial layer 202 can be made of amorphous silicon or polycrystalline silicon and can be obtained by chemical vapor deposition.

[0056] like Figure 3 and Figure 4 As shown, a first hole 301 is formed in the stacked structure 102. The first hole 301 can be obtained by sequentially etching the mask layer 104, the sacrificial active layer 103, the stacked structure 102 and the substrate 101 by plasma etching.

[0057] By forming a first hole 301 in the stacked structure 102, a vertical through-hole can be provided for the subsequent formation of bit lines, so that the bit lines can establish ohmic contact with the source region 707 through the first hole 301.

[0058] like Figure 5As shown, a first lateral trench 302 is formed by etching along a first horizontal orientation within the first hole 301 to release the sacrificial layer 1021 and thin the active layer 1022. In this step, the first lateral trench 302 can be obtained by free radical etching, wet etching, or other methods.

[0059] After the sacrificial layer 1021 is released, a cavity can be formed around the retained active layer 1022 to provide space for subsequent replacement processes. Furthermore, by thinning the active layer 1022, the ends of the active layer 1022 can be trimmed to facilitate the formation of a large-area ohmic contact in the source region 707.

[0060] like Figure 6 and Figure 7 As shown, a first dielectric layer 303, a word line sacrificial layer 304, and a word line isolation layer 305 are formed in the first hole 301 and the first transverse groove 302. The first dielectric layer 303 can be made of one or more materials such as silicon oxide, hafnium oxide, lanthanum oxide, zirconium oxide, and aluminum oxide, and can be obtained by atomic layer deposition (ALD). The word line sacrificial layer 304 can be made of silicon nitride and can be obtained by ALD or chemical vapor deposition (CVD). The word line isolation layer 305 can be made of silicon oxide and can be obtained by CVD.

[0061] By depositing a first dielectric layer 303 in the first hole 301 and the first lateral trench 302, the first dielectric layer 303 tightly covers the channel region of the active layer 1022. The first dielectric layer 303 is used as a gate dielectric layer to precisely control the electrical isolation between the gate and the channel. The word line sacrificial layer 304 serves as a temporary placeholder structure filling the outside of the first dielectric layer 303, which can be selectively removed in subsequent processes to achieve word line replacement.

[0062] like Figure 8 and Figure 9 As shown, a second filling region 401 is formed in the stacked structure 102. The deep trench where the second filling region 401 is located can be obtained by etching the stacked structure 102 using plasma etching. A second isolation layer 402 and a second sacrificial layer 403 are sequentially deposited in the second filling region 401. The second isolation layer 402 can be made of silicon oxide and can be obtained by atomic layer deposition. The second sacrificial layer 403 can be made of amorphous silicon or polycrystalline silicon and can be obtained by chemical vapor deposition.

[0063] Please continue to refer to Figure 8Before the second filling region 401 is formed in the stacked structure 102, the thickness of the mask layer 104 can be increased by deposition. This arrangement can, on the one hand, compensate for the mask layer 104 lost in the aforementioned etching process, ensuring that the thickness of the mask layer 104 is not too thin and affects the pattern transfer accuracy; on the other hand, it can also protect the first dielectric layer 303, the word line sacrificial layer 304, and the word line isolation layer 305, preventing damage to them in subsequent processes.

[0064] In this embodiment, the step of forming the first support structure 503 may include: S201: As Figure 10 and Figure 11 As shown, a support structure trench 501 is formed. Specifically, the mask layer 104, the second sacrificial layer 403, and the second isolation layer 402 can be etched stepwise using plasma etching and free radical etching methods. This step allows space to be reserved for the formation of the first support structure 503.

[0065] S202: As Figure 12 As shown, a second transverse groove 502 is formed by etching along the second horizontal orientation within the support structure trench 501. Specifically, the sacrificial layer 1021 can be transversely etched using methods such as free radical etching, wet etching, or atomic layer etching.

[0066] S203: As Figures 13 to 15 As shown, support material is deposited in the support structure trench 501 and the second transverse groove 502 to form a first support structure 503, such that the first support structure 503 is distributed vertically between two adjacent active layers 1022. The first support structure 503 can be obtained by atomic layer deposition or chemical vapor deposition.

[0067] By dividing the formation of the first support structure 503 into three steps—etching the support structure trench 501, laterally releasing the second transverse groove 502, and backfilling the support material—the first support structure 503 can be strictly spaced between two adjacent active layers 1022 in vertical orientation, thus ensuring the geometric accuracy of the first support structure 503.

[0068] In this embodiment, after releasing the sacrificial layer 1021 and thinning the active layer 1022 to form the first support structure 503, the method further includes: Figure 16 As shown, a third lateral trench 601 is formed in the first filling region 203 and the active layer 1022. Specifically, the first sacrificial layer 202 and the first isolation layer 201 can be etched stepwise by plasma etching and free radical etching, and then the active layer 1022 can be laterally etched by free radical etching, wet etching or atomic layer etching.

[0069] By forming a third lateral trench 601, space can be released between the first sacrificial layer 202 and the first isolation layer 201 in the second horizontal orientation, providing a surrounding cavity for subsequent word lines and ensuring that the word lines can partially or completely surround the active layer 1022 to form effective gate control.

[0070] After the third transverse groove 601 is formed, as Figure 17 As shown, a first isolation region 602 can be formed in the third transverse groove 601. The material filled in the first isolation region 602 can be silicon oxide. The first isolation region 602 can be obtained by chemical vapor deposition.

[0071] By forming a first isolation region 602 in the third transverse slot 601, the first isolation region 602 can be used as an interlayer isolation layer to establish good electrical isolation between the subsequently formed word lines and the channel region of the active layer 1022, thereby reducing leakage current.

[0072] After the formation of the first isolation zone 602, as Figure 18 and Figure 19 As shown, the word line isolation layer 305 and the word line sacrificial layer 304 can be etched stepwise by plasma etching and free radical etching to form the second hole 701 and the fourth transverse groove 702.

[0073] This step allows the fourth transverse groove 702 to expose the sidewall of the active layer 1022 surrounding the first isolation zone 602, providing process space for subsequent word line material to fill in partially or completely around the active layer 1022.

[0074] After the second hole 701 and the fourth transverse groove 702 are formed, as Figure 20 and Figure 21 As shown, a first conductive layer 703 can be formed in the fourth transverse groove 702. The material of the first conductive layer 703 can be titanium nitride, tantalum nitride, titanium aluminum alloy, tungsten, ruthenium, or molybdenum, etc. The first conductive layer 703 can be obtained by atomic layer deposition or chemical vapor deposition.

[0075] After the first conductive layer 703 is formed in the fourth transverse groove 702, as Figure 22 and Figure 23 As shown, the first conductive layer 703 can be etched back into the second hole 701 to form word lines and a fifth transverse groove 704 with each layer separated. At this time, the remaining part of the first conductive layer 703 forms the word lines. The etching of the first conductive layer 703 can be achieved by free radical etching, wet etching, or atomic layer etching.

[0076] After forming the letter lines and the fifth horizontal slot 704, as Figure 24 and Figure 25As shown, a third isolation layer 705 and a third sacrificial layer 706 can be deposited sequentially in the fifth transverse trench 704. The material of the third isolation layer 705 can be silicon nitride, and the material of the third sacrificial layer 706 can be silicon oxide, amorphous silicon, or monocrystalline silicon, etc. The third isolation layer 705 and the third sacrificial layer 706 can be obtained by atomic layer deposition or chemical vapor deposition.

[0077] After the deposition of the third isolation layer 705 and the third sacrificial layer 706 is completed, as Figure 26 and Figure 27 As shown, the third sacrificial layer 706, the third isolation layer 705, and the first dielectric layer 303 can be etched back into the second hole 701, exposing the active layer 1022. The etching back of the third sacrificial layer 706, the third isolation layer 705, and the first dielectric layer 303 can be achieved by free radical etching, wet etching, or atomic layer etching.

[0078] This step allows for the active removal of the occupant material and excess dielectric covering the periphery of the active layer 1022, re-exposing the channel region of the active layer 1022 so that it can subsequently form an effective ohmic contact with the bit line.

[0079] After that, as Figure 28 and Figure 29 As shown, the step of forming the source region 707 includes: doping the active layer 1022 exposed by the first lateral trench 302 to form the source region 707. Specifically, the source region 707 is formed of heavily doped silicon, which can be obtained by epitaxy, atomic layer deposition or chemical vapor deposition of heavily doped silicon. Optionally, doping can be achieved in the exposed active layer 1022 by vapor phase doping, plasma doping or other methods.

[0080] Please continue to refer to Figure 28 and Figure 29 After forming the source region 707, metals such as titanium, cobalt, and nickel can be deposited and annealed using atomic layer deposition, physical vapor deposition, or chemical vapor deposition to obtain the first contact region 708. Furthermore, one or more materials such as titanium nitride, tungsten, ruthenium, and molybdenum can be deposited using atomic layer deposition or chemical vapor deposition to obtain the second conductive layer 709.

[0081] This step enables the bit line to establish a stable electrical connection with the source region 707 of the active layer 1022 through the first contact region 708, thereby ensuring the normal operation of the semiconductor memory.

[0082] In this embodiment, the step of forming the capacitor structure may include: S401: As Figure 30As shown, a first trench 801 is formed in the mask layer 104. The first trench 801 extends along the second horizontal orientation and penetrates the stacked structure 102. The first trench 801 can be etched to stop exposing the second sacrificial layer 403 and expose the ends of each active layer 1022.

[0083] In the above steps, the second sacrificial layer 403 is removed by plasma etching, and the second isolation layer 402 is removed by free radical etching or atomic layer etching. The etching of the first trench 801 is stopped at... Figure 30 The position shown can avoid etching damage to the substrate 101.

[0084] S402: As Figure 31 As shown, a second trench 802 is formed, and a sacrificial layer 1021 is etched laterally in the second trench 802 to release space. The second trench 802 includes a first sub-trench extending along a first horizontal orientation and a second sub-trench extending along a second horizontal orientation.

[0085] Specifically, such as Figure 32 and Figure 33 As shown, the sacrificial layer 1021 is removed in the second trench 802 by means of free radical etching, atomic layer etching or wet etching. Then, the active layer 1022 is thinned by means of free radical etching, atomic layer etching or wet etching, and the fourth isolation layer 803 is filled by means of atomic layer deposition or chemical vapor deposition. The material of the fourth isolation layer 803 can be silicon oxide.

[0086] S403: Deposit conductive material in the space formed in step S402 above to form multiple capacitor plates 806 arranged at intervals along a vertical orientation.

[0087] Specifically, such as Figures 34 to 36 As shown, the active layer 1022 can be laterally etched in the second trench 802 using methods such as free radical etching, atomic layer etching, or wet etching to form the sixth lateral trench 804. This step releases the mounting space for the capacitor plate 806, allowing the subsequently deposited capacitor plate 806 to be horizontally embedded and fully contact the drain region 805 at the end of the active layer 1022.

[0088] After the sixth transverse groove 804 is formed, as Figures 37 to 39As shown, a drain region 805 and a third conductive layer are formed in the sixth transverse trench 804, wherein the third conductive layer is the capacitor plate 806. The drain region 805 can be formed of heavily doped silicon, which can be achieved by epitaxy, atomic layer deposition, or chemical vapor deposition. Optionally, drain doping can be achieved in the exposed active layer 1022 by vapor phase doping, plasma doping, etc., and metals such as titanium, cobalt, and nickel can be deposited by atomic layer deposition, physical vapor deposition, or chemical vapor deposition, followed by annealing to achieve metal silicide contact. The material of the third conductive layer can be one or more of titanium nitride, tungsten, ruthenium, molybdenum, etc., and the third conductive layer can be obtained by atomic layer deposition, chemical vapor deposition, etc.

[0089] It should be noted that in other embodiments, the sixth transverse groove 804 can be filled when forming the third conductive layer to form a columnar electrode; then, the fourth isolation layer 803 is etched laterally to form the capacitor plate 806.

[0090] Please continue to refer to Figures 37 to 39 Then, a fourth sacrificial layer 807 is formed. The material of the fourth sacrificial layer 807 can be silicon nitride. The fourth sacrificial layer 807 can be obtained by atomic layer deposition, chemical vapor deposition, etc. Subsequently, it can be etched back by dry etching, free radical etching, wet etching, etc., to disconnect the third conductive layer of each layer from the fourth sacrificial layer 807. Finally, the fourth isolation layer 803 is laterally etched in the second trench 802 by free radical etching, atomic layer etching or wet etching, etc., and silicon nitride is filled by atomic layer deposition, chemical vapor deposition, etc. to form the fourth sacrificial layer 807, and then etched back.

[0091] It should be noted that in other embodiments, the step of lateral etching of the fourth isolation layer 803 can be omitted, and only one side of the capacitor plate 806 can be used to reduce the difficulty of the process.

[0092] Furthermore, such as Figures 40 to 42 As shown, the fourth sacrificial layer 807 is laterally etched in the second trench 802 using free radical etching, atomic layer etching, or wet etching to form the seventh lateral trench 808. During this step, a portion of the fourth sacrificial layer 807 may remain during the lateral etching process to form the second support structure 812. In other words, the second support structure 812 is formed by etching away a portion of the fourth sacrificial layer 807; in fact, the material of the second support structure 812 is the same as that of the fourth sacrificial layer 807.

[0093] This method of using the fourth sacrificial layer 807 remaining during the etching process to form the second support structure 812 eliminates the need for separate deposition and patterning of the second support structure 812. Instead, the original fourth sacrificial layer 807 is directly retained at the required thickness, saving the steps of secondary deposition of support material, photolithography, and pattern transfer, thus simplifying the process.

[0094] In this embodiment, the step of forming the capacitor structure further includes: S404: As Figures 43 to 45 As shown, a second dielectric layer 809 is deposited in the seventh transverse trench 808, wherein the second dielectric layer 809 covers the upper surface, lower surface, and sidewalls of the capacitor plate 806. The second dielectric layer 809 serves as the capacitor dielectric layer.

[0095] Specifically, the material of the second dielectric layer 809 can be one or more of the following: hafnium oxide, lanthanum oxide, zirconium oxide, aluminum oxide, titanium oxide, etc. The second dielectric layer 809 can be obtained by atomic layer deposition.

[0096] S405: After depositing the second dielectric layer 809 in the seventh transverse trench 808, please continue to refer to... Figures 43 to 45 A fourth conductive layer 810 is deposited on the second dielectric layer 809, wherein the fourth conductive layer 810 serves as the upper electrode.

[0097] Specifically, the fourth conductive layer 810 can be made of one or more materials such as titanium nitride, tungsten, ruthenium, and molybdenum, and the fourth conductive layer 810 can be obtained by atomic layer deposition.

[0098] S406: A conductive filling layer 811 is deposited in the region enclosed by the fourth conductive layer 810.

[0099] Specifically, the conductive filling layer 811 can be made of one or more materials such as silicon, germanium, and tungsten, and the conductive filling layer 811 can be obtained by chemical vapor deposition.

[0100] The capacitor structure formed by this manufacturing method, by covering the upper, lower, and side surfaces of the capacitor plate 806 with a dielectric layer and then covering the upper plate with the dielectric layer, allows for the reuse of the upper and lower surfaces of the capacitor plate 806. This configuration can increase the capacitance by 1.5 to 1.9 times, reduce the required capacitor size, and increase the in-plane density.

[0101] The semiconductor memory manufactured through the above steps is as follows: Figures 43 to 46 As shown, the semiconductor memory has a planar stacked structure.

[0102] In another embodiment, such as Figure 50 and Figure 51As shown, the first conductive layer 703 used to form word lines is configured to completely surround the active layer 1022 to form a gate-around transistor structure. This structure can be formed by controlling the deposition thickness of the first dielectric layer 303.

[0103] Specifically, when forming the third transverse trench 601, a first dielectric layer 303 is deposited by atomic layer deposition, and its thickness is controlled by adjusting the number of deposition cycles so that it completely covers the sidewalls, upper surface and lower surface of the active layer 1022. Then, the deposited first conductive layer 703 is filled on the outside of the first dielectric layer 303, thereby achieving all-round coverage of the channel region of the active layer 1022.

[0104] While this application discloses the above information, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of this application; therefore, the scope of protection of this application shall be determined by the scope defined in the claims.

[0105] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the term "comprising" or any other variations thereof is intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0106] In the above embodiments, descriptions of directions such as "up" and "down" are based on the accompanying drawings.

[0107] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application.

[0108] Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A semiconductor memory, characterized in that, include: Multiple active layers (1022) with a first horizontal orientation are arranged at intervals in a vertical orientation, and the active layers (1022) form a source region (707) and a drain region (805) at both ends of the first horizontal orientation, respectively. A capacitor structure is located at the end of the active layer (1022) along the first horizontal orientation, the capacitor structure is connected to the drain region (805), and the capacitor structure includes a plurality of capacitor plates (806) arranged at intervals in the vertical orientation. as well as A first support structure (503) and a second support structure (812), wherein the first support structure (503) is located at both ends of the capacitor structure along the second horizontal orientation and extends along the vertical orientation, for providing lateral mechanical support for the capacitor structure, wherein the second horizontal orientation is perpendicular to the first horizontal orientation; and the second support structure (812) is located between two adjacent capacitor plates (806).

2. The semiconductor memory according to claim 1, characterized in that, The first support structure (503) and the second support structure (812) are aligned in the vertical orientation.

3. The semiconductor memory according to claim 1, characterized in that, Along the first horizontal orientation, both the first support structure (503) and the second support structure (812) are provided with multiple supports.

4. The semiconductor memory according to claim 3, characterized in that, The capacitor structure further includes a capacitor dielectric layer and an upper electrode plate. The capacitor dielectric layer covers the upper surface, lower surface and side surface of the capacitor electrode plate (806), and the two second support structures (812) spaced apart in the first horizontal orientation are separated by the capacitor dielectric layer; the upper electrode plate covers the capacitor dielectric layer.

5. The semiconductor memory according to claim 1, characterized in that, The semiconductor memory further includes a substrate (101) and a mask layer (104), the substrate (101) being located at the bottom of the vertical orientation and the mask layer (104) being located at the top of the vertical orientation; the first support structure (503) extends downward from above the mask layer (104) to the substrate (101) to form a three-sided surrounding structure around the capacitor structure.

6. The semiconductor memory according to claim 1, characterized in that, The semiconductor memory further includes bit lines and a plurality of word lines, the bit lines being located at one end of the active layer (1022) away from the capacitor structure, and the bit lines being connected to the source region (707) of each of the active layers (1022); the plurality of word lines are arranged alternately with the plurality of active layers (1022) in the vertical orientation, and the word lines at least partially surround the active layer (1022).

7. The semiconductor memory according to claim 1, characterized in that, The first support structure (503) is made of silicon, oxygen, carbon and nitrogen, and the second support structure (812) is made of silicon nitride.

8. A method for manufacturing a semiconductor memory, characterized in that, Includes the following steps: A substrate (101) is provided, and a stacked structure (102) is formed on the top surface of the substrate (101), the stacked structure (102) including alternating stacked active layers (1022) and sacrificial layers (1021). Form the first support structure (503); A source region (707) and a drain region (805) are formed at both ends of the active layer (1022) along the first horizontal orientation, respectively. A capacitor structure is formed at one end of the active layer (1022) along the first horizontal orientation. The capacitor structure is connected to the drain region (805). The capacitor structure includes a plurality of capacitor plates (806) arranged at intervals in the vertical orientation. A second support structure (812) is formed between two adjacent capacitor plates (806).

9. The method for manufacturing a semiconductor memory according to claim 8, characterized in that, The steps for forming the source region (707) include: The stacked structure (102) is etched along the vertical orientation to form a first hole (301); A first transverse groove (302) is formed by etching along the first horizontal orientation within the first hole (301) to release the sacrificial layer (1021) and thin the active layer (1022). The active layer (1022) exposed by the first transverse trench (302) is doped to form the source region (707).

10. The method for manufacturing a semiconductor memory according to claim 8, characterized in that, Also includes: A mask layer (104) is formed on the top surface of the stacked structure (102). The step of forming the first support structure (503) includes: The mask layer (104) is etched along the vertical orientation to form a support structure trench (501). A second transverse groove (502) is formed by etching along the second horizontal orientation within the support structure groove (501). Deposit support material in the support structure trench (501) and the second transverse groove (502) to form the first support structure (503), such that the first support structure (503) is distributed at intervals between two adjacent active layers (1022) in the vertical orientation.

11. The method for manufacturing a semiconductor memory according to claim 10, characterized in that, The steps for forming the capacitor structure include: A first trench (801) is formed in the mask layer (104), the first trench (801) extends along the second horizontal orientation and penetrates the stacked structure (102); A second trench (802) is formed, and the sacrificial layer (1021) is laterally etched in the second trench (802) to release space, wherein the second trench (802) includes a first sub-groove extending along the first horizontal orientation and a second sub-groove extending along the second horizontal orientation; Conductive material is deposited within the space to form a plurality of capacitor plates (806) spaced apart along the vertical orientation.

12. The method for manufacturing a semiconductor memory according to claim 11, characterized in that, The step of forming the second support structure (812) includes: A sacrificial material layer is filled between two adjacent capacitor plates (806); The sacrificial material layer is etched back to form a transverse groove, and a portion of the sacrificial material layer remains to form the second support structure (812).

13. The method for manufacturing a semiconductor memory according to claim 12, characterized in that, The step of forming the capacitor structure further includes: A capacitor dielectric layer is deposited in the transverse groove, and the capacitor dielectric layer covers the upper surface, lower surface and sidewall of the capacitor plate (806); The upper electrode is deposited on the capacitor dielectric layer; A conductive filler layer (811) is deposited in the area enclosed by the upper electrode plate.

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