Semiconductor device and method of manufacturing the same

Abstract

According to the embodiments of the present application, a semiconductor device and a manufacturing method thereof are disclosed. When forming the bottom structure, an etching stop layer is formed before forming the two-dimensional electron gas in the barrier layer and the channel layer in the bottom structure; when etching the bottom structure to form the opening area of the drain and the source, the end point detection technology is used to determine the etching end point, and the etching of the bottom structure is stopped at the etching stop layer, so as to improve the uniformity of the ohmic contact of the drain and the source, improve the yield of the device and the reliability of the device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically, to a semiconductor device and a method for manufacturing the same. Background Technology

[0002] In existing GaN-based HEMT (High Electron Mobility Transistor) fabrication processes, to form ohmic contacts with low contact resistance, the barrier layers in the source and drain regions are often etched before metal deposition. However, this method has significant drawbacks. First, due to etching errors, the etching depth varies considerably between different grooves on the same wafer, resulting in poor uniformity of contact resistance between the source and drain, thus affecting product yield. Second, excessive etching depth can lead to device reliability issues and failure. Summary of the Invention

[0003] In view of this, the present invention proposes to add an etch stop layer as a groove etching layer below the 2DEG in the epitaxial structure to improve the uniformity of the ohmic contact between the drain and the source, thereby improving the device yield and device reliability.

[0004] In a first aspect, embodiments of the present invention provide a method for manufacturing a semiconductor device, the method comprising:

[0005] A substrate layer is formed, and a channel layer is formed on the substrate layer; an etch stop layer is formed before the channel layer is formed; a barrier layer is formed on the channel layer, and a two-dimensional electron gas is formed at the interface between the channel layer and the barrier layer; opening regions of the drain and source are formed; the opening regions of the drain and source penetrate the barrier layer and the channel layer, and stop at the upper surface of the etch stop layer; metal is deposited in the opening regions of the drain and source to form a drain structure and a source structure, respectively.

[0006] Preferably, the etch stop layer comprises a III-V group semiconductor.

[0007] Preferably, the etch stop layer comprises one of InGaN, AllnGaN, AlN, AllnN, and AlGaN.

[0008] Preferably, when the etch stop layer is AlGaN, the Al content in the etch stop layer is less than the Al content in the barrier layer.

[0009] Preferably, when the etching stop layer is AlGaN, the Al content is 0.001~0.01.

[0010] Preferably, the thickness of the etching stop layer is less than the thickness of the barrier layer.

[0011] Preferably, the thickness of the etching stop layer is 1 nm to 5 nm.

[0012] Preferably, when forming the opening regions of the drain and source electrodes through etching, different elements in the etching stop layer and the channel layer are monitored, and the etching endpoint is determined by endpoint detection technology.

[0013] Preferably, when the etching stop layer includes Al elements, when the opening regions of the drain and source are formed by etching, the endpoint detection technology is used to collect Al characteristic signals to determine the etching endpoint.

[0014] Preferably, the manufacturing method further includes: forming a buffer layer between the substrate layer and the channel layer; and forming a gate structure on the barrier layer.

[0015] Preferably, the buffer layer includes a first buffer medium layer and a second buffer medium layer located on top of the first buffer medium layer.

[0016] Preferably, the first buffer medium layer is an AlGaN layer, and the second buffer medium layer is GaN.

[0017] Preferably, the buffer layer further includes a third buffer layer located between the first buffer layer and the second buffer layer.

[0018] Preferably, the third buffer medium layer is C-doped GaN.

[0019] Preferably, the thickness of the channel layer is 3nm to 30nm.

[0020] Secondly, embodiments of the present invention also provide a semiconductor device, characterized in that it comprises: a channel layer; a barrier layer located on the channel layer, wherein a two-dimensional electron gas is formed at the interface between the barrier layer and the channel layer; an etch stop layer located below the channel layer; and source and drain structures penetrating the barrier layer and the channel layer, wherein the lower surfaces of the source and drain structures are in contact with the etch stop layer.

[0021] Preferably, the etch stop layer comprises a III-V group semiconductor.

[0022] Preferably, in the etching stop layer, the content of the element that is different from that in the adjacent underlying structural material is less than 0.01.

[0023] Preferably, the etch stop layer comprises one of InGaN, AllnGaN, AlN, AllnN, and AlGaN.

[0024] Preferably, when the etch stop layer is AlGaN, the Al content in the etch stop layer is less than the Al content in the barrier layer.

[0025] Preferably, when the etch stop layer is AlGaN, the Al content in the etch stop layer is 0.001~0.01.

[0026] Preferably, the thickness of the etching stop layer is less than the thickness of the barrier layer.

[0027] Preferably, the thickness of the etching stop layer is 1 nm to 5 nm.

[0028] Preferably, the semiconductor device further includes: a substrate layer; a buffer layer located between the substrate layer and the channel layer; wherein the buffer layer includes a first buffer dielectric layer and a second buffer dielectric layer located above the first buffer dielectric layer; and a gate structure located on the barrier layer.

[0029] Preferably, the first buffer medium layer is an AlGaN layer, and the second buffer medium layer is near-intrinsic or intrinsic GaN.

[0030] Preferably, the semiconductor device further includes a third buffer dielectric layer located between the first buffer dielectric layer and the second buffer dielectric layer.

[0031] Preferably, the third buffer medium layer is C-doped GaN.

[0032] Preferably, the distance between the upper surface of the etch stop layer and the lower surface of the barrier layer is greater than 3 nm.

[0033] Preferably, the thickness of the channel layer is 3nm~30nm.

[0034] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0035] In this invention, during the formation of the underlying structure of a semiconductor device, an etch stop layer is formed before the two-dimensional electron gas formed in the barrier layer and channel layer of the underlying structure. During the etching of the underlying structure to form the opening regions of the drain and source electrodes, different elements in the etch stop layer and the channel layer are monitored, and an endpoint detection technique is used to determine the etching endpoint. This replaces the prior art's method of solely relying on etch selectivity combined with timed etch control, stopping the etching of the underlying structure at the etch stop layer. This improves the uniformity of the ohmic contact between the drain and source electrodes, thereby increasing device yield and reliability. Simultaneously, the distance between the etch stop layer and the two-dimensional electron gas can be adjusted by adjusting the thickness of the channel layer, and the influence of the etch stop layer on the two-dimensional electron gas can be reduced by adjusting the thickness and content of the etch stop layer. Attached Figure Description

[0036] The above and other objects, features and advantages of the present invention will become clearer from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0037] Figure 1 This is a cross-sectional view of a semiconductor device according to an embodiment of this application;

[0038] Figure 2 This is a flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of this application;

[0039] Figures 3 to 9 These are cross-sectional views of each stage of the semiconductor device manufacturing method of this application; Detailed Implementation

[0040] The present invention is described below based on embodiments, but the invention is not limited to these embodiments. In the detailed description of the invention below, certain specific details are described in detail. Those skilled in the art will fully understand the invention even without these details. To avoid obscuring the essence of the invention, well-known methods, processes, flows, elements, and circuits are not described in detail.

[0041] Furthermore, those skilled in the art should understand that the accompanying drawings provided herein are for illustrative purposes only and are not necessarily drawn to scale.

[0042] The present application is described below based on embodiments, but it is not limited to these embodiments. In the detailed description of the present application below, certain specific details are described in detail. Those skilled in the art can fully understand the present application without these details. To avoid obscuring the substance of the present application, well-known methods, processes, flows, elements, and circuits are not described in detail.

[0043] Those skilled in the art will understand that the accompanying drawings provided herein are for illustrative purposes and are not necessarily drawn to scale.

[0044] Unless the context explicitly requires it, words such as "including" or "contains" throughout the application should be interpreted as including rather than exclusive or exhaustive; that is, meaning "including but not limited to".

[0045] In the description of this application, it should be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, in the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0046] In the semiconductor field (especially for GaN HEMT devices), "near intrinsic" refers to the channel layer or buffer layer having an extremely low doping content (typically ≤10¹). 5 ~10¹ 6 In the 2DEG state (cm⁻³), the conductivity is mainly dominated by thermally excited carriers, approaching that of a pure, undoped intrinsic semiconductor. This design aims to generate a 2DEG using the polarization effect while minimizing impurity scattering, ensuring high electron mobility, and maintaining high resistivity in the channel region to suppress leakage. During the trench etching process, once the etching reaches this near-intrinsic layer, a non-ohmic contact will form due to the high-resistivity interface, directly leading to device performance degradation or failure.

[0047] In this application specification and claims, unless otherwise expressly stated, the terms "Al content," "Al composition," or "Al mole fraction," when used to describe a Group III-V nitride (III-V nitride) layer (e.g., AlGaN), are defined as the ratio of the number of Al atoms to the total number of Group III atoms (e.g., Al+Ga), i.e., Al / (Al+Ga). This value can be determined by measurement using reciprocal space mapping (RSM) in X-ray photoelectron spectroscopy (XPS), X-ray energy-dispersive spectroscopy (EDS), or X-ray diffraction (XRD). For simplicity, this application sometimes also uses Al. x Ga 1-x The form N is used to represent the Al content, where x is the Al content and satisfies 0 ≤ x < 1.

[0048] This application provides a semiconductor device with an etch stop layer. Exemplarily, the semiconductor device is a power transistor, such as a GaN HEMT (high electron mobility transistor).

[0049] Figure 1 This is a cross-sectional view of a semiconductor device according to an embodiment of this application. The semiconductor device includes: a bottom layer structure, a source structure, a drain structure, and a gate structure.

[0050] The underlying structure includes a substrate layer 100, a buffer layer 110, an etch stop layer 120, a channel layer 130, and a barrier layer 140. The substrate layer 100 is, for example, a silicon substrate, a silicon carbide substrate, a gallium nitride substrate, or a sapphire substrate. The channel layer 130 comprises a group III-V nitride, such as a gallium nitride (GaN) layer. The barrier layer 140 comprises a group III-V nitride, such as an AlGaN layer, an InGaN layer, or a combination of AlN and AlGaN layers, wherein the AlN layer is located between the AlGaN layer and the channel layer. The bandgap of the barrier layer 140 is larger than that of the channel layer 130 to form a heterojunction between them. A high content of two-dimensional electron gas (2DEG) is induced at the interface between the two layers through a polarization effect. The 2DEG serves as the conductive channel for the semiconductor device. The content of the 2DEG can be controlled by adjusting the gate voltage, thereby changing the conductivity. As an example, the thickness of the channel layer 130 is greater than the thickness of the barrier layer 140. The substrate layer 100 and the etch stop layer 120 have different lattice constants, and the buffer layer 110 serves as a transition layer between the substrate layer 100 and the etch stop layer 120.

[0051] The etch stop layer 120 comprises a III-V group semiconductor other than GaN. As an example, the etch stop layer 120 may include any one of InGaN, AllnGaN, AlN, AllnN, and AlGaN, but is not limited thereto. To avoid affecting the formation of the two-dimensional electron gas, in this embodiment, the thickness of the etch stop layer 120 is less than the thickness of the barrier layer 140. As an example, the thickness of the etch stop layer 120 is set to 1 nm to 5 nm.

[0052] The closer the material ratio of the etch stop layer 120 to its adjacent underlying structure, the lower the manufacturing difficulty. Therefore, the lower the proportion of elemental components in the etch stop layer 120 that differ from those in its adjacent underlying structure, the better. For example, in the etch stop layer, the content of elements that differ from those in the adjacent underlying structure material is set to be less than 0.01. For instance, when the etch stop layer 120 is AlGaN and its underlying material is GaN, the Al content in the etch stop layer 120 is less than the Al content in the barrier layer. Specifically, the Al content in the etch stop layer 120 can be set to 0.001~0.01.

[0053] It should be noted that the thickness of the barrier layer 140 is generally set to be greater than 10 nm, and the Al content in the barrier layer is generally greater than 0.1%. In this embodiment, in order to distinguish the etch stop layer 120 from the barrier layer 140 without affecting the formation of the two-dimensional electron gas, the thickness of the etch stop layer 120 is set to be less than the thickness of the barrier layer 140, and the Al content in the etch stop layer 120 is set to be less than the Al content in the barrier layer. In this embodiment, as an example, the Al content is set to 0.001~0.01, and the thickness of the etch stop layer is set to 1 nm~5 nm, but this should not be a limitation. Any thickness and / or content of the etch stop layer 120 that can reduce the impact on the two-dimensional electron gas is within the protection scope of this application.

[0054] In this embodiment, the influence of the etch stop layer 130 on the two-dimensional electron gas is adjusted by changing the spacing between the upper surface of the etch stop layer 120 and the lower surface of the barrier layer 140. For example, the spacing between the upper surface of the etch stop layer 120 and the lower surface of the barrier layer 140 is greater than 3 nm. Specifically, in this embodiment, the channel layer 130 is located between the etch stop layer 120 and the barrier layer 140, so the distance between the etch stop layer 120 and the two-dimensional electron gas can be adjusted by changing the thickness of the channel layer 130, thereby reducing the influence of the etch stop layer 120 on the two-dimensional electron gas. For example, the thickness of the channel layer 130 can be set to 3 nm to 30 nm.

[0055] As an example, buffer layer 110 may include a first buffer dielectric layer and a second buffer dielectric layer located on top of the first buffer dielectric layer. As an example, the first buffer dielectric layer is an AlGaN layer, and the second buffer dielectric layer is near-intrinsic or intrinsic GaN.

[0056] As an example, the buffer layer may further include a third buffer layer located between the first buffer layer and the second buffer layer. As an example, the third buffer layer is C-doped GaN.

[0057] It should be noted that the composition and number of layers of the buffer layer described above are only for illustrative purposes. Any composition and number of layers that can serve as a buffer layer between the substrate layer 100 and the etch stop layer 120 are acceptable.

[0058] like Figure 1 As shown, the semiconductor device further includes a first dielectric layer 161, which is located on the upper surface of the underlying structure. Specifically, the first dielectric layer 161 is located on the barrier layer 140. The first dielectric layer 161 covers the gate structure 150 and the barrier layer 140. The material of the first dielectric layer 161 is, for example, SiO2, Si3N4, SiON, Al2O3, etc.

[0059] like Figure 1 As shown, as an example, the semiconductor device further includes a second dielectric layer 154. The second dielectric layer 154 covers the first dielectric layer 161 and a gate structure located above the barrier layer, wherein the gate structure is located between the source and drain structures.

[0060] like Figure 1 As shown, the source structure 1543 and the drain structure 1544 penetrate the second dielectric layer 154, the first dielectric layer 161, the barrier layer 140 and the channel layer 130, and stop at the etch stop layer 120, so that the lower surface of the source structure 1541 and the drain structure 1542 contacts the upper surface of the etch stop layer 120.

[0061] In other examples, the first dielectric layer 161 may be omitted, thereby forming a second dielectric layer 154 that covers the gate structure 150 and the barrier layer 140 directly above the barrier layer 140.

[0062] like Figure 1 As shown, the semiconductor device further includes a third dielectric layer 155 and metal interconnect layers 111-113. The third dielectric layer 155 is located on the second dielectric layer 154, and the metal interconnect layers 111-113 are located on the third dielectric layer 155. Interconnect via structures 171-173 penetrate the third dielectric layer 155. The metal interconnect layer 113 and the gate structure 150 are electrically connected through the interconnect via structure 173. The metal interconnect layer 112 and the source structure 1544 are electrically connected through the interconnect via structure 172, and the metal interconnect layer 111 and the drain structure 1541 are electrically connected through the interconnect via structure 171. The interconnect via structures 171-173 are metal structures filled in the corresponding interconnect vias, and the metal structures can be, for example, metals such as tungsten, aluminum, or copper.

[0063] like Figure 1 As shown, the gate structure 150 includes a P-type gate 151 and a gate metal 152. A gate material layer is formed above the barrier layer, and a gate metal layer is formed above the gate material layer. The gate metal layer can be formed, for example, by sputtering deposition. The material of the gate metal layer is, for example, TiN, Ti, AlCu, TaN, etc. The gate material layer and the gate metal layer are patterned to form the P-type gate 151 and the gate metal 152, respectively.

[0064] The semiconductor device of this application has an etch stop layer 120 structure located below a two-dimensional electron gas, which is significantly different from conventional semiconductor devices. During the formation of the drain structure 1543 and the source structure 1544, the opening regions of the drain and source formed by etching automatically stop on the upper surface of the etch stop layer 120, ensuring that the openings of the source and drain have approximately the same depth. This improves the uniformity of the ohmic contact between the drain and source, thereby improving the device yield and reliability. Furthermore, the distance between the etch stop layer and the two-dimensional electron gas is adjusted by adjusting the thickness of the channel layer 130. Simultaneously, the influence of the etch stop layer 120 on the two-dimensional electron gas is reduced by adjusting the thickness and content of the etch stop layer 120.

[0065] This application also provides a method for manufacturing a semiconductor device. This method can be used to manufacture the semiconductor devices described in the above embodiments. Figure 2 The manufacturing method includes:

[0066] S1: Forming the underlying structure; wherein, during the formation of the underlying structure, an etch stop layer is formed before the two-dimensional electron gas formed in the barrier layer and the channel layer in the underlying structure;

[0067] Specifically, forming the underlying structure includes: forming a substrate; forming a channel layer on the substrate; forming an etch stop layer before forming the channel layer; forming a barrier layer on the channel layer; wherein a two-dimensional electron gas is formed at the interface between the channel layer and the barrier layer.

[0068] S2: Forming opening regions for the drain and source; wherein, the underlying structure is etched, the opening regions for the drain and source penetrate the barrier layer and the channel layer, and the etching of the underlying structure stops at the upper surface of the etch stop layer.

[0069] S3: Deposit metal in the opening regions of the drain and source to form the drain structure and source structure, respectively.

[0070] Specifically, the following are examples: Figure 1 Taking the semiconductor device shown as an example, the manufacturing process steps of the semiconductor device will be explained in detail.

[0071] like Figure 3 As shown, a bottom layer structure is formed. During the formation of the bottom layer structure, an etch stop layer is formed before the two-dimensional electron gas formed in the barrier layer and channel layer of the bottom layer structure. Specifically, the formation of the bottom layer structure includes the following steps: forming a substrate layer 100; epitaxially forming a buffer layer 110 on the substrate layer 100; epitaxially forming an etch stop layer 120 on the buffer layer 110; epitaxially forming a channel layer 130 on the etch stop layer 120; and epitaxially forming a barrier layer 140 on the channel layer 130.

[0072] The substrate layer 100 may include a Si substrate, a SiC substrate, a GaN substrate, sapphire, etc. The buffer layer 110 epitaxially formed on the substrate layer 100 may include a first buffer dielectric layer above the substrate layer 100 and a second buffer dielectric layer above the first buffer dielectric layer. As an example, the first buffer dielectric layer is an AlGaN layer, and the second buffer dielectric layer is a GaN layer. As another example, the buffer layer may further include a third buffer dielectric layer located between the first and second buffer dielectric layers, wherein the third buffer dielectric layer is C-doped GaN. There are no restrictions on the number of buffer layers or their material; any number and composition of buffer layers capable of achieving buffering are acceptable.

[0073] The etch stop layer 120 comprises a III-V group semiconductor. For example, the etch stop layer 120 comprises any one of InGaN, AllnGaN, AlN, AllnN, and AlGaN. When the etch stop layer 120 is AlGaN, the Al content in the etch stop layer 120 is less than the Al content in the barrier layer 140. As an example, when the etch stop layer 120 is AlGaN, the Al content is 0.001~0.01.

[0074] The channel layer 130 includes a group III-V nitride, such as a GaN layer, and the barrier layer 140 includes a group III-V nitride, such as an AlGaN layer, an InGaN layer, or a combination of an AlN layer and an AlGaN layer, wherein the AlN layer is located between the AlGaN layer and the channel layer.

[0075] In this example, the thickness of the etch stop layer 120 is less than the thickness of the barrier layer 140. As an example, the thickness of the etch stop layer 120 is 1 nm to 5 nm, and the thickness of the barrier layer 140 is greater than 10 nm.

[0076] As an example, the thickness of the channel layer is 3~30nm. The greater the thickness of the channel layer, the larger the spacing between the etch stop layer 120 and the two-dimensional electron gas, thus reducing the influence of the etch stop layer 120 on the two-dimensional electron gas. Therefore, the influence of the etch stop layer on the two-dimensional electron gas can be adjusted by regulating the thickness of the channel layer 130.

[0077] like Figure 4 As shown, a gate structure 150 is formed on the underlying structure.

[0078] As an example, the gate structure 150 includes a P-type gate 151 and a gate metal 152. A P-type gate material layer is epitaxially formed on the barrier layer 140, and the gate metal layer is deposited, for example, by sputtering. The P-type gate material layer can be a Mg-doped GaN layer or an AlGaN layer. The gate metal layer is formed on the P-type gate material layer. The P-type gate material layer and the gate metal layer are patterned to form the P-type gate 151 and the gate metal 152, respectively, resulting in a cross-sectional view of the device as shown. Figure 4 As shown. The material of the gate metal 142 is, for example, TiN, Ti, AlCu, TaN, etc.

[0079] like Figure 5 As shown, a first dielectric layer 161 is formed on the barrier layer 140 and the gate structure 150, wherein the first dielectric layer 161 serves as a passivation layer on the epitaxial layer.

[0080] like Figure 6 As shown, the underlying structure is etched to form opening regions for the drain and source electrodes; wherein, when forming the opening regions for the drain and source electrodes, the etching of the underlying structure stops at the upper surface of the etch stop layer.

[0081] Specifically, a second dielectric layer 154 is formed on top of the first dielectric layer 161. The second dielectric layer 154 covers the first dielectric layer 161. Preferably, the upper surface of the second dielectric layer 154 is planarized.

[0082] As an example, photoresist serves as the etching mask for the second dielectric layer 154, covering the area except for the drain and source openings. The underlying structure is then etched, stopping at an etch stop layer. Dry etching is used to form the drain opening 1541 and the source opening 1542, which penetrate the second dielectric layer 154, the first dielectric layer 161, the barrier layer 140, and the channel layer 130. The bottoms of the drain opening 1541 and the source opening 1542 are located on the upper surface of the etch stop layer 120.

[0083] Specifically, when forming the drain opening 1541 and source opening 1542 through etching, an endpoint detection technique is used to determine the etching endpoint. Specifically, the endpoint detection technique can be used to collect characteristic signals of elements in the etch stop layer that differ from those in the channel layer to determine the etching endpoint. For example, when the etch stop layer includes Al elements, when forming the opening regions of the drain and source through etching, the endpoint detection technique is used to collect Al characteristic signals to determine the etching endpoint.

[0084] Specifically, endpoint detection technology is an in-situ real-time monitoring technology for dry plasma etching. By collecting optical, electrical, and radio frequency signals, it accurately determines the moment when the upper film is completely etched through and reaches the lower interface, automatically stopping the etching process to avoid under-etching or over-etching. This prevents device failure caused by residual film due to under-etching, or damage to the lower layer, 2DEG degradation, leakage current, and decreased breakdown voltage due to over-etching. As an example, endpoint detection technology can employ OES optical emission spectroscopy. In the plasma, the etching products are excited by radio frequency, and different elements / groups have fixed characteristic emission wavelengths. The peak intensity of the corresponding product is stable during the etching of the upper material. Once the lower layer is reached, the original product peak drops sharply, while the characteristic peak of the lower element rises sharply. The software recognizes this abrupt change and triggers endpoint shutdown. Other examples include using LI laser interferometry, RF impedance / radio frequency signals, and white light interference spectroscopy.

[0085] This invention employs Etching End Point Detection (EPD) to replace the previous technology's reliance solely on etching selectivity combined with timed etching control. It can automatically adapt to wafer material thickness deviations and chamber etching rate drift, eliminating the need for long-term over-etching and effectively reducing etching damage to lower functional layers. Furthermore, this detection method is not limited by chip pattern density, achieving precise etching depth control even for low-density patterns such as small openings. It does not require stringent high etching selectivity process conditions, broadening the process adaptability window, effectively improving inter-wafer and inter-batch process consistency, reducing wafer scrap caused by process deviations, and enhancing device production yield and performance uniformity.

[0086] like Figure 7 As shown, metal deposition is performed on the source and drain electrodes, and metal is filled into the drain opening 1541 and the source opening 1542 to form the drain structure 1543 and the source structure 1544, respectively.

[0087] like Figure 8 As shown, a third dielectric layer 155 is formed above the second dielectric layer 154, and interconnect openings 191-193 are formed in the third dielectric layer 155. The third dielectric layer 155 is an interlayer dielectric layer (ILD).

[0088] like Figure 9 As shown, interconnect vias 191-193 are filled with metal to form interconnect via structures 171-173. Interconnect via structure 171 connects to drain structure 1543, interconnect via structure 172 connects to source structure 1544, and interconnect via structure 173 connects to gate metal 152. Metal interconnect layers 111-113 are formed on the third dielectric layer 155. Metal interconnect layers 111 and interconnect via structure 171 are connected, metal interconnect layers 112 and interconnect via structure 172 are connected, and metal interconnect layers 113 and interconnect via structure 173 are connected.

[0089] In summary, this invention discloses a semiconductor device and its manufacturing method. During the formation of the underlying structure of the semiconductor device, an etch stop layer is formed before the two-dimensional electron gas formed by the barrier layer and channel layer in the underlying structure. When etching the underlying structure to form the opening regions of the drain and source, the etching endpoint is determined by monitoring different elements in the etch stop layer and the channel layer, using endpoint detection technology. This replaces the prior art's method of simply relying on etch selectivity combined with timed etch control, stopping the etching of the underlying structure at the etch stop layer. This improves the uniformity of the ohmic contact between the drain and source, thereby increasing the device yield and reliability. Furthermore, the distance between the etch stop layer and the two-dimensional electron gas can be adjusted by adjusting the thickness of the channel layer, and the influence of the etch stop layer on the two-dimensional electron gas can be reduced by adjusting the thickness and content of the etch stop layer.

[0090] As used herein, the specific content or thickness values ​​mentioned above may contain some errors. The terms "approximately," "generally," "roughly," and "about" are used to describe and explain small variations. When used in conjunction with an event or situation, the terms may refer to examples where the event or situation occurred precisely or very approximately. For example, when used in conjunction with a numerical value, the terms may refer to a range of variation less than or equal to ±10% of the value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if the difference between two values ​​is less than or equal to ±10% of the average of the values ​​(e.g., less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%), then the two values ​​can be considered "substantially" or "approximately" the same.

[0091] The above embodiments use an enhancement-mode transistor as an example, but are not limited to this; a depletion-mode transistor can also be used. Furthermore, the above embodiments describe both the drain and source structures, but can also be applied only to the drain structure or only to the source structure depending on the actual application requirements.

[0092] Although the embodiments or implementations are described and explained separately above, some common technologies are involved. Those skilled in the art can replace and integrate them among the embodiments or implementations. If any content is not explicitly described in one embodiment or implementation, reference can be made to another embodiment that is described.

[0093] As described above, these embodiments of the present invention do not exhaustively cover all details, nor do they limit the invention to the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, include: Forming a substrate layer, A channel layer is formed on the substrate layer; An etch stop layer is formed before the trench layer is formed; A barrier layer is formed on the channel layer, and a two-dimensional electron gas is formed at the interface between the channel layer and the barrier layer; This forms the opening regions for the drain and source electrodes; The opening regions of the drain and source electrodes penetrate the barrier layer and the channel layer, and stop at the upper surface of the etch stop layer; Metal is deposited in the opening regions of the drain and source electrodes to form drain and source structures, respectively.

2. The semiconductor device manufacturing method according to claim 1, characterized in that: The etch stop layer comprises a III-V semiconductor.

3. The semiconductor device manufacturing method according to claim 1, characterized in that: The etch stop layer includes one of InGaN, AllnGaN, AlN, AllnN, and AlGaN.

4. The semiconductor device manufacturing method according to claim 2, characterized in that: When the etch stop layer is AlGaN, the Al content in the etch stop layer is less than the Al content in the barrier layer.

5. The semiconductor device manufacturing method according to claim 2, characterized in that: When the etching stop layer is AlGaN, the Al content is 0.001~0.

01.

6. The semiconductor device manufacturing method according to claim 2, characterized in that: The thickness of the etch stop layer is less than the thickness of the barrier layer.

7. The semiconductor device manufacturing method according to claim 1, characterized in that: The thickness of the etching stop layer is 1 nm to 5 nm.

8. The semiconductor device manufacturing method according to claim 1, characterized in that: By etching to form opening regions for the drain and source, different elements in the etching stop layer and channel layer are monitored, and the etching endpoint is determined using endpoint detection technology.

9. The semiconductor device manufacturing method according to claim 2, characterized in that: When the etching stop layer includes Al elements, when the opening regions of the drain and source are formed by etching, the endpoint detection technology is used to collect Al characteristic signals to determine the etching endpoint.

10. The semiconductor device manufacturing method according to claim 1, characterized in that, The manufacturing method further includes: A buffer layer is formed between the substrate layer and the channel layer; A gate structure is formed on the barrier layer.

11. The semiconductor device manufacturing method according to claim 10, characterized in that: The buffer layer includes a first buffer medium layer and a second buffer medium layer located on top of the first buffer medium layer.

12. The semiconductor device manufacturing method according to claim 11, characterized in that: The first buffer medium layer is AlGaN, and the second buffer medium layer is GaN.

13. The semiconductor device manufacturing method according to claim 11, characterized in that: The buffer layer further includes a third buffer layer located between the first buffer layer and the second buffer layer.

14. The semiconductor device manufacturing method according to claim 13, characterized in that: The third buffer medium layer is C-doped GaN.

15. The semiconductor device manufacturing method according to claim 1, characterized in that: The thickness of the channel layer is 3nm to 30nm.

16. A semiconductor device, characterized in that, include: Channel layer; A barrier layer is located on the channel layer, and a two-dimensional electron gas is formed at the interface between the barrier layer and the channel layer. An etch stop layer is located below the channel layer; The source and drain structures extend through the barrier layer and the channel layer, wherein the lower surfaces of the source and drain structures are in contact with the etch stop layer.

17. The semiconductor device according to claim 16, characterized in that: The etch stop layer comprises a III-V semiconductor.

18. The semiconductor device according to claim 16, characterized in that: In the etching stop layer, the content of the element that is different from that in the adjacent underlying structural material is less than 0.

01.

19. The semiconductor device according to claim 16, characterized in that: The etch stop layer includes one of InGaN, AllnGaN, AlN, AllnN, and AlGaN.

20. The semiconductor device according to claim 19, characterized in that: When the etch stop layer is AlGaN, the Al content in the etch stop layer is less than the Al content in the barrier layer.

21. The semiconductor device according to claim 19, characterized in that: When the etching stop layer is AlGaN, the Al content in the etching stop layer is 0.001~0.

01.

22. The semiconductor device according to claim 16, characterized in that: The thickness of the etch stop layer is less than the thickness of the barrier layer.

23. The semiconductor device according to claim 16, characterized in that: The thickness of the etching stop layer is 1 nm to 5 nm.

24. The semiconductor device according to claim 16, characterized in that, The semiconductor device further includes: Substrate layer; A buffer layer located between a substrate layer and a channel layer; wherein the buffer layer includes a first buffer dielectric layer and a second buffer dielectric layer located above the first buffer dielectric layer; and A gate structure located on the barrier layer.

25. The semiconductor device according to claim 24, characterized in that: The first buffer medium layer is an AlGaN layer, and the second buffer medium layer is near-intrinsic or intrinsic GaN.

26. The semiconductor device according to claim 24, characterized in that: Also includes: The buffer layer further includes a third buffer layer located between the first buffer layer and the second buffer layer.

27. The semiconductor device according to claim 26, characterized in that: The third buffer medium layer is C-doped GaN.

28. The semiconductor device according to claim 16, characterized in that: The distance between the upper surface of the etch stop layer and the lower surface of the barrier layer is greater than 3 nm.

29. The semiconductor device according to claim 16, characterized in that: The thickness of the channel layer is 3nm to 30nm.

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