Planar siC jfet based on channel ion implantation and method for manufacturing the same

Abstract

The application discloses a planar SiC JFET based on channel ion implantation and a preparation method thereof, and comprises a substrate layer and an N-drift layer located above the substrate layer; two P-type gate regions are symmetrically distributed on both sides of the N-drift layer; each P-type gate region comprises a deep P-type well region and a surface P+ gate region located above the deep P-type well region; an N+ source region is located on the surface of the N-drift layer between the two P-type gate regions; gate ohmic contact metal is located on the upper surface of part of the P-type gate region; source ohmic contact metal is located on the upper surface of part of the N+ source region; an oxide layer is located on the upper surfaces of the P-type gate region, the N+ source region, the gate and the source ohmic contact metal; the source is connected through a source contact hole and the source ohmic contact metal; the gate is connected through a gate contact hole and the gate ohmic contact metal; a drain and drain ohmic contact metal are sequentially stacked below the substrate layer, so that the planar SiC JFET has the advantages of simple structure, no need for trench etching and high channel symmetry.

Description

Technical Field

[0001] This invention belongs to the field of microelectronics technology, specifically relating to a planar SiC (silicon carbide) JFET (Junction Field-Effect Transistor) based on channel ion implantation and its fabrication method. Background Technology

[0002] As power electronics technology advances towards higher frequencies, higher voltages, higher power densities, and higher efficiency, traditional silicon (Si)-based power devices are gradually approaching their physical limits. Wide-bandgap semiconductor materials, represented by silicon carbide (SiC), have become key materials for fabricating next-generation high-performance power devices due to their high breakdown electric field, high thermal conductivity, high saturated electron drift velocity, and excellent chemical stability. Among SiC power devices, junction field-effect transistors (JFETs), with their PN junction gates, do not suffer from the reliability defects of the gate oxide layer found in MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), giving them significant advantages in extreme application environments such as high temperature, high reliability, and high radiation resistance.

[0003] Currently, traditional vertical-channel SiC JFETs mostly employ a vertical trench structure. In this structure, a high aspect ratio trench is typically formed on the SiC epitaxial layer using a dry etching process, and a P-type gate region is formed by doping the trench sidewalls using tilted ion implantation technology. The area left in the middle serves as the vertical conductive channel. However, this structure faces many severe challenges in actual fabrication processes.

[0004] First, etching trenches with high aspect ratios, smooth vertical sidewalls, and flat, low-damage bottoms is extremely difficult. SiC materials are chemically very stable, and plasma etching can easily introduce defects such as lattice damage, micro-trenches, fan-shaped edges, or tilting into the sidewalls, leading to increased leakage current and impaired mobility in the device.

[0005] Secondly, achieving uniform, steep, and precisely controllable depth and concentration P-type ion implantation on the sidewalls of trenches with high aspect ratios is extremely difficult. Tilted ion implantation requires extremely high precision in equipment angle control. Shadowing effects and anisotropy during implantation can lead to inconsistent channel widths, severely impacting device consistency, yield, and threshold voltage stability. The implantation angle, energy, dose, and mask alignment accuracy are all critical, resulting in a highly complex and costly process.

[0006] Therefore, how to provide a planar SiC JFET with a simple structure, no need for trench etching, and high channel symmetry has become an important issue. Summary of the Invention

[0007] To address the aforementioned problems in the prior art, this invention provides a planar SiC JFET based on channel ion implantation and its fabrication method.

[0008] The technical problem to be solved by this invention is achieved through the following technical solution: In a first aspect, the present invention provides a planar SiC JFET based on channel ion implantation, the planar SiC JFET comprising: A substrate layer, and an N-drift layer located on the substrate layer; Two P-type gate regions are symmetrically distributed on both sides of the interior of the N-drift layer; each P-type gate region includes a deep P-type well region and a surface P+ gate region located above the deep P-type well region. The N+ source region is located on the surface of the N-drift layer between the two P-type gate regions; The gate ohmic contact metal is located on the upper surface of a portion of the P-type gate region; The source ohmic contact metal is located on the upper surface of a portion of the N+ source region; An oxide layer is located on the upper surface of the P-type gate region, the N+ source region, the gate ohmic contact metal, and the source ohmic contact metal; the oxide layer has source contact holes and gate contact holes. The source electrode is connected to the source electrode ohmic contact metal via the source electrode contact hole; The gate is connected to the gate ohmic contact metal via the gate contact hole; A drain ohmic contact metal is superimposed beneath the substrate layer; The drain electrode is superimposed on the drain ohmic contact metal.

[0009] Secondly, the present invention provides a method for fabricating a planar SiC JFET based on channel ion implantation, the method comprising: Select a substrate layer and grow an N-drift layer on the substrate layer; On both sides of the upper surface of the N-drift layer, a deep P-well region and a surface P+ gate region located above the deep P-type well region are formed by high-energy channel ion implantation process and multi-step conventional ion implantation process to obtain a P-type gate region. An N+ source region is formed on the surface of the N- drift layer between the two P-type gate regions using an ion implantation process. An initial oxide layer is formed on the upper surface of the P-type gate region and the N+ source region by deposition and etching operations; the initial oxide layer has gate ohmic contact holes and source ohmic contact holes. Using a magnetron sputtering process, gate ohmic contact metal and source ohmic contact metal are formed in the gate ohmic contact hole and the source ohmic contact hole, located on the upper surface of a portion of the P-type gate region and a portion of the N+ source region; Using the magnetron sputtering process, a drain ohmic contact metal is formed beneath the substrate layer; Based on the initial oxide layer, an oxide layer is formed on the upper surfaces of the P-type gate region, the N+ source region, the gate ohmic contact metal, and the source ohmic contact metal through deposition and etching operations; A gate, source, and drain are formed using a magnetron sputtering process; the source is connected to the source ohmic contact metal through the source contact hole; the gate is connected to the gate ohmic contact metal through the gate contact hole; and the drain is superimposed on the drain ohmic contact metal.

[0010] This invention provides a planar SiC JFET based on channel ion implantation. Compared to traditional SiC JFETs, which have a vertical trench structure and require high aspect ratio etching and tilted ion implantation, resulting in complex processes and high precision requirements, the planar SiC JFET of this invention eliminates the need for complex trench etching processes with high aspect ratios and tilted ion implantation during actual manufacturing. It can directly form a vertically P-type gate region with high symmetry on both sides of the N-drift layer surface, achieving stable characteristics under simple processes. This significantly simplifies the process fabrication flow and reduces process complexity.

[0011] Two P-type gate regions are symmetrically distributed on both sides of the N-drift layer, with the N-type region in the middle serving as the conductive channel of the JFET. Each P-type gate region contains a layered doping configuration of a deep P-type well region and a surface P+ gate region. This spatially symmetrical distribution of P-type regions generates a highly symmetrical internal longitudinal electric field, ensuring the uniformity of channel pinch-off and depletion layer expansion on both sides under forward and reverse bias, thereby significantly improving the stability of the device threshold voltage and the consistency of the saturation current.

[0012] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0013] Figure 1 This is a cross-sectional view of a planar SiC JFET based on channel ion implantation provided in an embodiment of the present invention; Figure 2 This is a schematic flowchart of a method for fabricating a planar SiC JFET based on channel ion implantation provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of the fabrication process of a planar SiC JFET based on channel ion implantation provided in an embodiment of the present invention.

[0014] Reference numerals: 1. Substrate; 2. N-drift layer; 3. P-type gate region; 4. N+ source region; 5. Initial oxide layer; 6. Source ohmic contact metal; 7. Gate ohmic contact metal; 8. Drain ohmic contact metal; 9. Oxide layer; 10. Source; 11. Drain. Detailed Implementation

[0015] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0016] To address the issues of complex fabrication processes, poor channel symmetry, and inconsistent performance inherent in traditional SiC JFETs, this invention provides a planar SiC JFET based on channel ion implantation. (See [link to relevant documentation]). Figure 1 , Figure 1 This is a cross-sectional view of a planar SiC JFET based on channel ion implantation provided in an embodiment of the present invention. The planar SiC JFET includes a substrate layer 1, an N-drift layer 2, a P-type gate region 3, an N+ source region 4, a source ohmic contact metal 6, a gate ohmic contact metal 7, a drain ohmic contact metal 8, an oxide layer 9, a source 10, a gate, and a drain 11.

[0017] In this embodiment of the invention, substrate 1 can specifically be an N+ substrate, the material of which can be SiC, and N (nitrogen) ion implantation is used, with a doping concentration range of 1×10⁻⁶. 18 cm -3 ~1×10 20 cm -3 The thickness range can be 100μm~500μm.

[0018] Substrate 1 is used to provide mechanical support and serve as a low-resistance drain current path for the device.

[0019] The N-drift layer 2 is located above the substrate layer 1. Specifically, the N-drift layer 2 is an N-type conductive epitaxial layer, which can be made of SiC and implanted with N-ions. The doping concentration of the N-drift layer 2 can range from 1 × 10⁻⁶. 14 cm -3 ~1×10 17 cm -3 The thickness range can be 1μm to 100μm.

[0020] In this embodiment of the invention, two P-type gate regions 3 are symmetrically distributed on both sides inside the N-drift layer 2. Each P-type gate region 3 includes a deep P-type well region and a surface P+ gate region located above the deep P-type well region.

[0021] The doping concentration of the surface P+ region is higher than that of the deep P-type well region. The deep P-type well region (lightly doped) forms a PN junction with the N-drift layer 2, which is mainly responsible for bearing high voltage and expanding the depletion layer to clamp the channel. The surface P+ region (heavily doped) is mainly used to reduce contact resistance and form a good ohmic contact with the metal.

[0022] Specifically, the deep P-type well region exhibits P-type conductivity, with a doping concentration ranging from 1 × 10⁻⁶. 16 cm -3 ~1×10 20 cm -3 The depth range can be 2μm~3μm. The deep P-type well region is formed by high-energy channel ion implantation of Al (aluminum) ions and high-temperature activation annealing. The channel effect inside the SiC crystal allows the implanted Al ions to penetrate vertically along a specific crystal orientation, thereby forming a vertically extended P-type doped region inside the N-drift layer 2.

[0023] The channeling effect, also known as channeling, refers to the phenomenon in crystalline materials where, when injected ions or charged particles are incident along a direction where the atomic arrangement of the crystal is relatively sparse or regular (such as the direction of the principal crystal axis), they may have fewer collisions with the lattice atoms and thus be able to penetrate to a deeper location than expected.

[0024] The surface P+ gate region and the deep P-type well region form a continuous P-type doped structure. The surface P+ gate region is of the P+ type conductivity type (heavily doped), and its doping concentration can range from 1 × 10⁻⁶. 18 cm -3 ~1×10 20 cm -3 The depth range can be 0.1μm to 0.5μm. The surface P+ gate region is formed by conventional ion implantation of Al ions followed by high-temperature activation annealing, which is used to reduce the contact resistance between the P-type gate region 3 and the subsequently formed gate ohmic contact metal 7.

[0025] In this embodiment of the invention, the spacing between the two P-type gate regions 3 can be in the range of 0.1μm to 2.0μm. This spacing is the conductive channel width of the planar SiC JFET, which can be precisely adjusted by controlling the injection conditions and lateral diffusion length of the deep P-type well region.

[0026] In this embodiment of the invention, the N+ source region 4 is located on the surface of the N- drift layer 2 between the two P-type gate regions 3.

[0027] Specifically, N+ source region 4 is of the N+ type conductivity (heavily doped), formed by N-ion implantation, with a doping concentration ranging from 1×10⁻⁶. 18 cm -3 ~1×10 20 cm -3The depth range is 0.1μm~0.5μm.

[0028] In this embodiment of the invention, the gate ohmic contact metal 7 is located on the upper surface of a portion of the P-type gate region 3.

[0029] The gate ohmic contact metal 7 is made of a metal alloy, preferably a Ti / Ni / Al metal alloy, with a thickness ranging from 0.1 μm to 0.3 μm.

[0030] In this embodiment of the invention, the source ohmic contact metal 6 is located on the upper surface of a portion of the N+ source region 4.

[0031] The source ohmic contact metal 6 is made of a metal alloy, preferably a Ti / Ni / Al metal alloy, with a thickness ranging from 0.1 μm to 0.3 μm.

[0032] In this embodiment of the invention, oxide layer 9 is located on the upper surface of P-type gate region 3, N+ source region 4, gate ohmic contact metal 7 and source ohmic contact metal 6; oxide layer 9 has source contact holes and gate contact holes.

[0033] The oxide layer 9 can be made of SiO2 (silicon dioxide) and its thickness can range from 1μm to 3μm.

[0034] Specifically, a source contact hole penetrates the oxide layer 9 and extends to the upper surface of the source ohmic contact metal 6 above the N+ source region 4, so that the source ohmic contact metal 6 is partially exposed at the bottom of the source contact hole; a gate contact hole is formed around the active region of the device, the gate contact hole penetrates the oxide layer 9 and extends to the upper surface of the gate ohmic contact metal 7 above the P-type gate region 3, so that the gate ohmic contact metal 7 is partially exposed at the bottom of the gate contact hole.

[0035] In this embodiment of the invention, the source electrode 10 is connected to the source electrode ohmic contact metal 6 through a source electrode contact hole.

[0036] Specifically, the source electrode 10 is disposed on the upper surface of the oxide layer 9 and is electrically connected to the source ohmic contact metal 6 above the N+ source region 4 through a source contact hole. The source electrode 10 fills the interior of the source contact hole and directly contacts the upper surface of the source ohmic contact metal 6 exposed at the bottom of the source contact hole, forming a low-resistance electrical connection. The source electrode 10 extends horizontally on the upper surface of the oxide layer 9 for connection to external circuitry.

[0037] The source electrode 10 can be made of Al, and its thickness can range from 3 μm to 6 μm.

[0038] In this embodiment of the invention, the gate is connected to the gate ohmic contact metal 7 through a gate contact hole.

[0039] The gate is filled into the gate contact hole and makes direct contact with the upper surface of the gate ohmic contact metal 7 exposed at the bottom of the gate contact hole, forming a low-resistance electrical connection.

[0040] The gate material can be Al, and the thickness can range from 3μm to 6μm.

[0041] In this embodiment of the invention, the drain ohmic contact metal 8 is superimposed on the substrate layer 1. The material of the drain ohmic contact metal 8 is a metal alloy, preferably a Ti / Ni / Al metal alloy, and its thickness ranges from 0.1 μm to 0.3 μm.

[0042] In this embodiment of the invention, the drain electrode 11 is superimposed on the drain ohmic contact metal 8. The material of the drain electrode 11 can be Al, and the thickness can be in the range of 3μm to 6μm.

[0043] Compared to traditional SiC JFETs, which have a vertical trench structure and require high aspect ratio etching and tilted ion implantation, resulting in complex processes and high precision requirements, the planar SiC JFET of this invention eliminates the need for complex trench etching processes with high aspect ratios and tilted ion implantation during actual manufacturing. It can directly form a vertically p-type gate region 3 with high symmetry on both sides of the N-drift layer 2 surface, achieving stable characteristics under simple processes, significantly simplifying the process fabrication flow and reducing process complexity.

[0044] Two P-type gate regions 3 are symmetrically distributed on both sides of the N-drift layer 2, with the N-type region in the middle serving as the conductive channel of the JFET. Each P-type gate region 3 contains a layered doping configuration of a deep P-type well region and a surface P+ gate region. This spatially symmetrical distribution of P-type regions can generate a highly symmetrical internal longitudinal electric field, ensuring the uniformity of channel pinch-off and depletion layer expansion on both sides under forward and reverse bias, thereby significantly improving the stability of the device threshold voltage and the consistency of the saturation current.

[0045] Based on the same inventive concept, embodiments of the present invention also provide a method for fabricating a planar SiC JFET based on channel ion implantation, see [link to relevant documentation]. Figure 2 , Figure 2 This is a schematic flowchart of a method for fabricating a planar SiC JFET based on channel ion implantation according to an embodiment of the present invention, which specifically includes the following steps: Step S201: Select substrate layer 1 and grow N-drift layer 2 on substrate layer 1.

[0046] See Figure 3 , Figure 3 This is a schematic diagram illustrating the fabrication process of a planar SiC JFET based on channel ion implantation, as provided in an embodiment of the present invention. (See attached diagram.) Figure 3In (a), substrate 1 is first selected, which can be an N+ substrate made of SiC, using N-ion implantation. The doping concentration range of substrate 1 can be 1 × 10⁻⁶. 18 cm -3 ~1×10 20 cm -3 The thickness range can be 100μm~500μm.

[0047] An N-drift layer 2 is grown on substrate layer 1. Specifically, N-drift layer 2 is an N-type conductive epitaxial layer, which can be made of SiC and implanted with N-ions. The doping concentration of N-drift layer 2 can range from 1 × 10⁻⁶. 14 cm -3 ~1×10 17 cm -3 The thickness range can be 1μm to 100μm.

[0048] In step S202, a deep P-well region and a surface P+ gate region located above the deep P-type well region are formed on both sides of the upper surface of the N-drift layer 2 using a high-energy channel ion implantation process and a multi-step conventional ion implantation process, resulting in a P-type gate region 3.

[0049] In this embodiment of the invention, a SiO2 layer is deposited on the N-drift layer 2 as an ICP (Inductively Coupled Plasma) etching mask. Afterwards, photoresist is applied, exposed, and developed. The etched mask layer forms an ion implantation window, and the photoresist is removed. Using high-energy channel ion implantation and multi-step conventional ion implantation processes, Al ions are implanted on both sides of the upper surface of the N-drift layer 2 to form a deep P-well region and a surface P+ gate region. The mask layer is then removed, and the surface is cleaned to form a wafer. See [link to relevant documentation]. Figure 3 (b) in the middle.

[0050] The doping concentration of the surface P+ region is higher than that of the deep P-type well region.

[0051] Specifically, the deep P-type well region exhibits P-type conductivity, with a doping concentration ranging from 1 × 10⁻⁶. 16 cm -3 ~1×10 20 cm -3 The depth can range from 2μm to 3μm. The surface P+ gate region is of P+ type conductivity, and its doping concentration can range from 1×10⁻⁶. 18 cm -3 ~1×10 20 cm -3 The depth range can be 0.1μm~0.5μm.

[0052] In this embodiment of the invention, the high-energy channel ion implantation process uses Al ion implantation, with an implantation energy range of 500 keV to 1 MeV and an implantation dose range of 1 × 10⁻⁶. 14 cm -3 ~1×10 15 cm -3 .

[0053] In step S203, an N+ source region 4 is formed on the surface of the N- drift layer 2 between the two P-type gate regions 3 using an ion implantation process.

[0054] In this embodiment of the invention, a SiO2 layer is deposited on the N-drift layer 2 as an ICP etching mask. Afterwards, photoresist is applied, exposed, and developed. The photoresist is etched to form an ion implantation window, and the photoresist is removed. Using an ion implantation process, N ions are implanted downwards onto the surface of the N-drift layer 2 between two P-type gate regions 3 to form an N+ source region 4. The mask layer is then removed, and the surface is cleaned to produce a wafer. (See [link]). Figure 3 (c) A C film is magnetron sputtered on the N-drift layer 2, followed by high-temperature activation annealing, and the C film is removed and the film is cleaned to form a smooth sheet.

[0055] Specifically, N+ source region 4 is of the N+ type conductivity (heavily doped), formed by N-ion implantation, with a doping concentration ranging from 1×10⁻⁶. 18 cm -3 ~1×10 20 cm -3 The depth range is 0.1μm~0.5μm.

[0056] In step S204, an initial oxide layer 5 is formed on the upper surface of the P-type gate region 3 and the N+ source region 4 through deposition and etching operations; the initial oxide layer 5 has gate ohmic contact holes and source ohmic contact holes.

[0057] In this embodiment of the invention, a layer of SiO2 is deposited on the upper surface of the P-type gate region 3 and the N+ source region 4 as an ICP etching mask. Then, the mask is coated, exposed, and developed to form gate ohmic contact holes and source ohmic contact holes, thus obtaining the initial oxide layer 5.

[0058] In step S205, using magnetron sputtering, gate ohmic contact metal 7 and source ohmic contact metal 6 are formed on the upper surfaces of a portion of the P-type gate region 3 and a portion of the N+ source region 4 in the gate ohmic contact hole and the source ohmic contact hole.

[0059] In this embodiment of the invention, a Ti / Ni / Al metal alloy is magnetron sputtered in the gate ohmic contact hole and the source ohmic contact hole. The gate ohmic contact metal 7 and the source ohmic contact metal 6 are located on the upper surface of a portion of the P-type gate region 3 and a portion of the N+ source region 4, respectively. Figure 3 (d) in the middle.

[0060] The gate ohmic contact metal 7 and the source ohmic contact metal 6 are made of metal alloys, preferably Ti / Ni / Al metal alloys, with a thickness ranging from 0.1 μm to 0.3 μm.

[0061] Step S206: Using magnetron sputtering, a drain ohmic contact metal 8 is formed under the substrate layer 1.

[0062] On the back side of the device, below substrate layer 1, a Ti / Ni / Al metal alloy is magnetron sputtered to form the drain ohmic contact metal 8. The metals on both the front and back sides undergo rapid thermal annealing in an Ar atmosphere. (See [link to documentation]). Figure 3 (e) in the middle.

[0063] Specifically, the material of the drain ohmic contact metal 8 is a metal alloy, preferably a Ti / Ni / Al metal alloy, with a thickness ranging from 0.1 μm to 0.3 μm.

[0064] In step S207, based on the initial oxide layer 5, an oxide layer 9 is formed on the upper surfaces of the P-type gate region 3, the N+ source region 4, the gate ohmic contact metal 7, and the source ohmic contact metal 6 through deposition and etching operations.

[0065] Based on the initial oxide layer 5, a SiO2 layer is deposited on the device surface as an ICP etching mask. Then, photoresist is applied, exposed, and developed. The mask layer is etched to form source contact holes, and the photoresist is removed. (See [link to previous section]) Figure 3 (f) Afterwards, the photoresist is applied again, exposed, developed, and the mask layer is etched. Gate contact holes are formed around the active region of the device, and the photoresist is removed, finally obtaining an oxide layer 9 located on the upper surfaces of the P-type gate region 3, the N+ source region 4, the gate ohmic contact metal 7, and the source ohmic contact metal 6. The oxide layer 9 has source contact holes and gate contact holes.

[0066] The thickness of the oxide layer 9 can range from 1 μm to 3 μm.

[0067] In step S208, a gate, a source 10, and a drain 11 are formed using a magnetron sputtering process; the source 10 is connected to the source ohmic contact metal 6 through a source contact hole; the gate is connected to the gate ohmic contact metal 7 through a gate contact hole; and the drain 11 is superimposed on the drain ohmic contact metal 8.

[0068] In this embodiment of the invention, a metal Al layer is formed by sputtering and evaporating on the device surface using magnetron sputtering. Following this, a resist coating, exposure, and development are performed, and a wet etching process is used to etch the metal Al to form the gate and source 10. The source 10 is connected to the source ohmic contact metal 6 through a source contact hole; the gate is connected to the gate ohmic contact metal 7 through a gate contact hole. A drain 11 is formed by sputtering and evaporating on the back side of the device, superimposed on the drain ohmic contact metal 8, as shown below. Figure 1 As shown.

[0069] Specifically, the gate, source 10 and drain 11 can all be made of Al, with a thickness ranging from 3 μm to 6 μm.

[0070] In this embodiment of the invention, a planar vertical-channel SiC JFET structure with channel implantation is employed. By utilizing high-energy channel ion implantation and multi-step conventional ion implantation processes, symmetrical deep P-type well regions are formed on both sides of the epitaxial surface. This achieves a high degree of symmetry in the vertical P-type gate region 3 without the need for complex processes such as trench etching or tilted ion implantation. Compared to traditional JFET structures, this significantly simplifies the fabrication process, greatly reduces the difficulty and complexity of the process, and saves on process costs.

[0071] Furthermore, in this embodiment of the invention, channel injection is not limited to single, double, or multiple channel injections; planar SiCJFET structures include, but are not limited to, strip, square, hexagonal, octagonal, and dodecagonal cell shapes.

[0072] It should be noted that the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the invention.

[0073] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0074] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings and the disclosure in carrying out the claimed invention. In the description of the invention, the word "comprising" does not exclude other components or steps, "a" or "an" does not exclude a plurality, and "a plurality" means two or more, unless otherwise explicitly specified. Furthermore, while different embodiments may describe certain measures, this does not mean that these measures cannot be combined to produce good results.

[0075] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0076] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0077] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0078] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A planar SiC JFET based on channel ion implantation, characterized in that, The planar SiC JFET includes: A substrate layer, and an N-drift layer located on the substrate layer; Two P-type gate regions are symmetrically distributed on both sides of the interior of the N-drift layer; each P-type gate region includes a deep P-type well region and a surface P+ gate region located above the deep P-type well region. The N+ source region is located on the surface of the N-drift layer between the two P-type gate regions; The gate ohmic contact metal is located on the upper surface of a portion of the P-type gate region; The source ohmic contact metal is located on the upper surface of a portion of the N+ source region; An oxide layer is located on the upper surface of the P-type gate region, the N+ source region, the gate ohmic contact metal, and the source ohmic contact metal; the oxide layer has source contact holes and gate contact holes. The source electrode is connected to the source electrode ohmic contact metal via the source electrode contact hole; The gate is connected to the gate ohmic contact metal via the gate contact hole; A drain ohmic contact metal is superimposed beneath the substrate layer; The drain electrode is superimposed on the drain ohmic contact metal.

2. The planar SiC JFET according to claim 1, characterized in that, The doping concentration of the surface P+ region is higher than that of the deep P-type well region.

3. The planar SiC JFET according to claim 2, characterized in that, The doping concentration range of the surface P+ region is 1×10⁻⁶. 18 cm -3 ~1×10 20 cm -3 The doping concentration range of the deep P-type well region is 1×10⁻⁶. 16 cm -3 ~1×10 20 cm -3 .

4. The planar SiC JFET according to claim 1, characterized in that, Both the surface P+ region and the deep P-type well region are doped with Al ions.

5. The planar SiC JFET according to claim 1, characterized in that, Both the gate ohmic contact metal and the source ohmic contact metal are made of Ti / Ni / Al alloy.

6. The planar SiC JFET according to claim 1, characterized in that, The source, gate, and drain are all made of Al.

7. The planar SiC JFET according to claim 1, characterized in that, The oxide layer is made of SiO2.

8. The planar SiC JFET according to claim 1, characterized in that, The thickness of the substrate layer ranges from 100 μm to 500 μm; the thickness of the N-drift layer ranges from 1 μm to 100 μm; the depth of the deep P-type well region ranges from 2 μm to 3 μm; the depth of the surface P+ gate region ranges from 0.1 μm to 0.5 μm; the depth of the N+ source region ranges from 0.1 μm to 0.5 μm; the thickness of the gate ohmic contact metal ranges from 0.1 μm to 0.3 μm; the thickness of the source ohmic contact metal ranges from 0.1 μm to 0.3 μm; the thickness of the oxide layer ranges from 1 μm to 3 μm; the thickness of the source ranges from 3 μm to 6 μm; the thickness of the gate ranges from 3 μm to 6 μm; and the thickness of the drain ranges from 3 μm to 6 μm.

9. A method for fabricating a planar SiC JFET based on channel ion implantation, characterized in that, The preparation method includes: Select a substrate layer and grow an N-drift layer on the substrate layer; On both sides of the upper surface of the N-drift layer, a deep P-well region and a surface P+ gate region located above the deep P-type well region are formed by high-energy channel ion implantation process and multi-step conventional ion implantation process to obtain a P-type gate region. An N+ source region is formed on the surface of the N- drift layer between the two P-type gate regions using an ion implantation process. An initial oxide layer is formed on the upper surface of the P-type gate region and the N+ source region by deposition and etching operations; the initial oxide layer has gate ohmic contact holes and source ohmic contact holes. Using a magnetron sputtering process, gate ohmic contact metal and source ohmic contact metal are formed in the gate ohmic contact hole and the source ohmic contact hole, located on the upper surface of a portion of the P-type gate region and a portion of the N+ source region; Using the magnetron sputtering process, a drain ohmic contact metal is formed beneath the substrate layer; Based on the initial oxide layer, an oxide layer is formed on the upper surfaces of the P-type gate region, the N+ source region, the gate ohmic contact metal, and the source ohmic contact metal through deposition and etching operations; A gate, source, and drain are formed using a magnetron sputtering process; the source is connected to the source ohmic contact metal through the source contact hole; the gate is connected to the gate ohmic contact metal through the gate contact hole; and the drain is superimposed on the drain ohmic contact metal.

10. The preparation method according to claim 9, characterized in that, The high-energy channel ion implantation process has an implantation energy range of 500 keV to 1 MeV and an implantation dose range of 1 × 10⁻⁶. 14 cm -3 ~1×10 15 cm -3 .

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